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GBHawk: don't clear timer/serial interrupts when they happen at the same time as a set

This commit is contained in:
alyosha-tas 2020-10-24 21:46:31 -04:00
parent 72511add3b
commit bd3ee6f45c
2 changed files with 5 additions and 6 deletions
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6
src/BizHawk.Emulation.Cores/Consoles/Nintendo/GBHawk/GBHawk.IEmulator.cs
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@ -364,9 +364,9 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
public void SetIntRegs(byte r)
{
// For timer interrupts or serial interrupts that occur on the same cycle as the IRQ clear
// the clear wins on GB but the set wins on GBC
if (((REG_FF0F & 4) == 4) && ((r & 4) == 0) && timer.IRQ_block && !is_GBC) { r |= 4; }
if (((REG_FF0F & 8) == 8) && ((r & 8) == 0) && serialport.IRQ_block && !is_GBC) { r |= 8; }
// the cear wins on GB and GBA (tested on GBP.) Assuming true for GBC E too.
if (((REG_FF0F & 4) == 4) && ((r & 4) == 0) && timer.IRQ_block) { r |= 4; }
if (((REG_FF0F & 8) == 8) && ((r & 8) == 0) && serialport.IRQ_block) { r |= 8; }
REG_FF0F = r;
}

5
src/BizHawk.Emulation.Cores/Consoles/Nintendo/GBHawk/Timer.cs
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@ -7,8 +7,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
// Timer Emulation
// NOTES:
//
// For GB, it looks like divider reg should start at 1 on reset.
// for GBC, a starting value of 0xFFFF passes all tests. GBA is not explicitly tested but for now is set to 0xFFFF as well.
// Currently, a starting value of 0xFFFE passes all tests. GBA is not explicitly tested but for now is set to 0xFFFE as well.
//
// Some additional glitches happen on GBC, but they are non-deterministic and not emulated here
//
@ -29,7 +28,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
public byte timer_old;
public byte timer_control;
public byte pending_reload;
public bool IRQ_block; // if the timer IRQ happens on the same cycle as a previous one was cleared, the IRQ is blocked, only on GBC
public bool IRQ_block; // if the timer IRQ happens on the same cycle as a previous one was cleared, the IRQ is set
public bool old_state;
public bool state;
public bool reload_block;