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GBHawk: rewok interrupt handling to pass more tests and behave like gambatte on Gensan 2

This commit is contained in:
alyosha-tas 2020-09-25 20:19:53 -04:00
parent 39f6668f18
commit bac502671f
2 changed files with 38 additions and 38 deletions
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58
src/BizHawk.Emulation.Cores/CPUs/LR35902/Interrupts.cs
View File

@ -6,24 +6,24 @@ namespace BizHawk.Emulation.Cores.Components.LR35902
{
cur_instr = new ushort[]
{IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
DEC16, SPl, SPh,
IDLE,
WR, SPl, SPh, PCh,
INT_GET, 4, W,
DEC16, SPl, SPh,
INT_GET, 3, W,
WR, SPl, SPh, PCl,
INT_GET, 2, W,
IDLE,
INT_GET, 1, W,
IDLE,
INT_GET, 0, W,
ASGN, PCh, 0,
IDLE,
IDLE,
TR, PCl, W,
DEC16, SPl, SPh,
INT_GET, 1, W,
WR, SPl, SPh, PCl,
IRQ_CLEAR,
IDLE,
TR, PCl, W,
OP };
}
@ -31,28 +31,28 @@ namespace BizHawk.Emulation.Cores.Components.LR35902
{
cur_instr = new ushort[]
{IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
DEC16, SPl, SPh,
IDLE,
WR, SPl, SPh, PCh,
IDLE,
DEC16, SPl, SPh,
IDLE,
WR, SPl, SPh, PCl,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
INT_GET, 4, W,
INT_GET, 3, W,
INT_GET, 2, W,
INT_GET, 1, W,
INT_GET, 0, W,
TR, PCl, W,
IDLE,
ASGN, PCh, 0,
DEC16, SPl, SPh,
INT_GET, 1, W,
WR, SPl, SPh, PCl,
IRQ_CLEAR,
IDLE,
IDLE,
TR, PCl, W,
OP };
}

18
src/BizHawk.Emulation.Cores/CPUs/LR35902/LR35902.cs
View File

@ -605,16 +605,17 @@ namespace BizHawk.Emulation.Cores.Components.LR35902
interrupt_src_reg = GetIntRegs(0);
interrupt_enable_reg = GetIntRegs(1);
if (interrupt_src_reg.Bit(bit_check) && interrupt_enable_reg.Bit(bit_check)) { int_src = bit_check; int_clear = (byte)(1 << bit_check); }
/*
if (interrupt_src.Bit(0) && interrupt_enable.Bit(0)) { int_src = 0; int_clear = 1; }
else if (interrupt_src.Bit(1) && interrupt_enable.Bit(1)) { int_src = 1; int_clear = 2; }
else if (interrupt_src.Bit(2) && interrupt_enable.Bit(2)) { int_src = 2; int_clear = 4; }
else if (interrupt_src.Bit(3) && interrupt_enable.Bit(3)) { int_src = 3; int_clear = 8; }
else if (interrupt_src.Bit(4) && interrupt_enable.Bit(4)) { int_src = 4; int_clear = 16; }
//if (interrupt_src_reg.Bit(bit_check) && interrupt_enable_reg.Bit(bit_check)) { int_src = bit_check; int_clear = (byte)(1 << bit_check); }
if (interrupt_src_reg.Bit(0) && interrupt_enable_reg.Bit(0)) { int_src = 0; int_clear = 1; }
else if (interrupt_src_reg.Bit(1) && interrupt_enable_reg.Bit(1)) { int_src = 1; int_clear = 2; }
else if (interrupt_src_reg.Bit(2) && interrupt_enable_reg.Bit(2)) { int_src = 2; int_clear = 4; }
else if (interrupt_src_reg.Bit(3) && interrupt_enable_reg.Bit(3)) { int_src = 3; int_clear = 8; }
else if (interrupt_src_reg.Bit(4) && interrupt_enable_reg.Bit(4)) { int_src = 4; int_clear = 16; }
else { int_src = 5; int_clear = 0; }
*/
Regs[instr_table[instr_pntr++]] = INT_vectors[int_src];
break;
case HALT_CHK:
I_use = FlagI;
@ -640,7 +641,6 @@ namespace BizHawk.Emulation.Cores.Components.LR35902
SetIntRegs(interrupt_src_reg);
if ((interrupt_src_reg & interrupt_enable_reg) == 0) { FlagI = false; }
// reset back to default state
int_src = 5;
int_clear = 0;