nes-support tengen board (mapper64)
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zeromus
parent
e5f1c142f8
commit
b7863fb7d1
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@ -139,6 +139,7 @@
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</Compile>
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<Compile Include="Consoles\Nintendo\NES\Boards\TAITO_74_161_161_32.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Taito_TC0190FMC.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\TENGEN-800032.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\UxROM.cs">
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<SubType>Code</SubType>
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</Compile>
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@ -51,7 +51,7 @@ Open bus and bus conflict emulation is not considered complete or thorough in an
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060 Multicart Junk
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061 Multicart Junk
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062 Multicart Junk
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064 Tengen Needed
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064 Tengen Good
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065 Misc (J) Nothing
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066 GxROM Complete
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067 Misc (J) Nothing
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@ -0,0 +1,267 @@
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using System;
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using System.IO;
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using System.Diagnostics;
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namespace BizHawk.Emulation.Consoles.Nintendo
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{
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//AKA mapper 64
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public class TENGEN_800032 : NES.NESBoardBase
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{
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//configuration
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int prg_bank_mask_8k;
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int chr_bank_mask_1k;
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//regenerable state
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IntBuffer prg_banks_8k = new IntBuffer(4);
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IntBuffer chr_banks_1k = new IntBuffer(8);
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//state
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IntBuffer regs = new IntBuffer(16);
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int address;
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bool chr_1k, chr_mode, prg_mode;
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//irq
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int irq_countdown;
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int a12_old;
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int irq_reload, irq_counter;
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bool irq_pending, irq_enable;
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bool irq_mode;
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bool irq_reload_pending;
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public override void Dispose()
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{
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base.Dispose();
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prg_banks_8k.Dispose();
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chr_banks_1k.Dispose();
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}
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("regs", ref regs);
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ser.Sync("address", ref address);
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ser.Sync("chr_1k", ref chr_1k);
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ser.Sync("chr_mode", ref chr_mode);
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ser.Sync("prg_mode", ref prg_mode);
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ser.Sync("irq_countdown", ref irq_countdown);
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ser.Sync("a12_old", ref a12_old);
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ser.Sync("irq_reload", ref irq_reload);
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ser.Sync("irq_counter", ref irq_counter);
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ser.Sync("irq_pending", ref irq_pending);
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ser.Sync("irq_enable", ref irq_enable);
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ser.Sync("irq_mode", ref irq_mode);
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ser.Sync("irq_reload_pending", ref irq_reload_pending);
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if (ser.IsReader)
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Sync();
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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switch (Cart.board_type)
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{
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case "TENGEN-800032":
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AssertPrg(64,128); AssertChr(64,128); AssertVram(0); AssertWram(00);
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break;
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}
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prg_bank_mask_8k = Cart.prg_size / 8 - 1;
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chr_bank_mask_1k = Cart.chr_size / 1 - 1;
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SetMirrorType(EMirrorType.Vertical);
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Sync();
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return true;
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}
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void Sync()
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{
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if (prg_mode)
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{
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prg_banks_8k[0] = regs[0xF] & prg_bank_mask_8k;
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prg_banks_8k[1] = regs[0x6] & prg_bank_mask_8k;
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prg_banks_8k[2] = regs[0x7] & prg_bank_mask_8k;
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prg_banks_8k[3] = 0xFF & prg_bank_mask_8k;
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}
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else
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{
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prg_banks_8k[0] = regs[0x6] & prg_bank_mask_8k;
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prg_banks_8k[1] = regs[0x7] & prg_bank_mask_8k;
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prg_banks_8k[2] = regs[0xF] & prg_bank_mask_8k;
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prg_banks_8k[3] = 0xFF & prg_bank_mask_8k;
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}
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if (chr_mode)
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{
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chr_banks_1k[0] = regs[0x2] & chr_bank_mask_1k;
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chr_banks_1k[1] = regs[0x3] & chr_bank_mask_1k;
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chr_banks_1k[2] = regs[0x4] & chr_bank_mask_1k;
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chr_banks_1k[3] = regs[0x5] & chr_bank_mask_1k;
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if (chr_1k)
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{
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chr_banks_1k[4] = regs[0x0] & chr_bank_mask_1k;
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chr_banks_1k[5] = regs[0x8] & chr_bank_mask_1k;
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chr_banks_1k[6] = regs[0x1] & chr_bank_mask_1k;
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chr_banks_1k[7] = regs[0x9] & chr_bank_mask_1k;
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}
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else
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{
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chr_banks_1k[4] = ((regs[0x0] & 0xFE) + 0) & chr_bank_mask_1k;
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chr_banks_1k[5] = ((regs[0x0] & 0xFE) + 1) & chr_bank_mask_1k;
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chr_banks_1k[6] = ((regs[0x1] & 0xFE) + 0) & chr_bank_mask_1k;
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chr_banks_1k[7] = ((regs[0x1] & 0xFE) + 1) & chr_bank_mask_1k;
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}
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}
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else
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{
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chr_banks_1k[4] = regs[0x2] & chr_bank_mask_1k;
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chr_banks_1k[5] = regs[0x3] & chr_bank_mask_1k;
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chr_banks_1k[6] = regs[0x4] & chr_bank_mask_1k;
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chr_banks_1k[7] = regs[0x5] & chr_bank_mask_1k;
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if (chr_1k)
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{
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chr_banks_1k[0] = regs[0x0] & chr_bank_mask_1k;
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chr_banks_1k[1] = regs[0x8] & chr_bank_mask_1k;
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chr_banks_1k[2] = regs[0x1] & chr_bank_mask_1k;
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chr_banks_1k[3] = regs[0x9] & chr_bank_mask_1k;
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}
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else
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{
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chr_banks_1k[0] = ((regs[0x0] & 0xFE) + 0) & chr_bank_mask_1k;
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chr_banks_1k[1] = ((regs[0x0] & 0xFE) + 1) & chr_bank_mask_1k;
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chr_banks_1k[2] = ((regs[0x1] & 0xFE) + 0) & chr_bank_mask_1k;
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chr_banks_1k[3] = ((regs[0x1] & 0xFE) + 1) & chr_bank_mask_1k;
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}
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}
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}
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public override void WritePRG(int addr, byte value)
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{
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//Console.WriteLine("mapping {0:X4} = {1:X2}", addr, value);
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addr &= 0xE001;
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switch (addr)
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{
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case 0x0000:
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address = value & 0xF;
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chr_1k = value.Bit(5);
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prg_mode = value.Bit(6);
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chr_mode = value.Bit(7);
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Sync();
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break;
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case 0x0001: //data port
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regs[address] = value;
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Sync();
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break;
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case 0x2000:
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if (value.Bit(0)) SetMirrorType(EMirrorType.Horizontal);
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else SetMirrorType(EMirrorType.Vertical);
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break;
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case 0x4000:
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irq_reload = value;
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break;
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case 0x4001:
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irq_mode = value.Bit(0);
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if(irq_mode) irq_countdown = 12;
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irq_reload_pending = true;
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break;
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case 0x6000:
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irq_enable = false;
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irq_pending = false;
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SyncIRQ();
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break;
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case 0x6001:
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irq_enable = true;
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SyncIRQ();
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break;
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}
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}
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public override byte ReadPRG(int addr)
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{
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int bank_8k = addr >> 13;
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int ofs = addr & ((1 << 13) - 1);
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bank_8k = prg_banks_8k[bank_8k];
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addr = (bank_8k << 13) | ofs;
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return ROM[addr];
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = chr_banks_1k[bank_1k];
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addr = (bank_1k << 10) | ofs;
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return VROM[addr];
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}
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else
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return base.ReadPPU(addr);
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}
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void SyncIRQ()
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{
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NES.irq_cart = irq_pending;
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}
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void ClockIRQ()
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{
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if (irq_reload_pending)
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{
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irq_counter = irq_reload + 1;
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irq_reload_pending = false;
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}
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else if (irq_counter == 0)
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{
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irq_counter = irq_reload;
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}
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else
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{
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irq_counter--;
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if (irq_counter == 0 && irq_enable)
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{
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irq_pending = true;
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SyncIRQ();
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}
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}
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}
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public override void ClockPPU()
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{
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if (irq_countdown > 0)
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{
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irq_countdown--;
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if (irq_countdown == 0)
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{
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ClockIRQ();
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if (irq_mode)
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irq_countdown = 12;
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}
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}
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}
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public override void AddressPPU(int addr)
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{
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int a12 = (addr >> 12) & 1;
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bool rising_edge = (a12 == 1 && a12_old == 0);
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if (rising_edge)
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{
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//this number is totally guessed to make klax work
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irq_countdown = 25;
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}
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a12_old = a12;
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}
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}
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}
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