ShuriZma
/
BizHawk
mirror of https://github.com/TASEmulators/BizHawk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

O2Hawk: more CPU work

This commit is contained in:
alyosha-tas 2019-11-08 10:44:00 -05:00
parent 9a5f40a4c5
commit aced228b43
5 changed files with 295 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

268
BizHawk.Emulation.Cores/CPUs/Intel8048/Execute.cs
View File

@ -27,73 +27,73 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x01: ILLEGAL(); break; // ILLEGAL case 0x01: ILLEGAL(); break; // ILLEGAL
case 0x02: ILLEGAL(); break; // ILLEGAL case 0x02: ILLEGAL(); break; // ILLEGAL
case 0x03: OP_A_DIR(ADD8); break; // ADD A,# case 0x03: OP_A_DIR(ADD8); break; // ADD A,#
case 0x04: ILLEGAL(); break; // LSR (Direct) case 0x04: JP_2k(0); break; // JP 2K 0
case 0x05: OP_IMP(EI); break; // EI case 0x05: OP_IMP(EI); break; // EI
case 0x06: ILLEGAL(); break; // ROR (Direct) case 0x06: ILLEGAL(); break; // ILLEGAL
case 0x07: OP_IMP(DECA); break; // DEC A case 0x07: OP_IMP(DECA); break; // DEC A
case 0x08: ILLEGAL(); break; // ASL , LSL (Direct) case 0x08: ILLEGAL(); break; // ILLEGAL
case 0x09: ILLEGAL(); break; // ROL (Direct) case 0x09: ILLEGAL(); break; // ILLEGAL
case 0x0A: ILLEGAL(); break; // DEC (Direct) case 0x0A: ILLEGAL(); break; // ILLEGAL
case 0x0B: ILLEGAL(); break; // ILLEGAL case 0x0B: ILLEGAL(); break; // ILLEGAL
case 0x0C: ILLEGAL(); break; // INC (Direct) case 0x0C: ILLEGAL(); break; // ILLEGAL
case 0x0D: ILLEGAL(); break; // TST (Direct) case 0x0D: ILLEGAL(); break; // ILLEGAL
case 0x0E: ILLEGAL(); break; // JMP (Direct) case 0x0E: ILLEGAL(); break; // ILLEGAL
case 0x0F: ILLEGAL(); break; // CLR (Direct) case 0x0F: ILLEGAL(); break; // ILLEGAL
case 0x10: ILLEGAL(); break; // Page 2 case 0x10: ILLEGAL(); break; // ILLEGAL
case 0x11: ILLEGAL(); break; // Page 3 case 0x11: ILLEGAL(); break; // ILLEGAL
case 0x12: ILLEGAL(); break; // NOP (Inherent) case 0x12: JPB(0); break; // JPB 0
case 0x13: OP_A_DIR(ADC8); break; // ADC A,# case 0x13: OP_A_DIR(ADC8); break; // ADC A,#
case 0x14: CALL(0); break; // CALL case 0x14: CALL(0); break; // CALL
case 0x15: OP_IMP(DI); break; // DI case 0x15: OP_IMP(DI); break; // DI
case 0x16: ILLEGAL(); break; // LBRA (Relative) case 0x16: ILLEGAL(); break; // ILLEGAL
case 0x17: OP_IMP(INCA); break; // INC A case 0x17: OP_IMP(INCA); break; // INC A
case 0x18: ILLEGAL(); break; // ILLEGAL case 0x18: ILLEGAL(); break; // ILLEGAL
case 0x19: ILLEGAL(); break; // DAA (Inherent) case 0x19: ILLEGAL(); break; // ILLEGAL
case 0x1A: ILLEGAL(); break; // ORCC (Immediate) case 0x1A: ILLEGAL(); break; // ILLEGAL
case 0x1B: ILLEGAL(); break; // ILLEGAL case 0x1B: ILLEGAL(); break; // ILLEGAL
case 0x1C: ILLEGAL(); break; // ANDCC (Immediate) case 0x1C: ILLEGAL(); break; // ILLEGAL
case 0x1D: ILLEGAL(); break; // SEX (Inherent) case 0x1D: ILLEGAL(); break; // ILLEGAL
case 0x1E: ILLEGAL(); break; // EXG (Immediate) case 0x1E: ILLEGAL(); break; // ILLEGAL
case 0x1F: ILLEGAL(); break; // TFR (Immediate) case 0x1F: ILLEGAL(); break; // ILLEGAL
case 0x20: ILLEGAL(); break; // BRA (Relative) case 0x20: OP_A_R(XCH_RAM, R0); break; // XCH A,@R0
case 0x21: ILLEGAL(); break; // BRN (Relative) case 0x21: OP_A_R(XCH_RAM, R1); break; // XCH A,@R1
case 0x22: ILLEGAL(); break; // BHI (Relative) case 0x22: ILLEGAL(); break; // ILLEGAL
case 0x23: ILLEGAL(); break; // BLS (Relative) case 0x23: ILLEGAL(); break; // ILLEGAL
case 0x24: ILLEGAL(); break; // BHS , BCC (Relative) case 0x24: JP_2k(1); break; // JP 2K 1
case 0x25: OP_IMP(EN); break; // EN case 0x25: OP_IMP(EN); break; // EN
case 0x26: ILLEGAL(); break; // BNE (Relative) case 0x26: JP_COND(!T0); break; // JP NT0
case 0x27: OP_IMP(CLR); break; // CLR A case 0x27: OP_IMP(CLR); break; // CLR A
case 0x28: ILLEGAL(); break; // BVC (Relative) case 0x28: OP_A_R(XCH, R0); break; // XCH A,R0
case 0x29: ILLEGAL(); break; // BVS (Relative) case 0x29: OP_A_R(XCH, R1); break; // XCH A,R1
case 0x2A: ILLEGAL(); break; // BPL (Relative) case 0x2A: OP_A_R(XCH, R2); break; // XCH A,R2
case 0x2B: ILLEGAL(); break; // BMI (Relative) case 0x2B: OP_A_R(XCH, R3); break; // XCH A,R3
case 0x2C: ILLEGAL(); break; // BGE (Relative) case 0x2C: OP_A_R(XCH, R4); break; // XCH A,R4
case 0x2D: ILLEGAL(); break; // BLT (Relative) case 0x2D: OP_A_R(XCH, R5); break; // XCH A,R5
case 0x2E: ILLEGAL(); break; // BGT (Relative) case 0x2E: OP_A_R(XCH, R6); break; // XCH A,R6
case 0x2F: ILLEGAL(); break; // BLE (Relative) case 0x2F: OP_A_R(XCH, R7); break; // XCH A,R7
case 0x30: ILLEGAL(); break; // LEAX (Indexed) case 0x30: OP_A_R(XCHD_RAM, R0); break; // XCHD A,@R0
case 0x31: ILLEGAL(); break; // LEAY (Indexed) case 0x31: OP_A_R(XCHD_RAM, R1); break; // XCHD A,@R0
case 0x32: ILLEGAL(); break; // LEAS (Indexed) case 0x32: JPB(1); break; // JPB 1
case 0x33: ILLEGAL(); break; // LEAU (Indexed) case 0x33: ILLEGAL(); break; // ILLEGAL
case 0x34: CALL(1); break; // CALL case 0x34: CALL(1); break; // CALL
case 0x35: OP_IMP(DN); break; // DN case 0x35: OP_IMP(DN); break; // DN
case 0x36: ILLEGAL(); break; // PSHU (Immediate) case 0x36: JP_COND(T0); break; // JP T0
case 0x37: OP_IMP(COM); break; // COM A case 0x37: OP_IMP(COM); break; // COM A
case 0x38: ILLEGAL(); break; // ILLEGAL case 0x38: ILLEGAL(); break; // ILLEGAL
case 0x39: ILLEGAL(); break; // RTS (Inherent) case 0x39: ILLEGAL(); break; // ILLEGAL
case 0x3A: ILLEGAL(); break; // ABX (Inherent) case 0x3A: ILLEGAL(); break; // ILLEGAL
case 0x3B: ILLEGAL(); break; // RTI (Inherent) case 0x3B: ILLEGAL(); break; // ILLEGAL
case 0x3C: ILLEGAL(); break; // CWAI (Inherent) case 0x3C: ILLEGAL(); break; // ILLEGAL
case 0x3D: ILLEGAL(); break; // MUL (Inherent) case 0x3D: ILLEGAL(); break; // ILLEGAL
case 0x3E: ILLEGAL(); break; // ILLEGAL case 0x3E: ILLEGAL(); break; // ILLEGAL
case 0x3F: ILLEGAL(); break; // SWI (Inherent) case 0x3F: ILLEGAL(); break; // ILLEGAL
case 0x40: OP_A_R(OR8RAM, R0); break; // OR A,@R0 case 0x40: OP_A_R(OR8RAM, R0); break; // OR A,@R0
case 0x41: OP_A_R(OR8RAM, R1); break; // OR A,@R1 case 0x41: OP_A_R(OR8RAM, R1); break; // OR A,@R1
case 0x42: ILLEGAL(); break; // ILLEGAL case 0x42: ILLEGAL(); break; // ILLEGAL
case 0x43: OP_A_DIR(OR8); break; // OR A,# case 0x43: OP_A_DIR(OR8); break; // OR A,#
case 0x44: ILLEGAL(); break; // LSRA (Inherent) case 0x44: JP_2k(2); break; // JP 2K 2
case 0x45: ILLEGAL(); break; // ILLEGAL case 0x45: ILLEGAL(); break; // ILLEGAL
case 0x46: ILLEGAL(); break; // RORA (Inherent) case 0x46: JP_COND(!T1); break; // JP NT1
case 0x47: OP_IMP(SWP); break; // SWP case 0x47: OP_IMP(SWP); break; // SWP
case 0x48: OP_A_R(OR8, R0); break; // OR A,R0 case 0x48: OP_A_R(OR8, R0); break; // OR A,R0
case 0x49: OP_A_R(OR8, R1); break; // OR A,R1 case 0x49: OP_A_R(OR8, R1); break; // OR A,R1
@ -105,11 +105,11 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x4F: OP_A_R(OR8, R7); break; // OR A,R7 case 0x4F: OP_A_R(OR8, R7); break; // OR A,R7
case 0x50: OP_A_R(AND8RAM, R0); break; // AND A,@R0 case 0x50: OP_A_R(AND8RAM, R0); break; // AND A,@R0
case 0x51: OP_A_R(AND8RAM, R1); break; // AND A,@R1 case 0x51: OP_A_R(AND8RAM, R1); break; // AND A,@R1
case 0x52: ILLEGAL(); break; // ILLEGAL case 0x52: JPB(2); break; // JPB 2
case 0x53: OP_A_DIR(AND8); break; // AND A,# case 0x53: OP_A_DIR(AND8); break; // AND A,#
case 0x54: CALL(2); break; // CALL case 0x54: CALL(2); break; // CALL
case 0x55: ILLEGAL(); break; // ILLEGAL case 0x55: ILLEGAL(); break; // ILLEGAL
case 0x56: ILLEGAL(); break; // RORB (Inherent) case 0x56: JP_COND(T1); break; // JP T1
case 0x57: OP_IMP(DA); break; // DA A case 0x57: OP_IMP(DA); break; // DA A
case 0x58: OP_A_R(AND8, R0); break; // AND A,R0 case 0x58: OP_A_R(AND8, R0); break; // AND A,R0
case 0x59: OP_A_R(AND8, R1); break; // AND A,R1 case 0x59: OP_A_R(AND8, R1); break; // AND A,R1
@ -122,10 +122,10 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x60: OP_A_R(ADD8RAM, R0); break; // ADD A,@R0 case 0x60: OP_A_R(ADD8RAM, R0); break; // ADD A,@R0
case 0x61: OP_A_R(ADD8RAM, R1); break; // ADD A,@R1 case 0x61: OP_A_R(ADD8RAM, R1); break; // ADD A,@R1
case 0x62: ILLEGAL(); break; // ILLEGAL case 0x62: ILLEGAL(); break; // ILLEGAL
case 0x63: ILLEGAL(); break; // COM (Indexed) case 0x63: ILLEGAL(); break; // ILLEGAL
case 0x64: ILLEGAL(); break; // LSR (Indexed) case 0x64: JP_2k(3); break; // JP 2K 3
case 0x65: ILLEGAL(); break; // ILLEGAL case 0x65: ILLEGAL(); break; // ILLEGAL
case 0x66: ILLEGAL(); break; // ROR (Indexed) case 0x66: ILLEGAL(); break; // ILLEGAL
case 0x67: OP_IMP(RRC); break; // RRC case 0x67: OP_IMP(RRC); break; // RRC
case 0x68: OP_A_R(ADD8, R0); break; // ADD A,R0 case 0x68: OP_A_R(ADD8, R0); break; // ADD A,R0
case 0x69: OP_A_R(ADD8, R1); break; // ADD A,R1 case 0x69: OP_A_R(ADD8, R1); break; // ADD A,R1
@ -137,11 +137,11 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x6F: OP_A_R(ADD8, R7); break; // ADD A,R7 case 0x6F: OP_A_R(ADD8, R7); break; // ADD A,R7
case 0x70: OP_A_R(ADC8RAM, R0); break; // ADC A,@R0 case 0x70: OP_A_R(ADC8RAM, R0); break; // ADC A,@R0
case 0x71: OP_A_R(ADC8RAM, R1); break; // ADC A,@R1 case 0x71: OP_A_R(ADC8RAM, R1); break; // ADC A,@R1
case 0x72: ILLEGAL(); break; // ILLEGAL case 0x72: JPB(3); break; // JPB 3
case 0x73: ILLEGAL(); break; // COM (Extended) case 0x73: ILLEGAL(); break; // ILLEGAL
case 0x74: CALL(3); break; // CALL case 0x74: CALL(3); break; // CALL
case 0x75: ILLEGAL(); break; // ILLEGAL case 0x75: OP_IMP(CLK_OUT); break; // ENT0 CLK
case 0x76: ILLEGAL(); break; // ROR (Extended) case 0x76: JP_COND(F1); break; // JP F1
case 0x77: OP_IMP(ROR); break; // ROR case 0x77: OP_IMP(ROR); break; // ROR
case 0x78: OP_A_R(ADC8, R0); break; // ADC A,R0 case 0x78: OP_A_R(ADC8, R0); break; // ADC A,R0
case 0x79: OP_A_R(ADC8, R1); break; // ADC A,R1 case 0x79: OP_A_R(ADC8, R1); break; // ADC A,R1
@ -151,13 +151,13 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x7D: OP_A_R(ADC8, R5); break; // ADC A,R5 case 0x7D: OP_A_R(ADC8, R5); break; // ADC A,R5
case 0x7E: OP_A_R(ADC8, R6); break; // ADC A,R6 case 0x7E: OP_A_R(ADC8, R6); break; // ADC A,R6
case 0x7F: OP_A_R(ADC8, R7); break; // ADC A,R7 case 0x7F: OP_A_R(ADC8, R7); break; // ADC A,R7
case 0x80: ILLEGAL(); break; // SUBA (Immediate) case 0x80: ILLEGAL(); break; // ILLEGAL
case 0x81: ILLEGAL(); break; // CMPA (Immediate) case 0x81: ILLEGAL(); break; // ILLEGAL
case 0x82: ILLEGAL(); break; // SBCA (Immediate) case 0x82: ILLEGAL(); break; // ILLEGAL
case 0x83: ILLEGAL(); break; // SUBD (Immediate) case 0x83: ILLEGAL(); break; // ILLEGAL
case 0x84: ILLEGAL(); break; // ANDA (Immediate) case 0x84: JP_2k(4); break; // JP 2K 4
case 0x85: OP_IMP(CL0); break; // CLR F0 case 0x85: OP_IMP(CL0); break; // CLR F0
case 0x86: ILLEGAL(); break; // LDA (Immediate) case 0x86: JP_COND(!IRQPending); break; // JP !IRQ
case 0x87: ILLEGAL(); break; // ILLEGAL case 0x87: ILLEGAL(); break; // ILLEGAL
case 0x88: OP_PB_DIR(OR8, BUS); break; // OR BUS,# case 0x88: OP_PB_DIR(OR8, BUS); break; // OR BUS,#
case 0x89: OP_PB_DIR(OR8, P1); break; // OR P1,# case 0x89: OP_PB_DIR(OR8, P1); break; // OR P1,#
@ -167,13 +167,13 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x8D: OP_EXP_A(OR8, P5); break; // OR P5,A case 0x8D: OP_EXP_A(OR8, P5); break; // OR P5,A
case 0x8E: OP_EXP_A(OR8, P6); break; // OR P6,A case 0x8E: OP_EXP_A(OR8, P6); break; // OR P6,A
case 0x8F: OP_EXP_A(OR8, P7); break; // OR P7,A case 0x8F: OP_EXP_A(OR8, P7); break; // OR P7,A
case 0x90: ILLEGAL(); break; // SUBA (Direct) case 0x90: ILLEGAL(); break; // ILLEGAL
case 0x91: ILLEGAL(); break; // CMPA (Direct) case 0x91: ILLEGAL(); break; // ILLEGAL
case 0x92: ILLEGAL(); break; // SBCA (Direct) case 0x92: JPB(4); break; // JPB 4
case 0x93: ILLEGAL(); break; // SUBD (Direct) case 0x93: ILLEGAL(); break; // ILLEGAL
case 0x94: CALL(4); break; // CALL case 0x94: CALL(4); break; // CALL
case 0x95: OP_IMP(CM0); break; // COM F0 case 0x95: OP_IMP(CM0); break; // COM F0
case 0x96: ILLEGAL(); break; // LDA (Direct) case 0x96: JP_COND(Regs[A] != 0); break; // JP (A != 0)
case 0x97: OP_IMP(CLC); break; // CLR C case 0x97: OP_IMP(CLC); break; // CLR C
case 0x98: OP_PB_DIR(AND8, BUS); break; // AND BUS,# case 0x98: OP_PB_DIR(AND8, BUS); break; // AND BUS,#
case 0x99: OP_PB_DIR(AND8, P1); break; // AND P1,# case 0x99: OP_PB_DIR(AND8, P1); break; // AND P1,#
@ -183,45 +183,45 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0x9D: OP_EXP_A(AND8, P5); break; // AND P5,A case 0x9D: OP_EXP_A(AND8, P5); break; // AND P5,A
case 0x9E: OP_EXP_A(AND8, P6); break; // AND P6,A case 0x9E: OP_EXP_A(AND8, P6); break; // AND P6,A
case 0x9F: OP_EXP_A(AND8, P7); break; // AND P7,A case 0x9F: OP_EXP_A(AND8, P7); break; // AND P7,A
case 0xA0: ILLEGAL(); break; // SUBA (Indexed) case 0xA0: ILLEGAL(); break; // ILLEGAL
case 0xA1: ILLEGAL(); break; // CMPA (Indexed) case 0xA1: ILLEGAL(); break; // ILLEGAL
case 0xA2: ILLEGAL(); break; // SBCA (Indexed) case 0xA2: ILLEGAL(); break; // ILLEGAL
case 0xA3: ILLEGAL(); break; // SUBD (Indexed) case 0xA3: ILLEGAL(); break; // ILLEGAL
case 0xA4: ILLEGAL(); break; // ANDA (Indexed) case 0xA4: JP_2k(5); break; // JP 2K 5
case 0xA5: OP_IMP(CL1); break; // CLR F1 case 0xA5: OP_IMP(CL1); break; // CLR F1
case 0xA6: ILLEGAL(); break; // LDA (Indexed) case 0xA6: ILLEGAL(); break; // ILLEGAL
case 0xA7: OP_IMP(CMC); break; // COM C case 0xA7: OP_IMP(CMC); break; // COM C
case 0xA8: ILLEGAL(); break; // EORA (Indexed) case 0xA8: ILLEGAL(); break; // ILLEGAL
case 0xA9: ILLEGAL(); break; // ADCA (Indexed) case 0xA9: ILLEGAL(); break; // ILLEGAL
case 0xAA: ILLEGAL(); break; // ORA (Indexed) case 0xAA: ILLEGAL(); break; // ILLEGAL
case 0xAB: ILLEGAL(); break; // ADDA (Indexed) case 0xAB: ILLEGAL(); break; // ILLEGAL
case 0xAC: ILLEGAL(); break; // CMPX (Indexed) case 0xAC: ILLEGAL(); break; // ILLEGAL
case 0xAD: ILLEGAL(); break; // JSR (Indexed) case 0xAD: ILLEGAL(); break; // ILLEGAL
case 0xAE: ILLEGAL(); break; // LDX (Indexed) case 0xAE: ILLEGAL(); break; // ILLEGAL
case 0xAF: ILLEGAL(); break; // STX (Indexed) case 0xAF: ILLEGAL(); break; // ILLEGAL
case 0xB0: ILLEGAL(); break; // SUBA (Extended) case 0xB0: ILLEGAL(); break; // ILLEGAL
case 0xB1: ILLEGAL(); break; // CMPA (Extended) case 0xB1: ILLEGAL(); break; // ILLEGAL
case 0xB2: ILLEGAL(); break; // SBCA (Extended) case 0xB2: JPB(5); break; // JPB 5
case 0xB3: ILLEGAL(); break; // SUBD (Extended) case 0xB3: ILLEGAL(); break; // ILLEGAL
case 0xB4: CALL(5); break; // CALL case 0xB4: CALL(5); break; // CALL
case 0xB5: OP_IMP(CM1); break; // COM F1 case 0xB5: OP_IMP(CM1); break; // COM F1
case 0xB6: ILLEGAL(); break; // LDA (Extended) case 0xB6: JP_COND(FlagF0); break; // JP F0
case 0xB7: ILLEGAL(); break; // STA (Extended) case 0xB7: ILLEGAL(); break; // ILLEGAL
case 0xB8: ILLEGAL(); break; // EORA (Extended) case 0xB8: ILLEGAL(); break; // ILLEGAL
case 0xB9: ILLEGAL(); break; // ADCA (Extended) case 0xB9: ILLEGAL(); break; // ILLEGAL
case 0xBA: ILLEGAL(); break; // ORA (Extended) case 0xBA: ILLEGAL(); break; // ILLEGAL
case 0xBB: ILLEGAL(); break; // ADDA (Extended) case 0xBB: ILLEGAL(); break; // ILLEGAL
case 0xBC: ILLEGAL(); break; // CMPX (Extended) case 0xBC: ILLEGAL(); break; // ILLEGAL
case 0xBD: ILLEGAL(); break; // JSR (Extended) case 0xBD: ILLEGAL(); break; // ILLEGAL
case 0xBE: ILLEGAL(); break; // LDX (Extended) case 0xBE: ILLEGAL(); break; // ILLEGAL
case 0xBF: ILLEGAL(); break; // STX (Extended) case 0xBF: ILLEGAL(); break; // ILLEGAL
case 0xC0: ILLEGAL(); break; // SUBB (Immediate) case 0xC0: ILLEGAL(); break; // ILLEGAL
case 0xC1: ILLEGAL(); break; // CMPB (Immediate) case 0xC1: ILLEGAL(); break; // ILLEGAL
case 0xC2: ILLEGAL(); break; // SBCB (Immediate) case 0xC2: ILLEGAL(); break; // ILLEGAL
case 0xC3: ILLEGAL(); break; // ADDD (Immediate) case 0xC3: ILLEGAL(); break; // ILLEGAL
case 0xC4: ILLEGAL(); break; // ANDB (Immediate) case 0xC4: JP_2k(6); break; // JP 2K 6
case 0xC5: ILLEGAL(); break; // BITB (Immediate) case 0xC5: OP_IMP(SEL_RB0); break; // SEL RB 0
case 0xC6: ILLEGAL(); break; // LDB (Immediate) case 0xC6: JP_COND(Regs[A] == 0); break; // JP (A == 0)
case 0xC7: ILLEGAL(); break; // ILLEGAL case 0xC7: ILLEGAL(); break; // ILLEGAL
case 0xC8: OP_R_IMP(DEC8, R0); break; // DEC R0 case 0xC8: OP_R_IMP(DEC8, R0); break; // DEC R0
case 0xC9: OP_R_IMP(DEC8, R1); break; // DEC R1 case 0xC9: OP_R_IMP(DEC8, R1); break; // DEC R1
@ -233,12 +233,12 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0xCF: OP_R_IMP(DEC8, R7); break; // DEC R7 case 0xCF: OP_R_IMP(DEC8, R7); break; // DEC R7
case 0xD0: OP_A_R(XOR8RAM, R0); break; // XOR A,@R0 case 0xD0: OP_A_R(XOR8RAM, R0); break; // XOR A,@R0
case 0xD1: OP_A_R(XOR8RAM, R1); break; // XOR A,@R1 case 0xD1: OP_A_R(XOR8RAM, R1); break; // XOR A,@R1
case 0xD2: ILLEGAL(); break; // ILLEGAL case 0xD2: JPB(6); break; // JPB 6
case 0xD3: OP_A_DIR(XOR8); break; // XOR A,# case 0xD3: OP_A_DIR(XOR8); break; // XOR A,#
case 0xD4: CALL(6); break; // CALL case 0xD4: CALL(6); break; // CALL
case 0xD5: ILLEGAL(); break; // BITB (Direct) case 0xD5: OP_IMP(SEL_RB1); break; // SEL RB 1
case 0xD6: ILLEGAL(); break; // LDB (Direct) case 0xD6: ILLEGAL(); break; // ILLEGAL
case 0xD7: ILLEGAL(); break; // STB (Direct) case 0xD7: ILLEGAL(); break; // ILLEGAL
case 0xD8: OP_A_R(XOR8, R0); break; // XOR A,R0 case 0xD8: OP_A_R(XOR8, R0); break; // XOR A,R0
case 0xD9: OP_A_R(XOR8, R1); break; // XOR A,R1 case 0xD9: OP_A_R(XOR8, R1); break; // XOR A,R1
case 0xDA: OP_A_R(XOR8, R2); break; // XOR A,R2 case 0xDA: OP_A_R(XOR8, R2); break; // XOR A,R2
@ -247,38 +247,38 @@ namespace BizHawk.Emulation.Common.Components.I8048
case 0xDD: OP_A_R(XOR8, R5); break; // XOR A,R5 case 0xDD: OP_A_R(XOR8, R5); break; // XOR A,R5
case 0xDE: OP_A_R(XOR8, R6); break; // XOR A,R6 case 0xDE: OP_A_R(XOR8, R6); break; // XOR A,R6
case 0xDF: OP_A_R(XOR8, R7); break; // XOR A,R7 case 0xDF: OP_A_R(XOR8, R7); break; // XOR A,R7
case 0xE0: ILLEGAL(); break; // SUBB (Indexed) case 0xE0: ILLEGAL(); break; // ILLEGAL
case 0xE1: ILLEGAL(); break; // CMPB (Indexed) case 0xE1: ILLEGAL(); break; // ILLEGAL
case 0xE2: ILLEGAL(); break; // SBCB (Indexed) case 0xE2: ILLEGAL(); break; // ILLEGAL
case 0xE3: ILLEGAL(); break; // ADDD (Indexed) case 0xE3: ILLEGAL(); break; // ILLEGAL
case 0xE4: ILLEGAL(); break; // ANDB (Indexed) case 0xE4: JP_2k(7); break; // JP 2K 7
case 0xE5: ILLEGAL(); break; // BITB (Indexed) case 0xE5: OP_IMP(SEL_MB0); break; // SEL MB 0
case 0xE6: ILLEGAL(); break; // LDB (Indexed) case 0xE6: JP_COND(!FlagC); break; // JP NC
case 0xE7: OP_IMP(ROL); break; // ROL case 0xE7: OP_IMP(ROL); break; // ROL
case 0xE8: ILLEGAL(); break; // EORB (Indexed) case 0xE8: DJNZ(R0); break; // DJNZ R0
case 0xE9: ILLEGAL(); break; // ADCB (Indexed) case 0xE9: DJNZ(R1); break; // DJNZ R1
case 0xEA: ILLEGAL(); break; // ORB (Indexed) case 0xEA: DJNZ(R2); break; // DJNZ R2
case 0xEB: ILLEGAL(); break; // ADDB (Indexed) case 0xEB: DJNZ(R3); break; // DJNZ R3
case 0xEC: ILLEGAL(); break; // LDD (Indexed) case 0xEC: DJNZ(R4); break; // DJNZ R4
case 0xED: ILLEGAL(); break; // STD (Indexed) case 0xED: DJNZ(R5); break; // DJNZ R5
case 0xEE: ILLEGAL(); break; // LDU (Indexed) case 0xEE: DJNZ(R6); break; // DJNZ R6
case 0xEF: ILLEGAL(); break; // STU (Indexed) case 0xEF: DJNZ(R7); break; // DJNZ R7
case 0xF0: ILLEGAL(); break; // SUBB (Extended) case 0xF0: ILLEGAL(); break; // ILLEGAL
case 0xF1: ILLEGAL(); break; // CMPB (Extended) case 0xF1: ILLEGAL(); break; // ILLEGAL
case 0xF2: ILLEGAL(); break; // SBCB (Extended) case 0xF2: JPB(7); break; // JPB 7
case 0xF3: ILLEGAL(); break; // ADDD (Extended) case 0xF3: ILLEGAL(); break; // ILLEGAL
case 0xF4: CALL(7); break; // CALL case 0xF4: CALL(7); break; // CALL
case 0xF5: ILLEGAL(); break; // BITB (Extended) case 0xF5: OP_IMP(SEL_MB1); break; // SEL MB 1
case 0xF6: ILLEGAL(); break; // LDB (Extended) case 0xF6: JP_COND(FlagC); break; // JP C
case 0xF7: OP_IMP(RLC); break; // RLC case 0xF7: OP_IMP(RLC); break; // RLC
case 0xF8: ILLEGAL(); break; // EORB (Extended) case 0xF8: ILLEGAL(); break; // ILLEGAL
case 0xF9: ILLEGAL(); break; // ADCB (Extended) case 0xF9: ILLEGAL(); break; // ILLEGAL
case 0xFA: ILLEGAL(); break; // ORB (Extended) case 0xFA: ILLEGAL(); break; // ILLEGAL
case 0xFB: ILLEGAL(); break; // ADDB (Extended) case 0xFB: ILLEGAL(); break; // ILLEGAL
case 0xFC: ILLEGAL(); break; // LDD (Extended) case 0xFC: ILLEGAL(); break; // ILLEGAL
case 0xFD: ILLEGAL(); break; // STD (Extended) case 0xFD: ILLEGAL(); break; // ILLEGAL
case 0xFE: ILLEGAL(); break; // LDU (Extended) case 0xFE: ILLEGAL(); break; // ILLEGAL
case 0xFF: ILLEGAL(); break; // STU (Extended) case 0xFF: ILLEGAL(); break; // ILLEGAL
} }
} }
} }

45
BizHawk.Emulation.Cores/CPUs/Intel8048/I8048.cs
View File

@ -67,6 +67,16 @@ namespace BizHawk.Emulation.Common.Components.I8048
public const ushort CMP16 = 56; public const ushort CMP16 = 56;
public const ushort CMP16D = 57; public const ushort CMP16D = 57;
public const ushort CLR_E = 63; public const ushort CLR_E = 63;
public const ushort CLK_OUT = 64;
public const ushort IN = 65;
public const ushort OUT = 66;
public const ushort XCH = 67;
public const ushort XCH_RAM = 68;
public const ushort XCHD_RAM = 69;
public const ushort SEL_MB0 = 70;
public const ushort SEL_MB1 = 71;
public const ushort SEL_RB0 = 72;
public const ushort SEL_RB1 = 73;
public I8048() public I8048()
{ {
@ -91,12 +101,15 @@ namespace BizHawk.Emulation.Common.Components.I8048
} }
// Memory Access // Memory Access
public Func<ushort, byte> ReadMemory; public Func<ushort, byte> ReadMemory;
public Action<ushort, byte> WriteMemory; public Action<ushort, byte> WriteMemory;
public Func<ushort, byte> PeekMemory; public Func<ushort, byte> PeekMemory;
public Func<ushort, byte> DummyReadMemory; public Func<ushort, byte> DummyReadMemory;
// Port Access
public Func<ushort, byte> ReadPort;
public Action<ushort, byte> WritePort;
//this only calls when the first byte of an instruction is fetched. //this only calls when the first byte of an instruction is fetched.
public Action<ushort> OnExecFetch; public Action<ushort> OnExecFetch;
@ -250,6 +263,36 @@ namespace BizHawk.Emulation.Common.Components.I8048
break; break;
case BIT: case BIT:
BIT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]); BIT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
break;
case CLK_OUT:
break;
case IN:
break;
case OUT:
break;
case XCH:
break;
case XCH_RAM:
break;
case XCHD_RAM:
break;
case SEL_MB0:
break;
case SEL_MB1:
break;
case SEL_RB0:
break;
case SEL_RB1:
break; break;
} }

105
BizHawk.Emulation.Cores/CPUs/Intel8048/OP_Tables.cs
View File

@ -109,5 +109,110 @@ namespace BizHawk.Emulation.Common.Components.I8048
IRQS = 9; IRQS = 9;
} }
public void DJNZ(ushort reg)
{
if ((Regs[reg] - 1) == 0)
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
else
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
IRQS = 9;
}
public void JPB(ushort Tebit)
{
if (Regs[A].Bit(Tebit))
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
else
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
IRQS = 9;
}
public void JP_COND(bool cond)
{
if (cond)
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
else
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
}
IRQS = 9;
}
public void JP_2k(ushort high_addr)
{
PopulateCURINSTR(IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE,
IDLE);
IRQS = 9;
}
} }
} }

10
BizHawk.Emulation.Cores/Consoles/Magnavox/Odyssey2/MemoryMap.cs
View File

@ -55,5 +55,15 @@ namespace BizHawk.Emulation.Cores.Nintendo.O2Hawk
return mapper.PeekMemory(addr); return mapper.PeekMemory(addr);
} }
} }
public byte ReadPort(ushort addr)
{
return 0;
}
public void WritePort(ushort addr, byte value)
{
}
} }
} }

2
BizHawk.Emulation.Cores/Consoles/Magnavox/Odyssey2/O2Hawk.cs
View File

@ -57,6 +57,8 @@ namespace BizHawk.Emulation.Cores.Nintendo.O2Hawk
WriteMemory = WriteMemory, WriteMemory = WriteMemory,
PeekMemory = PeekMemory, PeekMemory = PeekMemory,
DummyReadMemory = ReadMemory, DummyReadMemory = ReadMemory,
ReadPort = ReadPort,
WritePort = WritePort,
OnExecFetch = ExecFetch, OnExecFetch = ExecFetch,
}; };