diff --git a/BizHawk.Emulation/BizHawk.Emulation.csproj b/BizHawk.Emulation/BizHawk.Emulation.csproj
index 9d21383aa5..6386d1f9a1 100644
--- a/BizHawk.Emulation/BizHawk.Emulation.csproj
+++ b/BizHawk.Emulation/BizHawk.Emulation.csproj
@@ -239,6 +239,7 @@
     <Compile Include="CPUs\68000\OpcodeTable.cs" />
     <Compile Include="CPUs\68000\Tables.cs" />
     <Compile Include="CPUs\CP1610\CP1610.cs" />
+    <Compile Include="CPUs\CP1610\Disassembler.cs" />
     <Compile Include="CPUs\CP1610\Execute.cs" />
     <Compile Include="CPUs\HuC6280\Disassembler.cs" />
     <Compile Include="CPUs\HuC6280\Execute.cs" />
diff --git a/BizHawk.Emulation/CPUs/CP1610/Disassembler.cs b/BizHawk.Emulation/CPUs/CP1610/Disassembler.cs
index ee92884c75..9d9ff56c4a 100644
--- a/BizHawk.Emulation/CPUs/CP1610/Disassembler.cs
+++ b/BizHawk.Emulation/CPUs/CP1610/Disassembler.cs
@@ -10,7 +10,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
 		public string Disassemble(ushort pc, out int bytesToAdvance)
 		{
 			bytesToAdvance = 1;
-			int second, third, op1, op2, op3, temp1, temp2;
+			int second, third, op1, op2, op3;
 			string result = "";
 			int opcode = ReadMemory(RegisterPC) & 0x3FF;
 			switch (opcode)
@@ -25,48 +25,31 @@ namespace BizHawk.Emulation.CPUs.CP1610
 					return "DIS";
 				case 0x004:
 					// 0000:0000:0000:0100    0000:00rr:aaaa:aaff    0000:00aa:aaaa:aaaa
-					second = ReadMemory(++RegisterPC);
-					third = ReadMemory(++RegisterPC);
+					second = ReadMemory((byte)(RegisterPC + 1));
+					third = ReadMemory((byte)(RegisterPC + 1));
 					// rr indicates the register into which to store the return address
 					op1 = (second >> 8) & 0x3;
 					// ff indicates how to affect the Interrupt (I) flag in the CP1610
 					op2 = second & 0x3;
 					// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
 					op3 = ((second << 8) & 0xFC00) | (third & 0x3FF);
-					temp1 = 0x4 ^ op1;
+					result = "J";
 					if (op1 != 0x3)
+						result += "SR";
+					switch (op2)
 					{
-						switch (op2)
-						{
-							case 0x0:
-								result = "JSR";
-								break;
-							case 0x1:
-								result = "JSRE";
-								break;
-							case 0x2:
-								result = "JSRD";
-								break;
-							case 0x3:
-								break;
-						}
-						result += " R" + temp1 + ",";
+						case 0x1:
+							result += "E";
+							break;
+						case 0x2:
+							result += "D";
+							break;
+						case 0x3:
+							// Unknown opcode.
+							break;
 					}
-					else
-						switch (op2)
-						{
-							case 0x0:
-								result = "J";
-								break;
-							case 0x1:
-								result = "JE";
-								break;
-							case 0x2:
-								result = "JD";
-								break;
-							case 0x3:
-								break;
-						}
+					if (op1 != 0x3)
+						result += " R" + (op1 + 4) + ",";
 					result += string.Format(" ${0:X4})", op3);
 					bytesToAdvance = 3;
 					return result;
diff --git a/BizHawk.Emulation/CPUs/CP1610/Execute.cs b/BizHawk.Emulation/CPUs/CP1610/Execute.cs
index 40f770261e..e47f6b6183 100644
--- a/BizHawk.Emulation/CPUs/CP1610/Execute.cs
+++ b/BizHawk.Emulation/CPUs/CP1610/Execute.cs
@@ -31,7 +31,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
 		public void Execute(int cycles)
 		{
 			byte target;
-			int op1, op2, temp, result;
+			int second, third, op1, op2, op3, temp, result;
             PendingCycles += cycles;
 			while (PendingCycles > 0)
 			{
@@ -53,7 +53,33 @@ namespace BizHawk.Emulation.CPUs.CP1610
 						PendingCycles -= 4; TotalExecutedCycles += 4;
 						break;
 					case 0x004: // J, JE, JD, JSR, JSRE, JSRD
-						throw new NotImplementedException();
+						// 0000:0000:0000:0100    0000:00rr:aaaa:aaff    0000:00aa:aaaa:aaaa
+						second = ReadMemory(RegisterPC++);
+						third = ReadMemory(RegisterPC++);
+						// rr indicates the register into which to store the return address
+						op1 = (second >> 8) & 0x3;
+						// ff indicates how to affect the Interrupt (I) flag in the CP1610
+						op2 = second & 0x3;
+						// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
+						op3 = ((second << 8) & 0xFC00) | (third & 0x3FF);
+						if (op1 != 0x3)
+							// Store the return address.
+							Register[op1 + 4] = (ushort)((RegisterPC + 1) & 0xFFFF);
+						switch (op2)
+						{
+							case 0x1:
+								FlagI = true;
+								break;
+							case 0x2:
+								FlagI = false;
+								break;
+							case 0x3:
+								// Unknown opcode.
+								throw new ArgumentException();
+						}
+						RegisterPC = (ushort)op3;
+						PendingCycles -= 12; TotalExecutedCycles += 12;
+						break;
 					case 0x005: // TCI
 						throw new NotImplementedException();
 					case 0x006: // CLRC