Fix VRAM end of line testROM and a desync in GB Wario Land II

This commit is contained in:
TiKevin83 2020-05-21 11:41:37 -04:00
parent 7bda234fe1
commit 9e33f5f6db
4 changed files with 18 additions and 1 deletions

View File

@ -655,6 +655,11 @@ unsigned Memory::nontrivial_read(unsigned const p, unsigned long const cc) {
if (!lcd_.vramReadable(cc))
return 0xFF;
if (lcd_.vramExactlyReadable(cc))
if (p < 0x9000) {
return 0x00;
}
return cart_.vrambankptr()[p];
}

View File

@ -290,6 +290,15 @@ bool LCD::vramReadable(unsigned long const cc) {
|| cc + 2 >= m0TimeOfCurrentLine(cc);
}
bool LCD::vramExactlyReadable(unsigned long const cc) {
bool currentVramExactlyReadable = (cc + 2 == m0TimeOfCurrentLine(cc));
bool vramAlreadyExactlyRead = vramHasBeenExactlyRead;
if (currentVramExactlyReadable) {
vramHasBeenExactlyRead = true;
}
return !vramAlreadyExactlyRead && currentVramExactlyReadable;
}
bool LCD::vramWritable(unsigned long const cc) {
if (cc >= eventTimes_.nextEventTime())
update(cc);
@ -848,4 +857,5 @@ SYNCFUNC(LCD)
SSS(lycIrq_);
SSS(nextM0Time_);
NSS(statReg_);
NSS(vramHasBeenExactlyRead);
}

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@ -102,6 +102,7 @@ public:
void resetCc(unsigned long oldCC, unsigned long newCc);
void speedChange(unsigned long cycleCounter);
bool vramReadable(unsigned long cycleCounter);
bool vramExactlyReadable(unsigned long cycleCounter);
bool vramWritable(unsigned long cycleCounter);
bool oamReadable(unsigned long cycleCounter);
bool oamWritable(unsigned long cycleCounter);
@ -228,6 +229,7 @@ public:
LycIrq lycIrq_;
NextM0Time nextM0Time_;
unsigned char statReg_;
bool vramHasBeenExactlyRead = false;
static void setDmgPalette(unsigned long palette[],
unsigned long const dmgColors[],
@ -235,13 +237,13 @@ public:
unsigned long gbcToRgb32(const unsigned bgr15);
void doCgbColorChange(unsigned char *const pdata, unsigned long *const palette, unsigned index, const unsigned data);
void refreshPalettes();
void setDBuffer();
void doMode2IrqEvent();
void event();
unsigned long m0TimeOfCurrentLine(unsigned long cc);
bool cgbpAccessible(unsigned long cycleCounter);
bool lycRegChangeStatTriggerBlockedByM0OrM1Irq(unsigned data, unsigned long cc);
bool lycRegChangeTriggersStatIrq(unsigned old, unsigned data, unsigned long cc);
bool statChangeTriggersM0LycOrM1StatIrqCgb(unsigned old, unsigned data, bool lycperiod, unsigned long cc);

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