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Lua - Implement onmemoryread() and onmemorywrite() to the remaining C# cores except Genesis

This commit is contained in:
adelikat 2012-10-13 20:15:28 +00:00
parent d2e6d50360
commit 98ae0abe28
5 changed files with 179 additions and 116 deletions
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14
BizHawk.Emulation/Consoles/Atari/2600/Atari2600.Core.cs
View File

@ -94,12 +94,24 @@ namespace BizHawk
public byte ReadMemory(ushort addr)
{
return mapper.ReadMemory((ushort)(addr&0x1FFF));
byte temp = mapper.ReadMemory((ushort)(addr&0x1FFF));
if (CoreInputComm.MemoryCallbackSystem.ReadCallback != null)
{
CoreInputComm.MemoryCallbackSystem.TriggerRead(addr);
}
return temp;
}
public void WriteMemory(ushort addr, byte value)
{
mapper.WriteMemory((ushort)(addr & 0x1FFF), value);
if (CoreInputComm.MemoryCallbackSystem.WriteCallback != null)
{
CoreInputComm.MemoryCallbackSystem.WriteCallback();
}
}
public void HardReset()

10
BizHawk.Emulation/Consoles/Calculator/TI83.cs
View File

@ -39,6 +39,11 @@ namespace BizHawk.Emulation.Consoles.Calculator
ret = rom[romPage * 0x4000 + addr - 0x4000]; //other rom page
else ret = ram[addr - 0x8000];
if (CoreInputComm.MemoryCallbackSystem.ReadCallback != null)
{
CoreInputComm.MemoryCallbackSystem.TriggerRead(addr);
}
return ret;
}
@ -49,6 +54,11 @@ namespace BizHawk.Emulation.Consoles.Calculator
else if (addr < 0x8000)
return; //other rom page
else ram[addr - 0x8000] = value;
if (CoreInputComm.MemoryCallbackSystem.WriteCallback != null)
{
CoreInputComm.MemoryCallbackSystem.WriteCallback();
}
}
public void WriteHardware(ushort addr, byte value)

25
BizHawk.Emulation/Consoles/Coleco/ColecoVision.Core.cs
View File

@ -18,24 +18,34 @@ namespace BizHawk.Emulation.Consoles.Coleco
public byte ReadMemory(ushort addr)
{
byte ret;
if (addr < 0x2000)
{
return rom[addr];
ret = rom[addr];
}
else if (addr >= 0x2000 && addr < 0x6000)
{
return expansion[addr];
ret = expansion[addr];
}
else if (addr >= 0x6000 && addr < 0x8000)
{
return ram[addr & 1023];
ret = ram[addr & 1023];
}
else if (addr >= 0x8000)
{
return cartridgeslot[addr];
ret = cartridgeslot[addr];
}
else
{
ret = 0xFF;
}
else return 0xFF;
if (CoreInputComm.MemoryCallbackSystem.ReadCallback != null)
{
CoreInputComm.MemoryCallbackSystem.TriggerRead(addr);
}
return ret;
}
public void WriteMemory(ushort addr, byte value)
@ -44,6 +54,11 @@ namespace BizHawk.Emulation.Consoles.Coleco
{
ram[addr] = value;
}
if (CoreInputComm.MemoryCallbackSystem.WriteCallback != null)
{
CoreInputComm.MemoryCallbackSystem.WriteCallback();
}
}
public void HardReset()

13
BizHawk.Emulation/Consoles/Intellivision/MemoryMap.cs
View File

@ -21,6 +21,7 @@ namespace BizHawk.Emulation.Consoles.Intellivision
ushort? stic = Stic.ReadSTIC(addr);
ushort? psg = Psg.ReadPSG(addr);
ushort? core = null;
switch (addr & 0xF000)
{
case 0x0000:
@ -113,6 +114,12 @@ namespace BizHawk.Emulation.Consoles.Intellivision
// Write-only Graphics RAM.
break;
}
if (CoreInputComm.MemoryCallbackSystem.ReadCallback != null)
{
CoreInputComm.MemoryCallbackSystem.TriggerRead(addr);
}
if (cart != null)
return (ushort)cart;
else if (stic != null)
@ -278,6 +285,12 @@ namespace BizHawk.Emulation.Consoles.Intellivision
return true;
}
}
if (CoreInputComm.MemoryCallbackSystem.WriteCallback != null)
{
CoreInputComm.MemoryCallbackSystem.WriteCallback();
}
return (cart || stic || psg);
}
}

233
BizHawk.Emulation/Consoles/Sega/SMS/MemoryMap.Sega.cs
View File

@ -1,126 +1,139 @@
namespace BizHawk.Emulation.Consoles.Sega
{
public partial class SMS
{
// The Sega memory mapper layout looks like so:
// $0000-$03FF - ROM (unpaged)
// $0400-$3FFF - ROM mapper slot 0
// $4000-$7FFF - ROM mapper slot 1
// $8000-$BFFF - ROM mapper slot 2 - OR - SaveRAM
// $C000-$DFFF - System RAM
// $E000-$FFFF - System RAM (mirror)
// $FFFC - SaveRAM mapper control
// $FFFD - Mapper slot 0 control
// $FFFE - Mapper slot 1 control
// $FFFF - Mapper slot 2 control
public partial class SMS
{
// The Sega memory mapper layout looks like so:
// $0000-$03FF - ROM (unpaged)
// $0400-$3FFF - ROM mapper slot 0
// $4000-$7FFF - ROM mapper slot 1
// $8000-$BFFF - ROM mapper slot 2 - OR - SaveRAM
// $C000-$DFFF - System RAM
// $E000-$FFFF - System RAM (mirror)
// $FFFC - SaveRAM mapper control
// $FFFD - Mapper slot 0 control
// $FFFE - Mapper slot 1 control
// $FFFF - Mapper slot 2 control
const ushort BankSizeMask = 0x3FFF;
const ushort RamSizeMask = 0x1FFF;
const ushort BankSizeMask = 0x3FFF;
const ushort RamSizeMask = 0x1FFF;
byte ReadMemory(ushort address)
{
if (address < 1024)
return RomData[address];
if (address < BankSize)
return RomData[(RomBank0*BankSize) + address];
if (address < BankSize * 2)
return RomData[(RomBank1*BankSize) + (address & BankSizeMask)];
if (address < BankSize * 3)
{
switch (SaveRamBank)
{
case 0: return RomData[(RomBank2*BankSize) + (address & BankSizeMask)];
case 1: return SaveRAM[address & BankSizeMask];
case 2: return SaveRAM[BankSize + (address & BankSizeMask)];
}
}
return SystemRam[address & RamSizeMask];
}
byte ReadMemory(ushort address)
{
byte ret;
if (address < 1024)
ret = RomData[address];
if (address < BankSize)
ret = RomData[(RomBank0 * BankSize) + address];
if (address < BankSize * 2)
ret = RomData[(RomBank1 * BankSize) + (address & BankSizeMask)];
if (address < BankSize * 3)
{
switch (SaveRamBank)
{
case 0: ret = RomData[(RomBank2 * BankSize) + (address & BankSizeMask)]; break;
case 1: ret = SaveRAM[address & BankSizeMask]; break;
case 2: ret = SaveRAM[BankSize + (address & BankSizeMask)]; break;
}
}
ret = SystemRam[address & RamSizeMask];
void WriteMemory(ushort address, byte value)
{
if (address >= 0xC000)
SystemRam[address & RamSizeMask] = value;
if (CoreInputComm.MemoryCallbackSystem.ReadCallback != null)
{
CoreInputComm.MemoryCallbackSystem.TriggerRead(address);
}
else if (address >= 0x8000)
{
SaveRamModified = true;
switch (SaveRamBank)
{
case 1: SaveRAM[address & BankSizeMask] = value; return;
case 2: SaveRAM[BankSize + (address & BankSizeMask)] = value; return;
}
}
return ret;
}
if (address >= 0xFFFC)
{
if (address == 0xFFFC)
{
if ((value & 8) != 0)
SaveRamBank = (byte)((value & 4) == 0 ? 1 : 2); // SaveRAM selected
else
SaveRamBank = 0; // ROM bank selected
}
else if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks);
return;
}
}
void WriteMemory(ushort address, byte value)
{
if (address >= 0xC000)
SystemRam[address & RamSizeMask] = value;
void InitSegaMapper()
{
Cpu.ReadMemory = ReadMemory;
Cpu.WriteMemory = WriteMemory;
WriteMemory(0xFFFC, 0);
WriteMemory(0xFFFD, 0);
WriteMemory(0xFFFE, 1);
WriteMemory(0xFFFF, 2);
}
else if (address >= 0x8000)
{
SaveRamModified = true;
switch (SaveRamBank)
{
case 1: SaveRAM[address & BankSizeMask] = value; return;
case 2: SaveRAM[BankSize + (address & BankSizeMask)] = value; return;
}
}
// Mapper when loading a BIOS as a ROM
if (address >= 0xFFFC)
{
if (address == 0xFFFC)
{
if ((value & 8) != 0)
SaveRamBank = (byte)((value & 4) == 0 ? 1 : 2); // SaveRAM selected
else
SaveRamBank = 0; // ROM bank selected
}
else if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks);
return;
}
bool BiosMapped { get { return (Port3E & 0x08) == 0; } }
if (CoreInputComm.MemoryCallbackSystem.WriteCallback != null)
{
CoreInputComm.MemoryCallbackSystem.WriteCallback();
}
}
byte ReadMemoryBIOS(ushort address)
{
if (BiosMapped == false && address < BankSize * 3)
return 0x00;
void InitSegaMapper()
{
Cpu.ReadMemory = ReadMemory;
Cpu.WriteMemory = WriteMemory;
WriteMemory(0xFFFC, 0);
WriteMemory(0xFFFD, 0);
WriteMemory(0xFFFE, 1);
WriteMemory(0xFFFF, 2);
}
if (address < 1024)
return RomData[address];
if (address < BankSize)
return RomData[(RomBank0 * BankSize) + address];
if (address < BankSize * 2)
return RomData[(RomBank1 * BankSize) + (address & BankSizeMask)];
if (address < BankSize * 3)
return RomData[(RomBank2 * BankSize) + (address & BankSizeMask)];
return SystemRam[address & RamSizeMask];
}
// Mapper when loading a BIOS as a ROM
void WriteMemoryBIOS(ushort address, byte value)
{
if (address >= 0xC000)
SystemRam[address & RamSizeMask] = value;
bool BiosMapped { get { return (Port3E & 0x08) == 0; } }
if (address >= 0xFFFC)
{
if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks);
return;
}
}
byte ReadMemoryBIOS(ushort address)
{
if (BiosMapped == false && address < BankSize * 3)
return 0x00;
void InitBiosMapper()
{
Cpu.ReadMemory = ReadMemoryBIOS;
Cpu.WriteMemory = WriteMemoryBIOS;
WriteMemory(0xFFFC, 0);
WriteMemory(0xFFFD, 0);
WriteMemory(0xFFFE, 1);
WriteMemory(0xFFFF, 2);
}
}
if (address < 1024)
return RomData[address];
if (address < BankSize)
return RomData[(RomBank0 * BankSize) + address];
if (address < BankSize * 2)
return RomData[(RomBank1 * BankSize) + (address & BankSizeMask)];
if (address < BankSize * 3)
return RomData[(RomBank2 * BankSize) + (address & BankSizeMask)];
return SystemRam[address & RamSizeMask];
}
void WriteMemoryBIOS(ushort address, byte value)
{
if (address >= 0xC000)
SystemRam[address & RamSizeMask] = value;
if (address >= 0xFFFC)
{
if (address == 0xFFFD) RomBank0 = (byte)(value % RomBanks);
else if (address == 0xFFFE) RomBank1 = (byte)(value % RomBanks);
else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks);
return;
}
}
void InitBiosMapper()
{
Cpu.ReadMemory = ReadMemoryBIOS;
Cpu.WriteMemory = WriteMemoryBIOS;
WriteMemory(0xFFFC, 0);
WriteMemory(0xFFFD, 0);
WriteMemory(0xFFFE, 1);
WriteMemory(0xFFFF, 2);
}
}
}