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gpgx waterbox: move bg_pattern_cache to alloc_invisible

This commit is contained in:
nattthebear 2016-03-23 21:10:18 -04:00
parent 06f9d78452
commit 92e708d011
6 changed files with 58 additions and 31 deletions
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1
BizHawk.Emulation.Cores/Consoles/Sega/gpgx/GPGX.IStatable.cs
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@ -40,6 +40,7 @@ namespace BizHawk.Emulation.Cores.Consoles.Sega.gpgx
Core.gpgx_set_input_callback(InputCallback); Core.gpgx_set_input_callback(InputCallback);
RefreshMemCallbacks(); RefreshMemCallbacks();
Core.gpgx_set_cdd_callback(cd_callback_handle); Core.gpgx_set_cdd_callback(cd_callback_handle);
Core.gpgx_invalidate_pattern_cache();
UpdateVideo(); UpdateVideo();
} }

11
BizHawk.Emulation.Cores/Consoles/Sega/gpgx/LibGPGX.cs
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@ -304,9 +304,18 @@ namespace BizHawk.Emulation.Cores.Consoles.Sega.gpgx
[BizImport(CallingConvention.Cdecl)] [BizImport(CallingConvention.Cdecl)]
public abstract void gpgx_poke_vram(int addr, byte value); public abstract void gpgx_poke_vram(int addr, byte value);
[BizImport(CallingConvention.Cdecl)] /// <summary>
/// regenerate whatever portions of the bg pattern cache are currently dirty.
/// </summary>
[BizImport(CallingConvention.Cdecl)] // the core will handle this itself; you only need to call this when using the cache for your own purposes
public abstract void gpgx_flush_vram(); public abstract void gpgx_flush_vram();
/// <summary>
/// mark the bg pattern cache as dirty
/// </summary>
[BizImport(CallingConvention.Cdecl)]
public abstract void gpgx_invalidate_pattern_cache();
[StructLayout(LayoutKind.Sequential)] [StructLayout(LayoutKind.Sequential)]
public struct RegisterInfo public struct RegisterInfo
{ {

8
waterbox/gpgx/cinterface/cinterface.c
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@ -211,7 +211,7 @@ typedef struct
} vdpview_t; } vdpview_t;
extern uint8 bg_pattern_cache[]; extern uint8 *bg_pattern_cache;
extern uint32 pixel[]; extern uint32 pixel[];
GPGX_EX void gpgx_get_vdp_view(vdpview_t *view) GPGX_EX void gpgx_get_vdp_view(vdpview_t *view)
@ -509,6 +509,7 @@ GPGX_EX int gpgx_init(const char *feromextension, ECL_ENTRY int (*feload_archive
bitmap.pitch = 1024 * 4; bitmap.pitch = 1024 * 4;
bitmap.data = alloc_invisible(2 * 1024 * 1024); bitmap.data = alloc_invisible(2 * 1024 * 1024);
tempsram = alloc_invisible(24 * 1024); tempsram = alloc_invisible(24 * 1024);
bg_pattern_cache = alloc_invisible(0x80000);
ext.md_cart.rom = alloc_sealed(32 * 1024 * 1024); ext.md_cart.rom = alloc_sealed(32 * 1024 * 1024);
scd.bootrom = malloc(0x20000); // FIXME: this should be sealed, but that crashes. huh? scd.bootrom = malloc(0x20000); // FIXME: this should be sealed, but that crashes. huh?
@ -617,6 +618,11 @@ GPGX_EX void gpgx_set_draw_mask(int mask)
color_update_m5(0x00, *(uint16 *)&cram[border << 1]); color_update_m5(0x00, *(uint16 *)&cram[border << 1]);
} }
GPGX_EX void gpgx_invalidate_pattern_cache(void)
{
vdp_invalidate_full_cache();
}
typedef struct typedef struct
{ {
unsigned int value; unsigned int value;

66
waterbox/gpgx/core/vdp_ctrl.c
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@ -147,7 +147,7 @@ static void (*set_irq_line)(unsigned int level);
static void (*set_irq_line_delay)(unsigned int level); static void (*set_irq_line_delay)(unsigned int level);
/* Vertical counter overflow values (see hvc.h) */ /* Vertical counter overflow values (see hvc.h) */
static const uint16 vc_table[4][2] = static const uint16 vc_table[4][2] =
{ {
/* NTSC, PAL */ /* NTSC, PAL */
{0xDA , 0xF2}, /* Mode 4 (192 lines) */ {0xDA , 0xF2}, /* Mode 4 (192 lines) */
@ -203,6 +203,16 @@ void flush_vram_cache(void)
} }
} }
void vdp_invalidate_full_cache(void)
{
bg_list_index = 0x800;
for (int i=0;i<bg_list_index;i++)
{
bg_name_list[i] = i;
bg_name_dirty[i] = 0xFF;
}
}
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/
/* Init, reset, context functions */ /* Init, reset, context functions */
/*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/
@ -470,7 +480,7 @@ int vdp_context_load(uint8 *state, uint8 version)
{ {
if (system_hw > SYSTEM_SG) if (system_hw > SYSTEM_SG)
{ {
for (i=0;i<0x10;i++) for (i=0;i<0x10;i++)
{ {
pending = 1; pending = 1;
addr_latch = temp_reg[i]; addr_latch = temp_reg[i];
@ -479,7 +489,7 @@ int vdp_context_load(uint8 *state, uint8 version)
} }
else else
{ {
for (i=0;i<0x08;i++) for (i=0;i<0x08;i++)
{ {
pending = 1; pending = 1;
addr_latch = temp_reg[i]; addr_latch = temp_reg[i];
@ -489,7 +499,7 @@ int vdp_context_load(uint8 *state, uint8 version)
} }
else else
{ {
for (i=0;i<0x20;i++) for (i=0;i<0x20;i++)
{ {
vdp_reg_w(i, temp_reg[i], 0); vdp_reg_w(i, temp_reg[i], 0);
} }
@ -560,7 +570,7 @@ int vdp_context_load(uint8 *state, uint8 version)
} }
/* invalidate cache */ /* invalidate cache */
for (i=0;i<bg_list_index;i++) for (i=0;i<bg_list_index;i++)
{ {
bg_name_list[i]=i; bg_name_list[i]=i;
bg_name_dirty[i]=0xFF; bg_name_dirty[i]=0xFF;
@ -578,7 +588,7 @@ void vdp_dma_update(unsigned int cycles)
{ {
int dma_cycles, dma_bytes; int dma_cycles, dma_bytes;
/* DMA transfer rate (bytes per line) /* DMA transfer rate (bytes per line)
According to the manual, here's a table that describes the transfer According to the manual, here's a table that describes the transfer
rates of each of the three DMA types: rates of each of the three DMA types:
@ -825,20 +835,20 @@ void vdp_68k_ctrl_w(unsigned int data)
} }
} }
/* /*
FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch, Sol Deace) FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch, Sol Deace)
-------------------------------------------------------------------------- --------------------------------------------------------------------------
Each VRAM access is byte wide, so one VRAM write (word) need two slot access. Each VRAM access is byte wide, so one VRAM write (word) need two slot access.
NOTE: Invalid code 0x02 (register write) should not behave the same as VRAM NOTE: Invalid code 0x02 (register write) should not behave the same as VRAM
access, i.e data is ignored and only one access slot is used for each word, access, i.e data is ignored and only one access slot is used for each word,
BUT a few games ("Clue", "Microcosm") which accidentally corrupt code value BUT a few games ("Clue", "Microcosm") which accidentally corrupt code value
will have issues when emulating FIFO timings. They likely work fine on real will have issues when emulating FIFO timings. They likely work fine on real
hardware because of periodical 68k wait-states which have been observed and hardware because of periodical 68k wait-states which have been observed and
would naturaly add some delay between writes. Until those wait-states are would naturaly add some delay between writes. Until those wait-states are
accurately measured and emulated, delay is forced when invalid code value accurately measured and emulated, delay is forced when invalid code value
is being used. is being used.
*/ */
fifo_byte_access = ((code & 0x0F) <= 0x02); fifo_byte_access = ((code & 0x0F) <= 0x02);
} }
@ -1007,7 +1017,7 @@ void vdp_sms_ctrl_w(unsigned int data)
/* Check VDP mode changes */ /* Check VDP mode changes */
mode = (reg[0] & 0x06) | (reg[1] & 0x18); mode = (reg[0] & 0x06) | (reg[1] & 0x18);
prev ^= mode; prev ^= mode;
if (prev) if (prev)
{ {
/* Check for extended modes */ /* Check for extended modes */
@ -1204,7 +1214,7 @@ void vdp_tms_ctrl_w(unsigned int data)
/* Write VDP register */ /* Write VDP register */
vdp_reg_w(data, addr_latch, Z80.cycles); vdp_reg_w(data, addr_latch, Z80.cycles);
/* Check VDP mode changes */ /* Check VDP mode changes */
if (data < 2) if (data < 2)
{ {
@ -1485,7 +1495,7 @@ unsigned int vdp_hvc_r(unsigned int cycles)
/* return H-Counter in LSB & V-Counter in MSB */ /* return H-Counter in LSB & V-Counter in MSB */
data |= ((vc & 0xff) << 8); data |= ((vc & 0xff) << 8);
#ifdef LOGVDP #ifdef LOGVDP
error("[%d(%d)][%d(%d)] HVC read -> 0x%x (%x)\n", v_counter, (cycles/MCYCLES_PER_LINE-1)%lines_per_frame, cycles, cycles%MCYCLES_PER_LINE, data, m68k_get_reg(M68K_REG_PC)); error("[%d(%d)][%d(%d)] HVC read -> 0x%x (%x)\n", v_counter, (cycles/MCYCLES_PER_LINE-1)%lines_per_frame, cycles, cycles%MCYCLES_PER_LINE, data, m68k_get_reg(M68K_REG_PC));
#endif #endif
@ -1716,7 +1726,7 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
if ((r & 0x20) && vint_pending) if ((r & 0x20) && vint_pending)
{ {
/* Update IRQ status */ /* Update IRQ status */
if (d & 0x20) if (d & 0x20)
{ {
set_irq_line_delay(6); set_irq_line_delay(6);
} }
@ -1851,7 +1861,7 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
} }
/* Invalidate pattern cache */ /* Invalidate pattern cache */
for (i=0;i<bg_list_index;i++) for (i=0;i<bg_list_index;i++)
{ {
bg_name_list[i] = i; bg_name_list[i] = i;
bg_name_dirty[i] = 0xFF; bg_name_dirty[i] = 0xFF;
@ -1963,7 +1973,7 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
case 8: /* Horizontal Scroll (Mode 4 only) */ case 8: /* Horizontal Scroll (Mode 4 only) */
{ {
int line; int line;
/* Hscroll is latched at HCount 0xF3, HCount 0xF6 on MD */ /* Hscroll is latched at HCount 0xF3, HCount 0xF6 on MD */
/* Line starts at HCount 0xF4, HCount 0xF6 on MD */ /* Line starts at HCount 0xF4, HCount 0xF6 on MD */
if (system_hw < SYSTEM_MD) if (system_hw < SYSTEM_MD)
@ -2150,16 +2160,16 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
static void vdp_fifo_update(unsigned int cycles) static void vdp_fifo_update(unsigned int cycles)
{ {
int slots, count = 0; int slots, count = 0;
const int *fifo_timing; const int *fifo_timing;
const int fifo_cycles_h32[16+2] = const int fifo_cycles_h32[16+2] =
{ {
230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370, 230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370,
MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510 MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510
}; };
const int fifo_cycles_h40[18+2] = const int fifo_cycles_h40[18+2] =
{ {
352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380, 352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380,
MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820 MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820
@ -2474,7 +2484,7 @@ static void vdp_68k_data_w_m5(unsigned int data)
fifo_slots += (1 + fifo_byte_access); fifo_slots += (1 + fifo_byte_access);
} }
} }
/* Write data */ /* Write data */
vdp_bus_w(data); vdp_bus_w(data);
@ -2962,7 +2972,7 @@ static void vdp_z80_data_w_gg(unsigned int data)
{ {
/* Color index (0-31) */ /* Color index (0-31) */
int index = (addr >> 1) & 0x1F; int index = (addr >> 1) & 0x1F;
/* Write CRAM data */ /* Write CRAM data */
*p = data; *p = data;
@ -3053,7 +3063,7 @@ static void vdp_dma_68k_ext(unsigned int length)
} }
} }
/* Increment source address */ /* Increment source address */
source += 2; source += 2;
@ -3081,7 +3091,7 @@ static void vdp_dma_68k_ram(unsigned int length)
{ {
/* access Work-RAM by default */ /* access Work-RAM by default */
data = *(uint16 *)(work_ram + (source & 0xFFFF)); data = *(uint16 *)(work_ram + (source & 0xFFFF));
/* Increment source address */ /* Increment source address */
source += 2; source += 2;
@ -3115,7 +3125,7 @@ static void vdp_dma_68k_io(unsigned int length)
data = ((zstate ^ 3) ? *(uint16 *)(work_ram + (source & 0xFFFF)) : 0xFFFF); data = ((zstate ^ 3) ? *(uint16 *)(work_ram + (source & 0xFFFF)) : 0xFFFF);
} }
/* The I/O chip and work RAM try to drive the data bus which results /* The I/O chip and work RAM try to drive the data bus which results
in both values being combined in random ways when read. in both values being combined in random ways when read.
We return the I/O chip values which seem to have precedence, */ We return the I/O chip values which seem to have precedence, */
else if (source <= 0xA1001F) else if (source <= 0xA1001F)
@ -3153,7 +3163,7 @@ static void vdp_dma_copy(unsigned int length)
{ {
int name; int name;
uint8 data; uint8 data;
/* VRAM source address */ /* VRAM source address */
uint16 source = dma_src; uint16 source = dma_src;
@ -3258,7 +3268,7 @@ static void vdp_dma_fill(unsigned int length)
color_update_m5(0x00, data); color_update_m5(0x00, data);
} }
} }
/* Increment CRAM address */ /* Increment CRAM address */
addr += reg[15]; addr += reg[15];
} }
@ -3275,7 +3285,7 @@ static void vdp_dma_fill(unsigned int length)
{ {
/* Write VSRAM data */ /* Write VSRAM data */
*(uint16 *)&vsram[addr & 0x7E] = data; *(uint16 *)&vsram[addr & 0x7E] = data;
/* Increment VSRAM address */ /* Increment VSRAM address */
addr += reg[15]; addr += reg[15];
} }

1
waterbox/gpgx/core/vdp_ctrl.h
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@ -104,5 +104,6 @@ extern int vdp_68k_irq_ack(int int_level);
void write_vram_byte(int addr, uint8 val); void write_vram_byte(int addr, uint8 val);
void flush_vram_cache(void); void flush_vram_cache(void);
void vdp_invalidate_full_cache(void);
#endif /* _VDP_H_ */ #endif /* _VDP_H_ */

2
waterbox/gpgx/core/vdp_render.c
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@ -560,7 +560,7 @@ static const uint32 tms_palette[16] =
#endif #endif
/* Cached and flipped patterns */ /* Cached and flipped patterns */
uint8 bg_pattern_cache[0x80000]; uint8 *bg_pattern_cache;
/* Sprite pattern name offset look-up table (Mode 5) */ /* Sprite pattern name offset look-up table (Mode 5) */
static uint8 name_lut[0x400]; static uint8 name_lut[0x400];