From 8c12c5cbff17d32f82962ab597d2bc6acb08dba7 Mon Sep 17 00:00:00 2001 From: adelikat Date: Sat, 24 Jan 2015 20:57:37 +0000 Subject: [PATCH] do read/writes in the z80 core itself, refactor sms and ti83 to not use them on their end of the callback, fixes sms only having read/write callbacks on a few mappers --- BizHawk.Emulation.Cores/CPUs/Z80/Execute.cs | 2706 ++++++++--------- BizHawk.Emulation.Cores/CPUs/Z80/Z80A.cs | 20 + BizHawk.Emulation.Cores/Calculator/TI83.cs | 4 - .../Consoles/Sega/SMS/MemoryMap.ExtRam.cs | 3 - .../Consoles/Sega/SMS/MemoryMap.Sega.cs | 3 - 5 files changed, 1373 insertions(+), 1363 deletions(-) diff --git a/BizHawk.Emulation.Cores/CPUs/Z80/Execute.cs b/BizHawk.Emulation.Cores/CPUs/Z80/Execute.cs index ed36f2c9f5..f8ecd9fb71 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80/Execute.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80/Execute.cs @@ -56,17 +56,17 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x01: // LD BC, nn - RegBC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegBC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x02: // LD (BC), A - WriteMemory(RegBC.Word, RegAF.High); + WriteMemoryWrapper(RegBC.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x03: // INC BC @@ -82,7 +82,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x06: // LD B, n - RegBC.High = ReadMemory(RegPC.Word++); + RegBC.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x07: // RLCA @@ -105,7 +105,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x0A: // LD A, (BC) - RegAF.High = ReadMemory(RegBC.Word); + RegAF.High = ReadMemoryWrapper(RegBC.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0B: // DEC BC @@ -121,7 +121,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x0E: // LD C, n - RegBC.Low = ReadMemory(RegPC.Word++); + RegBC.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0F: // RRCA @@ -129,7 +129,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x10: // DJNZ d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (--RegBC.High != 0) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -141,11 +141,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x11: // LD DE, nn - RegDE.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegDE.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x12: // LD (DE), A - WriteMemory(RegDE.Word, RegAF.High); + WriteMemoryWrapper(RegDE.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x13: // INC DE @@ -161,7 +161,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x16: // LD D, n - RegDE.High = ReadMemory(RegPC.Word++); + RegDE.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x17: // RLA @@ -169,7 +169,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x18: // JR d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); RegPC.Word = (ushort)(RegPC.Word + TSB); totalExecutedCycles += 12; pendingCycles -= 12; break; @@ -185,7 +185,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x1A: // LD A, (DE) - RegAF.High = ReadMemory(RegDE.Word); + RegAF.High = ReadMemoryWrapper(RegDE.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1B: // DEC DE @@ -201,7 +201,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x1E: // LD E, n - RegDE.Low = ReadMemory(RegPC.Word++); + RegDE.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1F: // RRA @@ -209,7 +209,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x20: // JR NZ, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -221,13 +221,13 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x21: // LD HL, nn - RegHL.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegHL.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x22: // LD (nn), HL - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegHL.Low); - WriteMemory(TUS, RegHL.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegHL.Low); + WriteMemoryWrapper(TUS, RegHL.High); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x23: // INC HL @@ -243,7 +243,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x26: // LD H, n - RegHL.High = ReadMemory(RegPC.Word++); + RegHL.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x27: // DAA @@ -251,7 +251,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x28: // JR Z, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -274,8 +274,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x2A: // LD HL, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegHL.Low = ReadMemory(TUS++); RegHL.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegHL.Low = ReadMemoryWrapper(TUS++); RegHL.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x2B: // DEC HL @@ -291,7 +291,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x2E: // LD L, n - RegHL.Low = ReadMemory(RegPC.Word++); + RegHL.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x2F: // CPL @@ -299,7 +299,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x30: // JR NC, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -311,11 +311,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x31: // LD SP, nn - RegSP.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegSP.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x32: // LD (nn), A - WriteMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256), RegAF.High); + WriteMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256), RegAF.High); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x33: // INC SP @@ -323,15 +323,15 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 6; pendingCycles -= 6; break; case 0x34: // INC (HL) - TB = ReadMemory(RegHL.Word); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemory(RegHL.Word, TB); + TB = ReadMemoryWrapper(RegHL.Word); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemoryWrapper(RegHL.Word, TB); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x35: // DEC (HL) - TB = ReadMemory(RegHL.Word); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemory(RegHL.Word, TB); + TB = ReadMemoryWrapper(RegHL.Word); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemoryWrapper(RegHL.Word, TB); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x36: // LD (HL), n - WriteMemory(RegHL.Word, ReadMemory(RegPC.Word++)); + WriteMemoryWrapper(RegHL.Word, ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x37: // SCF @@ -339,7 +339,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x38: // JR C, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -362,7 +362,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 11; pendingCycles -= 11; break; case 0x3A: // LD A, (nn) - RegAF.High = ReadMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256)); + RegAF.High = ReadMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256)); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x3B: // DEC SP @@ -378,7 +378,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x3E: // LD A, n - RegAF.High = ReadMemory(RegPC.Word++); + RegAF.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x3F: // CCF @@ -409,7 +409,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x46: // LD B, (HL) - RegBC.High = ReadMemory(RegHL.Word); + RegBC.High = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x47: // LD B, A @@ -440,7 +440,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x4E: // LD C, (HL) - RegBC.Low = ReadMemory(RegHL.Word); + RegBC.Low = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x4F: // LD C, A @@ -471,7 +471,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x56: // LD D, (HL) - RegDE.High = ReadMemory(RegHL.Word); + RegDE.High = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x57: // LD D, A @@ -502,7 +502,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x5E: // LD E, (HL) - RegDE.Low = ReadMemory(RegHL.Word); + RegDE.Low = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x5F: // LD E, A @@ -533,7 +533,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x66: // LD H, (HL) - RegHL.High = ReadMemory(RegHL.Word); + RegHL.High = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x67: // LD H, A @@ -564,7 +564,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x6E: // LD L, (HL) - RegHL.Low = ReadMemory(RegHL.Word); + RegHL.Low = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x6F: // LD L, A @@ -572,27 +572,27 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x70: // LD (HL), B - WriteMemory(RegHL.Word, RegBC.High); + WriteMemoryWrapper(RegHL.Word, RegBC.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x71: // LD (HL), C - WriteMemory(RegHL.Word, RegBC.Low); + WriteMemoryWrapper(RegHL.Word, RegBC.Low); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x72: // LD (HL), D - WriteMemory(RegHL.Word, RegDE.High); + WriteMemoryWrapper(RegHL.Word, RegDE.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x73: // LD (HL), E - WriteMemory(RegHL.Word, RegDE.Low); + WriteMemoryWrapper(RegHL.Word, RegDE.Low); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x74: // LD (HL), H - WriteMemory(RegHL.Word, RegHL.High); + WriteMemoryWrapper(RegHL.Word, RegHL.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x75: // LD (HL), L - WriteMemory(RegHL.Word, RegHL.Low); + WriteMemoryWrapper(RegHL.Word, RegHL.Low); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x76: // HALT @@ -600,7 +600,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x77: // LD (HL), A - WriteMemory(RegHL.Word, RegAF.High); + WriteMemoryWrapper(RegHL.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x78: // LD A, B @@ -628,7 +628,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x7E: // LD A, (HL) - RegAF.High = ReadMemory(RegHL.Word); + RegAF.High = ReadMemoryWrapper(RegHL.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x7F: // LD A, A @@ -659,7 +659,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x86: // ADD A, (HL) - RegAF.Word = TableALU[0, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x87: // ADD A, A @@ -691,7 +691,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x8E: // ADC A, (HL) - RegAF.Word = TableALU[1, RegAF.High, ReadMemory(RegHL.Word), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper(RegHL.Word), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x8F: // ADC A, A @@ -723,7 +723,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x96: // SUB (HL) - RegAF.Word = TableALU[2, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x97: // SUB A, A @@ -755,7 +755,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x9E: // SBC A, (HL) - RegAF.Word = TableALU[3, RegAF.High, ReadMemory(RegHL.Word), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper(RegHL.Word), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x9F: // SBC A, A @@ -787,7 +787,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA6: // AND (HL) - RegAF.Word = TableALU[4, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xA7: // AND A @@ -819,7 +819,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xAE: // XOR (HL) - RegAF.Word = TableALU[5, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xAF: // XOR A @@ -851,7 +851,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB6: // OR (HL) - RegAF.Word = TableALU[6, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xB7: // OR A @@ -883,7 +883,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xBE: // CP (HL) - RegAF.Word = TableALU[7, RegAF.High, ReadMemory(RegHL.Word), 0]; + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper(RegHL.Word), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xBF: // CP A @@ -893,7 +893,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 case 0xC0: // RET NZ if (!RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -902,11 +902,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC1: // POP BC - RegBC.Low = ReadMemory(RegSP.Word++); RegBC.High = ReadMemory(RegSP.Word++); + RegBC.Low = ReadMemoryWrapper(RegSP.Word++); RegBC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC2: // JP NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { RegPC.Word = TUS; @@ -914,14 +914,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC3: // JP nn - RegPC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegPC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC4: // CALL NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -931,22 +931,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC5: // PUSH BC - WriteMemory(--RegSP.Word, RegBC.High); WriteMemory(--RegSP.Word, RegBC.Low); + WriteMemoryWrapper(--RegSP.Word, RegBC.High); WriteMemoryWrapper(--RegSP.Word, RegBC.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC6: // ADD A, n - RegAF.Word = TableALU[0, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xC7: // RST $00 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x00; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC8: // RET Z if (RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -955,11 +955,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC9: // RET - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xCA: // JP Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { RegPC.Word = TUS; @@ -968,7 +968,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xCB: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // RLC B TUS = TableRotShift[1, 0, RegAF.Low + 256 * RegBC.High]; @@ -1007,8 +1007,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x06: // RLC (HL) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1055,8 +1055,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x0E: // RRC (HL) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1103,8 +1103,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x16: // RL (HL) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1151,8 +1151,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x1E: // RR (HL) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1199,8 +1199,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x26: // SLA (HL) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1247,8 +1247,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x2E: // SRA (HL) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1295,8 +1295,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x36: // SL1 (HL) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1343,8 +1343,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x3E: // SRL (HL) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory(RegHL.Word)]; - WriteMemory(RegHL.Word, (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper(RegHL.Word)]; + WriteMemoryWrapper(RegHL.Word, (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 15; pendingCycles -= 15; break; @@ -1415,7 +1415,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x46: // BIT 0, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1495,7 +1495,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x4E: // BIT 1, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1575,7 +1575,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x56: // BIT 2, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1655,7 +1655,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x5E: // BIT 3, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = !RegFlagZ; @@ -1735,7 +1735,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x66: // BIT 4, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1815,7 +1815,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6E: // BIT 5, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1895,7 +1895,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x76: // BIT 6, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlag3 = false; @@ -1975,7 +1975,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x7E: // BIT 7, (HL) - RegFlagZ = (ReadMemory(RegHL.Word) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper(RegHL.Word) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlag3 = false; @@ -2019,7 +2019,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x86: // RES 0, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x01))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x01))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x87: // RES 0, A @@ -2051,7 +2051,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x8E: // RES 1, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x02))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x02))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x8F: // RES 1, A @@ -2083,7 +2083,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x96: // RES 2, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x04))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x04))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x97: // RES 2, A @@ -2115,7 +2115,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x9E: // RES 3, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x08))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x08))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x9F: // RES 3, A @@ -2147,7 +2147,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xA6: // RES 4, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x10))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x10))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xA7: // RES 4, A @@ -2179,7 +2179,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xAE: // RES 5, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x20))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x20))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xAF: // RES 5, A @@ -2211,7 +2211,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xB6: // RES 6, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x40))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x40))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xB7: // RES 6, A @@ -2243,7 +2243,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xBE: // RES 7, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) & unchecked((byte)~0x80))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) & unchecked((byte)~0x80))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xBF: // RES 7, A @@ -2275,7 +2275,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xC6: // SET 0, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x01))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x01))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xC7: // SET 0, A @@ -2307,7 +2307,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xCE: // SET 1, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x02))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x02))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xCF: // SET 1, A @@ -2339,7 +2339,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xD6: // SET 2, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x04))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x04))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xD7: // SET 2, A @@ -2371,7 +2371,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xDE: // SET 3, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x08))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x08))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xDF: // SET 3, A @@ -2403,7 +2403,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xE6: // SET 4, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x10))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x10))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xE7: // SET 4, A @@ -2435,7 +2435,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xEE: // SET 5, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x20))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x20))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xEF: // SET 5, A @@ -2467,7 +2467,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xF6: // SET 6, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x40))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x40))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xF7: // SET 6, A @@ -2499,7 +2499,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xFE: // SET 7, (HL) - WriteMemory(RegHL.Word, (byte)(ReadMemory(RegHL.Word) | unchecked((byte)0x80))); + WriteMemoryWrapper(RegHL.Word, (byte)(ReadMemoryWrapper(RegHL.Word) | unchecked((byte)0x80))); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xFF: // SET 7, A @@ -2509,10 +2509,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xCC: // CALL Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -2522,24 +2522,24 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xCD: // CALL nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; break; case 0xCE: // ADC A, n - RegAF.Word = TableALU[1, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xCF: // RST $08 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x08; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD0: // RET NC if (!RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -2548,11 +2548,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD1: // POP DE - RegDE.Low = ReadMemory(RegSP.Word++); RegDE.High = ReadMemory(RegSP.Word++); + RegDE.Low = ReadMemoryWrapper(RegSP.Word++); RegDE.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD2: // JP NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { RegPC.Word = TUS; @@ -2560,14 +2560,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD3: // OUT n, A - WriteHardware(ReadMemory(RegPC.Word++), RegAF.High); + WriteHardware(ReadMemoryWrapper(RegPC.Word++), RegAF.High); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD4: // CALL NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -2577,22 +2577,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD5: // PUSH DE - WriteMemory(--RegSP.Word, RegDE.High); WriteMemory(--RegSP.Word, RegDE.Low); + WriteMemoryWrapper(--RegSP.Word, RegDE.High); WriteMemoryWrapper(--RegSP.Word, RegDE.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD6: // SUB n - RegAF.Word = TableALU[2, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xD7: // RST $10 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x10; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD8: // RET C if (RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -2607,7 +2607,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xDA: // JP C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { RegPC.Word = TUS; @@ -2615,14 +2615,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xDB: // IN A, n - RegAF.High = ReadHardware((ushort)ReadMemory(RegPC.Word++)); + RegAF.High = ReadHardware((ushort)ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xDC: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -2633,17 +2633,17 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xDD: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x01: // LD BC, nn - RegBC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegBC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x02: // LD (BC), A - WriteMemory(RegBC.Word, RegAF.High); + WriteMemoryWrapper(RegBC.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x03: // INC BC @@ -2659,7 +2659,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x06: // LD B, n - RegBC.High = ReadMemory(RegPC.Word++); + RegBC.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x07: // RLCA @@ -2682,7 +2682,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x0A: // LD A, (BC) - RegAF.High = ReadMemory(RegBC.Word); + RegAF.High = ReadMemoryWrapper(RegBC.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0B: // DEC BC @@ -2698,7 +2698,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x0E: // LD C, n - RegBC.Low = ReadMemory(RegPC.Word++); + RegBC.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0F: // RRCA @@ -2706,7 +2706,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x10: // DJNZ d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (--RegBC.High != 0) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -2718,11 +2718,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x11: // LD DE, nn - RegDE.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegDE.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x12: // LD (DE), A - WriteMemory(RegDE.Word, RegAF.High); + WriteMemoryWrapper(RegDE.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x13: // INC DE @@ -2738,7 +2738,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x16: // LD D, n - RegDE.High = ReadMemory(RegPC.Word++); + RegDE.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x17: // RLA @@ -2746,7 +2746,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x18: // JR d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); RegPC.Word = (ushort)(RegPC.Word + TSB); totalExecutedCycles += 12; pendingCycles -= 12; break; @@ -2762,7 +2762,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x1A: // LD A, (DE) - RegAF.High = ReadMemory(RegDE.Word); + RegAF.High = ReadMemoryWrapper(RegDE.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1B: // DEC DE @@ -2778,7 +2778,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x1E: // LD E, n - RegDE.Low = ReadMemory(RegPC.Word++); + RegDE.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1F: // RRA @@ -2786,7 +2786,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x20: // JR NZ, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -2798,13 +2798,13 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x21: // LD IX, nn - RegIX.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegIX.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x22: // LD (nn), IX - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegIX.Low); - WriteMemory(TUS, RegIX.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegIX.Low); + WriteMemoryWrapper(TUS, RegIX.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x23: // INC IX @@ -2820,7 +2820,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x26: // LD IXH, n - RegIX.High = ReadMemory(RegPC.Word++); + RegIX.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x27: // DAA @@ -2828,7 +2828,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x28: // JR Z, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -2851,8 +2851,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x2A: // LD IX, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegIX.Low = ReadMemory(TUS++); RegIX.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegIX.Low = ReadMemoryWrapper(TUS++); RegIX.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x2B: // DEC IX @@ -2868,7 +2868,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x2E: // LD IXL, n - RegIX.Low = ReadMemory(RegPC.Word++); + RegIX.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x2F: // CPL @@ -2876,7 +2876,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x30: // JR NC, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -2888,11 +2888,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x31: // LD SP, nn - RegSP.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegSP.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x32: // LD (nn), A - WriteMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256), RegAF.High); + WriteMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256), RegAF.High); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x33: // INC SP @@ -2900,18 +2900,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 6; pendingCycles -= 6; break; case 0x34: // INC (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - TB = ReadMemory((ushort)(RegIX.Word + Displacement)); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemory((ushort)(RegIX.Word + Displacement), TB); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + TB = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), TB); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x35: // DEC (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - TB = ReadMemory((ushort)(RegIX.Word + Displacement)); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemory((ushort)(RegIX.Word + Displacement), TB); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + TB = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), TB); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x36: // LD (IX+d), n - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), ReadMemory(RegPC.Word++)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x37: // SCF @@ -2919,7 +2919,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x38: // JR C, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -2942,7 +2942,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x3A: // LD A, (nn) - RegAF.High = ReadMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256)); + RegAF.High = ReadMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256)); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x3B: // DEC SP @@ -2958,7 +2958,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x3E: // LD A, n - RegAF.High = ReadMemory(RegPC.Word++); + RegAF.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x3F: // CCF @@ -2989,8 +2989,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x46: // LD B, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegBC.High = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegBC.High = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x47: // LD B, A @@ -3021,8 +3021,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x4E: // LD C, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegBC.Low = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegBC.Low = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x4F: // LD C, A @@ -3053,8 +3053,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x56: // LD D, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegDE.High = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegDE.High = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x57: // LD D, A @@ -3085,8 +3085,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x5E: // LD E, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegDE.Low = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegDE.Low = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x5F: // LD E, A @@ -3117,8 +3117,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x66: // LD H, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegHL.High = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegHL.High = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x67: // LD IXH, A @@ -3149,8 +3149,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x6E: // LD L, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegHL.Low = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegHL.Low = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x6F: // LD IXL, A @@ -3158,33 +3158,33 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x70: // LD (IX+d), B - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x71: // LD (IX+d), C - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x72: // LD (IX+d), D - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x73: // LD (IX+d), E - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x74: // LD (IX+d), H - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x75: // LD (IX+d), L - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x76: // HALT @@ -3192,8 +3192,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x77: // LD (IX+d), A - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x78: // LD A, B @@ -3221,8 +3221,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x7E: // LD A, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.High = ReadMemory((ushort)(RegIX.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.High = ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x7F: // LD A, A @@ -3253,8 +3253,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x86: // ADD A, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[0, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x87: // ADD A, A @@ -3286,8 +3286,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x8E: // ADC A, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[1, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), RegFlagC ? 1 : 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), RegFlagC ? 1 : 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x8F: // ADC A, A @@ -3319,8 +3319,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x96: // SUB (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[2, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x97: // SUB A, A @@ -3352,8 +3352,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x9E: // SBC A, (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[3, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), RegFlagC ? 1 : 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), RegFlagC ? 1 : 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x9F: // SBC A, A @@ -3385,8 +3385,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xA6: // AND (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[4, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xA7: // AND A @@ -3418,8 +3418,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xAE: // XOR (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[5, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xAF: // XOR A @@ -3451,8 +3451,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xB6: // OR (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[6, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xB7: // OR A @@ -3484,8 +3484,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xBE: // CP (IX+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[7, RegAF.High, ReadMemory((ushort)(RegIX.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xBF: // CP A @@ -3495,7 +3495,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 case 0xC0: // RET NZ if (!RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -3504,11 +3504,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC1: // POP BC - RegBC.Low = ReadMemory(RegSP.Word++); RegBC.High = ReadMemory(RegSP.Word++); + RegBC.Low = ReadMemoryWrapper(RegSP.Word++); RegBC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC2: // JP NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { RegPC.Word = TUS; @@ -3516,14 +3516,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC3: // JP nn - RegPC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegPC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC4: // CALL NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -3533,22 +3533,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC5: // PUSH BC - WriteMemory(--RegSP.Word, RegBC.High); WriteMemory(--RegSP.Word, RegBC.Low); + WriteMemoryWrapper(--RegSP.Word, RegBC.High); WriteMemoryWrapper(--RegSP.Word, RegBC.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC6: // ADD A, n - RegAF.Word = TableALU[0, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xC7: // RST $00 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x00; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC8: // RET Z if (RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -3557,11 +3557,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC9: // RET - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xCA: // JP Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { RegPC.Word = TUS; @@ -3569,452 +3569,452 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xCB: // (Prefix) - Displacement = (sbyte)ReadMemory(RegPC.Word++); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // RLC (IX+d)→B - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x01: // RLC (IX+d)→C - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x02: // RLC (IX+d)→D - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x03: // RLC (IX+d)→E - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x04: // RLC (IX+d)→H - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x05: // RLC (IX+d)→L - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x06: // RLC (IX+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x07: // RLC (IX+d)→A - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x08: // RRC (IX+d)→B - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x09: // RRC (IX+d)→C - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0A: // RRC (IX+d)→D - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0B: // RRC (IX+d)→E - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0C: // RRC (IX+d)→H - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0D: // RRC (IX+d)→L - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0E: // RRC (IX+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0F: // RRC (IX+d)→A - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x10: // RL (IX+d)→B - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x11: // RL (IX+d)→C - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x12: // RL (IX+d)→D - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x13: // RL (IX+d)→E - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x14: // RL (IX+d)→H - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x15: // RL (IX+d)→L - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x16: // RL (IX+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x17: // RL (IX+d)→A - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x18: // RR (IX+d)→B - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x19: // RR (IX+d)→C - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1A: // RR (IX+d)→D - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1B: // RR (IX+d)→E - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1C: // RR (IX+d)→H - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1D: // RR (IX+d)→L - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1E: // RR (IX+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1F: // RR (IX+d)→A - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x20: // SLA (IX+d)→B - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x21: // SLA (IX+d)→C - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x22: // SLA (IX+d)→D - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x23: // SLA (IX+d)→E - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x24: // SLA (IX+d)→H - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x25: // SLA (IX+d)→L - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x26: // SLA (IX+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x27: // SLA (IX+d)→A - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x28: // SRA (IX+d)→B - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x29: // SRA (IX+d)→C - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2A: // SRA (IX+d)→D - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2B: // SRA (IX+d)→E - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2C: // SRA (IX+d)→H - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2D: // SRA (IX+d)→L - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2E: // SRA (IX+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2F: // SRA (IX+d)→A - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x30: // SL1 (IX+d)→B - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x31: // SL1 (IX+d)→C - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x32: // SL1 (IX+d)→D - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x33: // SL1 (IX+d)→E - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x34: // SL1 (IX+d)→H - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x35: // SL1 (IX+d)→L - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x36: // SL1 (IX+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x37: // SL1 (IX+d)→A - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x38: // SRL (IX+d)→B - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x39: // SRL (IX+d)→C - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegBC.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3A: // SRL (IX+d)→D - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3B: // SRL (IX+d)→E - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegDE.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3C: // SRL (IX+d)→H - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3D: // SRL (IX+d)→L - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegHL.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3E: // SRL (IX+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3F: // SRL (IX+d)→A - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIX.Word + Displacement))]; - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIX.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; RegAF.High = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x40: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4022,7 +4022,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x41: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4030,7 +4030,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x42: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4038,7 +4038,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x43: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4046,7 +4046,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x44: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4054,7 +4054,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x45: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4062,7 +4062,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x46: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4070,7 +4070,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x47: // BIT 0, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4078,7 +4078,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x48: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4086,7 +4086,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x49: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4094,7 +4094,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4A: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4102,7 +4102,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4B: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4110,7 +4110,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4C: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4118,7 +4118,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4D: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4126,7 +4126,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4E: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4134,7 +4134,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4F: // BIT 1, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4142,7 +4142,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x50: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4150,7 +4150,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x51: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4158,7 +4158,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x52: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4166,7 +4166,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x53: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4174,7 +4174,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x54: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4182,7 +4182,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x55: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4190,7 +4190,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x56: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4198,7 +4198,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x57: // BIT 2, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4206,7 +4206,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x58: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4214,7 +4214,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x59: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4222,7 +4222,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5A: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4230,7 +4230,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5B: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4238,7 +4238,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5C: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4246,7 +4246,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5D: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4254,7 +4254,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5E: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4262,7 +4262,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5F: // BIT 3, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4270,7 +4270,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x60: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4278,7 +4278,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x61: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4286,7 +4286,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x62: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4294,7 +4294,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x63: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4302,7 +4302,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x64: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4310,7 +4310,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x65: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4318,7 +4318,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x66: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4326,7 +4326,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x67: // BIT 4, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4334,7 +4334,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x68: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4342,7 +4342,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x69: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4350,7 +4350,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6A: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4358,7 +4358,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6B: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4366,7 +4366,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6C: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4374,7 +4374,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6D: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4382,7 +4382,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6E: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4390,7 +4390,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6F: // BIT 5, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4398,7 +4398,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x70: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4406,7 +4406,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x71: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4414,7 +4414,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x72: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4422,7 +4422,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x73: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4430,7 +4430,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x74: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4438,7 +4438,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x75: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4446,7 +4446,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x76: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4454,7 +4454,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x77: // BIT 6, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -4462,7 +4462,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x78: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4470,7 +4470,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x79: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4478,7 +4478,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7A: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4486,7 +4486,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7B: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4494,7 +4494,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7C: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4502,7 +4502,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7D: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4510,7 +4510,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7E: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4518,7 +4518,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7F: // BIT 7, (IX+d) - RegFlagZ = (ReadMemory((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -4526,636 +4526,636 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x80: // RES 0, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x81: // RES 0, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x82: // RES 0, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x83: // RES 0, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x84: // RES 0, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x85: // RES 0, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x86: // RES 0, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x87: // RES 0, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x88: // RES 1, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x89: // RES 1, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8A: // RES 1, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8B: // RES 1, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8C: // RES 1, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8D: // RES 1, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8E: // RES 1, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8F: // RES 1, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x90: // RES 2, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x91: // RES 2, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x92: // RES 2, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x93: // RES 2, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x94: // RES 2, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x95: // RES 2, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x96: // RES 2, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x97: // RES 2, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x98: // RES 3, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x99: // RES 3, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9A: // RES 3, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9B: // RES 3, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9C: // RES 3, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9D: // RES 3, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9E: // RES 3, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9F: // RES 3, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA0: // RES 4, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA1: // RES 4, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA2: // RES 4, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA3: // RES 4, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA4: // RES 4, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA5: // RES 4, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA6: // RES 4, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA7: // RES 4, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA8: // RES 5, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA9: // RES 5, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAA: // RES 5, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAB: // RES 5, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAC: // RES 5, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAD: // RES 5, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAE: // RES 5, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAF: // RES 5, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB0: // RES 6, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB1: // RES 6, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB2: // RES 6, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB3: // RES 6, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB4: // RES 6, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB5: // RES 6, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB6: // RES 6, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB7: // RES 6, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB8: // RES 7, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB9: // RES 7, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBA: // RES 7, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBB: // RES 7, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBC: // RES 7, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBD: // RES 7, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBE: // RES 7, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBF: // RES 7, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) & unchecked((byte)~0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC0: // SET 0, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC1: // SET 0, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC2: // SET 0, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC3: // SET 0, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC4: // SET 0, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC5: // SET 0, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC6: // SET 0, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC7: // SET 0, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x01)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC8: // SET 1, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC9: // SET 1, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCA: // SET 1, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCB: // SET 1, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCC: // SET 1, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCD: // SET 1, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCE: // SET 1, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCF: // SET 1, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x02)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD0: // SET 2, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD1: // SET 2, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD2: // SET 2, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD3: // SET 2, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD4: // SET 2, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD5: // SET 2, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD6: // SET 2, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD7: // SET 2, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x04)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD8: // SET 3, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD9: // SET 3, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDA: // SET 3, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDB: // SET 3, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDC: // SET 3, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDD: // SET 3, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDE: // SET 3, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDF: // SET 3, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x08)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE0: // SET 4, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE1: // SET 4, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE2: // SET 4, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE3: // SET 4, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE4: // SET 4, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE5: // SET 4, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE6: // SET 4, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE7: // SET 4, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x10)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE8: // SET 5, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE9: // SET 5, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEA: // SET 5, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEB: // SET 5, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEC: // SET 5, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xED: // SET 5, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEE: // SET 5, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEF: // SET 5, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x20)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF0: // SET 6, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF1: // SET 6, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF2: // SET 6, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF3: // SET 6, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF4: // SET 6, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF5: // SET 6, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF6: // SET 6, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF7: // SET 6, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x40)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF8: // SET 7, (IX+d)→B - RegBC.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.High); + RegBC.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF9: // SET 7, (IX+d)→C - RegBC.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegBC.Low); + RegBC.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegBC.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFA: // SET 7, (IX+d)→D - RegDE.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.High); + RegDE.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFB: // SET 7, (IX+d)→E - RegDE.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegDE.Low); + RegDE.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegDE.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFC: // SET 7, (IX+d)→H - RegHL.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.High); + RegHL.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.High); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFD: // SET 7, (IX+d)→L - RegHL.Low = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegHL.Low); + RegHL.Low = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegHL.Low); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFE: // SET 7, (IX+d) - WriteMemory((ushort)(RegIX.Word + Displacement), (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFF: // SET 7, (IX+d)→A - RegAF.High = (byte)(ReadMemory((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); - WriteMemory((ushort)(RegIX.Word + Displacement), RegAF.High); + RegAF.High = (byte)(ReadMemoryWrapper((ushort)(RegIX.Word + Displacement)) | unchecked((byte)0x80)); + WriteMemoryWrapper((ushort)(RegIX.Word + Displacement), RegAF.High); totalExecutedCycles += 23; pendingCycles -= 23; break; } break; case 0xCC: // CALL Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -5165,24 +5165,24 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xCD: // CALL nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; break; case 0xCE: // ADC A, n - RegAF.Word = TableALU[1, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xCF: // RST $08 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x08; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD0: // RET NC if (!RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -5191,11 +5191,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD1: // POP DE - RegDE.Low = ReadMemory(RegSP.Word++); RegDE.High = ReadMemory(RegSP.Word++); + RegDE.Low = ReadMemoryWrapper(RegSP.Word++); RegDE.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD2: // JP NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { RegPC.Word = TUS; @@ -5203,14 +5203,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD3: // OUT n, A - WriteHardware(ReadMemory(RegPC.Word++), RegAF.High); + WriteHardware(ReadMemoryWrapper(RegPC.Word++), RegAF.High); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD4: // CALL NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -5220,22 +5220,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD5: // PUSH DE - WriteMemory(--RegSP.Word, RegDE.High); WriteMemory(--RegSP.Word, RegDE.Low); + WriteMemoryWrapper(--RegSP.Word, RegDE.High); WriteMemoryWrapper(--RegSP.Word, RegDE.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD6: // SUB n - RegAF.Word = TableALU[2, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xD7: // RST $10 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x10; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD8: // RET C if (RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -5250,7 +5250,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xDA: // JP C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { RegPC.Word = TUS; @@ -5258,14 +5258,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xDB: // IN A, n - RegAF.High = ReadHardware((ushort)ReadMemory(RegPC.Word++)); + RegAF.High = ReadHardware((ushort)ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xDC: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -5279,18 +5279,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 1337; pendingCycles -= 1337; break; case 0xDE: // SBC A, n - RegAF.Word = TableALU[3, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xDF: // RST $18 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x18; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE0: // RET PO if (!RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -5299,11 +5299,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE1: // POP IX - RegIX.Low = ReadMemory(RegSP.Word++); RegIX.High = ReadMemory(RegSP.Word++); + RegIX.Low = ReadMemoryWrapper(RegSP.Word++); RegIX.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0xE2: // JP PO, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagP) { RegPC.Word = TUS; @@ -5311,16 +5311,16 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xE3: // EX (SP), IX - TUS = RegSP.Word; TBL = ReadMemory(TUS++); TBH = ReadMemory(TUS--); - WriteMemory(TUS++, RegIX.Low); WriteMemory(TUS, RegIX.High); + TUS = RegSP.Word; TBL = ReadMemoryWrapper(TUS++); TBH = ReadMemoryWrapper(TUS--); + WriteMemoryWrapper(TUS++, RegIX.Low); WriteMemoryWrapper(TUS, RegIX.High); RegIX.Low = TBL; RegIX.High = TBH; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE4: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -5330,22 +5330,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE5: // PUSH IX - WriteMemory(--RegSP.Word, RegIX.High); WriteMemory(--RegSP.Word, RegIX.Low); + WriteMemoryWrapper(--RegSP.Word, RegIX.High); WriteMemoryWrapper(--RegSP.Word, RegIX.Low); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xE6: // AND n - RegAF.Word = TableALU[4, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xE7: // RST $20 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x20; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE8: // RET PE if (RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -5358,7 +5358,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xEA: // JP PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { RegPC.Word = TUS; @@ -5370,10 +5370,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xEC: // CALL PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -5384,7 +5384,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xED: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; @@ -5607,9 +5607,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x43: // LD (nn), BC - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegBC.Low); - WriteMemory(TUS, RegBC.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegBC.Low); + WriteMemoryWrapper(TUS, RegBC.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x44: // NEG @@ -5617,7 +5617,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x45: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -5658,8 +5658,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x4B: // LD BC, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegBC.Low = ReadMemory(TUS++); RegBC.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegBC.Low = ReadMemoryWrapper(TUS++); RegBC.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4C: // NEG @@ -5667,7 +5667,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x4D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x4E: // IM $0 @@ -5707,9 +5707,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x53: // LD (nn), DE - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegDE.Low); - WriteMemory(TUS, RegDE.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegDE.Low); + WriteMemoryWrapper(TUS, RegDE.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x54: // NEG @@ -5717,7 +5717,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x55: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -5763,8 +5763,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x5B: // LD DE, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegDE.Low = ReadMemory(TUS++); RegDE.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegDE.Low = ReadMemoryWrapper(TUS++); RegDE.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5C: // NEG @@ -5772,7 +5772,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x5D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x5E: // IM $2 @@ -5817,9 +5817,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x63: // LD (nn), HL - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegHL.Low); - WriteMemory(TUS, RegHL.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegHL.Low); + WriteMemoryWrapper(TUS, RegHL.High); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x64: // NEG @@ -5827,7 +5827,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x65: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -5836,8 +5836,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x67: // RRD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 & 0x0F)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -5877,8 +5877,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x6B: // LD HL, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegHL.Low = ReadMemory(TUS++); RegHL.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegHL.Low = ReadMemoryWrapper(TUS++); RegHL.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x6C: // NEG @@ -5886,7 +5886,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x6E: // IM $0 @@ -5894,8 +5894,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6F: // RLD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 >> 4)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -5935,9 +5935,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x73: // LD (nn), SP - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegSP.Low); - WriteMemory(TUS, RegSP.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegSP.Low); + WriteMemoryWrapper(TUS, RegSP.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x74: // NEG @@ -5945,7 +5945,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x75: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -5985,8 +5985,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x7B: // LD SP, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegSP.Low = ReadMemory(TUS++); RegSP.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegSP.Low = ReadMemoryWrapper(TUS++); RegSP.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7C: // NEG @@ -5994,7 +5994,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x7D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x7E: // IM $2 @@ -6101,7 +6101,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA0: // LDI - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -6110,7 +6110,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA1: // CPI - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -6121,14 +6121,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA2: // INI - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA3: // OUTI - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6147,7 +6147,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA8: // LDD - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -6156,7 +6156,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA9: // CPD - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -6167,14 +6167,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAA: // IND - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAB: // OUTD - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6193,7 +6193,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB0: // LDIR - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -6210,7 +6210,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB1: // CPIR - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -6229,7 +6229,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB2: // INIR - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6244,7 +6244,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB3: // OTIR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6271,7 +6271,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB8: // LDDR - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -6288,7 +6288,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB9: // CPDR - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -6307,7 +6307,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBA: // INDR - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6322,7 +6322,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBB: // OTDR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -6543,18 +6543,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xEE: // XOR n - RegAF.Word = TableALU[5, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xEF: // RST $28 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x28; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF0: // RET P if (!RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -6563,11 +6563,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF1: // POP AF - RegAF.Low = ReadMemory(RegSP.Word++); RegAF.High = ReadMemory(RegSP.Word++); + RegAF.Low = ReadMemoryWrapper(RegSP.Word++); RegAF.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xF2: // JP P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { RegPC.Word = TUS; @@ -6579,10 +6579,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xF4: // CALL P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -6592,22 +6592,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF5: // PUSH AF - WriteMemory(--RegSP.Word, RegAF.High); WriteMemory(--RegSP.Word, RegAF.Low); + WriteMemoryWrapper(--RegSP.Word, RegAF.High); WriteMemoryWrapper(--RegSP.Word, RegAF.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF6: // OR n - RegAF.Word = TableALU[6, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xF7: // RST $30 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x30; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF8: // RET M if (RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -6620,7 +6620,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xFA: // JP M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { RegPC.Word = TUS; @@ -6633,10 +6633,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xFC: // CALL M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -6650,29 +6650,29 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 1337; pendingCycles -= 1337; break; case 0xFE: // CP n - RegAF.Word = TableALU[7, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xFF: // RST $38 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x38; totalExecutedCycles += 11; pendingCycles -= 11; break; } break; case 0xDE: // SBC A, n - RegAF.Word = TableALU[3, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xDF: // RST $18 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x18; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE0: // RET PO if (!RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -6681,11 +6681,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE1: // POP HL - RegHL.Low = ReadMemory(RegSP.Word++); RegHL.High = ReadMemory(RegSP.Word++); + RegHL.Low = ReadMemoryWrapper(RegSP.Word++); RegHL.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xE2: // JP PO, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagP) { RegPC.Word = TUS; @@ -6693,16 +6693,16 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xE3: // EX (SP), HL - TUS = RegSP.Word; TBL = ReadMemory(TUS++); TBH = ReadMemory(TUS--); - WriteMemory(TUS++, RegHL.Low); WriteMemory(TUS, RegHL.High); + TUS = RegSP.Word; TBL = ReadMemoryWrapper(TUS++); TBH = ReadMemoryWrapper(TUS--); + WriteMemoryWrapper(TUS++, RegHL.Low); WriteMemoryWrapper(TUS, RegHL.High); RegHL.Low = TBL; RegHL.High = TBH; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xE4: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -6712,22 +6712,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE5: // PUSH HL - WriteMemory(--RegSP.Word, RegHL.High); WriteMemory(--RegSP.Word, RegHL.Low); + WriteMemoryWrapper(--RegSP.Word, RegHL.High); WriteMemoryWrapper(--RegSP.Word, RegHL.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE6: // AND n - RegAF.Word = TableALU[4, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xE7: // RST $20 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x20; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE8: // RET PE if (RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -6740,7 +6740,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xEA: // JP PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { RegPC.Word = TUS; @@ -6752,10 +6752,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xEC: // CALL PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -6766,7 +6766,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xED: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; @@ -6989,9 +6989,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x43: // LD (nn), BC - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegBC.Low); - WriteMemory(TUS, RegBC.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegBC.Low); + WriteMemoryWrapper(TUS, RegBC.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x44: // NEG @@ -6999,7 +6999,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x45: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -7040,8 +7040,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x4B: // LD BC, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegBC.Low = ReadMemory(TUS++); RegBC.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegBC.Low = ReadMemoryWrapper(TUS++); RegBC.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4C: // NEG @@ -7049,7 +7049,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x4D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x4E: // IM $0 @@ -7089,9 +7089,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x53: // LD (nn), DE - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegDE.Low); - WriteMemory(TUS, RegDE.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegDE.Low); + WriteMemoryWrapper(TUS, RegDE.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x54: // NEG @@ -7099,7 +7099,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x55: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -7145,8 +7145,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x5B: // LD DE, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegDE.Low = ReadMemory(TUS++); RegDE.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegDE.Low = ReadMemoryWrapper(TUS++); RegDE.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5C: // NEG @@ -7154,7 +7154,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x5D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x5E: // IM $2 @@ -7199,9 +7199,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x63: // LD (nn), HL - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegHL.Low); - WriteMemory(TUS, RegHL.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegHL.Low); + WriteMemoryWrapper(TUS, RegHL.High); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x64: // NEG @@ -7209,7 +7209,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x65: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -7218,8 +7218,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x67: // RRD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 & 0x0F)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -7259,8 +7259,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x6B: // LD HL, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegHL.Low = ReadMemory(TUS++); RegHL.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegHL.Low = ReadMemoryWrapper(TUS++); RegHL.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x6C: // NEG @@ -7268,7 +7268,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x6E: // IM $0 @@ -7276,8 +7276,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6F: // RLD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 >> 4)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -7317,9 +7317,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x73: // LD (nn), SP - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegSP.Low); - WriteMemory(TUS, RegSP.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegSP.Low); + WriteMemoryWrapper(TUS, RegSP.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x74: // NEG @@ -7327,7 +7327,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x75: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -7367,8 +7367,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x7B: // LD SP, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegSP.Low = ReadMemory(TUS++); RegSP.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegSP.Low = ReadMemoryWrapper(TUS++); RegSP.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7C: // NEG @@ -7376,7 +7376,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x7D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x7E: // IM $2 @@ -7483,7 +7483,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA0: // LDI - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -7492,7 +7492,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA1: // CPI - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -7503,14 +7503,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA2: // INI - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA3: // OUTI - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7529,7 +7529,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA8: // LDD - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -7538,7 +7538,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA9: // CPD - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -7549,14 +7549,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAA: // IND - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAB: // OUTD - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7575,7 +7575,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB0: // LDIR - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -7592,7 +7592,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB1: // CPIR - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -7611,7 +7611,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB2: // INIR - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7626,7 +7626,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB3: // OTIR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7653,7 +7653,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB8: // LDDR - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -7670,7 +7670,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB9: // CPDR - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -7689,7 +7689,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBA: // INDR - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7704,7 +7704,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBB: // OTDR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -7925,18 +7925,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xEE: // XOR n - RegAF.Word = TableALU[5, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xEF: // RST $28 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x28; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF0: // RET P if (!RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -7945,11 +7945,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF1: // POP AF - RegAF.Low = ReadMemory(RegSP.Word++); RegAF.High = ReadMemory(RegSP.Word++); + RegAF.Low = ReadMemoryWrapper(RegSP.Word++); RegAF.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xF2: // JP P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { RegPC.Word = TUS; @@ -7961,10 +7961,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xF4: // CALL P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -7974,22 +7974,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF5: // PUSH AF - WriteMemory(--RegSP.Word, RegAF.High); WriteMemory(--RegSP.Word, RegAF.Low); + WriteMemoryWrapper(--RegSP.Word, RegAF.High); WriteMemoryWrapper(--RegSP.Word, RegAF.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF6: // OR n - RegAF.Word = TableALU[6, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xF7: // RST $30 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x30; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF8: // RET M if (RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -8002,7 +8002,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 6; pendingCycles -= 6; break; case 0xFA: // JP M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { RegPC.Word = TUS; @@ -8015,10 +8015,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xFC: // CALL M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -8029,17 +8029,17 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xFD: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x01: // LD BC, nn - RegBC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegBC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x02: // LD (BC), A - WriteMemory(RegBC.Word, RegAF.High); + WriteMemoryWrapper(RegBC.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x03: // INC BC @@ -8055,7 +8055,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x06: // LD B, n - RegBC.High = ReadMemory(RegPC.Word++); + RegBC.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x07: // RLCA @@ -8078,7 +8078,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x0A: // LD A, (BC) - RegAF.High = ReadMemory(RegBC.Word); + RegAF.High = ReadMemoryWrapper(RegBC.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0B: // DEC BC @@ -8094,7 +8094,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x0E: // LD C, n - RegBC.Low = ReadMemory(RegPC.Word++); + RegBC.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x0F: // RRCA @@ -8102,7 +8102,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x10: // DJNZ d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (--RegBC.High != 0) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -8114,11 +8114,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x11: // LD DE, nn - RegDE.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegDE.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x12: // LD (DE), A - WriteMemory(RegDE.Word, RegAF.High); + WriteMemoryWrapper(RegDE.Word, RegAF.High); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x13: // INC DE @@ -8134,7 +8134,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x16: // LD D, n - RegDE.High = ReadMemory(RegPC.Word++); + RegDE.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x17: // RLA @@ -8142,7 +8142,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x18: // JR d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); RegPC.Word = (ushort)(RegPC.Word + TSB); totalExecutedCycles += 12; pendingCycles -= 12; break; @@ -8158,7 +8158,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x1A: // LD A, (DE) - RegAF.High = ReadMemory(RegDE.Word); + RegAF.High = ReadMemoryWrapper(RegDE.Word); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1B: // DEC DE @@ -8174,7 +8174,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x1E: // LD E, n - RegDE.Low = ReadMemory(RegPC.Word++); + RegDE.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x1F: // RRA @@ -8182,7 +8182,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x20: // JR NZ, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -8194,13 +8194,13 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x21: // LD IY, nn - RegIY.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegIY.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x22: // LD (nn), IY - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegIY.Low); - WriteMemory(TUS, RegIY.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegIY.Low); + WriteMemoryWrapper(TUS, RegIY.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x23: // INC IY @@ -8216,7 +8216,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x26: // LD IYH, n - RegIY.High = ReadMemory(RegPC.Word++); + RegIY.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x27: // DAA @@ -8224,7 +8224,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x28: // JR Z, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagZ) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -8247,8 +8247,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x2A: // LD IY, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegIY.Low = ReadMemory(TUS++); RegIY.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegIY.Low = ReadMemoryWrapper(TUS++); RegIY.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x2B: // DEC IY @@ -8264,7 +8264,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x2E: // LD IYL, n - RegIY.Low = ReadMemory(RegPC.Word++); + RegIY.Low = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x2F: // CPL @@ -8272,7 +8272,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x30: // JR NC, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (!RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -8284,11 +8284,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0x31: // LD SP, nn - RegSP.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegSP.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0x32: // LD (nn), A - WriteMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256), RegAF.High); + WriteMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256), RegAF.High); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x33: // INC SP @@ -8296,18 +8296,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 6; pendingCycles -= 6; break; case 0x34: // INC (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - TB = ReadMemory((ushort)(RegIY.Word + Displacement)); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemory((ushort)(RegIY.Word + Displacement), TB); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + TB = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); RegAF.Low = (byte)(TableInc[++TB] | (RegAF.Low & 1)); WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), TB); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x35: // DEC (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - TB = ReadMemory((ushort)(RegIY.Word + Displacement)); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemory((ushort)(RegIY.Word + Displacement), TB); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + TB = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); RegAF.Low = (byte)(TableDec[--TB] | (RegAF.Low & 1)); WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), TB); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x36: // LD (IY+d), n - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), ReadMemory(RegPC.Word++)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x37: // SCF @@ -8315,7 +8315,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x38: // JR C, d - TSB = (sbyte)ReadMemory(RegPC.Word++); + TSB = (sbyte)ReadMemoryWrapper(RegPC.Word++); if (RegFlagC) { RegPC.Word = (ushort)(RegPC.Word + TSB); @@ -8338,7 +8338,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x3A: // LD A, (nn) - RegAF.High = ReadMemory((ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256)); + RegAF.High = ReadMemoryWrapper((ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256)); totalExecutedCycles += 13; pendingCycles -= 13; break; case 0x3B: // DEC SP @@ -8354,7 +8354,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x3E: // LD A, n - RegAF.High = ReadMemory(RegPC.Word++); + RegAF.High = ReadMemoryWrapper(RegPC.Word++); totalExecutedCycles += 7; pendingCycles -= 7; break; case 0x3F: // CCF @@ -8385,8 +8385,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x46: // LD B, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegBC.High = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegBC.High = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x47: // LD B, A @@ -8417,8 +8417,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x4E: // LD C, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegBC.Low = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegBC.Low = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x4F: // LD C, A @@ -8449,8 +8449,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x56: // LD D, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegDE.High = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegDE.High = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x57: // LD D, A @@ -8481,8 +8481,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x5E: // LD E, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegDE.Low = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegDE.Low = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x5F: // LD E, A @@ -8513,8 +8513,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x66: // LD H, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegHL.High = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegHL.High = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x67: // LD IYH, A @@ -8545,8 +8545,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x6E: // LD L, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegHL.Low = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegHL.Low = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x6F: // LD IYL, A @@ -8554,33 +8554,33 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x70: // LD (IY+d), B - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegBC.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegBC.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x71: // LD (IY+d), C - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegBC.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegBC.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x72: // LD (IY+d), D - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegDE.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegDE.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x73: // LD (IY+d), E - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegDE.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegDE.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x74: // LD (IY+d), H - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegHL.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegHL.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x75: // LD (IY+d), L - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegHL.Low); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegHL.Low); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x76: // HALT @@ -8588,8 +8588,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0x77: // LD (IY+d), A - Displacement = (sbyte)ReadMemory(RegPC.Word++); - WriteMemory((ushort)(RegIY.Word + Displacement), RegAF.High); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), RegAF.High); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x78: // LD A, B @@ -8617,8 +8617,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x7E: // LD A, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.High = ReadMemory((ushort)(RegIY.Word + Displacement)); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.High = ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)); totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x7F: // LD A, A @@ -8649,8 +8649,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x86: // ADD A, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[0, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x87: // ADD A, A @@ -8682,8 +8682,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x8E: // ADC A, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[1, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), RegFlagC ? 1 : 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), RegFlagC ? 1 : 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x8F: // ADC A, A @@ -8715,8 +8715,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x96: // SUB (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[2, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x97: // SUB A, A @@ -8748,8 +8748,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0x9E: // SBC A, (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[3, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), RegFlagC ? 1 : 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), RegFlagC ? 1 : 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0x9F: // SBC A, A @@ -8781,8 +8781,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xA6: // AND (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[4, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xA7: // AND A @@ -8814,8 +8814,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xAE: // XOR (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[5, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xAF: // XOR A @@ -8847,8 +8847,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xB6: // OR (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[6, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xB7: // OR A @@ -8880,8 +8880,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 9; pendingCycles -= 9; break; case 0xBE: // CP (IY+d) - Displacement = (sbyte)ReadMemory(RegPC.Word++); - RegAF.Word = TableALU[7, RegAF.High, ReadMemory((ushort)(RegIY.Word + Displacement)), 0]; + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)), 0]; totalExecutedCycles += 19; pendingCycles -= 19; break; case 0xBF: // CP A @@ -8891,7 +8891,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 case 0xC0: // RET NZ if (!RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -8900,11 +8900,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC1: // POP BC - RegBC.Low = ReadMemory(RegSP.Word++); RegBC.High = ReadMemory(RegSP.Word++); + RegBC.Low = ReadMemoryWrapper(RegSP.Word++); RegBC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC2: // JP NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { RegPC.Word = TUS; @@ -8912,14 +8912,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC3: // JP nn - RegPC.Word = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + RegPC.Word = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xC4: // CALL NZ, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -8929,22 +8929,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC5: // PUSH BC - WriteMemory(--RegSP.Word, RegBC.High); WriteMemory(--RegSP.Word, RegBC.Low); + WriteMemoryWrapper(--RegSP.Word, RegBC.High); WriteMemoryWrapper(--RegSP.Word, RegBC.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC6: // ADD A, n - RegAF.Word = TableALU[0, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[0, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xC7: // RST $00 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x00; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xC8: // RET Z if (RegFlagZ) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -8953,11 +8953,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xC9: // RET - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xCA: // JP Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { RegPC.Word = TUS; @@ -8965,396 +8965,396 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xCB: // (Prefix) - Displacement = (sbyte)ReadMemory(RegPC.Word++); + Displacement = (sbyte)ReadMemoryWrapper(RegPC.Word++); ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x01: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x02: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x03: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x04: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x05: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x06: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x07: // RLC (IY+d) - TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 0, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x08: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x09: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0A: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0B: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0C: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0D: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0E: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x0F: // RRC (IY+d) - TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 1, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x10: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x11: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x12: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x13: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x14: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x15: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x16: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x17: // RL (IY+d) - TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 2, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x18: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x19: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1A: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1B: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1C: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1D: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1E: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x1F: // RR (IY+d) - TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 3, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x20: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x21: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x22: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x23: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x24: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x25: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x26: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x27: // SLA (IY+d) - TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 4, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x28: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x29: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2A: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2B: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2C: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2D: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2E: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x2F: // SRA (IY+d) - TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 5, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x30: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x31: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x32: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x33: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x34: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x35: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x36: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x37: // SL1 (IY+d) - TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 6, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x38: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x39: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3A: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3B: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3C: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3D: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3E: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x3F: // SRL (IY+d) - TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemory((ushort)(RegIY.Word + Displacement))]; - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); + TUS = TableRotShift[1, 7, RegAF.Low + 256 * ReadMemoryWrapper((ushort)(RegIY.Word + Displacement))]; + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(TUS >> 8)); RegAF.Low = (byte)TUS; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x40: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9362,7 +9362,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x41: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9370,7 +9370,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x42: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9378,7 +9378,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x43: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9386,7 +9386,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x44: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9394,7 +9394,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x45: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9402,7 +9402,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x46: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9410,7 +9410,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x47: // BIT 0, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x01) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9418,7 +9418,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x48: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9426,7 +9426,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x49: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9434,7 +9434,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4A: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9442,7 +9442,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4B: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9450,7 +9450,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4C: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9458,7 +9458,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4D: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9466,7 +9466,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4E: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9474,7 +9474,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4F: // BIT 1, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x02) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9482,7 +9482,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x50: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9490,7 +9490,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x51: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9498,7 +9498,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x52: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9506,7 +9506,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x53: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9514,7 +9514,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x54: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9522,7 +9522,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x55: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9530,7 +9530,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x56: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9538,7 +9538,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x57: // BIT 2, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x04) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9546,7 +9546,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x58: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9554,7 +9554,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x59: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9562,7 +9562,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5A: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9570,7 +9570,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5B: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9578,7 +9578,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5C: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9586,7 +9586,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5D: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9594,7 +9594,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5E: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9602,7 +9602,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5F: // BIT 3, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x08) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9610,7 +9610,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x60: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9618,7 +9618,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x61: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9626,7 +9626,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x62: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9634,7 +9634,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x63: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9642,7 +9642,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x64: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9650,7 +9650,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x65: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9658,7 +9658,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x66: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9666,7 +9666,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x67: // BIT 4, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x10) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9674,7 +9674,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x68: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9682,7 +9682,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x69: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9690,7 +9690,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6A: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9698,7 +9698,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6B: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9706,7 +9706,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6C: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9714,7 +9714,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6D: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9722,7 +9722,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6E: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9730,7 +9730,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x6F: // BIT 5, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x20) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9738,7 +9738,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x70: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9746,7 +9746,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x71: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9754,7 +9754,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x72: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9762,7 +9762,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x73: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9770,7 +9770,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x74: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9778,7 +9778,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x75: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9786,7 +9786,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x76: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9794,7 +9794,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x77: // BIT 6, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x40) == 0; RegFlagP = RegFlagZ; RegFlagS = false; RegFlagH = true; @@ -9802,7 +9802,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x78: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9810,7 +9810,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x79: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9818,7 +9818,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7A: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9826,7 +9826,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7B: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9834,7 +9834,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7C: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9842,7 +9842,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7D: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9850,7 +9850,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7E: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9858,7 +9858,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7F: // BIT 7, (IY+d) - RegFlagZ = (ReadMemory((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; + RegFlagZ = (ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & 0x80) == 0; RegFlagP = RegFlagZ; RegFlagS = !RegFlagZ; RegFlagH = true; @@ -9866,524 +9866,524 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x80: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x81: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x82: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x83: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x84: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x85: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x86: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x87: // RES 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x88: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x89: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8A: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8B: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8C: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8D: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8E: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x8F: // RES 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x90: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x91: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x92: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x93: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x94: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x95: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x96: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x97: // RES 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x98: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x99: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9A: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9B: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9C: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9D: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9E: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0x9F: // RES 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA0: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA1: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA2: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA3: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA4: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA5: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA6: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA7: // RES 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA8: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xA9: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAA: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAB: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAC: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAD: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAE: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xAF: // RES 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB0: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB1: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB2: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB3: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB4: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB5: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB6: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB7: // RES 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB8: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xB9: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBA: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBB: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBC: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBD: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBE: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xBF: // RES 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) & unchecked((byte)~0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC0: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC1: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC2: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC3: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC4: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC5: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC6: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC7: // SET 0, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x01))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC8: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xC9: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCA: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCB: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCC: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCD: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCE: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xCF: // SET 1, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x02))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD0: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD1: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD2: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD3: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD4: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD5: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD6: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD7: // SET 2, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x04))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD8: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xD9: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDA: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDB: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDC: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDD: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDE: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xDF: // SET 3, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x08))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE0: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE1: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE2: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE3: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE4: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE5: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE6: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE7: // SET 4, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x10))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE8: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE9: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEA: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEB: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEC: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xED: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEE: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xEF: // SET 5, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x20))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF0: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF1: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF2: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF3: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF4: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF5: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF6: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF7: // SET 6, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x40))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF8: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xF9: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFA: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFB: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFC: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFD: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFE: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xFF: // SET 7, (IY+d) - WriteMemory((ushort)(RegIY.Word + Displacement), (byte)(ReadMemory((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); + WriteMemoryWrapper((ushort)(RegIY.Word + Displacement), (byte)(ReadMemoryWrapper((ushort)(RegIY.Word + Displacement)) | unchecked((byte)0x80))); totalExecutedCycles += 23; pendingCycles -= 23; break; } break; case 0xCC: // CALL Z, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagZ) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -10393,24 +10393,24 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xCD: // CALL nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; break; case 0xCE: // ADC A, n - RegAF.Word = TableALU[1, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[1, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xCF: // RST $08 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x08; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD0: // RET NC if (!RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -10419,11 +10419,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD1: // POP DE - RegDE.Low = ReadMemory(RegSP.Word++); RegDE.High = ReadMemory(RegSP.Word++); + RegDE.Low = ReadMemoryWrapper(RegSP.Word++); RegDE.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD2: // JP NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { RegPC.Word = TUS; @@ -10431,14 +10431,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xD3: // OUT n, A - WriteHardware(ReadMemory(RegPC.Word++), RegAF.High); + WriteHardware(ReadMemoryWrapper(RegPC.Word++), RegAF.High); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD4: // CALL NC, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -10448,22 +10448,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xD5: // PUSH DE - WriteMemory(--RegSP.Word, RegDE.High); WriteMemory(--RegSP.Word, RegDE.Low); + WriteMemoryWrapper(--RegSP.Word, RegDE.High); WriteMemoryWrapper(--RegSP.Word, RegDE.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD6: // SUB n - RegAF.Word = TableALU[2, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[2, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xD7: // RST $10 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x10; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xD8: // RET C if (RegFlagC) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -10478,7 +10478,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xDA: // JP C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { RegPC.Word = TUS; @@ -10486,14 +10486,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xDB: // IN A, n - RegAF.High = ReadHardware((ushort)ReadMemory(RegPC.Word++)); + RegAF.High = ReadHardware((ushort)ReadMemoryWrapper(RegPC.Word++)); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xDC: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -10507,18 +10507,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 1337; pendingCycles -= 1337; break; case 0xDE: // SBC A, n - RegAF.Word = TableALU[3, RegAF.High, ReadMemory(RegPC.Word++), RegFlagC ? 1 : 0]; + RegAF.Word = TableALU[3, RegAF.High, ReadMemoryWrapper(RegPC.Word++), RegFlagC ? 1 : 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xDF: // RST $18 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x18; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE0: // RET PO if (!RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -10527,11 +10527,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE1: // POP IY - RegIY.Low = ReadMemory(RegSP.Word++); RegIY.High = ReadMemory(RegSP.Word++); + RegIY.Low = ReadMemoryWrapper(RegSP.Word++); RegIY.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0xE2: // JP PO, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagP) { RegPC.Word = TUS; @@ -10539,16 +10539,16 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xE3: // EX (SP), IY - TUS = RegSP.Word; TBL = ReadMemory(TUS++); TBH = ReadMemory(TUS--); - WriteMemory(TUS++, RegIY.Low); WriteMemory(TUS, RegIY.High); + TUS = RegSP.Word; TBL = ReadMemoryWrapper(TUS++); TBH = ReadMemoryWrapper(TUS--); + WriteMemoryWrapper(TUS++, RegIY.Low); WriteMemoryWrapper(TUS, RegIY.High); RegIY.Low = TBL; RegIY.High = TBH; totalExecutedCycles += 23; pendingCycles -= 23; break; case 0xE4: // CALL C, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagC) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -10558,22 +10558,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xE5: // PUSH IY - WriteMemory(--RegSP.Word, RegIY.High); WriteMemory(--RegSP.Word, RegIY.Low); + WriteMemoryWrapper(--RegSP.Word, RegIY.High); WriteMemoryWrapper(--RegSP.Word, RegIY.Low); totalExecutedCycles += 15; pendingCycles -= 15; break; case 0xE6: // AND n - RegAF.Word = TableALU[4, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[4, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xE7: // RST $20 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x20; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xE8: // RET PE if (RegFlagP) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -10586,7 +10586,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0xEA: // JP PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { RegPC.Word = TUS; @@ -10598,10 +10598,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xEC: // CALL PE, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagP) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -10612,7 +10612,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 break; case 0xED: // (Prefix) ++RegR; - switch (ReadMemory(RegPC.Word++)) + switch (ReadMemoryWrapper(RegPC.Word++)) { case 0x00: // NOP totalExecutedCycles += 4; pendingCycles -= 4; @@ -10835,9 +10835,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x43: // LD (nn), BC - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegBC.Low); - WriteMemory(TUS, RegBC.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegBC.Low); + WriteMemoryWrapper(TUS, RegBC.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x44: // NEG @@ -10845,7 +10845,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x45: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -10886,8 +10886,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x4B: // LD BC, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegBC.Low = ReadMemory(TUS++); RegBC.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegBC.Low = ReadMemoryWrapper(TUS++); RegBC.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x4C: // NEG @@ -10895,7 +10895,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x4D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x4E: // IM $0 @@ -10935,9 +10935,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x53: // LD (nn), DE - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegDE.Low); - WriteMemory(TUS, RegDE.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegDE.Low); + WriteMemoryWrapper(TUS, RegDE.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x54: // NEG @@ -10945,7 +10945,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x55: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -10991,8 +10991,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x5B: // LD DE, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegDE.Low = ReadMemory(TUS++); RegDE.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegDE.Low = ReadMemoryWrapper(TUS++); RegDE.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x5C: // NEG @@ -11000,7 +11000,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x5D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x5E: // IM $2 @@ -11045,9 +11045,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x63: // LD (nn), HL - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegHL.Low); - WriteMemory(TUS, RegHL.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegHL.Low); + WriteMemoryWrapper(TUS, RegHL.High); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x64: // NEG @@ -11055,7 +11055,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x65: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -11064,8 +11064,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x67: // RRD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB2 >> 4) + (TB1 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 & 0x0F)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -11105,8 +11105,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x6B: // LD HL, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegHL.Low = ReadMemory(TUS++); RegHL.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegHL.Low = ReadMemoryWrapper(TUS++); RegHL.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 16; pendingCycles -= 16; break; case 0x6C: // NEG @@ -11114,7 +11114,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x6E: // IM $0 @@ -11122,8 +11122,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x6F: // RLD - TB1 = RegAF.High; TB2 = ReadMemory(RegHL.Word); - WriteMemory(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); + TB1 = RegAF.High; TB2 = ReadMemoryWrapper(RegHL.Word); + WriteMemoryWrapper(RegHL.Word, (byte)((TB1 & 0x0F) + (TB2 << 4))); RegAF.High = (byte)((TB1 & 0xF0) + (TB2 >> 4)); RegFlagS = RegAF.High > 127; RegFlagZ = RegAF.High == 0; @@ -11163,9 +11163,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x73: // LD (nn), SP - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - WriteMemory(TUS++, RegSP.Low); - WriteMemory(TUS, RegSP.High); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + WriteMemoryWrapper(TUS++, RegSP.Low); + WriteMemoryWrapper(TUS, RegSP.High); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x74: // NEG @@ -11173,7 +11173,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x75: // RETN - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); IFF1 = IFF2; totalExecutedCycles += 14; pendingCycles -= 14; break; @@ -11213,8 +11213,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 15; pendingCycles -= 15; break; case 0x7B: // LD SP, (nn) - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); - RegSP.Low = ReadMemory(TUS++); RegSP.High = ReadMemory(TUS); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); + RegSP.Low = ReadMemoryWrapper(TUS++); RegSP.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 20; pendingCycles -= 20; break; case 0x7C: // NEG @@ -11222,7 +11222,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 8; pendingCycles -= 8; break; case 0x7D: // RETI - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 14; pendingCycles -= 14; break; case 0x7E: // IM $2 @@ -11329,7 +11329,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA0: // LDI - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -11338,7 +11338,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA1: // CPI - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -11349,14 +11349,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA2: // INI - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA3: // OUTI - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11375,7 +11375,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xA8: // LDD - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -11384,7 +11384,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xA9: // CPD - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -11395,14 +11395,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAA: // IND - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; totalExecutedCycles += 16; pendingCycles -= 16; break; case 0xAB: // OUTD - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11421,7 +11421,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB0: // LDIR - WriteMemory(RegDE.Word++, TB1 = ReadMemory(RegHL.Word++)); + WriteMemoryWrapper(RegDE.Word++, TB1 = ReadMemoryWrapper(RegHL.Word++)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -11438,7 +11438,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB1: // CPIR - TB1 = ReadMemory(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word++); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -11457,7 +11457,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB2: // INIR - WriteMemory(RegHL.Word++, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word++, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11472,7 +11472,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB3: // OTIR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word++)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word++)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11499,7 +11499,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xB8: // LDDR - WriteMemory(RegDE.Word--, TB1 = ReadMemory(RegHL.Word--)); + WriteMemoryWrapper(RegDE.Word--, TB1 = ReadMemoryWrapper(RegHL.Word--)); TB1 += RegAF.High; RegFlag5 = (TB1 & 0x02) != 0; RegFlag3 = (TB1 & 0x08) != 0; --RegBC.Word; RegFlagP = RegBC.Word != 0; @@ -11516,7 +11516,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xB9: // CPDR - TB1 = ReadMemory(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); + TB1 = ReadMemoryWrapper(RegHL.Word--); TB2 = (byte)(RegAF.High - TB1); RegFlagN = true; RegFlagH = TableHalfBorrow[RegAF.High, TB1]; RegFlagZ = TB2 == 0; @@ -11535,7 +11535,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBA: // INDR - WriteMemory(RegHL.Word--, ReadHardware(RegBC.Word)); + WriteMemoryWrapper(RegHL.Word--, ReadHardware(RegBC.Word)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11550,7 +11550,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xBB: // OTDR - WriteHardware(RegBC.Word, ReadMemory(RegHL.Word--)); + WriteHardware(RegBC.Word, ReadMemoryWrapper(RegHL.Word--)); --RegBC.High; RegFlagZ = RegBC.High == 0; RegFlagN = true; @@ -11771,18 +11771,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xEE: // XOR n - RegAF.Word = TableALU[5, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[5, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xEF: // RST $28 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x28; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF0: // RET P if (!RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -11791,11 +11791,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF1: // POP AF - RegAF.Low = ReadMemory(RegSP.Word++); RegAF.High = ReadMemory(RegSP.Word++); + RegAF.Low = ReadMemoryWrapper(RegSP.Word++); RegAF.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xF2: // JP P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { RegPC.Word = TUS; @@ -11807,10 +11807,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xF4: // CALL P, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (!RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -11820,22 +11820,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 } break; case 0xF5: // PUSH AF - WriteMemory(--RegSP.Word, RegAF.High); WriteMemory(--RegSP.Word, RegAF.Low); + WriteMemoryWrapper(--RegSP.Word, RegAF.High); WriteMemoryWrapper(--RegSP.Word, RegAF.Low); totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF6: // OR n - RegAF.Word = TableALU[6, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[6, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xF7: // RST $30 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x30; totalExecutedCycles += 11; pendingCycles -= 11; break; case 0xF8: // RET M if (RegFlagS) { - RegPC.Low = ReadMemory(RegSP.Word++); RegPC.High = ReadMemory(RegSP.Word++); + RegPC.Low = ReadMemoryWrapper(RegSP.Word++); RegPC.High = ReadMemoryWrapper(RegSP.Word++); totalExecutedCycles += 11; pendingCycles -= 11; } else @@ -11848,7 +11848,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 10; pendingCycles -= 10; break; case 0xFA: // JP M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { RegPC.Word = TUS; @@ -11861,10 +11861,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 4; pendingCycles -= 4; break; case 0xFC: // CALL M, nn - TUS = (ushort)(ReadMemory(RegPC.Word++) + ReadMemory(RegPC.Word++) * 256); + TUS = (ushort)(ReadMemoryWrapper(RegPC.Word++) + ReadMemoryWrapper(RegPC.Word++) * 256); if (RegFlagS) { - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = TUS; totalExecutedCycles += 17; pendingCycles -= 17; } @@ -11878,22 +11878,22 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 1337; pendingCycles -= 1337; break; case 0xFE: // CP n - RegAF.Word = TableALU[7, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xFF: // RST $38 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x38; totalExecutedCycles += 11; pendingCycles -= 11; break; } break; case 0xFE: // CP n - RegAF.Word = TableALU[7, RegAF.High, ReadMemory(RegPC.Word++), 0]; + RegAF.Word = TableALU[7, RegAF.High, ReadMemoryWrapper(RegPC.Word++), 0]; totalExecutedCycles += 7; pendingCycles -= 7; break; case 0xFF: // RST $38 - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x38; totalExecutedCycles += 11; pendingCycles -= 11; break; @@ -11912,7 +11912,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 iff2 = iff1; iff1 = false; - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x66; NMICallback(); @@ -11930,14 +11930,14 @@ namespace BizHawk.Emulation.Cores.Components.Z80 totalExecutedCycles += 13; pendingCycles -= 13; break; case 1: - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); RegPC.Word = 0x38; totalExecutedCycles += 13; pendingCycles -= 13; break; case 2: TUS = (ushort)(RegI * 256 + 0); - WriteMemory(--RegSP.Word, RegPC.High); WriteMemory(--RegSP.Word, RegPC.Low); - RegPC.Low = ReadMemory(TUS++); RegPC.High = ReadMemory(TUS); + WriteMemoryWrapper(--RegSP.Word, RegPC.High); WriteMemoryWrapper(--RegSP.Word, RegPC.Low); + RegPC.Low = ReadMemoryWrapper(TUS++); RegPC.High = ReadMemoryWrapper(TUS); totalExecutedCycles += 19; pendingCycles -= 19; break; } @@ -11952,7 +11952,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80 public string State() { ushort tempPC = RegPC.Word; - string a = string.Format("{0:X4} {1:X2} {2} ", RegPC.Word, ReadMemory(RegPC.Word), Disassembler.Disassemble(() => ReadMemory(tempPC++)).PadRight(41)); + string a = string.Format("{0:X4} {1:X2} {2} ", RegPC.Word, ReadMemoryWrapper(RegPC.Word), Disassembler.Disassemble(() => ReadMemoryWrapper(tempPC++)).PadRight(41)); string b = string.Format("AF:{0:X4} BC:{1:X4} DE:{2:X4} HL:{3:X4} IX:{4:X4} IY:{5:X4} SP:{6:X4} Cy:{7}", RegAF.Word, RegBC.Word, RegDE.Word, RegHL.Word, RegIX.Word, RegIY.Word, RegSP.Word, TotalExecutedCycles); string val = a + b + " "; diff --git a/BizHawk.Emulation.Cores/CPUs/Z80/Z80A.cs b/BizHawk.Emulation.Cores/CPUs/Z80/Z80A.cs index dc37155efd..2b62f94a13 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80/Z80A.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80/Z80A.cs @@ -38,6 +38,26 @@ namespace BizHawk.Emulation.Cores.Components.Z80 public Func ReadMemory; public Action WriteMemory; + public byte ReadMemoryWrapper(ushort addr) + { + if (MemoryCallbacks != null) + { + MemoryCallbacks.CallReads(addr); + } + + return ReadMemory(addr); + } + + public void WriteMemoryWrapper(ushort addr, byte value) + { + if (MemoryCallbacks != null) + { + MemoryCallbacks.CallWrites(addr); + } + + WriteMemory(addr, value); + } + public IMemoryCallbackSystem MemoryCallbacks { get; set; } // Utility function, not used by core diff --git a/BizHawk.Emulation.Cores/Calculator/TI83.cs b/BizHawk.Emulation.Cores/Calculator/TI83.cs index 819dcca181..272515cbbf 100644 --- a/BizHawk.Emulation.Cores/Calculator/TI83.cs +++ b/BizHawk.Emulation.Cores/Calculator/TI83.cs @@ -97,8 +97,6 @@ namespace BizHawk.Emulation.Cores.Calculators ret = rom[romPage * 0x4000 + addr - 0x4000]; //other rom page else ret = ram[addr - 0x8000]; - MemoryCallbacks.CallReads(addr); - return ret; } @@ -109,8 +107,6 @@ namespace BizHawk.Emulation.Cores.Calculators else if (addr < 0x8000) return; //other rom page else ram[addr - 0x8000] = value; - - MemoryCallbacks.CallWrites(addr); } public void WriteHardware(ushort addr, byte value) diff --git a/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.ExtRam.cs b/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.ExtRam.cs index 4262cd9319..dd78244898 100644 --- a/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.ExtRam.cs +++ b/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.ExtRam.cs @@ -16,7 +16,6 @@ else ret = SystemRam[address & RamSizeMask]; - MemoryCallbacks.CallReads(address); return ret; } @@ -26,8 +25,6 @@ ExtRam[address & ExtRamMask] = value; else if (address >= 0xC000) SystemRam[address & RamSizeMask] = value; - - MemoryCallbacks.CallWrites((uint)address); } void InitExt2kMapper(int size) diff --git a/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.Sega.cs b/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.Sega.cs index 77f253ff4c..0f1a30d1d3 100644 --- a/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.Sega.cs +++ b/BizHawk.Emulation.Cores/Consoles/Sega/SMS/MemoryMap.Sega.cs @@ -53,8 +53,6 @@ ret = SystemRam[address & RamSizeMask]; } - MemoryCallbacks.CallReads(address); - return ret; } @@ -91,7 +89,6 @@ else if (address == 0xFFFF) RomBank2 = (byte)(value % RomBanks); return; } - MemoryCallbacks.CallWrites((uint)address); } void InitSegaMapper()