template for plus3 (but not implemented yet)
This commit is contained in:
Asnivor
parent
27ba7e0008
commit
85d38a3379
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@ -54,6 +54,7 @@ namespace BizHawk.Emulation.Common
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FirmwareAndOption("5EA7C2B824672E914525D1D5C419D71B84A426A2", 16384, "ZXSpectrum", "48ROM", "48.ROM", "Spectrum 48K ROM");
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FirmwareAndOption("16375D42EA109B47EDDED7A16028DE7FDB3013A1", 32768, "ZXSpectrum", "128ROM", "128.ROM", "Spectrum 128K ROM");
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FirmwareAndOption("8CAFB292AF58617907B9E6B9093D3588A75849B8", 32768, "ZXSpectrum", "PLUS2ROM", "PLUS2.ROM", "Spectrum 128K +2 ROM");
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FirmwareAndOption("929BF1A5E5687EBD8D7245F9B513A596C0EC21A4", 65563, "ZXSpectrum", "PLUS3ROM", "PLUS3.ROM", "Spectrum 128K +3 ROM");
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// for saturn, we think any bios region can pretty much run any iso
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// so, we're going to lay this out carefully so that we choose things in a sensible order, but prefer the correct region
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@ -277,6 +277,9 @@
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<Compile Include="Computers\SinclairSpectrum\Machine\SpectrumBase.Memory.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\SpectrumBase.Sound.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128KPlus2\ZX128Plus2.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128KPlus3\ZX128Plus3.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128KPlus3\ZX128Plus3.Memory.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128KPlus3\ZX128Plus3.Port.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128K\ZX128.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128K\ZX128.Memory.cs" />
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<Compile Include="Computers\SinclairSpectrum\Machine\ZXSpectrum128K\ZX128.Port.cs" />
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@ -0,0 +1,284 @@
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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{
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public partial class ZX128Plus3 : SpectrumBase
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{
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/* 128k paging controlled by writes to port 0x7ffd
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*
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*
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#7FFD (32765) - decoded as A15=0, A1=0 and /IORQ=0. Bits 0..5 are latched. Bits 0..2 select RAM bank in secton D. Bit 3 selects RAM bank to dispay screen (0 - RAM5, 1 - RAM7). Bit 4 selects ROM bank (0 - ROM0, 1 - ROM1). Bit 5, when set locks future writing to #7FFD port until reset. Reading #7FFD port is the same as writing #FF into it.
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#BFFD (49149) - write data byte into AY-3-8912 chip.
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#FFFD (65533) - select AY-3-8912 addres (D4..D7 ignored) and reading data byte.
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* 0xffff +--------+--------+--------+--------+--------+--------+--------+--------+
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| Bank 0 | Bank 1 | Bank 2 | Bank 3 | Bank 4 | Bank 5 | Bank 6 | Bank 7 |
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| | |(also at| | |(also at| | |
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| | | 0x8000)| | | 0x4000)| | |
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| | | | | | screen | | screen |
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0xc000 +--------+--------+--------+--------+--------+--------+--------+--------+
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| Bank 2 | Any one of these pages may be switched in.
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| |
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0x8000 +--------+
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| Bank 5 |
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| |
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| screen |
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0x4000 +--------+--------+
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| ROM 0 | ROM 1 | Either ROM may be switched in.
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| | |
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| | |
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| | |
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0x0000 +--------+--------+
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*/
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/// <summary>
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/// Simulates reading from the bus (no contention)
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/// Paging should be handled here
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/// </summary>
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/// <param name="addr"></param>
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/// <returns></returns>
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public override byte ReadBus(ushort addr)
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{
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int divisor = addr / 0x4000;
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byte result = 0xff;
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switch (divisor)
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{
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// ROM 0x000
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case 0:
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if (!ROMPaged)
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result = Memory[0][addr % 0x4000];
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else
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result = Memory[1][addr % 0x4000];
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break;
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// RAM 0x4000 (RAM5 - Bank5 or shadow bank RAM7)
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case 1:
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result = Memory[7][addr % 0x4000];
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break;
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// RAM 0x8000 (RAM2 - Bank2)
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case 2:
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result = Memory[4][addr % 0x4000];
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break;
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// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
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case 3:
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switch (RAMPaged)
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{
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case 0:
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result = Memory[2][addr % 0x4000];
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break;
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case 1:
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result = Memory[3][addr % 0x4000];
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break;
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case 2:
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result = Memory[4][addr % 0x4000];
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break;
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case 3:
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result = Memory[5][addr % 0x4000];
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break;
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case 4:
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result = Memory[6][addr % 0x4000];
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break;
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case 5:
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result = Memory[7][addr % 0x4000];
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break;
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case 6:
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result = Memory[8][addr % 0x4000];
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break;
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case 7:
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result = Memory[9][addr % 0x4000];
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break;
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}
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break;
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default:
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break;
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}
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return result;
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}
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/// <summary>
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/// Simulates writing to the bus (no contention)
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/// Paging should be handled here
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/// </summary>
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/// <param name="addr"></param>
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/// <param name="value"></param>
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public override void WriteBus(ushort addr, byte value)
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{
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int divisor = addr / 0x4000;
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switch (divisor)
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{
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// ROM 0x000
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case 0:
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if (!ROMPaged)
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Memory[0][addr % 0x4000] = value;
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else
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Memory[1][addr % 0x4000] = value;
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break;
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// RAM 0x4000 (RAM5 - Bank5 or shadow bank RAM7)
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case 1:
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Memory[7][addr % 0x4000] = value;
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break;
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// RAM 0x8000 (RAM2 - Bank2)
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case 2:
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Memory[4][addr % 0x4000] = value;
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break;
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// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
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case 3:
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switch (RAMPaged)
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{
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case 0:
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Memory[2][addr % 0x4000] = value;
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break;
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case 1:
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Memory[3][addr % 0x4000] = value;
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break;
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case 2:
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Memory[4][addr % 0x4000] = value;
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break;
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case 3:
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Memory[5][addr % 0x4000] = value;
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break;
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case 4:
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Memory[6][addr % 0x4000] = value;
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break;
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case 5:
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Memory[7][addr % 0x4000] = value;
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break;
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case 6:
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Memory[8][addr % 0x4000] = value;
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break;
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case 7:
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Memory[9][addr % 0x4000] = value;
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break;
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}
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break;
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default:
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break;
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}
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}
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/// <summary>
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/// Reads a byte of data from a specified memory address
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/// (with memory contention if appropriate)
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/// </summary>
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/// <param name="addr"></param>
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/// <returns></returns>
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public override byte ReadMemory(ushort addr)
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{
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var data = ReadBus(addr);
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if ((addr & 0xC000) == 0x4000)
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{
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// addr is in RAM not ROM - apply memory contention if neccessary
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var delay = GetContentionValue(CurrentFrameCycle);
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CPU.TotalExecutedCycles += delay;
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}
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return data;
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}
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/// <summary>
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/// Writes a byte of data to a specified memory address
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/// (with memory contention if appropriate)
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/// </summary>
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/// <param name="addr"></param>
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/// <param name="value"></param>
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public override void WriteMemory(ushort addr, byte value)
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{
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if (addr < 0x4000)
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{
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// Do nothing - we cannot write to ROM
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return;
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}
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else if (addr < 0xC000)
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{
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// possible contended RAM
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var delay = GetContentionValue(CurrentFrameCycle);
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CPU.TotalExecutedCycles += delay;
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}
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WriteBus(addr, value);
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}
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public override void ReInitMemory()
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{
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if (Memory.ContainsKey(0))
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Memory[0] = ROM0;
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else
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Memory.Add(0, ROM0);
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if (Memory.ContainsKey(1))
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Memory[1] = ROM1;
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else
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Memory.Add(1, ROM1);
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if (Memory.ContainsKey(2))
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Memory[2] = RAM0;
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else
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Memory.Add(2, RAM0);
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if (Memory.ContainsKey(3))
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Memory[3] = RAM1;
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else
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Memory.Add(3, RAM1);
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if (Memory.ContainsKey(4))
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Memory[4] = RAM2;
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else
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Memory.Add(4, RAM2);
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if (Memory.ContainsKey(5))
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Memory[5] = RAM3;
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else
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Memory.Add(5, RAM3);
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if (Memory.ContainsKey(6))
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Memory[6] = RAM4;
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else
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Memory.Add(6, RAM4);
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if (Memory.ContainsKey(7))
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Memory[7] = RAM5;
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else
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Memory.Add(7, RAM5);
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if (Memory.ContainsKey(8))
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Memory[8] = RAM6;
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else
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Memory.Add(8, RAM6);
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if (Memory.ContainsKey(9))
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Memory[9] = RAM7;
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else
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Memory.Add(9, RAM7);
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}
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/// <summary>
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/// Sets up the ROM
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/// </summary>
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/// <param name="buffer"></param>
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/// <param name="startAddress"></param>
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public override void InitROM(RomData romData)
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{
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RomData = romData;
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// 128k uses ROM0 and ROM1
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// 128k loader is in ROM0, and fallback 48k rom is in ROM1
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for (int i = 0; i < 0x4000; i++)
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{
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ROM0[i] = RomData.RomBytes[i];
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ROM1[i] = RomData.RomBytes[i + 0x4000];
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}
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}
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}
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}
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@ -0,0 +1,188 @@
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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{
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public partial class ZX128Plus3 : SpectrumBase
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{
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/// <summary>
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/// Reads a byte of data from a specified port address
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/// </summary>
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/// <param name="port"></param>
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/// <returns></returns>
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public override byte ReadPort(ushort port)
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{
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int result = 0xFF;
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// Check whether the low bit is reset
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// Technically the ULA should respond to every even I/O address
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bool lowBitReset = (port & 0x0001) == 0;
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ContendPort((ushort)port);
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// Kempston Joystick
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if ((port & 0xe0) == 0 || (port & 0x20) == 0)
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{
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return (byte)KempstonDevice.JoyLine;
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}
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else if (lowBitReset)
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{
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// Even I/O address so get input
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// The high byte indicates which half-row of keys is being polled
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/*
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IN: Reads keys (bit 0 to bit 4 inclusive)
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0xfefe SHIFT, Z, X, C, V 0xeffe 0, 9, 8, 7, 6
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0xfdfe A, S, D, F, G 0xdffe P, O, I, U, Y
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0xfbfe Q, W, E, R, T 0xbffe ENTER, L, K, J, H
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0xf7fe 1, 2, 3, 4, 5 0x7ffe SPACE, SYM SHFT, M, N, B
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*/
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if ((port & 0x8000) == 0)
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result &= KeyboardDevice.KeyLine[7];
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if ((port & 0x4000) == 0)
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result &= KeyboardDevice.KeyLine[6];
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if ((port & 0x2000) == 0)
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result &= KeyboardDevice.KeyLine[5];
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if ((port & 0x1000) == 0)
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result &= KeyboardDevice.KeyLine[4];
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if ((port & 0x800) == 0)
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result &= KeyboardDevice.KeyLine[3];
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if ((port & 0x400) == 0)
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result &= KeyboardDevice.KeyLine[2];
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if ((port & 0x200) == 0)
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result &= KeyboardDevice.KeyLine[1];
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if ((port & 0x100) == 0)
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result &= KeyboardDevice.KeyLine[0];
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result = result & 0x1f; //mask out lower 4 bits
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result = result | 0xa0; //set bit 5 & 7 to 1
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if (TapeDevice.CurrentMode == TapeOperationMode.Load)
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{
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if (!TapeDevice.GetEarBit(CPU.TotalExecutedCycles))
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{
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result &= ~(TAPE_BIT); // reset is EAR ON
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}
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else
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{
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result |= (TAPE_BIT); // set is EAR Off
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}
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}
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else
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{
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if (KeyboardDevice.IsIssue2Keyboard)
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{
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if ((LastULAOutByte & (EAR_BIT + MIC_BIT)) == 0)
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{
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result &= ~(TAPE_BIT);
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}
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else
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{
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result |= TAPE_BIT;
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}
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}
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else
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{
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if ((LastULAOutByte & EAR_BIT) == 0)
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{
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result &= ~(TAPE_BIT);
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}
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else
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{
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result |= TAPE_BIT;
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}
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}
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}
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}
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else
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{
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// devices other than the ULA will respond here
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// (e.g. the AY sound chip in a 128k spectrum
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// AY register activate
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// Kemptson Mouse
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// if unused port the floating memory bus should be returned (still todo)
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}
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return (byte)result;
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}
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/// <summary>
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/// Writes a byte of data to a specified port address
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/// </summary>
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/// <param name="port"></param>
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/// <param name="value"></param>
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public override void WritePort(ushort port, byte value)
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{
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// paging
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if (port == 0x7ffd)
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{
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// Bits 0, 1, 2 select the RAM page
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var rp = value & 0x07;
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if (rp < 8)
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RAMPaged = rp;
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// ROM page
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if ((value & 0x10) != 0)
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{
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// 48k ROM
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ROMPaged = true;
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}
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else
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{
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ROMPaged = false;
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}
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// Bit 5 signifies that paging is disabled until next reboot
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if ((value & 0x20) != 0)
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PagingDisabled = true;
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return;
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}
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// Check whether the low bit is reset
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// Technically the ULA should respond to every even I/O address
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bool lowBitReset = (port & 0x01) == 0;
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ContendPort(port);
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// Only even addresses address the ULA
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if (lowBitReset)
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{
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// store the last OUT byte
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LastULAOutByte = value;
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/*
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Bit 7 6 5 4 3 2 1 0
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+-------------------------------+
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| | | | E | M | Border |
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+-------------------------------+
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*/
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// Border - LSB 3 bits hold the border colour
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BorderColour = value & BORDER_BIT;
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// Buzzer
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BuzzerDevice.ProcessPulseValue(false, (value & EAR_BIT) != 0);
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// Tape
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TapeDevice.ProcessMicBit((value & MIC_BIT) != 0);
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}
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}
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}
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}
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@ -0,0 +1,56 @@
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using BizHawk.Emulation.Cores.Components.Z80A;
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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||||
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namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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{
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public partial class ZX128Plus3 : SpectrumBase
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{
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#region Construction
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/// <summary>
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/// Main constructor
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/// </summary>
|
||||
/// <param name="spectrum"></param>
|
||||
/// <param name="cpu"></param>
|
||||
public ZX128Plus3(ZXSpectrum spectrum, Z80A cpu, byte[] file)
|
||||
{
|
||||
Spectrum = spectrum;
|
||||
CPU = cpu;
|
||||
|
||||
ROMPaged = false;
|
||||
SHADOWPaged = false;
|
||||
RAMPaged = 0;
|
||||
PagingDisabled = false;
|
||||
|
||||
// init addressable memory from ROM and RAM banks
|
||||
ReInitMemory();
|
||||
|
||||
//RAM = new byte[0x4000 + 0xC000];
|
||||
|
||||
//DisplayLineTime = 132;
|
||||
VsyncNumerator = 3546900;
|
||||
|
||||
InitScreenConfig();
|
||||
InitScreen();
|
||||
|
||||
ResetULACycle();
|
||||
|
||||
BuzzerDevice = new Buzzer(this);
|
||||
BuzzerDevice.Init(44100, UlaFrameCycleCount);
|
||||
|
||||
KeyboardDevice = new Keyboard48(this);
|
||||
KempstonDevice = new KempstonJoystick(this);
|
||||
|
||||
TapeProvider = new DefaultTapeProvider(file);
|
||||
|
||||
TapeDevice = new Tape(TapeProvider);
|
||||
TapeDevice.Init(this);
|
||||
}
|
||||
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue