CDL - finish SMS memory maps, mostly
This commit is contained in:
parent
642f965685
commit
8497c25414
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@ -9,7 +9,10 @@ namespace BizHawk.Emulation.Cores.Sega.MasterSystem
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enum CDLog_AddrType
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enum CDLog_AddrType
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{
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{
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None,
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None,
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ROM, MainRAM, SaveRAM, CartRAM,
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ROM,
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MainRAM,
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SaveRAM,
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CartRAM, //"Cart (Volatile) RAM" aka ExtRam
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}
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}
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[Flags]
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[Flags]
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@ -20,6 +20,14 @@
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return SystemRam[address & RamSizeMask];
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return SystemRam[address & RamSizeMask];
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}
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}
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CDLog_MapResults MapMemoryCM(ushort address, bool write)
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{
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if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
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else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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void WriteMemoryCM(ushort address, byte value)
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void WriteMemoryCM(ushort address, byte value)
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{
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{
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if (address >= 0xC000)
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if (address >= 0xC000)
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@ -34,6 +42,7 @@
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{
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{
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ReadMemory = ReadMemoryCM;
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ReadMemory = ReadMemoryCM;
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WriteMemory = WriteMemoryCM;
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WriteMemory = WriteMemoryCM;
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MapMemory = MapMemoryCM;
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WriteMemoryCM(0x0000, 0);
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WriteMemoryCM(0x0000, 0);
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WriteMemoryCM(0x4000, 1);
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WriteMemoryCM(0x4000, 1);
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WriteMemoryCM(0x8000, 0);
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WriteMemoryCM(0x8000, 0);
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@ -63,6 +72,25 @@
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return SystemRam[address & RamSizeMask];
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return SystemRam[address & RamSizeMask];
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}
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}
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CDLog_MapResults MapMemoryCMRam(ushort address, bool write)
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{
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if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0x8000)
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{
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if (address >= 0x6000 && RomBank3 == 1)
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return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & 0x1FFF };
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else
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
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}
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else if (address < 0xC000)
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{
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if (address >= 0xA000 && RomBank3 == 1)
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return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & 0x1FFF };
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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}
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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void WriteMemoryCMRam(ushort address, byte value)
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void WriteMemoryCMRam(ushort address, byte value)
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{
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{
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if (address >= 0xC000)
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if (address >= 0xC000)
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@ -87,6 +115,7 @@
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{
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{
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ReadMemory = ReadMemoryCMRam;
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ReadMemory = ReadMemoryCMRam;
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WriteMemory = WriteMemoryCMRam;
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WriteMemory = WriteMemoryCMRam;
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MapMemory = MapMemoryCMRam;
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WriteMemoryCM(0x0000, 0);
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WriteMemoryCM(0x0000, 0);
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WriteMemoryCM(0x4000, 1);
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WriteMemoryCM(0x4000, 1);
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WriteMemoryCM(0x8000, 0);
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WriteMemoryCM(0x8000, 0);
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@ -19,6 +19,13 @@
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return ret;
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return ret;
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}
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}
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CDLog_MapResults MapMemoryExt(ushort address, bool write)
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{
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if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & ExtRamMask };
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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void WriteMemoryExt(ushort address, byte value)
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void WriteMemoryExt(ushort address, byte value)
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{
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{
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if (address < 0xC000 && address >= 0x8000)
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if (address < 0xC000 && address >= 0x8000)
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@ -33,6 +40,7 @@
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ExtRamMask = size - 1;
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ExtRamMask = size - 1;
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ReadMemory = ReadMemoryExt;
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ReadMemory = ReadMemoryExt;
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WriteMemory = WriteMemoryExt;
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WriteMemory = WriteMemoryExt;
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MapMemory = MapMemoryExt;
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}
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}
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}
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}
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}
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}
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@ -13,6 +13,13 @@
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return SystemRam[address & RamSizeMask];
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return SystemRam[address & RamSizeMask];
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}
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}
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CDLog_MapResults MapMemoryKR(ushort address, bool write)
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{
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if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x7FFF };
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else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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void WriteMemoryKR(ushort address, byte value)
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void WriteMemoryKR(ushort address, byte value)
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{
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{
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if (address >= 0xC000)
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if (address >= 0xC000)
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@ -25,6 +32,7 @@
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{
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{
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ReadMemory = ReadMemoryKR;
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ReadMemory = ReadMemoryKR;
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WriteMemory = WriteMemoryKR;
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WriteMemory = WriteMemoryKR;
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MapMemory = MapMemoryKR;
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RomBank0 = 0;
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RomBank0 = 0;
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RomBank1 = 1;
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RomBank1 = 1;
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RomBank2 = 0;
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RomBank2 = 0;
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@ -44,6 +52,16 @@
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return SystemRam[address & RamSizeMask];
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return SystemRam[address & RamSizeMask];
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}
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}
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CDLog_MapResults MapMemoryMSX(ushort address, bool write)
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{
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if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x3FFF };
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if (address < 0x6000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * 0x2000) + (address & 0x1FFF) };
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if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * 0x2000) + (address & 0x1FFF) };
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if (address < 0xA000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * 0x2000) + (address & 0x1FFF) };
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if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank3 * 0x2000) + (address & 0x1FFF) };
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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byte ReadMemoryNemesis(ushort address)
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byte ReadMemoryNemesis(ushort address)
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{
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{
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if (address < 0x2000) return RomData[(15 * 0x2000) + (address & 0x1FFF)];
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if (address < 0x2000) return RomData[(15 * 0x2000) + (address & 0x1FFF)];
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@ -55,6 +73,17 @@
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return SystemRam[address & RamSizeMask];
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return SystemRam[address & RamSizeMask];
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}
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}
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CDLog_MapResults MapMemoryNemesis(ushort address, bool write)
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{
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if (address < 0x2000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (15 * 0x2000) + (address & 0x1FFF) };
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if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x3FFF };
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if (address < 0x6000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * 0x2000) + (address & 0x1FFF) };
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if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * 0x2000) + (address & 0x1FFF) };
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if (address < 0xA000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * 0x2000) + (address & 0x1FFF) };
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if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank3 * 0x2000) + (address & 0x1FFF) };
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else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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void WriteMemoryMSX(ushort address, byte value)
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void WriteMemoryMSX(ushort address, byte value)
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{
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{
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if (address >= 0xC000)
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if (address >= 0xC000)
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@ -74,6 +103,7 @@
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{
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{
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ReadMemory = ReadMemoryMSX;
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ReadMemory = ReadMemoryMSX;
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WriteMemory = WriteMemoryMSX;
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WriteMemory = WriteMemoryMSX;
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ReadMemory = ReadMemoryMSX;
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RomBank0 = 0;
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RomBank0 = 0;
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RomBank1 = 0;
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RomBank1 = 0;
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RomBank2 = 0;
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RomBank2 = 0;
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@ -84,6 +114,7 @@
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{
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{
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InitMSXMapper();
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InitMSXMapper();
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ReadMemory = ReadMemoryNemesis;
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ReadMemory = ReadMemoryNemesis;
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MapMemory = MapMemoryNemesis;
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}
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}
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}
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}
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}
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}
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@ -56,6 +56,42 @@
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return ret;
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return ret;
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}
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}
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CDLog_MapResults MapMemorySega(ushort address, bool write)
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{
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if (address < 0xC000)
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{
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if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
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return new CDLog_MapResults();
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else if (BiosMapped && BiosRom != null)
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return new CDLog_MapResults(); //bios tracking of CDL is not supported
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else if (address < 1024)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0x4000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * BankSize) + address };
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else if (address < 0x8000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
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else
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{
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switch (SaveRamBank)
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{
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case 0: return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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case 1:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (address & BankSizeMask) % SaveRAM.Length };
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else return new CDLog_MapResults();
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case 2:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (BankSize + (address & BankSizeMask)) & BankSizeMask };
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else return new CDLog_MapResults();
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default:
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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}
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else
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{
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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void WriteMemorySega(ushort address, byte value)
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void WriteMemorySega(ushort address, byte value)
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{
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{
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if (address >= 0xC000)
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if (address >= 0xC000)
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@ -91,42 +127,6 @@
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}
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}
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}
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}
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CDLog_MapResults MapMemorySega(ushort address, bool write)
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{
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if (address < 0xC000)
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{
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if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
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return new CDLog_MapResults();
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else if (BiosMapped && BiosRom != null)
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return new CDLog_MapResults(); //bios tracking of CDL is not supported
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else if (address < 1024)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
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else if (address < 0x4000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * BankSize) + address };
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else if (address < 0x8000)
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return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + address };
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else
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{
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switch (SaveRamBank)
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{
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case 0: return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
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case 1:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (address & BankSizeMask) % SaveRAM.Length };
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else return new CDLog_MapResults();
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case 2:
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if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (BankSize + (address & BankSizeMask)) & BankSizeMask };
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else return new CDLog_MapResults();
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default:
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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}
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else
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{
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return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
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}
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}
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void InitSegaMapper()
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void InitSegaMapper()
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{
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{
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ReadMemory = ReadMemorySega;
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ReadMemory = ReadMemorySega;
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@ -2,12 +2,7 @@
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{
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{
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public partial class SMS
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public partial class SMS
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{
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{
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// The CodeMasters mapper has 3 banks of 16kb, like the Sega mapper.
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//This doesn't look functional. Illogical and nothing like http://www.smspower.org/Articles/TerebiOekaki
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// The differences are that the paging control addresses are different, and the first 1K of ROM is not protected.
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// Bank 0: Control Address $0000 - Maps $0000 - $3FFF
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// Bank 1: Control Address $4000 - Maps $4000 - $7FFF
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// Bank 2: Control Address $8000 - Maps $8000 - $BFFF
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// System RAM is at $C000+ as in the Sega mapper.
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byte xCoord = 128;
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byte xCoord = 128;
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byte yCoord = 100;
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byte yCoord = 100;
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void InitTerebiOekaki()
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void InitTerebiOekaki()
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{
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{
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Cpu.ReadMemory = ReadMemoryTO;
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ReadMemory = ReadMemoryTO;
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Cpu.WriteMemory = WriteMemoryTO;
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WriteMemory = WriteMemoryTO;
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}
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}
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}
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}
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}
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}
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