CDL - finish SMS memory maps, mostly

This commit is contained in:
zeromus 2015-11-01 10:44:36 -06:00
parent 642f965685
commit 8497c25414
6 changed files with 111 additions and 45 deletions

View File

@ -9,7 +9,10 @@ namespace BizHawk.Emulation.Cores.Sega.MasterSystem
enum CDLog_AddrType enum CDLog_AddrType
{ {
None, None,
ROM, MainRAM, SaveRAM, CartRAM, ROM,
MainRAM,
SaveRAM,
CartRAM, //"Cart (Volatile) RAM" aka ExtRam
} }
[Flags] [Flags]

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@ -20,6 +20,14 @@
return SystemRam[address & RamSizeMask]; return SystemRam[address & RamSizeMask];
} }
CDLog_MapResults MapMemoryCM(ushort address, bool write)
{
if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
else if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
void WriteMemoryCM(ushort address, byte value) void WriteMemoryCM(ushort address, byte value)
{ {
if (address >= 0xC000) if (address >= 0xC000)
@ -34,6 +42,7 @@
{ {
ReadMemory = ReadMemoryCM; ReadMemory = ReadMemoryCM;
WriteMemory = WriteMemoryCM; WriteMemory = WriteMemoryCM;
MapMemory = MapMemoryCM;
WriteMemoryCM(0x0000, 0); WriteMemoryCM(0x0000, 0);
WriteMemoryCM(0x4000, 1); WriteMemoryCM(0x4000, 1);
WriteMemoryCM(0x8000, 0); WriteMemoryCM(0x8000, 0);
@ -63,6 +72,25 @@
return SystemRam[address & RamSizeMask]; return SystemRam[address & RamSizeMask];
} }
CDLog_MapResults MapMemoryCMRam(ushort address, bool write)
{
if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
else if (address < 0x8000)
{
if (address >= 0x6000 && RomBank3 == 1)
return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & 0x1FFF };
else
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
}
else if (address < 0xC000)
{
if (address >= 0xA000 && RomBank3 == 1)
return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & 0x1FFF };
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
}
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
void WriteMemoryCMRam(ushort address, byte value) void WriteMemoryCMRam(ushort address, byte value)
{ {
if (address >= 0xC000) if (address >= 0xC000)
@ -87,6 +115,7 @@
{ {
ReadMemory = ReadMemoryCMRam; ReadMemory = ReadMemoryCMRam;
WriteMemory = WriteMemoryCMRam; WriteMemory = WriteMemoryCMRam;
MapMemory = MapMemoryCMRam;
WriteMemoryCM(0x0000, 0); WriteMemoryCM(0x0000, 0);
WriteMemoryCM(0x4000, 1); WriteMemoryCM(0x4000, 1);
WriteMemoryCM(0x8000, 0); WriteMemoryCM(0x8000, 0);

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@ -19,6 +19,13 @@
return ret; return ret;
} }
CDLog_MapResults MapMemoryExt(ushort address, bool write)
{
if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.CartRAM, Address = address & ExtRamMask };
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
void WriteMemoryExt(ushort address, byte value) void WriteMemoryExt(ushort address, byte value)
{ {
if (address < 0xC000 && address >= 0x8000) if (address < 0xC000 && address >= 0x8000)
@ -33,6 +40,7 @@
ExtRamMask = size - 1; ExtRamMask = size - 1;
ReadMemory = ReadMemoryExt; ReadMemory = ReadMemoryExt;
WriteMemory = WriteMemoryExt; WriteMemory = WriteMemoryExt;
MapMemory = MapMemoryExt;
} }
} }
} }

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@ -13,6 +13,13 @@
return SystemRam[address & RamSizeMask]; return SystemRam[address & RamSizeMask];
} }
CDLog_MapResults MapMemoryKR(ushort address, bool write)
{
if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x7FFF };
else if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
void WriteMemoryKR(ushort address, byte value) void WriteMemoryKR(ushort address, byte value)
{ {
if (address >= 0xC000) if (address >= 0xC000)
@ -25,6 +32,7 @@
{ {
ReadMemory = ReadMemoryKR; ReadMemory = ReadMemoryKR;
WriteMemory = WriteMemoryKR; WriteMemory = WriteMemoryKR;
MapMemory = MapMemoryKR;
RomBank0 = 0; RomBank0 = 0;
RomBank1 = 1; RomBank1 = 1;
RomBank2 = 0; RomBank2 = 0;
@ -44,6 +52,16 @@
return SystemRam[address & RamSizeMask]; return SystemRam[address & RamSizeMask];
} }
CDLog_MapResults MapMemoryMSX(ushort address, bool write)
{
if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x3FFF };
if (address < 0x6000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * 0x2000) + (address & 0x1FFF) };
if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * 0x2000) + (address & 0x1FFF) };
if (address < 0xA000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * 0x2000) + (address & 0x1FFF) };
if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank3 * 0x2000) + (address & 0x1FFF) };
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
byte ReadMemoryNemesis(ushort address) byte ReadMemoryNemesis(ushort address)
{ {
if (address < 0x2000) return RomData[(15 * 0x2000) + (address & 0x1FFF)]; if (address < 0x2000) return RomData[(15 * 0x2000) + (address & 0x1FFF)];
@ -55,6 +73,17 @@
return SystemRam[address & RamSizeMask]; return SystemRam[address & RamSizeMask];
} }
CDLog_MapResults MapMemoryNemesis(ushort address, bool write)
{
if (address < 0x2000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (15 * 0x2000) + (address & 0x1FFF) };
if (address < 0x4000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address & 0x3FFF };
if (address < 0x6000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * 0x2000) + (address & 0x1FFF) };
if (address < 0x8000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * 0x2000) + (address & 0x1FFF) };
if (address < 0xA000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * 0x2000) + (address & 0x1FFF) };
if (address < 0xC000) return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank3 * 0x2000) + (address & 0x1FFF) };
else return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
void WriteMemoryMSX(ushort address, byte value) void WriteMemoryMSX(ushort address, byte value)
{ {
if (address >= 0xC000) if (address >= 0xC000)
@ -74,6 +103,7 @@
{ {
ReadMemory = ReadMemoryMSX; ReadMemory = ReadMemoryMSX;
WriteMemory = WriteMemoryMSX; WriteMemory = WriteMemoryMSX;
ReadMemory = ReadMemoryMSX;
RomBank0 = 0; RomBank0 = 0;
RomBank1 = 0; RomBank1 = 0;
RomBank2 = 0; RomBank2 = 0;
@ -84,6 +114,7 @@
{ {
InitMSXMapper(); InitMSXMapper();
ReadMemory = ReadMemoryNemesis; ReadMemory = ReadMemoryNemesis;
MapMemory = MapMemoryNemesis;
} }
} }
} }

View File

@ -56,6 +56,42 @@
return ret; return ret;
} }
CDLog_MapResults MapMemorySega(ushort address, bool write)
{
if (address < 0xC000)
{
if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
return new CDLog_MapResults();
else if (BiosMapped && BiosRom != null)
return new CDLog_MapResults(); //bios tracking of CDL is not supported
else if (address < 1024)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
else if (address < 0x4000)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * BankSize) + address };
else if (address < 0x8000)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + (address & BankSizeMask) };
else
{
switch (SaveRamBank)
{
case 0: return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
case 1:
if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (address & BankSizeMask) % SaveRAM.Length };
else return new CDLog_MapResults();
case 2:
if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (BankSize + (address & BankSizeMask)) & BankSizeMask };
else return new CDLog_MapResults();
default:
return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
}
}
else
{
return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
}
void WriteMemorySega(ushort address, byte value) void WriteMemorySega(ushort address, byte value)
{ {
if (address >= 0xC000) if (address >= 0xC000)
@ -91,42 +127,6 @@
} }
} }
CDLog_MapResults MapMemorySega(ushort address, bool write)
{
if (address < 0xC000)
{
if ((Port3E & 0x48) == 0x48) // cart and bios disabled, return empty bus
return new CDLog_MapResults();
else if (BiosMapped && BiosRom != null)
return new CDLog_MapResults(); //bios tracking of CDL is not supported
else if (address < 1024)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = address };
else if (address < 0x4000)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank0 * BankSize) + address };
else if (address < 0x8000)
return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank1 * BankSize) + address };
else
{
switch (SaveRamBank)
{
case 0: return new CDLog_MapResults() { Type = CDLog_AddrType.ROM, Address = (RomBank2 * BankSize) + (address & BankSizeMask) };
case 1:
if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (address & BankSizeMask) % SaveRAM.Length };
else return new CDLog_MapResults();
case 2:
if (SaveRAM != null) return new CDLog_MapResults() { Type = CDLog_AddrType.SaveRAM, Address = (BankSize + (address & BankSizeMask)) & BankSizeMask };
else return new CDLog_MapResults();
default:
return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
}
}
else
{
return new CDLog_MapResults() { Type = CDLog_AddrType.MainRAM, Address = address & RamSizeMask };
}
}
void InitSegaMapper() void InitSegaMapper()
{ {
ReadMemory = ReadMemorySega; ReadMemory = ReadMemorySega;

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@ -2,12 +2,7 @@
{ {
public partial class SMS public partial class SMS
{ {
// The CodeMasters mapper has 3 banks of 16kb, like the Sega mapper. //This doesn't look functional. Illogical and nothing like http://www.smspower.org/Articles/TerebiOekaki
// The differences are that the paging control addresses are different, and the first 1K of ROM is not protected.
// Bank 0: Control Address $0000 - Maps $0000 - $3FFF
// Bank 1: Control Address $4000 - Maps $4000 - $7FFF
// Bank 2: Control Address $8000 - Maps $8000 - $BFFF
// System RAM is at $C000+ as in the Sega mapper.
byte xCoord = 128; byte xCoord = 128;
byte yCoord = 100; byte yCoord = 100;
@ -51,8 +46,8 @@
void InitTerebiOekaki() void InitTerebiOekaki()
{ {
Cpu.ReadMemory = ReadMemoryTO; ReadMemory = ReadMemoryTO;
Cpu.WriteMemory = WriteMemoryTO; WriteMemory = WriteMemoryTO;
} }
} }
} }