quicknes: support Bite Off
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@ -121,7 +121,7 @@ protected:
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// Map 'size' bytes from 'CHR + bank * size' to PPU address space starting at 'addr'
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// Map 'size' bytes from 'CHR + bank * size' to PPU address space starting at 'addr'
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void set_chr_bank( nes_addr_t addr, bank_size_t size, int bank );
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void set_chr_bank( nes_addr_t addr, bank_size_t size, int bank );
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void set_chr_bank_ex( nes_addr_t addr, bank_size_t size, int bank );
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void set_chr_bank_ex( nes_addr_t addr, bank_size_t size, int bank ); // mmc24 only
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// Set PPU mirroring. All mappings implemented using mirror_manual().
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// Set PPU mirroring. All mappings implemented using mirror_manual().
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void mirror_manual( int page0, int page1, int page2, int page3 );
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void mirror_manual( int page0, int page1, int page2, int page3 );
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@ -44,7 +44,7 @@ public:
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enum { vaddr_clock_mask = 0x1000 };
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enum { vaddr_clock_mask = 0x1000 };
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void set_nt_banks( int bank0, int bank1, int bank2, int bank3 );
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void set_nt_banks( int bank0, int bank1, int bank2, int bank3 );
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void set_chr_bank( int addr, int size, long data );
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void set_chr_bank( int addr, int size, long data );
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void set_chr_bank_ex( int addr, int size, long data );
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void set_chr_bank_ex( int addr, int size, long data ); // mmc24 only
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// Nametable and CHR RAM
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// Nametable and CHR RAM
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enum { nt_ram_size = 0x1000 };
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enum { nt_ram_size = 0x1000 };
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@ -103,13 +103,16 @@ private:
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// Mapping
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// Mapping
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enum { chr_page_size = 0x400 };
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enum { chr_page_size = 0x400 };
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long chr_pages [chr_addr_size / chr_page_size];
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long chr_pages [chr_addr_size / chr_page_size];
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long chr_pages_ex [chr_addr_size / chr_page_size];
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long chr_pages_ex [chr_addr_size / chr_page_size]; // mmc24 only
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long map_chr_addr( unsigned a ) /*const*/
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long map_chr_addr( unsigned a ) /*const*/
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{
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{
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if (!mmc24_enabled)
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if (!mmc24_enabled)
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return chr_pages [a / chr_page_size] + a;
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return chr_pages [a / chr_page_size] + a;
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// mmc24 calculations
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int page = a >> 12 & 1;
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int page = a >> 12 & 1;
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// can't check against bit 3 of address, because quicknes never actually fetches those
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int newval0 = (a & 0xff0) != 0xfd0;
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int newval0 = (a & 0xff0) != 0xfd0;
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int newval1 = (a & 0xff0) == 0xfe0;
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int newval1 = (a & 0xff0) == 0xfe0;
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@ -126,8 +129,8 @@ private:
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}
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}
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byte* nt_banks [4];
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byte* nt_banks [4];
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bool mmc24_enabled;
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bool mmc24_enabled; // true if mmc24 regs need to be latched and checked
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byte mmc24_latched [2];
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byte mmc24_latched [2]; // current latch value for the first\second 4k of memory
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// CHR data
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// CHR data
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byte const* chr_data; // points to chr ram when there is no read-only data
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byte const* chr_data; // points to chr ram when there is no read-only data
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@ -176,7 +176,16 @@ void Nes_Ppu_Rendering::draw_background_( int remain )
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byte const* nametable2 = get_nametable( addr ^ 0x400 );
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byte const* nametable2 = get_nametable( addr ^ 0x400 );
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int count2 = addr & 31;
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int count2 = addr & 31;
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int count = 32 - count2 - left_clip;
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int count = 32 - count2 - left_clip;
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if ( pixel_x )
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// this conditional is commented out because of mmc2\4
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// normally, the extra row of pixels is only fetched when pixel_ x is not 0, which makes sense
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// but here, we need a correct fetch pattern to pick up 0xfd\0xfe tiles off the edge of the display
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// this doesn't cause any problems with buffer overflow because the framebuffer we're rendering to is
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// already guarded (width = 272)
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// this doesn't give us a fully correct ppu fetch pattern, but it's close enough for punch out
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//if ( pixel_x )
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count2++;
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count2++;
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byte const* attr_table = &nametable [0x3c0 | (addr >> 4 & 0x38)];
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byte const* attr_table = &nametable [0x3c0 | (addr >> 4 & 0x38)];
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