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68000: fix bug with ADDQ.W/SUBQ.W operating on address registers

This commit is contained in:
beirich 2011-10-12 02:20:03 +00:00
parent 04b93b5b8b
commit 7cedd71729
1 changed files with 20 additions and 10 deletions
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22
BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs
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@ -238,18 +238,23 @@ namespace BizHawk.Emulation.CPUs.M68000
return;
}
case 1: // word
{
if (mode == 1)
{
int value = PeekValueL(mode, reg);
WriteValueL(mode, reg, value+data);
}
else
{
short value = PeekValueW(mode, reg);
int result = value + data;
int uresult = (ushort)value + data;
if (mode != 1)
{
N = (result & 0x8000) != 0;
Z = result == 0;
V = result > short.MaxValue || result < short.MinValue;
C = X = (uresult & 0x10000) != 0;
}
WriteValueW(mode, reg, (short)result);
}
if (mode <= 1) PendingCycles -= 4;
else PendingCycles -= 8 + EACyclesBW[mode, reg];
return;
@ -564,18 +569,23 @@ namespace BizHawk.Emulation.CPUs.M68000
return;
}
case 1: // word
{
if (mode == 1)
{
int value = PeekValueL(mode, reg);
WriteValueL(mode, reg, value - data);
}
else
{
short value = PeekValueW(mode, reg);
int result = value - data;
int uresult = (ushort)value - data;
if (mode != 1)
{
N = (result & 0x8000) != 0;
Z = result == 0;
V = result > short.MaxValue || result < short.MinValue;
C = X = (uresult & 0x10000) != 0;
}
WriteValueW(mode, reg, (short)result);
}
if (mode <= 1) PendingCycles -= 4;
else PendingCycles -= 8 + EACyclesBW[mode, reg];
return;