From 74e6f630c3322b67037c3611906752ded53bbdda Mon Sep 17 00:00:00 2001 From: alyosha-tas Date: Wed, 6 Jun 2018 07:33:49 -0400 Subject: [PATCH] z80: IO port re-work and contention --- .../CPUs/Z80A/Registers.cs | 12 +++++++++ .../CPUs/Z80A/Tables_Direct.cs | 26 +++++++++---------- .../CPUs/Z80A/Tables_Indirect.cs | 12 ++++----- BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs | 21 +++++++-------- 4 files changed, 41 insertions(+), 30 deletions(-) diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs index b1fd71d5b9..d7c7cbe90f 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs @@ -45,6 +45,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80A public ushort[] Regs = new ushort[36]; + // IO Contention Constants. Need to distinguish port access and normal memory accesses for zx spectrum + public const ushort BIO1 = 100; + public const ushort BIO2 = 101; + public const ushort BIO3 = 102; + public const ushort BIO4 = 103; + + public const ushort WIO1 = 105; + public const ushort WIO2 = 106; + public const ushort WIO3 = 107; + public const ushort WIO4 = 108; + + public bool FlagI; public bool FlagW; // wait flag, when set to true reads / writes will be delayed diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs index 09342f9922..4b4b5e50d6 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs @@ -534,19 +534,19 @@ namespace BizHawk.Emulation.Cores.Components.Z80A private void OUT_() { cur_instr = new ushort[] - {IDLE, + {TR, W, A, WAIT, RD_INC, Z, PCl, PCh, IDLE, - IDLE, - TR, W, A, + WAIT, + WAIT, OUT, Z, W, A, INC16, Z, W, WAIT, OP_F, OP}; - BUSRQ = new ushort[] { PCh, 0, 0, 0, 0, 0 ,0, PCh, 0, 0, 0}; + BUSRQ = new ushort[] { PCh, 0, 0, WIO1, WIO2, WIO3, WIO4, PCh, 0, 0, 0}; } private void OUT_REG_(ushort dest, ushort src) @@ -561,40 +561,40 @@ namespace BizHawk.Emulation.Cores.Components.Z80A OP_F, OP}; - BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0, 0 }; + BUSRQ = new ushort[] { WIO1, WIO2, WIO3, WIO4, PCh, 0, 0, 0 }; } private void IN_() { cur_instr = new ushort[] - {IDLE, + {TR, W, A, WAIT, RD_INC, Z, PCl, PCh, IDLE, - IDLE, - TR, W, A, + WAIT, + WAIT, IN, A, Z, W, INC16, Z, W, WAIT, OP_F, OP}; - BUSRQ = new ushort[] { PCh, 0, 0, 0, 0, 0, 0, PCh, 0, 0, 0 }; + BUSRQ = new ushort[] { PCh, 0, 0, WIO1, WIO2, WIO3, WIO4, PCh, 0, 0, 0 }; } private void IN_REG_(ushort dest, ushort src) { cur_instr = new ushort[] - {IDLE, - TR16, Z, W, C, B, + {TR16, Z, W, C, B, WAIT, - IN, dest, src, B, + WAIT, + IN, dest, Z, W, INC16, Z, W, WAIT, OP_F, OP}; - BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0, 0 }; + BUSRQ = new ushort[] { WIO1, WIO2, WIO3, WIO4, PCh, 0, 0, 0 }; } private void REG_OP_16_(ushort op, ushort dest_l, ushort dest_h, ushort src_l, ushort src_h) diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs index 5ac492c6f1..b8f3505fa4 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs @@ -447,15 +447,15 @@ { cur_instr = new ushort[] {IDLE, + IDLE, WAIT, WAIT, IN, ALU, C, B, IDLE, WAIT, - WR, L, H, ALU, - REP_OP_I, operation, 2, operation, repeat_instr }; + REP_OP_I, L, H, ALU, operation, 2, operation, repeat_instr }; - BUSRQ = new ushort[] { I, 0, 0, 0, H, 0, 0, 0}; + BUSRQ = new ushort[] { I, BIO1, BIO2, BIO3, BIO4, H, 0, 0}; } private void OUT_OP_R(ushort operation, ushort repeat_instr) @@ -467,10 +467,10 @@ RD, ALU, L, H, IDLE, WAIT, - OUT, C, B, ALU, - REP_OP_O, operation, 3, operation, repeat_instr }; + WAIT, + REP_OP_O, C, B, ALU, operation, 3, operation, repeat_instr }; - BUSRQ = new ushort[] { I, H, 0, 0, 0, 0, 0, 0}; + BUSRQ = new ushort[] { I, H, 0, 0, BIO1, BIO2, BIO3, BIO4 }; } // this is an indirect change of a a 16 bit register with memory diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs index ea5bcebfe8..34ec1bb5ff 100644 --- a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs +++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs @@ -14,7 +14,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A // operations that can take place in an instruction public const ushort IDLE = 0; public const ushort OP = 1; - public const ushort OP_R = 2; // used for repeating operations + public const ushort OP_F = 2; // used for repeating operations public const ushort HALT = 3; public const ushort RD = 4; public const ushort WR = 5; @@ -77,10 +77,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80A public const ushort HL_BIT = 62; public const ushort FTCH_DB = 63; public const ushort WAIT = 64; // enterred when readin or writing and FlagW is true - public const ushort OP_F = 65; // fetch the opcode, happens on cycle 3 of fetch cycle - public const ushort RST = 66; - public const ushort REP_OP_I = 67; - public const ushort REP_OP_O = 68; + public const ushort RST = 65; + public const ushort REP_OP_I = 66; + public const ushort REP_OP_O = 67; public byte temp_R; @@ -230,10 +229,9 @@ namespace BizHawk.Emulation.Cores.Components.Z80A temp_R &= 0x7F; Regs[R] = (byte)((Regs[R] & 0x80) | temp_R); break; - case OP_R: - + case OP_F: + opcode = FetchMemory(RegPC); break; - case HALT: halted = true; // NOTE: Check how halt state effects the DB @@ -503,14 +501,13 @@ namespace BizHawk.Emulation.Cores.Components.Z80A bus_pntr--; } break; - case OP_F: - opcode = FetchMemory(RegPC); - break; case RST: Regs[Z] = cur_instr[instr_pntr++]; Regs[W] = 0; break; case REP_OP_I: + Write_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]); + ushort temp4 = cur_instr[instr_pntr++]; if (temp4 == DEC16) { @@ -529,6 +526,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A Repeat_Op(); break; case REP_OP_O: + OUT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]); + ushort temp5 = cur_instr[instr_pntr++]; if (temp5 == DEC16) {