NESHawk: fix some regressions

This commit is contained in:
alyosha-tas 2021-12-23 20:00:13 -05:00
parent 2dae3505d7
commit 7463e24957
2 changed files with 10 additions and 12 deletions

View File

@ -763,13 +763,13 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
else
{
// when called from write, either a 2 or 3 cycle delay in activation.
if (timer % 2 == 1)
if (timer % 2 == 0)
{
delay = 2;
delay = 3;
}
else
{
delay = 3;
delay = 2;
}
}
}
@ -1232,7 +1232,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
}
else if (addr == 0x4017)
{
if (dmc.timer % 2 == 1)
if (dmc.timer % 2 == 0)
{
seq_tick = 3;
@ -1323,12 +1323,12 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
// the current code simply matches known behaviour
if (pending_reg != -1)
{
if (pending_reg == 0x4015 || pending_reg == 0x4003 || pending_reg == 0x4007)
if ( pending_reg == 0x4003 || pending_reg == 0x4007 || pending_reg == 0x4015 || pending_reg == 0x4017)
{
_WriteReg(pending_reg, pending_val);
pending_reg = -1;
}
else if (dmc.timer % 2 == 1)
else if (dmc.timer % 2 == 0)
{
_WriteReg(pending_reg, pending_val);
pending_reg = -1;

View File

@ -555,7 +555,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
if ((apu.dmc.timer == 2) && (apu.dmc.out_bits_remaining == 0))
{
Console.WriteLine("close " + cpu.TotalExecutedCycles + " " + apu.dmc.timer + " " + apu.dmc.sample_length + " " + cpu.opcode + " " + cpu.mi);
//Console.WriteLine("close " + cpu.TotalExecutedCycles + " " + apu.dmc.timer + " " + apu.dmc.sample_length + " " + cpu.opcode + " " + cpu.mi);
if (apu.dmc.sample_length != 0)
{
apu.dmc.fill_glitch = true;
@ -584,16 +584,14 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
// dmc dma end
/////////////////////////////
apu.RunOneFirst();
if (cpu.RDY && !IRQ_delay)
{
cpu.IRQ = _irq_apu || Board.IrqSignal;
}
else if (special_case_delay || apu.dmc_dma_countdown == 3)
{
{
cpu.IRQ = _irq_apu || Board.IrqSignal;
//if (cpu.IRQ) { Console.WriteLine("something IRQ"); }
special_case_delay = false;
}
@ -625,7 +623,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
IRQ_delay = false;
if (!dmc_dma_exec && !oam_dma_exec && !cpu.RDY)
if (!cpu.RDY && !dmc_dma_exec && !oam_dma_exec)
{
cpu.RDY = true;
IRQ_delay = true;