MSXHawk: Z80 with prebuilt instruction tables
This commit is contained in:
alyosha-tas
parent
ebfccf51de
commit
6b99a792b9
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@ -51,6 +51,7 @@ namespace MSXHawk
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bool nonMaskableInterrupt;
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bool nonMaskableInterruptPending;
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bool jp_cond_chk;
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bool cond_chk_fail;
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uint8_t opcode;
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uint8_t temp_R;
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@ -58,6 +59,9 @@ namespace MSXHawk
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uint8_t interruptMode;
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// when connected devices do not output a value on the BUS, they are responsible for determining open bus behaviour and returning it
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uint8_t ExternalDB;
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// since absolute pointer locations are not saved, we need to know where current pointer is looking in order to load it
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// this combined with opcode and instr_pntr gives the current cpu execution location
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uint8_t instr_bank;
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uint8_t Regs[36] = {};
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uint32_t PRE_SRC;
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@ -67,20 +71,17 @@ namespace MSXHawk
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uint32_t mem_pntr = 0;
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uint32_t irq_pntr = 0;
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uint32_t IRQS;
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uint32_t Ztemp2_saver = 0;
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uint32_t IRQS_cond_offset;
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// since absolute pointer locations are not saved, we need to know where current pointer is looking in order to load it
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// this combined with opcode and instr_pntr gives the current cpu execution location
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uint8_t instr_bank;
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uint64_t TotalExecutedCycles;
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uint32_t* cur_instr_ofst = nullptr;
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uint32_t* cur_bus_ofst = nullptr;
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uint32_t* cur_mem_ofst = nullptr;
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uint32_t* cur_irqs_ofst = nullptr;
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uint64_t TotalExecutedCycles;
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// non-state variables
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// EXCEPTION!: Ztemp2 must be stated to restore the instruction vector
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bool checker;
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uint32_t Ztemp1, Ztemp2, Ztemp3, Ztemp4;
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uint32_t Reg16_d, Reg16_s, ans, temp, carry, dest_t, src_t;
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@ -341,6 +342,90 @@ namespace MSXHawk
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uint32_t REP_OP_O_MEMRQ[5] = { 0, 0, 0, 0, 0 };
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uint32_t REP_OP_O_IRQS = 5;
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// halt
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uint32_t HALT_INST[4] = { IDLE,
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WAIT,
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OP_F,
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OP };
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uint32_t HALT_BUSRQ[4] = { PCh, 0, 0, 0 };
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uint32_t HALT_MEMRQ[4] = { PCh, 0, 0, 0 };
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uint32_t HALT_IRQS = 4;
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// NMI
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uint32_t NMI_INST[25] = { IDLE,
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IDLE,
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IDLE,
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IDLE,
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DEC16, SPl, SPh,
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TR, ALU, PCl,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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TR16, PCl, PCh, NMI_V, ZERO,
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WAIT,
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WR, SPl, SPh, ALU };
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uint32_t NMI_BUSRQ[11] = { 0, 0, 0, 0, 0, SPh, 0, 0, SPh, 0, 0 };
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uint32_t NMI_MEMRQ[11] = { 0, 0, 0, 0, 0, SPh, 0, 0, SPh, 0, 0 };
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uint32_t NMI_IRQS = 11;
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// IRQ0
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uint32_t IRQ0_INST[10] = { IDLE,
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IDLE,
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IORQ,
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WAIT,
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IDLE,
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WAIT,
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RD_INC, ALU, PCl, PCh };
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uint32_t IRQ0_BUSRQ[7] = { 0, 0, 0, 0, PCh, 0, 0 };
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uint32_t IRQ0_MEMRQ[7] = { 0, 0, 0, 0, PCh, 0, 0 };
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uint32_t IRQ0_IRQS = 7;
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// IRQ1
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uint32_t IRQ1_INST[27] = { IDLE,
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IDLE,
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IORQ,
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WAIT,
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IDLE,
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TR, ALU, PCl,
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DEC16, SPl, SPh,
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IDLE,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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TR16, PCl, PCh, IRQ_V, ZERO,
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WAIT,
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WR, SPl, SPh, ALU };
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uint32_t IRQ1_BUSRQ[13] = { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 };
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uint32_t IRQ1_MEMRQ[13] = { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 };
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uint32_t IRQ1_IRQS = 13;
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// IRQ2
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uint32_t IRQ2_INST[37] = { IDLE,
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IDLE,
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IORQ,
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WAIT,
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FTCH_DB,
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IDLE,
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DEC16, SPl, SPh,
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TR16, Z, W, DB, I,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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IDLE,
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WAIT,
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WR, SPl, SPh, PCl,
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IDLE,
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WAIT,
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RD_INC, PCl, Z, W,
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IDLE,
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WAIT,
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RD, PCh, Z, W };
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uint32_t IRQ2_BUSRQ[19] = { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0 };
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uint32_t IRQ2_MEMRQ[19] = { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0 };
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uint32_t IRQ2_IRQS = 19;
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#pragma endregion
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#pragma region Z80 functions
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@ -413,7 +498,7 @@ namespace MSXHawk
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NO_prefix = true;
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}
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void FetchInstruction()
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inline void FetchInstruction()
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{
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if (NO_prefix)
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{
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@ -494,6 +579,7 @@ namespace MSXHawk
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void ExecuteOne()
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{
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bus_pntr++; mem_pntr++;
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switch (cur_instr_ofst[instr_pntr++])
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{
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case IDLE:
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@ -845,7 +931,7 @@ namespace MSXHawk
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if (((Regs[C] | (Regs[B] << 8)) != 0) && (Ztemp3 > 0))
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{
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cur_instr_ofst = &LD_OP_R_INST[0];
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cur_instr_ofst[14] = Ztemp2;
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cur_instr_ofst[14] = Ztemp2; Ztemp2_saver = Ztemp2;
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cur_bus_ofst = &LD_OP_R_BUSRQ[0];
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cur_mem_ofst = &LD_OP_R_MEMRQ[0];
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cur_irqs_ofst = &LD_OP_R_IRQS;
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@ -871,7 +957,7 @@ namespace MSXHawk
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if (((Regs[C] | (Regs[B] << 8)) != 0) && (Ztemp3 > 0) && !FlagZget())
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{
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cur_instr_ofst = &LD_CP_R_INST[0];
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cur_instr_ofst[14] = Ztemp2;
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cur_instr_ofst[14] = Ztemp2; Ztemp2_saver = Ztemp2;
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cur_bus_ofst = &LD_CP_R_BUSRQ[0];
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cur_mem_ofst = &LD_CP_R_MEMRQ[0];
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cur_irqs_ofst = &LD_CP_R_IRQS;
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@ -945,7 +1031,7 @@ namespace MSXHawk
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if ((Regs[B] != 0) && (Ztemp3 > 0))
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{
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cur_instr_ofst = &REP_OP_I_INST[0];
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cur_instr_ofst[8] = Ztemp2;
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cur_instr_ofst[8] = Ztemp2; Ztemp2_saver = Ztemp2;
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cur_bus_ofst = &REP_OP_I_BUSRQ[0];
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cur_mem_ofst = &REP_OP_I_MEMRQ[0];
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cur_irqs_ofst = &REP_OP_I_IRQS;
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@ -1086,22 +1172,28 @@ namespace MSXHawk
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}
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else
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{
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cond_chk_fail = true;
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switch (cur_instr_ofst[instr_pntr++])
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{
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case 0: // DJNZ
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cur_irqs_ofst = &False_IRQS[0];
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IRQS_cond_offset = 0;
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break;
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case 1: // JR COND
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cur_irqs_ofst = &False_IRQS[1];
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IRQS_cond_offset = 1;
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break;
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case 2: // JP COND
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cur_irqs_ofst = &False_IRQS[2];
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IRQS_cond_offset = 2;
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break;
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case 3: // RET COND
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cur_irqs_ofst = &False_IRQS[3];
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IRQS_cond_offset = 3;
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break;
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case 4: // CALL
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cur_irqs_ofst = &False_IRQS[4];
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IRQS_cond_offset = 4;
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break;
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}
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}
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@ -1116,6 +1208,8 @@ namespace MSXHawk
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}
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else if (++irq_pntr == cur_irqs_ofst[0])
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{
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cond_chk_fail = false;
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if (EI_pending > 0)
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{
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EI_pending--;
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@ -1177,15 +1271,12 @@ namespace MSXHawk
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// otherwise start a new normal access
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else if (!halted)
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{
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PopulateCURINSTR
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(IDLE,
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WAIT,
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OP_F,
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OP);
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cur_instr_ofst = &HALT_INST[0];
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cur_bus_ofst = &HALT_BUSRQ[0];
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cur_mem_ofst = &HALT_MEMRQ[0];
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cur_irqs_ofst = &HALT_IRQS;
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PopulateBUSRQ(PCh, 0, 0, 0);
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PopulateMEMRQ(PCh, 0, 0, 0);
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IRQS = 4;
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instr_bank = 11;
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instr_pntr = mem_pntr = bus_pntr = irq_pntr = 0;
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}
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@ -1285,21 +1376,12 @@ namespace MSXHawk
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#pragma region Interrupts
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void NMI_()
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{
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PopulateCURINSTR(IDLE,
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IDLE,
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IDLE,
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IDLE,
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DEC16, SPl, SPh,
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TR, ALU, PCl,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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TR16, PCl, PCh, NMI_V, ZERO,
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WAIT,
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WR, SPl, SPh, ALU);
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cur_instr_ofst = &NMI_INST[0];
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cur_bus_ofst = &NMI_BUSRQ[0];
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cur_mem_ofst = &NMI_MEMRQ[0];
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cur_irqs_ofst = &NMI_IRQS;
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PopulateBUSRQ(0, 0, 0, 0, 0, SPh, 0, 0, SPh, 0, 0);
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PopulateMEMRQ(0, 0, 0, 0, 0, SPh, 0, 0, SPh, 0, 0);
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IRQS = 11;
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instr_bank = 12;
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}
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// Mode 0 interrupts only take effect if a CALL or RST is on the data bus
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@ -1309,67 +1391,34 @@ namespace MSXHawk
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//NOTE: TODO: When a CALL is present on the data bus, adjust WZ accordingly
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void INTERRUPT_0(uint32_t src)
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{
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PopulateCURINSTR(IDLE,
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IDLE,
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IORQ,
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WAIT,
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IDLE,
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WAIT,
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RD_INC, ALU, PCl, PCh);
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cur_instr_ofst = &IRQ0_INST[0];
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cur_bus_ofst = &IRQ0_BUSRQ[0];
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cur_mem_ofst = &IRQ0_MEMRQ[0];
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cur_irqs_ofst = &IRQ0_IRQS;
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PopulateBUSRQ(0, 0, 0, 0, PCh, 0, 0);
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PopulateMEMRQ(0, 0, 0, 0, PCh, 0, 0);
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IRQS = 7;
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instr_bank = 13;
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}
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// Just jump to $0038
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void INTERRUPT_1()
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{
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PopulateCURINSTR(IDLE,
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IDLE,
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IORQ,
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WAIT,
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IDLE,
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TR, ALU, PCl,
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DEC16, SPl, SPh,
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IDLE,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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TR16, PCl, PCh, IRQ_V, ZERO,
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WAIT,
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WR, SPl, SPh, ALU);
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cur_instr_ofst = &IRQ1_INST[0];
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cur_bus_ofst = &IRQ1_BUSRQ[0];
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cur_mem_ofst = &IRQ1_MEMRQ[0];
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cur_irqs_ofst = &IRQ1_IRQS;
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PopulateBUSRQ(0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0);
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PopulateMEMRQ(0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0);
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IRQS = 13;
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instr_bank = 14;
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}
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// Interrupt mode 2 uses the I vector combined with a byte on the data bus
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void INTERRUPT_2()
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{
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PopulateCURINSTR(IDLE,
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IDLE,
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IORQ,
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WAIT,
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FTCH_DB,
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IDLE,
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DEC16, SPl, SPh,
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TR16, Z, W, DB, I,
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WAIT,
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WR_DEC, SPl, SPh, PCh,
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IDLE,
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WAIT,
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WR, SPl, SPh, PCl,
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IDLE,
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WAIT,
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RD_INC, PCl, Z, W,
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IDLE,
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WAIT,
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RD, PCh, Z, W);
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cur_instr_ofst = &IRQ2_INST[0];
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cur_bus_ofst = &IRQ2_BUSRQ[0];
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cur_mem_ofst = &IRQ2_MEMRQ[0];
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cur_irqs_ofst = &IRQ2_IRQS;
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PopulateBUSRQ(0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0);
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PopulateMEMRQ(0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0);
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IRQS = 19;
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instr_bank = 15;
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}
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void ResetInterrupts()
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@ -2641,12 +2690,12 @@ namespace MSXHawk
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case 0xFF: RST_(0x38); break; // RST 0x38
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}
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std::memcpy(&NoIndex[i * 38], &cur_instr, 38);
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std::memcpy(&NoIndexBUSRQ[i * 19], &BUSRQ, 19);
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std::memcpy(&NoIndexMEMRQ[i * 19], &MEMRQ, 19);
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std::memcpy(&NoIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
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std::memcpy(&NoIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
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std::memcpy(&NoIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
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NoIndexIRQS[i] = IRQS;
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switch (opcode)
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switch (i)
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{
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case 0x00: INT_OP(RLC, B); break; // RLC B
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case 0x01: INT_OP(RLC, C); break; // RLC C
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@ -2906,12 +2955,12 @@ namespace MSXHawk
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case 0xFF: BIT_OP(SET, 7, A); break; // SET 7, A
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}
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std::memcpy(&CBIndex[i * 38], &cur_instr, 38);
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std::memcpy(&CBIndexBUSRQ[i * 19], &BUSRQ, 19);
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std::memcpy(&CBIndexMEMRQ[i * 19], &MEMRQ, 19);
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std::memcpy(&CBIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
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std::memcpy(&CBIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
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std::memcpy(&CBIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
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CBIndexIRQS[i] = IRQS;
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switch (opcode)
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switch (i)
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{
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case 0x40: IN_REG_(B, C); break; // IN B, (C)
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case 0x41: OUT_REG_(C, B); break; // OUT (C), B
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@ -2997,12 +3046,12 @@ namespace MSXHawk
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}
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std::memcpy(&EXTIndex[i * 38], &cur_instr, 38);
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std::memcpy(&EXTIndexBUSRQ[i * 19], &BUSRQ, 19);
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std::memcpy(&EXTIndexMEMRQ[i * 19], &MEMRQ, 19);
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std::memcpy(&EXTIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
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std::memcpy(&EXTIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
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std::memcpy(&EXTIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
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EXTIndexIRQS[i] = IRQS;
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switch (opcode)
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switch (i)
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{
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case 0x00: NOP_(); break; // NOP
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case 0x01: LD_IND_16(C, B, PCl, PCh); break; // LD BC, nn
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@ -3262,12 +3311,12 @@ namespace MSXHawk
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case 0xFF: RST_(0x38); break; // RST $38
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}
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std::memcpy(&IXIndex[i * 38], &cur_instr, 38);
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std::memcpy(&IXIndexBUSRQ[i * 19], &BUSRQ, 19);
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std::memcpy(&IXIndexMEMRQ[i * 19], &MEMRQ, 19);
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std::memcpy(&IXIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
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std::memcpy(&IXIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
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std::memcpy(&IXIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
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IXIndexIRQS[i] = IRQS;
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switch (opcode)
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switch (i)
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{
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case 0x00: NOP_(); break; // NOP
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case 0x01: LD_IND_16(C, B, PCl, PCh); break; // LD BC, nn
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@ -3527,12 +3576,12 @@ namespace MSXHawk
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case 0xFF: RST_(0x38); break; // RST $38
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}
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std::memcpy(&IYIndex[i * 38], &cur_instr, 38);
|
||||
std::memcpy(&IYIndexBUSRQ[i * 19], &BUSRQ, 19);
|
||||
std::memcpy(&IYIndexMEMRQ[i * 19], &MEMRQ, 19);
|
||||
std::memcpy(&IYIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
|
||||
std::memcpy(&IYIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
|
||||
std::memcpy(&IYIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
|
||||
IYIndexIRQS[i] = IRQS;
|
||||
|
||||
switch (opcode)
|
||||
switch (i)
|
||||
{
|
||||
case 0x00: I_INT_OP(RLC, B); break; // RLC (I* + n) -> B
|
||||
case 0x01: I_INT_OP(RLC, C); break; // RLC (I* + n) -> C
|
||||
|
|
@ -3792,9 +3841,9 @@ namespace MSXHawk
|
|||
case 0xFF: I_BIT_OP(SET, 7, A); break; // SET 7, (I* + n) -> A
|
||||
}
|
||||
|
||||
std::memcpy(&IXYCBIndex[i * 38], &cur_instr, 38);
|
||||
std::memcpy(&IXYCBIndexBUSRQ[i * 19], &BUSRQ, 19);
|
||||
std::memcpy(&IXYCBIndexMEMRQ[i * 19], &MEMRQ, 19);
|
||||
std::memcpy(&IXYCBIndex[i * 38], &cur_instr, sizeof(uint32_t) * 38);
|
||||
std::memcpy(&IXYCBIndexBUSRQ[i * 19], &BUSRQ, sizeof(uint32_t) * 19);
|
||||
std::memcpy(&IXYCBIndexMEMRQ[i * 19], &MEMRQ, sizeof(uint32_t) * 19);
|
||||
IXYCBIndexIRQS[i] = IRQS;
|
||||
}
|
||||
}
|
||||
|
|
@ -5340,12 +5389,15 @@ namespace MSXHawk
|
|||
*saver = (uint8_t)(IFF2 ? 1 : 0); saver++;
|
||||
*saver = (uint8_t)(nonMaskableInterrupt ? 1 : 0); saver++;
|
||||
*saver = (uint8_t)(nonMaskableInterruptPending ? 1 : 0); saver++;
|
||||
*saver = (uint8_t)(jp_cond_chk ? 1 : 0); saver++;
|
||||
*saver = (uint8_t)(cond_chk_fail ? 1 : 0); saver++;
|
||||
|
||||
*saver = opcode; saver++;
|
||||
*saver = temp_R; saver++;
|
||||
*saver = EI_pending; saver++;
|
||||
*saver = interruptMode; saver++;
|
||||
*saver = ExternalDB; saver++;
|
||||
*saver = instr_bank; saver++;
|
||||
|
||||
for (int i = 0; i < 36; i++) { *saver = Regs[i]; saver++; }
|
||||
|
||||
|
|
@ -5367,23 +5419,11 @@ namespace MSXHawk
|
|||
*saver = (uint8_t)(IRQS & 0xFF); saver++; *saver = (uint8_t)((IRQS >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((IRQS >> 16) & 0xFF); saver++; *saver = (uint8_t)((IRQS >> 24) & 0xFF); saver++;
|
||||
|
||||
for (int i = 0; i < 38; i++)
|
||||
{
|
||||
*saver = (uint8_t)(cur_instr[i] & 0xFF); saver++; *saver = (uint8_t)((cur_instr[i] >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((cur_instr[i] >> 16) & 0xFF); saver++; *saver = (uint8_t)((cur_instr[i] >> 24) & 0xFF); saver++;
|
||||
}
|
||||
*saver = (uint8_t)(Ztemp2_saver & 0xFF); saver++; *saver = (uint8_t)((Ztemp2_saver >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((Ztemp2_saver >> 16) & 0xFF); saver++; *saver = (uint8_t)((Ztemp2_saver >> 24) & 0xFF); saver++;
|
||||
|
||||
for (int i = 0; i < 19; i++)
|
||||
{
|
||||
*saver = (uint8_t)(BUSRQ[i] & 0xFF); saver++; *saver = (uint8_t)((BUSRQ[i] >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((BUSRQ[i] >> 16) & 0xFF); saver++; *saver = (uint8_t)((BUSRQ[i] >> 24) & 0xFF); saver++;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 19; i++)
|
||||
{
|
||||
*saver = (uint8_t)(MEMRQ[i] & 0xFF); saver++; *saver = (uint8_t)((MEMRQ[i] >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((MEMRQ[i] >> 16) & 0xFF); saver++; *saver = (uint8_t)((MEMRQ[i] >> 24) & 0xFF); saver++;
|
||||
}
|
||||
*saver = (uint8_t)(IRQS_cond_offset & 0xFF); saver++; *saver = (uint8_t)((IRQS_cond_offset >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((IRQS_cond_offset >> 16) & 0xFF); saver++; *saver = (uint8_t)((IRQS_cond_offset >> 24) & 0xFF); saver++;
|
||||
|
||||
*saver = (uint8_t)(TotalExecutedCycles & 0xFF); saver++; *saver = (uint8_t)((TotalExecutedCycles >> 8) & 0xFF); saver++;
|
||||
*saver = (uint8_t)((TotalExecutedCycles >> 16) & 0xFF); saver++; *saver = (uint8_t)((TotalExecutedCycles >> 24) & 0xFF); saver++;
|
||||
|
|
@ -5410,12 +5450,15 @@ namespace MSXHawk
|
|||
IFF2 = *loader == 1; loader++;
|
||||
nonMaskableInterrupt = *loader == 1; loader++;
|
||||
nonMaskableInterruptPending = *loader == 1; loader++;
|
||||
jp_cond_chk = *loader == 1; loader++;
|
||||
cond_chk_fail = *loader == 1; loader++;
|
||||
|
||||
opcode = *loader; loader++;
|
||||
temp_R = *loader; loader++;
|
||||
EI_pending = *loader; loader++;
|
||||
interruptMode = *loader; loader++;
|
||||
ExternalDB = *loader; loader++;
|
||||
instr_bank = *loader; loader++;
|
||||
|
||||
for (int i = 0; i < 36; i++) { Regs[i] = *loader; loader++; }
|
||||
|
||||
|
|
@ -5437,22 +5480,132 @@ namespace MSXHawk
|
|||
IRQS = *loader; loader++; IRQS |= (*loader << 8); loader++;
|
||||
IRQS |= (*loader << 16); loader++; IRQS |= (*loader << 24); loader++;
|
||||
|
||||
for (int i = 0; i < 38; i++)
|
||||
Ztemp2_saver = *loader; loader++; Ztemp2_saver |= (*loader << 8); loader++;
|
||||
Ztemp2_saver |= (*loader << 16); loader++; Ztemp2_saver |= (*loader << 24); loader++;
|
||||
|
||||
IRQS_cond_offset = *loader; loader++; IRQS_cond_offset |= (*loader << 8); loader++;
|
||||
IRQS_cond_offset |= (*loader << 16); loader++; IRQS_cond_offset |= (*loader << 24); loader++;
|
||||
|
||||
// load instruction pointers based on state
|
||||
if (instr_bank == 0)
|
||||
{
|
||||
cur_instr[i] = *loader; loader++; cur_instr[i] |= (*loader << 8); loader++;
|
||||
cur_instr[i] |= (*loader << 16); loader++; cur_instr[i] |= (*loader << 24); loader++;
|
||||
cur_instr_ofst = &NoIndex[opcode * 38];
|
||||
cur_bus_ofst = &NoIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &NoIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &NoIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 1)
|
||||
{
|
||||
cur_instr_ofst = &CBIndex[opcode * 38];
|
||||
cur_bus_ofst = &CBIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &CBIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &CBIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 2)
|
||||
{
|
||||
cur_instr_ofst = &EXTIndex[opcode * 38];
|
||||
cur_bus_ofst = &EXTIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &EXTIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &EXTIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 3)
|
||||
{
|
||||
cur_instr_ofst = &IXIndex[opcode * 38];
|
||||
cur_bus_ofst = &IXIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &IXIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &IXIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 4)
|
||||
{
|
||||
cur_instr_ofst = &IYIndex[opcode * 38];
|
||||
cur_bus_ofst = &IYIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &IYIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &IYIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 5)
|
||||
{
|
||||
cur_instr_ofst = &IXYCBIndex[opcode * 38];
|
||||
cur_bus_ofst = &IXYCBIndexBUSRQ[opcode * 19];
|
||||
cur_mem_ofst = &IXYCBIndexMEMRQ[opcode * 19];
|
||||
cur_irqs_ofst = &IXYCBIndexIRQS[opcode];
|
||||
}
|
||||
else if (instr_bank == 6)
|
||||
{
|
||||
cur_instr_ofst = &Reset_CPU[0];
|
||||
cur_bus_ofst = &Reset_BUSRQ[0];
|
||||
cur_mem_ofst = &Reset_MEMRQ[0];
|
||||
cur_irqs_ofst = &Reset_IRQS;
|
||||
}
|
||||
else if (instr_bank == 7)
|
||||
{
|
||||
cur_instr_ofst = &LD_OP_R_INST[0];
|
||||
cur_instr_ofst[14] = Ztemp2_saver;
|
||||
cur_bus_ofst = &LD_OP_R_BUSRQ[0];
|
||||
cur_mem_ofst = &LD_OP_R_MEMRQ[0];
|
||||
cur_irqs_ofst = &LD_OP_R_IRQS;
|
||||
}
|
||||
else if (instr_bank == 8)
|
||||
{
|
||||
cur_instr_ofst = &LD_CP_R_INST[0];
|
||||
cur_instr_ofst[14] = Ztemp2_saver;
|
||||
cur_bus_ofst = &LD_CP_R_BUSRQ[0];
|
||||
cur_mem_ofst = &LD_CP_R_MEMRQ[0];
|
||||
cur_irqs_ofst = &LD_CP_R_IRQS;
|
||||
}
|
||||
else if (instr_bank == 9)
|
||||
{
|
||||
cur_instr_ofst = &REP_OP_I_INST[0];
|
||||
cur_instr_ofst[8] = Ztemp2_saver;
|
||||
cur_bus_ofst = &REP_OP_I_BUSRQ[0];
|
||||
cur_mem_ofst = &REP_OP_I_MEMRQ[0];
|
||||
cur_irqs_ofst = &REP_OP_I_IRQS;
|
||||
}
|
||||
else if (instr_bank == 10)
|
||||
{
|
||||
cur_instr_ofst = &REP_OP_O_INST[0];
|
||||
cur_bus_ofst = &REP_OP_O_BUSRQ[0];
|
||||
cur_mem_ofst = &REP_OP_O_MEMRQ[0];
|
||||
cur_irqs_ofst = &REP_OP_O_IRQS;
|
||||
}
|
||||
else if (instr_bank == 11)
|
||||
{
|
||||
cur_instr_ofst = &HALT_INST[0];
|
||||
cur_bus_ofst = &HALT_BUSRQ[0];
|
||||
cur_mem_ofst = &HALT_MEMRQ[0];
|
||||
cur_irqs_ofst = &HALT_IRQS;
|
||||
}
|
||||
else if (instr_bank == 12)
|
||||
{
|
||||
cur_instr_ofst = &NMI_INST[0];
|
||||
cur_bus_ofst = &NMI_BUSRQ[0];
|
||||
cur_mem_ofst = &NMI_MEMRQ[0];
|
||||
cur_irqs_ofst = &NMI_IRQS;
|
||||
}
|
||||
else if (instr_bank == 13)
|
||||
{
|
||||
cur_instr_ofst = &IRQ0_INST[0];
|
||||
cur_bus_ofst = &IRQ0_BUSRQ[0];
|
||||
cur_mem_ofst = &IRQ0_MEMRQ[0];
|
||||
cur_irqs_ofst = &IRQ0_IRQS;
|
||||
}
|
||||
else if (instr_bank == 14)
|
||||
{
|
||||
cur_instr_ofst = &IRQ1_INST[0];
|
||||
cur_bus_ofst = &IRQ1_BUSRQ[0];
|
||||
cur_mem_ofst = &IRQ1_MEMRQ[0];
|
||||
cur_irqs_ofst = &IRQ1_IRQS;
|
||||
}
|
||||
else if (instr_bank == 15)
|
||||
{
|
||||
cur_instr_ofst = &IRQ2_INST[0];
|
||||
cur_bus_ofst = &IRQ2_BUSRQ[0];
|
||||
cur_mem_ofst = &IRQ2_MEMRQ[0];
|
||||
cur_irqs_ofst = &IRQ2_IRQS;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 19; i++)
|
||||
if (cond_chk_fail)
|
||||
{
|
||||
BUSRQ[i] = *loader; loader++; BUSRQ[i] |= (*loader << 8); loader++;
|
||||
BUSRQ[i] |= (*loader << 16); loader++; BUSRQ[i] |= (*loader << 24); loader++;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 19; i++)
|
||||
{
|
||||
MEMRQ[i] = *loader; loader++; MEMRQ[i] |= (*loader << 8); loader++;
|
||||
MEMRQ[i] |= (*loader << 16); loader++; MEMRQ[i] |= (*loader << 24); loader++;
|
||||
cur_irqs_ofst = &False_IRQS[IRQS_cond_offset];
|
||||
}
|
||||
|
||||
TotalExecutedCycles = *loader; loader++; TotalExecutedCycles |= ((uint64_t)*loader << 8); loader++;
|
||||
|
|
|
|||
Loading…
Reference in New Issue