GBHawk: more mode 1 work

This commit is contained in:
alyosha-tas 2020-12-06 19:39:25 -05:00
parent a46ffefc77
commit 699fb1171c
3 changed files with 47 additions and 50 deletions

View File

@ -145,11 +145,8 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
case 0xFF41: // STAT
// note that their is no stat interrupt bug in GBC
STAT = (byte)((value & 0xF8) | (STAT & 7) | 0x80);
//Console.WriteLine("stat " + " " + STAT + " " + value + " " + LY + " " + cycle + " " + Core.REG_FF0F);
if (((STAT & 3) == 0) && STAT.Bit(3) && !glitch_state) { HBL_INT = true; } else { HBL_INT = false; }
//if (((STAT & 3) == 1) && STAT.Bit(4)) { VBL_INT = true; } else if ((STAT & 3) == 1) { VBL_INT = false; }
// OAM not triggered?
// if (((STAT & 3) == 2) && STAT.Bit(5)) { OAM_INT = true; } else { OAM_INT = false; }
if (value.Bit(6) && LCDC.Bit(7))
{
@ -593,7 +590,6 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
stat_line_old = VBL_INT | HBL_INT | OAM_INT;
if (LY == 144) { HBL_INT = false; }
}
// glitchy check of mode 2
@ -602,7 +598,6 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
if (cycle <= 4)
{
if (!STAT.Bit(5)) { VBL_INT = false; }
if ((cycle == 4) && !STAT.Bit(4)) { VBL_INT = false; }
}
if ((cycle >= 2) && (cycle < 4))
@ -610,19 +605,18 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
// there is an edge case where a VBL INT is triggered if STAT bit 5 is set
if (STAT.Bit(5)) { VBL_INT = true; }
}
}
// mode 1 starts here, is asserted continuously
if (STAT.Bit(4))
if (cycle >= 4)
{
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
}
else
{
if (LY == 144)
{
if (cycle >= 4) { VBL_INT = true; }
}
else
{
VBL_INT = true;
}
// mode 1 is asserted continuously
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
if ((cycle == 4) && (LY == 144))
@ -719,6 +713,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
if (cycle < 4)
{
if (STAT.Bit(4) && ((STAT & 3) == 1)) { VBL_INT = true; }
else { VBL_INT = false; }
}
else
{

View File

@ -142,13 +142,10 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
break;
case 0xFF41: // STAT
// note that their is no stat interrupt bug in GBC
Console.WriteLine("stat " + " " + STAT + " " + value + " " + LY + " " + cycle + " " + Core.REG_FF0F);
//Console.WriteLine("stat " + " " + STAT + " " + value + " " + LY + " " + cycle + " " + Core.REG_FF0F);
STAT = (byte)((value & 0xF8) | (STAT & 7) | 0x80);
if (((STAT & 3) == 0) && STAT.Bit(3) && !glitch_state) { HBL_INT = true; } else { HBL_INT = false; }
//if (((STAT & 3) == 1) && STAT.Bit(4)) { VBL_INT = true; } else if ((STAT & 3) == 1) { VBL_INT = false; }
// OAM not triggered?
// if (((STAT & 3) == 2) && STAT.Bit(5)) { OAM_INT = true; } else { OAM_INT = false; }
if (value.Bit(6) && LCDC.Bit(7))
{
@ -595,7 +592,6 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
stat_line_old = VBL_INT | HBL_INT | OAM_INT;
if (LY == 144) { HBL_INT = false; }
}
// glitchy check of mode 2
@ -604,7 +600,6 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
if (cycle <= 4)
{
if (!STAT.Bit(5)) { VBL_INT = false; }
if ((cycle == 4) && !STAT.Bit(4)) { VBL_INT = false; }
}
if ((cycle >= 2) && (cycle < 4))
@ -612,19 +607,18 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
// there is an edge case where a VBL INT is triggered if STAT bit 5 is set
if (STAT.Bit(5)) { VBL_INT = true; }
}
}
// mode 1 starts here, is asserted continuously
if (STAT.Bit(4))
if (cycle >= 4)
{
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
}
else
{
if (LY == 144)
{
if (cycle >= 4) { VBL_INT = true; }
}
else
{
VBL_INT = true;
}
// mode 1 is asserted continuously
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
if ((cycle == 4) && (LY == 144))
@ -721,7 +715,8 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
// the last few cycles of mode 1 still trigger mode 1 int
if (cycle < 4)
{
if (STAT.Bit(4) && ((STAT & 3) == 1)) { VBL_INT = true; }
if (STAT.Bit(4) && ((STAT & 3) == 1)) { VBL_INT = true; }
else { VBL_INT = false; }
}
else
{

View File

@ -55,6 +55,8 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
case 0xFF41: // STAT
// writing to STAT during mode 0 or 1 causes a STAT IRQ
// this appears to be a glitchy LYC compare
//Console.WriteLine("stat " + " " + STAT + " " + value + " " + LY + " " + cycle + " " + Core.REG_FF0F);
if (!value.Bit(6)) { LYC_INT = false; }
if (LCDC.Bit(7))
@ -77,6 +79,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
STAT = (byte)((value & 0xF8) | (STAT & 7) | 0x80);
if (!STAT.Bit(4)) { VBL_INT = false; }
if (!STAT.Bit(3)) { HBL_INT = false; }
break;
case 0xFF42: // SCY
scroll_y = value;
@ -215,28 +218,31 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
// the VBL stat is continuously asserted
if (in_vbl)
{
if ((cycle <= 4) && (LY == 144))
// glitchy check of mode 2
if (LY == 144)
{
if (!STAT.Bit(5)) { VBL_INT = false; }
if ((cycle == 4) && !STAT.Bit(4)) { VBL_INT = false; }
}
if (STAT.Bit(4))
{
if (LY == 144)
if (cycle <= 4)
{
if (cycle >= 4) { VBL_INT = true; }
if (!STAT.Bit(5)) { VBL_INT = false; }
}
else
if ((cycle >= 2) && (cycle < 4))
{
VBL_INT = true;
// there is an edge case where a VBL INT is triggered if STAT bit 5 is set
if (STAT.Bit(5)) { VBL_INT = true; }
}
if (cycle >= 4)
{
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
}
if ((cycle >= 2) && (cycle < 4) && (LY == 144))
else
{
// there is an edge case where a VBL INT is triggered if STAT bit 5 is set
if (STAT.Bit(5)) { VBL_INT = true; }
// mode 1 is asserted continuously
if (STAT.Bit(4)) { VBL_INT = true; }
else { VBL_INT = false; }
}
if ((cycle == 4) && (LY == 144))
@ -334,6 +340,7 @@ namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
if (cycle < 4)
{
if (STAT.Bit(4) && ((STAT & 3) == 1)) { VBL_INT = true; }
else { VBL_INT = false; }
}
else
{