diff --git a/BizHawk.Emulation.Cores/Computers/MSX/MSX.IStatable.cs b/BizHawk.Emulation.Cores/Computers/MSX/MSX.IStatable.cs
index 05d0a907d2..a7be3096b3 100644
--- a/BizHawk.Emulation.Cores/Computers/MSX/MSX.IStatable.cs
+++ b/BizHawk.Emulation.Cores/Computers/MSX/MSX.IStatable.cs
@@ -60,13 +60,11 @@ namespace BizHawk.Emulation.Cores.Computers.MSX
 			{
 				ser.Sync(nameof(MSX_core), ref MSX_core, false);
 				LibMSX.MSX_load_state(MSX_Pntr, MSX_core);
-				Console.WriteLine("here1");
 			}
 			else
 			{
 				LibMSX.MSX_save_state(MSX_Pntr, MSX_core);
 				ser.Sync(nameof(MSX_core), ref MSX_core, false);
-				Console.WriteLine("here2");
 			}
 		}
 	}
diff --git a/libHawk/MSXHawk/MSXHawk/Z80A.h b/libHawk/MSXHawk/MSXHawk/Z80A.h
index b309f43c91..5e3b0e142b 100644
--- a/libHawk/MSXHawk/MSXHawk/Z80A.h
+++ b/libHawk/MSXHawk/MSXHawk/Z80A.h
@@ -343,14 +343,14 @@ namespace MSXHawk
 		uint32_t REP_OP_O_IRQS = 5;
 
 		// halt
-		uint32_t HALT_INST[4] = { IDLE,
-								WAIT,
-								OP_F,
-								OP };
+		uint32_t NO_HALT_INST[4] = { IDLE,
+									WAIT,
+									OP_F,
+									OP };
 
-		uint32_t HALT_BUSRQ[4] = { PCh, 0, 0, 0 };
-		uint32_t HALT_MEMRQ[4] = { PCh, 0, 0, 0 };
-		uint32_t HALT_IRQS = 4;
+		uint32_t NO_HALT_BUSRQ[4] = { PCh, 0, 0, 0 };
+		uint32_t NO_HALT_MEMRQ[4] = { PCh, 0, 0, 0 };
+		uint32_t NO_HALT_IRQS = 4;
 
 		// NMI
 		uint32_t NMI_INST[25] = { IDLE,
@@ -596,10 +596,10 @@ namespace MSXHawk
 				if (TraceCallback) { TraceCallback(0); }
 
 				bank_num = bank_offset = RegPCget();
+				RegPCset(bank_num + 1);
 				bank_offset &= low_mask;
 				bank_num = (bank_num >> bank_shift)& high_mask;
 				opcode = MemoryMap[bank_num][bank_offset];
-				RegPCset(RegPCget() + 1);
 				FetchInstruction();
 
 				temp_R = (Regs[R] & 0x7F);
@@ -859,11 +859,12 @@ namespace MSXHawk
 				}
 
 				bank_num = bank_offset = RegPCget();
+				RegPCset(bank_num + 1);
 				bank_offset &= low_mask;
 				bank_num = (bank_num >> bank_shift)& high_mask;
-				opcode = MemoryMap[bank_num][bank_offset];
-				RegPCset(RegPCget() + 1);
+				opcode = MemoryMap[bank_num][bank_offset];			
 				FetchInstruction();
+
 				instr_pntr = bus_pntr = mem_pntr = irq_pntr = 0;
 				I_skip = true;
 				break;
@@ -1255,10 +1256,10 @@ namespace MSXHawk
 				// otherwise start a new normal access
 				else if (!halted)
 				{
-					cur_instr_ofst = &HALT_INST[0];
-					cur_bus_ofst = &HALT_BUSRQ[0];
-					cur_mem_ofst = &HALT_MEMRQ[0];
-					cur_irqs_ofst = &HALT_IRQS;
+					cur_instr_ofst = &NO_HALT_INST[0];
+					cur_bus_ofst = &NO_HALT_BUSRQ[0];
+					cur_mem_ofst = &NO_HALT_MEMRQ[0];
+					cur_irqs_ofst = &NO_HALT_IRQS;
 
 					instr_bank = 11;
 
@@ -5530,10 +5531,10 @@ namespace MSXHawk
 			}
 			else if (instr_bank == 11)
 			{
-				cur_instr_ofst = &HALT_INST[0];
-				cur_bus_ofst = &HALT_BUSRQ[0];
-				cur_mem_ofst = &HALT_MEMRQ[0];
-				cur_irqs_ofst = &HALT_IRQS;
+				cur_instr_ofst = &NO_HALT_INST[0];
+				cur_bus_ofst = &NO_HALT_BUSRQ[0];
+				cur_mem_ofst = &NO_HALT_MEMRQ[0];
+				cur_irqs_ofst = &NO_HALT_IRQS;
 			}
 			else if (instr_bank == 12)
 			{