diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Execute.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Execute.cs
index 8feed65cbe..987c876bc5 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Execute.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Execute.cs
@@ -858,7 +858,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 					case 0xC8: RET_COND(FlagZ);							break; // RET Z
 					case 0xC9: RET_();									break; // RET
 					case 0xCA: JP_COND(FlagZ);							break; // JP Z
-					case 0xCB: PREFIX_(IXCBpre);						break; // PREFIX IXCB
+					case 0xCB: PREFETCH_(IXCBpre);						break; // PREFIX IXCB
 					case 0xCC: CALL_COND(FlagZ);						break; // CALL Z
 					case 0xCD: CALL_COND(true);							break; // CALL
 					case 0xCE: REG_OP_IND_INC(ADC8, A, PCl, PCh);		break; // ADC A, n
@@ -1123,7 +1123,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 					case 0xC8: RET_COND(FlagZ);							break; // RET Z
 					case 0xC9: RET_();									break; // RET
 					case 0xCA: JP_COND(FlagZ);							break; // JP Z
-					case 0xCB: PREFIX_(IYCBpre);						break; // PREFIy IyCB
+					case 0xCB: PREFETCH_(IYCBpre);						break; // PREFIX IyCB
 					case 0xCC: CALL_COND(FlagZ);						break; // CALL Z
 					case 0xCD: CALL_COND(true);							break; // CALL
 					case 0xCE: REG_OP_IND_INC(ADC8, A, PCl, PCh);		break; // ADC A, n
@@ -1183,28 +1183,6 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 				// the first byte fetched is the prefetch value to use with the instruction
 				// we pick Ix or Iy here, the indexed value is stored in WZ
 				// In this way, we don't need to pass them as an argument to the I_Funcs.
-				if (IXCB_prefetch)
-				{
-					IXCB_prefetch = false;
-					PF = opcode;
-					Regs[ALU] = PF;
-					Regs[W] = Regs[Ixh];
-					Regs[Z] = Regs[Ixl];
-					PREFETCH_(Ixl, Ixh);
-					return;
-				}
-
-				if (IYCB_prefetch)
-				{
-					IYCB_prefetch = false;
-					PF = opcode;
-					Regs[ALU] = PF;
-					Regs[W] = Regs[Iyh];
-					Regs[Z] = Regs[Iyl];
-					PREFETCH_(Iyl, Iyh);					
-					return;
-				}
-
 				IXCB_prefix = false;
 				IYCB_prefix = false;
 				NO_prefix = true;
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs
index a41949ee0c..240d2ce06f 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs
@@ -184,15 +184,15 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 							RD_INC, Z, PCl, PCh,
 							IDLE,
 							ASGN, W, 0,
+							IDLE,
+							IDLE,
 							ADDS, PCl, PCh, Z, W,
 							TR16, Z, W, PCl, PCh,
-							IDLE,
-							IDLE,
 							WAIT,					
 							OP_F,
 							OP };
 
-				BUSRQ = new ushort[] {PCh, 0, 0, 0, 0, 0, 0, 0, PCh, 0, 0, 0};
+				BUSRQ = new ushort[] {PCh, 0, 0, PCh, PCh, PCh, PCh, PCh, PCh, 0, 0, 0};
 			}
 			else
 			{
@@ -459,15 +459,30 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 			BUSRQ = new ushort[] { PCh, 0, 0, 0 };
 		}
 
-		private void PREFETCH_(ushort src_l, ushort src_h)
+		private void PREFETCH_(ushort src)
 		{
+			if (src == IXCBpre)
+			{
+				Regs[W] = Regs[Ixh];
+				Regs[Z] = Regs[Ixl];
+			}
+			else
+			{
+				Regs[W] = Regs[Iyh];
+				Regs[Z] = Regs[Iyl];
+			}
+
 			cur_instr = new ushort[]
-						{ADDS, Z, W, ALU, ZERO,
+						{IDLE,
+						WAIT,
+						RD_INC, ALU, PCl, PCh,
+						ADDS, Z, W, ALU, ZERO,
 						WAIT,
 						OP_F,
-						PREFIX, IXYprefetch };
+						IDLE,
+						PREFIX, src,};
 
-			BUSRQ = new ushort[] { PCh, 0, 0, 0 };
+			BUSRQ = new ushort[] { PCh, 0, 0, PCh, 0, 0, 0, 0 };
 		}
 
 		private void DI_()
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
index 051b727a0d..5617d14940 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
@@ -561,8 +561,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 					if (prefix_src == EXTDpre) { EXTD_prefix = true; }
 					if (prefix_src == IXpre) { IX_prefix = true; }
 					if (prefix_src == IYpre) { IY_prefix = true; }
-					if (prefix_src == IXCBpre) { IXCB_prefix = true; IXCB_prefetch = true; }
-					if (prefix_src == IYCBpre) { IYCB_prefix = true; IYCB_prefetch = true; }
+					if (prefix_src == IXCBpre) { IXCB_prefix = true; }
+					if (prefix_src == IYCBpre) { IYCB_prefix = true; }
 
 					RegPC++;
 					FetchInstruction();