From 6388e4a0a8b33661fbec70ce1b6a96c78218bd52 Mon Sep 17 00:00:00 2001
From: CasualPokePlayer <50538166+CasualPokePlayer@users.noreply.github.com>
Date: Wed, 28 Sep 2022 03:24:48 -0700
Subject: [PATCH] more vjaguar cleanup

---
 Assets/dll/virtualjaguar.wbx.zst              |   Bin 185994 -> 180853 bytes
 waterbox/virtualjaguar/BizInterface.cpp       |     2 +-
 waterbox/virtualjaguar/src/cdhle.cpp          |    26 +-
 waterbox/virtualjaguar/src/dsp.cpp            |     1 -
 waterbox/virtualjaguar/src/gpu.cpp            |     1 -
 waterbox/virtualjaguar/src/jagdasm.cpp        |   189 -
 waterbox/virtualjaguar/src/jagdasm.h          |     9 -
 waterbox/virtualjaguar/src/jaguar.cpp         |     8 +-
 waterbox/virtualjaguar/src/m68000/cpudefs.h   |     2 -
 waterbox/virtualjaguar/src/m68000/cpuemu.c    | 25705 ----------------
 waterbox/virtualjaguar/src/m68000/cpuextra.c  |   323 +-
 waterbox/virtualjaguar/src/m68000/cpuextra.h  |    11 +-
 waterbox/virtualjaguar/src/m68000/cpustbl.c   |  1586 +-
 waterbox/virtualjaguar/src/m68000/cputbl.h    |  3160 --
 waterbox/virtualjaguar/src/m68000/gencpu.c    |  2818 --
 waterbox/virtualjaguar/src/m68000/inlines.h   |   127 +-
 waterbox/virtualjaguar/src/m68000/m68kdasm.c  |   421 -
 .../virtualjaguar/src/m68000/m68kinterface.c  |   484 +-
 .../virtualjaguar/src/m68000/m68kinterface.h  |    30 +-
 waterbox/virtualjaguar/src/m68000/readcpu.c   |   108 +-
 waterbox/virtualjaguar/src/m68000/readcpu.h   |     3 +-
 waterbox/virtualjaguar/src/m68000/sysdeps.h   |    61 -
 waterbox/virtualjaguar/src/m68000/table68k    |   260 -
 23 files changed, 67 insertions(+), 35268 deletions(-)
 delete mode 100644 waterbox/virtualjaguar/src/jagdasm.cpp
 delete mode 100644 waterbox/virtualjaguar/src/jagdasm.h
 delete mode 100644 waterbox/virtualjaguar/src/m68000/gencpu.c
 delete mode 100644 waterbox/virtualjaguar/src/m68000/m68kdasm.c
 delete mode 100644 waterbox/virtualjaguar/src/m68000/table68k

diff --git a/Assets/dll/virtualjaguar.wbx.zst b/Assets/dll/virtualjaguar.wbx.zst
index 1ddde9803d4a9edf21c72db866c07db0ddb1ef45..125f17bd31788140b6307604c3a85ba804262dc8 100644
GIT binary patch
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DL$+v&

diff --git a/waterbox/virtualjaguar/BizInterface.cpp b/waterbox/virtualjaguar/BizInterface.cpp
index ea89ea087c..7a2ba10802 100644
--- a/waterbox/virtualjaguar/BizInterface.cpp
+++ b/waterbox/virtualjaguar/BizInterface.cpp
@@ -356,7 +356,7 @@ EXPORT void GetRegisters(u32* regs)
 {
 	for (u32 i = 0; i < 18; i++)
 	{
-		regs[i] = m68k_get_reg(NULL, (m68k_register_t)i);
+		regs[i] = m68k_get_reg((m68k_register_t)i);
 	}
 	memcpy(&regs[18], gpu_reg_bank_0, 128);
 	memcpy(&regs[50], gpu_reg_bank_1, 128);
diff --git a/waterbox/virtualjaguar/src/cdhle.cpp b/waterbox/virtualjaguar/src/cdhle.cpp
index dbd2a34dd1..76ffb2156e 100644
--- a/waterbox/virtualjaguar/src/cdhle.cpp
+++ b/waterbox/virtualjaguar/src/cdhle.cpp
@@ -336,7 +336,7 @@ static void ResetCallbacks(void)
 
 static void LoadISRStub(void)
 {
-	uint32_t isrAddr = m68k_get_reg(NULL, M68K_REG_A0);
+	uint32_t isrAddr = m68k_get_reg(M68K_REG_A0);
 	uint32_t addr = 0xF03010;
 
 	#define WRITE_GASM(x) do { GPUWriteWord(addr, x, M68K); addr += 2; } while (0)
@@ -405,7 +405,7 @@ void CDHLEHook(uint32_t which)
 
 static void CD_init(void)
 {
-	fprintf(stderr, "CD_init called %08X\n", m68k_get_reg(NULL, M68K_REG_A0));
+	fprintf(stderr, "CD_init called %08X\n", m68k_get_reg(M68K_REG_A0));
 	LoadISRStub();
 	cd_initm = false;
 }
@@ -414,7 +414,7 @@ static void CD_mode(void)
 {
 	// bit 0 = speed (0 = single, 1 = double)
 	// bit 1 = mode (0 = audio, 1 = data)
-	cd_mode = m68k_get_reg(NULL, M68K_REG_D0) & 3;
+	cd_mode = m68k_get_reg(M68K_REG_D0) & 3;
 	fprintf(stderr, "CD_mode mode = %d, speed = %d\n", cd_mode >> 1, cd_mode & 1);
 	NO_ERR();
 }
@@ -426,7 +426,7 @@ static void CD_ack(void)
 
 static void CD_jeri(void)
 {
-	bool njerry = m68k_get_reg(NULL, M68K_REG_D0) & 1;
+	bool njerry = m68k_get_reg(M68K_REG_D0) & 1;
 	if (cd_jerry ^ njerry)
 	{
 		fprintf(stderr, "changing jerry mode %d -> %d\n", cd_jerry, njerry);
@@ -437,7 +437,7 @@ static void CD_jeri(void)
 
 static void CD_spin(void)
 {
-	fprintf(stderr, "CD_spin: new session %04X\n", m68k_get_reg(NULL, M68K_REG_D1) & 0xFFFF);
+	fprintf(stderr, "CD_spin: new session %04X\n", m68k_get_reg(M68K_REG_D1) & 0xFFFF);
 	NO_ERR();
 }
 
@@ -486,8 +486,8 @@ static void CD_upaus(void)
 
 static void CD_read(void)
 {
-	uint32_t dstStart = m68k_get_reg(NULL, M68K_REG_A0);
-	uint32_t dstEnd = m68k_get_reg(NULL, M68K_REG_A1);
+	uint32_t dstStart = m68k_get_reg(M68K_REG_A0);
+	uint32_t dstEnd = m68k_get_reg(M68K_REG_A1);
 
 	fprintf(stderr, "CD READ: dstStart %08X, dstEnd %08X\n", dstStart, dstEnd);
 
@@ -498,7 +498,7 @@ static void CD_read(void)
 		return;
 	}
 
-	uint32_t timecode = m68k_get_reg(NULL, M68K_REG_D0);
+	uint32_t timecode = m68k_get_reg(M68K_REG_D0);
 
 	uint32_t frames = timecode & 0xFF;
 	uint32_t seconds = (timecode >> 8) & 0xFF;
@@ -517,8 +517,8 @@ static void CD_read(void)
 	{
 		if (cd_initm)
 		{
-			uint32_t marker = m68k_get_reg(NULL, M68K_REG_D1);
-			uint32_t circBufSz = m68k_get_reg(NULL, M68K_REG_D2);
+			uint32_t marker = m68k_get_reg(M68K_REG_D1);
+			uint32_t circBufSz = m68k_get_reg(M68K_REG_D2);
 			fprintf(stderr, "cd_initm read: marker %04X, circBufSz %04X\n", marker, circBufSz);
 			uint32_t lba = (minutes * 60 + seconds) * 75 + frames - 150;
 			uint8_t buf2352[2352 + 128];
@@ -630,7 +630,7 @@ static void CD_ptr(void)
 
 static void CD_osamp(void)
 {
-	cd_osamp = m68k_get_reg(NULL, M68K_REG_D0) & 3;
+	cd_osamp = m68k_get_reg(M68K_REG_D0) & 3;
 	NO_ERR();
 }
 
@@ -641,14 +641,14 @@ static void CD_getoc(void)
 
 static void CD_initm(void)
 {
-	fprintf(stderr, "CD_initm called %08X\n", m68k_get_reg(NULL, M68K_REG_A0));
+	fprintf(stderr, "CD_initm called %08X\n", m68k_get_reg(M68K_REG_A0));
 	LoadISRStub();
 	cd_initm = true;
 }
 
 static void CD_initf(void)
 {
-	fprintf(stderr, "CD_initf called %08X\n", m68k_get_reg(NULL, M68K_REG_A0));
+	fprintf(stderr, "CD_initf called %08X\n", m68k_get_reg(M68K_REG_A0));
 	LoadISRStub();
 	cd_initm = false;
 }
diff --git a/waterbox/virtualjaguar/src/dsp.cpp b/waterbox/virtualjaguar/src/dsp.cpp
index b0a0393906..9d997ffdc5 100644
--- a/waterbox/virtualjaguar/src/dsp.cpp
+++ b/waterbox/virtualjaguar/src/dsp.cpp
@@ -19,7 +19,6 @@
 #include <stdlib.h>
 #include "dac.h"
 #include "gpu.h"
-#include "jagdasm.h"
 #include "jaguar.h"
 #include "jerry.h"
 #include "m68000/m68kinterface.h"
diff --git a/waterbox/virtualjaguar/src/gpu.cpp b/waterbox/virtualjaguar/src/gpu.cpp
index 7cf108cc12..c3cc625698 100644
--- a/waterbox/virtualjaguar/src/gpu.cpp
+++ b/waterbox/virtualjaguar/src/gpu.cpp
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <string.h>
 #include "dsp.h"
-#include "jagdasm.h"
 #include "jaguar.h"
 #include "m68000/m68kinterface.h"
 #include "tom.h"
diff --git a/waterbox/virtualjaguar/src/jagdasm.cpp b/waterbox/virtualjaguar/src/jagdasm.cpp
deleted file mode 100644
index 4ce77e5b6c..0000000000
--- a/waterbox/virtualjaguar/src/jagdasm.cpp
+++ /dev/null
@@ -1,189 +0,0 @@
-//
-// Jaguar RISC Disassembly
-//
-// Originally by David Raingeard
-// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS)
-// Minor cleanups by James Hammons
-// (C) 2012 Underground Software
-//
-// JLH = James Hammons <jlhamm@acm.org>
-//
-// Who  When        What
-// ---  ----------  -------------------------------------------------------------
-// JLH  06/01/2012  Created this log (long overdue! ;-)
-// JLH  01/23/2013  Beautifying of disassembly, including hex digits of opcodes
-//                  and operands
-//
-
-#include "jagdasm.h"
-
-#include <stdio.h>
-#include "jaguar.h"
-
-#define ROPCODE(a) JaguarReadWord(a)
-
-uint8_t convert_zero[32] =
-{ 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 };
-
-const char * condition[32] =
-{
-	"",
-	"nz,",
-	"z,",
-	"???,",
-	"nc,",
-	"nc nz,",
-	"nc z,",
-	"???,",
-
-	"c,",
-	"c nz,",
-	"c z,",
-	"???,",
-	"???,",
-	"???,",
-	"???,",
-	"???,",
-
-	"???,",
-	"???,",
-	"???,",
-	"???,",
-	"nn,",
-	"nn nz,",
-	"nn z,",
-	"???,",
-
-	"n,",
-	"n nz,",
-	"n z,",
-	"???,",
-	"???,",
-	"???,",
-	"???,",
-	"never,"
-};
-
-char * signed_16bit(int16_t val)
-{
-	static char temp[10];
-
-	if (val < 0)
-		sprintf(temp, "-$%X", -val);
-	else
-		sprintf(temp, "$%X", val);
-
-	return temp;
-}
-
-unsigned dasmjag(int dsp_type, char * bufferOut, unsigned pc)
-{
-	char buffer[64];
-	int op = ROPCODE(pc);
-	int reg1 = (op >> 5) & 31;
-	int reg2 = op & 31;
-	int size = 2;
-	pc += 2;
-
-	switch (op >> 10)
-	{
-		case 0:		sprintf(buffer, "ADD     R%02d,R%02d", reg1, reg2);				break;
-		case 1:		sprintf(buffer, "ADDC    R%02d,R%02d", reg1, reg2);				break;
-		case 2:		sprintf(buffer, "ADDQ    $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 3:		sprintf(buffer, "ADDQT   $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 4:		sprintf(buffer, "SUB     R%02d,R%02d", reg1, reg2);				break;
-		case 5:		sprintf(buffer, "SUBC    R%02d,R%02d", reg1, reg2);				break;
-		case 6:		sprintf(buffer, "SUBQ    $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 7:		sprintf(buffer, "SUBQT   $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 8:		sprintf(buffer, "NEG     R%02d", reg2);							break;
-		case 9:		sprintf(buffer, "AND     R%02d,R%02d", reg1, reg2);				break;
-		case 10:	sprintf(buffer, "OR      R%02d,R%02d", reg1, reg2);				break;
-		case 11:	sprintf(buffer, "XOR     R%02d,R%02d", reg1, reg2);				break;
-		case 12:	sprintf(buffer, "NOT     R%02d", reg2);							break;
-		case 13:	sprintf(buffer, "BTST    $%X,R%02d", reg1, reg2);				break;
-		case 14:	sprintf(buffer, "BSET    $%X,R%02d", reg1, reg2);				break;
-		case 15:	sprintf(buffer, "BCLR    $%X,R%02d", reg1, reg2);				break;
-		case 16:	sprintf(buffer, "MULT    R%02d,R%02d", reg1, reg2);				break;
-		case 17:	sprintf(buffer, "IMULT   R%02d,R%02d", reg1, reg2);				break;
-		case 18:	sprintf(buffer, "IMULTN  R%02d,R%02d", reg1, reg2);				break;
-		case 19:	sprintf(buffer, "RESMAC  R%02d", reg2);							break;
-		case 20:	sprintf(buffer, "IMACN   R%02d,R%02d", reg1, reg2);				break;
-		case 21:	sprintf(buffer, "DIV     R%02d,R%02d", reg1, reg2);				break;
-		case 22:	sprintf(buffer, "ABS     R%02d", reg2);							break;
-		case 23:	sprintf(buffer, "SH      R%02d,R%02d", reg1, reg2);				break;
-		case 24:	sprintf(buffer, "SHLQ    $%X,R%02d", 32 - reg1, reg2);	break;
-		case 25:	sprintf(buffer, "SHRQ    $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 26:	sprintf(buffer, "SHA     R%02d,R%02d", reg1, reg2);				break;
-		case 27:	sprintf(buffer, "SHARQ   $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 28:	sprintf(buffer, "ROR     R%02d,R%02d", reg1, reg2);				break;
-		case 29:	sprintf(buffer, "RORQ    $%X,R%02d", convert_zero[reg1], reg2);	break;
-		case 30:	sprintf(buffer, "CMP     R%02d,R%02d", reg1, reg2);				break;
-		case 31:	sprintf(buffer, "CMPQ    %s,R%02d", signed_16bit((int16_t)(reg1 << 11) >> 11), reg2);break;
-		case 32:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, "SAT8    R%02d", reg2);
-					else
-						sprintf(buffer, "SUBQMOD $%X,R%02d", convert_zero[reg1], reg2);
-					break;
-		case 33:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, "SAT16   R%02d", reg2);
-					else
-						sprintf(buffer, "SAT16S  R%02d", reg2);
-					break;
-		case 34:	sprintf(buffer, "MOVE    R%02d,R%02d", reg1, reg2);				break;
-		case 35:	sprintf(buffer, "MOVEQ   %d,R%02d", reg1, reg2);				break;
-		case 36:	sprintf(buffer, "MOVETA  R%02d,R%02d", reg1, reg2);				break;
-		case 37:	sprintf(buffer, "MOVEFA  R%02d,R%02d", reg1, reg2);				break;
-		case 38:	sprintf(buffer, "MOVEI   #$%X,R%02d", ROPCODE(pc) | (ROPCODE(pc+2)<<16), reg2); size = 6; break;
-		case 39:	sprintf(buffer, "LOADB   (R%02d),R%02d", reg1, reg2);			break;
-		case 40:	sprintf(buffer, "LOADW   (R%02d),R%02d", reg1, reg2);			break;
-		case 41:	sprintf(buffer, "LOAD    (R%02d),R%02d", reg1, reg2);			break;
-		case 42:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, "LOADP   (R%02d),R%02d", reg1, reg2);
-					else
-						sprintf(buffer, "SAT32S  R%02d", reg2);
-					break;
-		case 43:	sprintf(buffer, "LOAD    (R14+$%X),R%02d", convert_zero[reg1]*4, reg2);break;
-		case 44:	sprintf(buffer, "LOAD    (R15+$%X),R%02d", convert_zero[reg1]*4, reg2);break;
-		case 45:	sprintf(buffer, "STOREB  R%02d,(R%02d)", reg2, reg1);			break;
-		case 46:	sprintf(buffer, "STOREW  R%02d,(R%02d)", reg2, reg1);			break;
-		case 47:	sprintf(buffer, "STORE   R%02d,(R%02d)", reg2, reg1);			break;
-		case 48:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, "STOREP  R%02d,(R%02d)", reg2, reg1);
-					else
-						sprintf(buffer, "MIRROR  R%02d", reg2);
-					break;
-		case 49:	sprintf(buffer, "STORE   R%02d,(R14+$%X)", reg2, convert_zero[reg1]*4);break;
-		case 50:	sprintf(buffer, "STORE   R%02d,(R15+$%X)", reg2, convert_zero[reg1]*4);break;
-		case 51:	sprintf(buffer, "MOVE    PC,R%02d", reg2);						break;
-		case 52:	sprintf(buffer, "JUMP    %s(R%02d)", condition[reg2], reg1);	break;
-		case 53:	sprintf(buffer, "JR      %s$%X", condition[reg2], pc + ((int8_t)(reg1 << 3) >> 2)); break;
-		case 54:	sprintf(buffer, "MMULT   R%02d,R%02d", reg1, reg2);				break;
-		case 55:	sprintf(buffer, "MTOI    R%02d,R%02d", reg1, reg2);				break;
-		case 56:	sprintf(buffer, "NORMI   R%02d,R%02d", reg1, reg2);				break;
-		case 57:	sprintf(buffer, "NOP");											break;
-		case 58:	sprintf(buffer, "LOAD    (R14+R%02d),R%02d", reg1, reg2);		break;
-		case 59:	sprintf(buffer, "LOAD    (R15+R%02d),R%02d", reg1, reg2);		break;
-		case 60:	sprintf(buffer, "STORE   R%02d,(R14+R%02d)", reg2, reg1);		break;
-		case 61:	sprintf(buffer, "STORE   R%02d,(R15+R%02d)", reg2, reg1);		break;
-		case 62:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, "SAT24   R%02d", reg2);
-					else
-						sprintf(buffer, "illegal [%d,%d]", reg1, reg2);
-					break;
-		case 63:	if (dsp_type == JAGUAR_GPU)
-						sprintf(buffer, (reg1 ? "UNPACK  R%02d" : "PACK    R%02d"), reg2);
-					else
-						sprintf(buffer, "ADDQMOD $%X,R%02d", convert_zero[reg1], reg2);
-					break;
-	}
-
-	if (size == 2)
-		sprintf(bufferOut, "%04X            %-24s", op, buffer);
-	else
-	{
-		uint16_t word1 = ROPCODE(pc), word2 = ROPCODE(pc + 2);
-		sprintf(bufferOut, "%04X %04X %04X  %-24s", op, word1, word2, buffer);
-	}
-
-	return size;
-}
diff --git a/waterbox/virtualjaguar/src/jagdasm.h b/waterbox/virtualjaguar/src/jagdasm.h
deleted file mode 100644
index 0171f2bd51..0000000000
--- a/waterbox/virtualjaguar/src/jagdasm.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __JAGDASM__
-#define __JAGDASM__
-
-#define JAGUAR_GPU 0
-#define JAGUAR_DSP 1
-
-unsigned dasmjag(int dsp_type, char * buffer, unsigned pc);
-
-#endif
diff --git a/waterbox/virtualjaguar/src/jaguar.cpp b/waterbox/virtualjaguar/src/jaguar.cpp
index e8a9208d7c..d11945c4e2 100644
--- a/waterbox/virtualjaguar/src/jaguar.cpp
+++ b/waterbox/virtualjaguar/src/jaguar.cpp
@@ -57,12 +57,12 @@ void M68KInstructionHook(void)
 {
 	if (jaguarCdInserted)
 	{
-		uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
+		uint32_t pc = m68k_get_reg(M68K_REG_PC);
 		if (pc >= 0x3000 && pc <= 0x306C)
 		{
 			CDHLEHook((pc - 0x3000) / 6);
 			// return
-			uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
+			uint32_t sp = m68k_get_reg(M68K_REG_SP);
 			m68k_set_reg(M68K_REG_PC, m68k_read_memory_32(sp));
 			m68k_set_reg(M68K_REG_SP, sp + 4);
 		}
@@ -73,12 +73,12 @@ void M68KInstructionHook(void)
 		uint32_t regs[18];
 		for (uint32_t i = 0; i < 18; i++)
 		{
-			regs[i] = m68k_get_reg(NULL, (m68k_register_t)i);
+			regs[i] = m68k_get_reg((m68k_register_t)i);
 		}
 		CPUTraceCallback(regs);
 	}
 
-	MAYBE_CALLBACK(ExecuteCallback, m68k_get_reg(NULL, M68K_REG_PC));
+	MAYBE_CALLBACK(ExecuteCallback, m68k_get_reg(M68K_REG_PC));
 }
 
 //
diff --git a/waterbox/virtualjaguar/src/m68000/cpudefs.h b/waterbox/virtualjaguar/src/m68000/cpudefs.h
index 191057f1f7..d6d7c6f22d 100644
--- a/waterbox/virtualjaguar/src/m68000/cpudefs.h
+++ b/waterbox/virtualjaguar/src/m68000/cpudefs.h
@@ -70,8 +70,6 @@ extern struct regstruct regs, lastint_regs;
 /* Possible exceptions sources for M68000_Exception() and Exception() */
 #define M68000_EXC_SRC_CPU      1  /* Direct CPU exception */
 #define M68000_EXC_SRC_AUTOVEC  2  /* Auto-vector exception (e.g. VBL) */
-//#define M68000_EXC_SRC_INT_MFP  3  /* MFP interrupt exception */
-//#define M68000_EXC_SRC_INT_DSP  4  /* DSP interrupt exception */
 
 #define SET_CFLG(x) (CFLG = (x))
 #define SET_NFLG(x) (NFLG = (x))
diff --git a/waterbox/virtualjaguar/src/m68000/cpuemu.c b/waterbox/virtualjaguar/src/m68000/cpuemu.c
index a97db34be9..205b2580f0 100644
--- a/waterbox/virtualjaguar/src/m68000/cpuemu.c
+++ b/waterbox/virtualjaguar/src/m68000/cpuemu.c
@@ -3,9 +3,6 @@
 #include "inlines.h"
 #include "cputbl.h"
 #define CPUFUNC(x) x##_ff
-#ifdef NOFLAGS
-#include "noflags.h"
-#endif
 
 const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };
 const int imm8_table[]   = { 8, 1, 2, 3, 4, 5, 6, 7 };
@@ -67,25685 +64,6 @@ const int movem_next[256] = {
 0xE0, 0xF0, 0xF0, 0xF2, 0xF0, 0xF4, 0xF4, 0xF6, 0xF0, 0xF8, 0xF8, 0xFA, 0xF8, 0xFC, 0xFC, 0xFE, 
 };
 
-
-#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
-#define PART_1 1
-#define PART_2 1
-#define PART_3 1
-#define PART_4 1
-#define PART_5 1
-#define PART_6 1
-#define PART_7 1
-#define PART_8 1
-#endif
-
-#ifdef PART_1
-unsigned long CPUFUNC(op_0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_10_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_18_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_20_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_28_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_30_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 22; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_38_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_39_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 24; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_3c_4)(uint32_t opcode) /* ORSR */
-{
-	OpcodeFamily = 4; CurrentInstrCycles = 20; 
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	src &= 0xFF;
-	regs.sr |= src;
-	MakeFromSR();
-}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_40_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_50_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_58_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_60_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_68_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_70_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_78_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_79_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_7c_4)(uint32_t opcode) /* ORSR */
-{
-	OpcodeFamily = 4; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel18; }
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	regs.sr |= src;
-	MakeFromSR();
-}}}m68k_incpc(4);
-endlabel18: ;
-return 20;
-}
-unsigned long CPUFUNC(op_80_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_90_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_98_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_a0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 30; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_a8_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_b0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 34; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_b8_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_b9_4)(uint32_t opcode) /* OR */
-{
-	OpcodeFamily = 1; CurrentInstrCycles = 36; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_100_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_108_4)(uint32_t opcode) /* MVPMR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 29; CurrentInstrCycles = 16; 
-{	uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	uint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_110_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_118_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_120_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 10; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_128_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_130_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_138_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_139_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 21; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_13a_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 2;
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_getpc () + 2;
-	dsta += (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_13b_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 3;
-	OpcodeFamily = 21; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_13c_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 21; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = get_ibyte(2);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_140_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_dreg(regs, dstreg) = (dst);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_148_4)(uint32_t opcode) /* MVPMR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 29; CurrentInstrCycles = 24; 
-{	uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	uint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16)
-              + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6);
-	m68k_dreg(regs, dstreg) = (val);
-}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_150_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_158_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_160_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_168_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_170_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_178_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 22; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_179_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 22; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_17a_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 2;
-	OpcodeFamily = 22; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_getpc () + 2;
-	dsta += (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_17b_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 3;
-	OpcodeFamily = 22; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_180_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 10; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_dreg(regs, dstreg) = (dst);
-	if ( src < 16 ) { m68k_incpc(2); return 8; }
-}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_188_4)(uint32_t opcode) /* MVPRM */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 28; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-	uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	m68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_190_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_198_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1a0_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_1a8_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1b0_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1b8_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 23; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1b9_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 23; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_1ba_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 2;
-	OpcodeFamily = 23; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_getpc () + 2;
-	dsta += (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1bb_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 3;
-	OpcodeFamily = 23; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1c0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_dreg(regs, dstreg) = (dst);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1c8_4)(uint32_t opcode) /* MVPRM */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 28; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-	uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	m68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16);
-	m68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src);
-}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_1d0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1d8_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1e0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_1e8_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1f0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1f8_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 24; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1f9_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 24; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_1fa_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 2;
-	OpcodeFamily = 24; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_getpc () + 2;
-	dsta += (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1fb_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = 3;
-	OpcodeFamily = 24; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_200_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_210_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_218_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_220_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_228_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_230_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 22; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_238_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_239_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 24; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_23c_4)(uint32_t opcode) /* ANDSR */
-{
-	OpcodeFamily = 5; CurrentInstrCycles = 20; 
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	src |= 0xFF00;
-	regs.sr &= src;
-	MakeFromSR();
-}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_240_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_250_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_258_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_260_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_268_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_270_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_278_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_279_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_27c_4)(uint32_t opcode) /* ANDSR */
-{
-	OpcodeFamily = 5; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel89; }
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	regs.sr &= src;
-	MakeFromSR();
-}}}m68k_incpc(4);
-endlabel89: ;
-return 20;
-}
-unsigned long CPUFUNC(op_280_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_290_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_298_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_2a0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 30; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_2a8_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_2b0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 34; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_2b8_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_2b9_4)(uint32_t opcode) /* AND */
-{
-	OpcodeFamily = 2; CurrentInstrCycles = 36; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_400_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_410_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_418_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_420_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_428_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_430_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 22; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_438_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_439_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_440_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_450_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_458_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_460_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_468_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_470_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_478_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_479_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_480_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_490_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_498_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_4a0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 30; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_4a8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_4b0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 34; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_4b8_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_4b9_4)(uint32_t opcode) /* SUB */
-{
-	OpcodeFamily = 7; CurrentInstrCycles = 36; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_600_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_610_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_618_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_620_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_628_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_630_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 22; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_638_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_639_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_640_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_650_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_658_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_660_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_668_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_670_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_678_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_679_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_680_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_690_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_698_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_6a0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 30; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_6a8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_6b0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 34; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_6b8_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_6b9_4)(uint32_t opcode) /* ADD */
-{
-	OpcodeFamily = 11; CurrentInstrCycles = 36; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_800_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 10; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}m68k_incpc(4);
-return 10;
-}
-unsigned long CPUFUNC(op_810_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_818_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_820_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 14; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_828_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_830_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 21; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_838_4)(uint32_t opcode) /* BTST */
-{
-	OpcodeFamily = 21; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_839_4)(uint32_t opcode) /* BTST */
-{
-	OpcodeFamily = 21; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(8);
-return 20;
-}
-unsigned long CPUFUNC(op_83a_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 21; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_83b_4)(uint32_t opcode) /* BTST */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 21; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_83c_4)(uint32_t opcode) /* BTST */
-{
-	OpcodeFamily = 21; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	int8_t dst = get_ibyte(4);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-}}}m68k_incpc(6);
-return 12;
-}
-unsigned long CPUFUNC(op_840_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_dreg(regs, dstreg) = (dst);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_850_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_858_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_860_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_868_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_870_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 22; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_878_4)(uint32_t opcode) /* BCHG */
-{
-	OpcodeFamily = 22; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_879_4)(uint32_t opcode) /* BCHG */
-{
-	OpcodeFamily = 22; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_87a_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 22; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_87b_4)(uint32_t opcode) /* BCHG */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 22; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	dst ^= (1 << src);
-	SET_ZFLG (((uint32_t)dst & (1 << src)) >> src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_880_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 14; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_dreg(regs, dstreg) = (dst);
-	if ( src < 16 ) { m68k_incpc(4); return 12; }
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_890_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_898_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8a0_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_8a8_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8b0_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 23; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_8b8_4)(uint32_t opcode) /* BCLR */
-{
-	OpcodeFamily = 23; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8b9_4)(uint32_t opcode) /* BCLR */
-{
-	OpcodeFamily = 23; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_8ba_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 23; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8bb_4)(uint32_t opcode) /* BCLR */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 23; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst &= ~(1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_8c0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= 31;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_dreg(regs, dstreg) = (dst);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_8d0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8d8_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8e0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_8e8_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8f0_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 24; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_8f8_4)(uint32_t opcode) /* BSET */
-{
-	OpcodeFamily = 24; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8f9_4)(uint32_t opcode) /* BSET */
-{
-	OpcodeFamily = 24; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_8fa_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 24; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8fb_4)(uint32_t opcode) /* BSET */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 24; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= 7;
-	SET_ZFLG (1 ^ ((dst >> src) & 1));
-	dst |= (1 << src);
-	m68k_write_memory_8(dsta,dst);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_a00_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_a10_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_a18_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_a20_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_a28_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_a30_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 22; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_a38_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_a39_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 24; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_a3c_4)(uint32_t opcode) /* EORSR */
-{
-	OpcodeFamily = 6; CurrentInstrCycles = 20; 
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	src &= 0xFF;
-	regs.sr ^= src;
-	MakeFromSR();
-}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_a40_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_a50_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_a58_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_a60_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_a68_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_a70_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 22; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_a78_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_a79_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 24; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_a7c_4)(uint32_t opcode) /* EORSR */
-{
-	OpcodeFamily = 6; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel204; }
-{	MakeSR();
-{	int16_t src = get_iword(2);
-	regs.sr ^= src;
-	MakeFromSR();
-}}}m68k_incpc(4);
-endlabel204: ;
-return 20;
-}
-#endif
-
-#ifdef PART_2
-unsigned long CPUFUNC(op_a80_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_a90_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_a98_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_aa0_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 30; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_aa8_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_ab0_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 34; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_ab8_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 32; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_ab9_4)(uint32_t opcode) /* EOR */
-{
-	OpcodeFamily = 3; CurrentInstrCycles = 36; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_c00_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_c10_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c18_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c20_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c28_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c30_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_c38_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c39_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 20;
-}
-unsigned long CPUFUNC(op_c3a_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c3b_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_c40_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_c50_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c58_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c60_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c68_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c70_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_c78_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c79_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 20;
-}
-unsigned long CPUFUNC(op_c7a_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_getpc () + 4;
-	dsta += (int32_t)(int16_t)get_iword(4);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c7b_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_c80_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(6);
-return 14;
-}
-unsigned long CPUFUNC(op_c90_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_c98_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_ca0_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 22; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_ca8_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 24; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_cb0_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 26; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_cb8_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 24; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_cb9_4)(uint32_t opcode) /* CMP */
-{
-	OpcodeFamily = 25; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(10);
-return 28;
-}
-unsigned long CPUFUNC(op_cba_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 2;
-	OpcodeFamily = 25; CurrentInstrCycles = 24; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_getpc () + 6;
-	dsta += (int32_t)(int16_t)get_iword(6);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_cbb_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = 3;
-	OpcodeFamily = 25; CurrentInstrCycles = 26; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t tmppc = m68k_getpc() + 6;
-	uint32_t dsta = get_disp_ea_000(tmppc, get_iword(6));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_1000_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_1008_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_1010_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1018_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1020_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_1028_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1030_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_1038_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1039_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_103a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_103b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_103c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_1080_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1088_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1090_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1098_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_10a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_10a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_10b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_10ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_10bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_10c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_10c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_10d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_10d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_10e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_10e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_10f8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10f9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_10fa_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_10fb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_10fc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1100_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1108_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_1110_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1118_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_1120_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_1128_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1130_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1138_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1139_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_113a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_113b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_113c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1140_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1148_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_1150_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1158_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_1160_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1168_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_1170_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_1178_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_1179_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_117a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_117b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_117c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_1180_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_1188_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_1190_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_1198_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_11a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_11a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_11b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 24;
-}
-unsigned long CPUFUNC(op_11b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_11b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_11ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_11bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 24;
-}
-unsigned long CPUFUNC(op_11bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_11c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_11c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_11d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_11d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_11e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_11e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_11f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_11f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_11f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_11fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_11fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_11fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_13c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_13c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_13d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_13d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_13e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_13e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_13f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_13f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_13f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(10);
-return 28;
-}
-unsigned long CPUFUNC(op_13fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_13fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_13fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int8_t src = get_ibyte(2);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}m68k_incpc(8);
-return 20;
-}
-unsigned long CPUFUNC(op_2000_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_2008_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_2010_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2018_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2020_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_2028_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2030_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_2038_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2039_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_203a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_203b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_203c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = get_ilong(2);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 12;
-}
-unsigned long CPUFUNC(op_2040_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_2048_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_2050_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2058_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2060_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_2068_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2070_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_2078_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2079_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_207a_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_207b_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_207c_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t val = src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(6);
-return 12;
-}
-unsigned long CPUFUNC(op_2080_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2088_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2090_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_2098_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_20a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_20a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_20b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_20ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_20bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_20c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_20c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_20d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_20d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_20e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_20e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_20f8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20f9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_20fa_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_20fb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_20fc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_2100_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2108_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_2110_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_2118_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_2120_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_2128_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_2130_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_2138_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-#endif
-
-#ifdef PART_3
-unsigned long CPUFUNC(op_2139_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_213a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_213b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_213c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_2140_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2148_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_2150_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_2158_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_2160_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_2168_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_2170_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_2178_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_2179_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_217a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_217b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_217c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_2180_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_2188_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_2190_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_2198_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_21a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 28;
-}
-unsigned long CPUFUNC(op_21a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_21b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 32;
-}
-unsigned long CPUFUNC(op_21b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_21b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 34; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_21ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_21bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 32;
-}
-unsigned long CPUFUNC(op_21bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_21c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_21c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_21d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_21d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_21e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_21e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_21f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_21f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_21f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_21fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_21fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_21fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_23c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_23c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_23d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_23d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_23e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 30; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 30;
-}
-unsigned long CPUFUNC(op_23e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_23f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 34; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_23f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_23f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 36; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(10);
-return 36;
-}
-unsigned long CPUFUNC(op_23fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 32; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 32;
-}
-unsigned long CPUFUNC(op_23fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 34; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(8);
-return 34;
-}
-unsigned long CPUFUNC(op_23fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	int32_t src = get_ilong(2);
-{	uint32_t dsta = get_ilong(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}m68k_incpc(10);
-return 28;
-}
-unsigned long CPUFUNC(op_3000_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_3008_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_3010_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3018_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3020_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_3028_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3030_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_3038_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3039_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_303a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_303b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_303c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_3040_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_3048_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_3050_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3058_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3060_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_3068_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3070_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_3078_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3079_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_307a_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_307b_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_307c_4)(uint32_t opcode) /* MOVEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 31; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	uint32_t val = (int32_t)(int16_t)src;
-	m68k_areg(regs, dstreg) = (val);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_3080_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3088_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3090_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_3098_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_30a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_30a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_30b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_30ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_30bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_30c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_30c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_30d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_30d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_30e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_30e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_30f8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30f9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_30fa_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_30fb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_30fc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-	m68k_areg(regs, dstreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3100_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3108_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_3110_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_3118_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_3120_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_3128_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_3130_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_3138_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_3139_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_313a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_313b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_313c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-	m68k_areg (regs, dstreg) = dsta;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3140_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3148_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_3150_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_3158_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_3160_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_3168_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_3170_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_3178_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_3179_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_317a_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_317b_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_317c_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_3180_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_3188_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_3190_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_3198_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_31a0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_31a8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_31b0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 24;
-}
-unsigned long CPUFUNC(op_31b8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_31b9_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_31ba_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_31bb_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 24;
-}
-unsigned long CPUFUNC(op_31bc_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_31c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_31c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_31d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_31d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_31e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_31e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_31f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_31f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_31f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_31fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_31fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_31fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_33c0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_33c8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_33d0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_33d8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_33e0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_33e8_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_33f0_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_33f8_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_33f9_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(6);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(10);
-return 28;
-}
-unsigned long CPUFUNC(op_33fa_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 24;
-}
-unsigned long CPUFUNC(op_33fb_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 26; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(8);
-return 26;
-}
-unsigned long CPUFUNC(op_33fc_4)(uint32_t opcode) /* MOVE */
-{
-	OpcodeFamily = 30; CurrentInstrCycles = 20; 
-{{	int16_t src = get_iword(2);
-{	uint32_t dsta = get_ilong(4);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}m68k_incpc(8);
-return 20;
-}
-unsigned long CPUFUNC(op_4000_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
-}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4010_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4018_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4020_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4028_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4030_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4038_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4039_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4040_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4050_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4058_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4060_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4068_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4070_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4078_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4079_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(srca,newv);
-}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4080_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, srcreg) = (newv);
-}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_4090_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_4098_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_40a0_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_40a8_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_40b0_4)(uint32_t opcode) /* NEGX */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 16; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_40b8_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_40b9_4)(uint32_t opcode) /* NEGX */
-{
-	OpcodeFamily = 16; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(srca,newv);
-}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_40c0_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 6;  
-{{	MakeSR();
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
-}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_40d0_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_40d8_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += 2;
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_40e0_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-	m68k_areg (regs, srcreg) = srca;
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_40e8_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_40f0_4)(uint32_t opcode) /* MVSR2 */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 32; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_40f8_4)(uint32_t opcode) /* MVSR2 */
-{
-	OpcodeFamily = 32; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_40f9_4)(uint32_t opcode) /* MVSR2 */
-{
-	OpcodeFamily = 32; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-	MakeSR();
-	m68k_write_memory_16(srca,regs.sr);
-}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4180_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 10; 
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; }
-}}}endlabel587: ;
-return 10;
-}
-unsigned long CPUFUNC(op_4190_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; }
-}}}}endlabel588: ;
-return 14;
-}
-unsigned long CPUFUNC(op_4198_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; }
-}}}}endlabel589: ;
-return 14;
-}
-unsigned long CPUFUNC(op_41a0_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 16; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; }
-}}}}endlabel590: ;
-return 16;
-}
-unsigned long CPUFUNC(op_41a8_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 18; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; }
-}}}}endlabel591: ;
-return 18;
-}
-unsigned long CPUFUNC(op_41b0_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 20; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; }
-}}}}endlabel592: ;
-return 20;
-}
-unsigned long CPUFUNC(op_41b8_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 18; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; }
-}}}}endlabel593: ;
-return 18;
-}
-unsigned long CPUFUNC(op_41b9_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 22; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(6);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; }
-}}}}endlabel594: ;
-return 22;
-}
-unsigned long CPUFUNC(op_41ba_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 18; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; }
-}}}}endlabel595: ;
-return 18;
-}
-unsigned long CPUFUNC(op_41bb_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 20; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; }
-}}}}endlabel596: ;
-return 20;
-}
-unsigned long CPUFUNC(op_41bc_4)(uint32_t opcode) /* CHK */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 80; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; }
-	else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; }
-}}}endlabel597: ;
-return 14;
-}
-unsigned long CPUFUNC(op_41d0_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 4;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_41e8_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_41f0_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_41f8_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 8;  
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_41f9_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 12; 
-{{	uint32_t srca = get_ilong(2);
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(6);
-return 12;
-}
-unsigned long CPUFUNC(op_41fa_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_41fb_4)(uint32_t opcode) /* LEA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 56; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	m68k_areg(regs, dstreg) = (srca);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_4200_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 4;  
-{{	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4210_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4218_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4220_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4228_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4230_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4238_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4239_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(0)) == 0);
-	SET_NFLG (((int8_t)(0)) < 0);
-	m68k_write_memory_8(srca,0);
-}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4240_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 4;  
-{{	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4250_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4258_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += 2;
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4260_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-	m68k_areg (regs, srcreg) = srca;
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4268_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(4);
-return 16;
-}
-#endif
-
-#ifdef PART_4
-unsigned long CPUFUNC(op_4270_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4278_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4279_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(0)) == 0);
-	SET_NFLG (((int16_t)(0)) < 0);
-	m68k_write_memory_16(srca,0);
-}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4280_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 6;  
-{{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_dreg(regs, srcreg) = (0);
-}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_4290_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_4298_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += 4;
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_42a0_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-	m68k_areg (regs, srcreg) = srca;
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_42a8_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_42b0_4)(uint32_t opcode) /* CLR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 18; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_42b8_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_42b9_4)(uint32_t opcode) /* CLR */
-{
-	OpcodeFamily = 18; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(0)) == 0);
-	SET_NFLG (((int32_t)(0)) < 0);
-	m68k_write_memory_32(srca,0);
-}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_4400_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4410_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4418_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4420_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4428_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4430_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4438_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4439_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(0)) < 0;
-	int flgn = ((int8_t)(dst)) < 0;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(srca,dst);
-}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4440_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4450_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4458_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4460_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4468_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4470_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4478_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4479_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(0)) < 0;
-	int flgn = ((int16_t)(dst)) < 0;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(srca,dst);
-}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4480_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, srcreg) = (dst);
-}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_4490_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_4498_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_44a0_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_44a8_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_44b0_4)(uint32_t opcode) /* NEG */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 15; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_44b8_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_44b9_4)(uint32_t opcode) /* NEG */
-{
-	OpcodeFamily = 15; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(0)) < 0;
-	int flgn = ((int32_t)(dst)) < 0;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(srca,dst);
-}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_44c0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_44d0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_44d8_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_44e0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_44e8_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_44f0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(4);
-return 22;
-}
-unsigned long CPUFUNC(op_44f8_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_44f9_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 24; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(6);
-return 24;
-}
-unsigned long CPUFUNC(op_44fa_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_44fb_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}}m68k_incpc(4);
-return 22;
-}
-unsigned long CPUFUNC(op_44fc_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{{	int16_t src = get_iword(2);
-	MakeSR();
-	regs.sr &= 0xFF00;
-	regs.sr |= src & 0xFF;
-	MakeFromSR();
-}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4600_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4610_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4618_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4620_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4628_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4630_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4638_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4639_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(dst)) == 0);
-	SET_NFLG (((int8_t)(dst)) < 0);
-	m68k_write_memory_8(srca,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4640_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4650_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4658_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4660_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4668_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4670_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4678_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4679_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_write_memory_16(srca,dst);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4680_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (dst);
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_4690_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_4698_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_46a0_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 22; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_46a8_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 24; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_46b0_4)(uint32_t opcode) /* NOT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 19; CurrentInstrCycles = 26; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_46b8_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 24; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_46b9_4)(uint32_t opcode) /* NOT */
-{
-	OpcodeFamily = 19; CurrentInstrCycles = 28; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	uint32_t dst = ~src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_write_memory_32(srca,dst);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_46c0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 12; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel688; }
-{{	int16_t src = m68k_dreg(regs, srcreg);
-	regs.sr = src;
-	MakeFromSR();
-}}}m68k_incpc(2);
-endlabel688: ;
-return 12;
-}
-unsigned long CPUFUNC(op_46d0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel689; }
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(2);
-endlabel689: ;
-return 16;
-}
-unsigned long CPUFUNC(op_46d8_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel690; }
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(2);
-endlabel690: ;
-return 16;
-}
-unsigned long CPUFUNC(op_46e0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 18; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel691; }
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(2);
-endlabel691: ;
-return 18;
-}
-unsigned long CPUFUNC(op_46e8_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel692; }
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(4);
-endlabel692: ;
-return 20;
-}
-unsigned long CPUFUNC(op_46f0_4)(uint32_t opcode) /* MV2SR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 33; CurrentInstrCycles = 22; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel693; }
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(4);
-endlabel693: ;
-return 22;
-}
-unsigned long CPUFUNC(op_46f8_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel694; }
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(4);
-endlabel694: ;
-return 20;
-}
-unsigned long CPUFUNC(op_46f9_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 24; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel695; }
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(6);
-endlabel695: ;
-return 24;
-}
-unsigned long CPUFUNC(op_46fa_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel696; }
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(4);
-endlabel696: ;
-return 20;
-}
-unsigned long CPUFUNC(op_46fb_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 22; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel697; }
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	regs.sr = src;
-	MakeFromSR();
-}}}}m68k_incpc(4);
-endlabel697: ;
-return 22;
-}
-unsigned long CPUFUNC(op_46fc_4)(uint32_t opcode) /* MV2SR */
-{
-	OpcodeFamily = 33; CurrentInstrCycles = 16; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel698; }
-{{	int16_t src = get_iword(2);
-	regs.sr = src;
-	MakeFromSR();
-}}}m68k_incpc(4);
-endlabel698: ;
-return 16;
-}
-unsigned long CPUFUNC(op_4800_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 6;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_4810_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4818_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4820_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4828_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4830_4)(uint32_t opcode) /* NBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 17; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4838_4)(uint32_t opcode) /* NBCD */
-{
-	OpcodeFamily = 17; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4839_4)(uint32_t opcode) /* NBCD */
-{
-	OpcodeFamily = 17; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = - (src & 0xF0);
-	uint16_t newv;
-	int cflg;
-	if (newv_lo > 9) { newv_lo -= 6; }
-	newv = newv_hi + newv_lo;	cflg = (newv & 0x1F0) > 0x90;
-	if (cflg) newv -= 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(srca,newv);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4840_4)(uint32_t opcode) /* SWAP */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 34; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (dst);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4850_4)(uint32_t opcode) /* PEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 57; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4868_4)(uint32_t opcode) /* PEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 57; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4870_4)(uint32_t opcode) /* PEA */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 57; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(4);
-return 22;
-}
-unsigned long CPUFUNC(op_4878_4)(uint32_t opcode) /* PEA */
-{
-	OpcodeFamily = 57; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4879_4)(uint32_t opcode) /* PEA */
-{
-	OpcodeFamily = 57; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_487a_4)(uint32_t opcode) /* PEA */
-{
-	OpcodeFamily = 57; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_487b_4)(uint32_t opcode) /* PEA */
-{
-	OpcodeFamily = 57; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	uint32_t dsta = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = dsta;
-	m68k_write_memory_32(dsta,srca);
-}}}m68k_incpc(4);
-return 22;
-}
-unsigned long CPUFUNC(op_4880_4)(uint32_t opcode) /* EXT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 36; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint16_t dst = (int16_t)(int8_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(dst)) == 0);
-	SET_NFLG (((int16_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4890_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 8;  
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(4);
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_48a0_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 8;  
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) - 0;
-{	uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
-	while (amask) { srca -= 2; m68k_write_memory_16(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; }
-	while (dmask) { srca -= 2; m68k_write_memory_16(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; }
-	m68k_areg(regs, dstreg) = srca;
-}}}m68k_incpc(4);
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_48a8_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_48b0_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 14; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_48b8_4)(uint32_t opcode) /* MVMLE */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = (int32_t)(int16_t)get_iword(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_48b9_4)(uint32_t opcode) /* MVMLE */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = get_ilong(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(8);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_48c0_4)(uint32_t opcode) /* EXT */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 36; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dst = (int32_t)(int16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(dst)) == 0);
-	SET_NFLG (((int32_t)(dst)) < 0);
-	m68k_dreg(regs, srcreg) = (dst);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_48d0_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 8;  
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(4);
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_48e0_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 8;  
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) - 0;
-{	uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
-	while (amask) { srca -= 4; m68k_write_memory_32(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; }
-	while (dmask) { srca -= 4; m68k_write_memory_32(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; }
-	m68k_areg(regs, dstreg) = srca;
-}}}m68k_incpc(4);
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_48e8_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_48f0_4)(uint32_t opcode) /* MVMLE */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 14; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_48f8_4)(uint32_t opcode) /* MVMLE */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = (int32_t)(int16_t)get_iword(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_48f9_4)(uint32_t opcode) /* MVMLE */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 38; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	retcycles = 0;
-{	uint32_t srca = get_ilong(4);
-{	uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(8);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4a00_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4a10_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_4a18_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_4a20_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_4a28_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a30_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_4a38_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a39_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_4a3a_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a3b_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_4a3c_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_4a40_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4a48_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4a50_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_4a58_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_4a60_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_4a68_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a70_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_4a78_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a79_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_4a7a_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_4a7b_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_4a7c_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_4a80_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4a88_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 4;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4a90_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4a98_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4aa0_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4aa8_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4ab0_4)(uint32_t opcode) /* TST */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 20; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4ab8_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4ab9_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_4aba_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_4abb_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4abc_4)(uint32_t opcode) /* TST */
-{
-	OpcodeFamily = 20; CurrentInstrCycles = 12; 
-{{	int32_t src = get_ilong(2);
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-}}m68k_incpc(6);
-return 12;
-}
-unsigned long CPUFUNC(op_4ac0_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
-}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4ad0_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4ad8_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_4ae0_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_4ae8_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4af0_4)(uint32_t opcode) /* TAS */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 98; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_4af8_4)(uint32_t opcode) /* TAS */
-{
-	OpcodeFamily = 98; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4af9_4)(uint32_t opcode) /* TAS */
-{
-	OpcodeFamily = 98; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	src |= 0x80;
-	m68k_write_memory_8(srca,src);
-}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_4c90_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(4);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_4c98_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-	m68k_areg(regs, dstreg) = srca;
-}}}m68k_incpc(4);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_4ca8_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cb0_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 18; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (18+retcycles);
-}
-unsigned long CPUFUNC(op_4cb8_4)(uint32_t opcode) /* MVMEL */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cb9_4)(uint32_t opcode) /* MVMEL */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 20; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = get_ilong(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(8);
- return (20+retcycles);
-}
-unsigned long CPUFUNC(op_4cba_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = 2;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_getpc () + 4;
-	srca += (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cbb_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = 3;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 18; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; }
-}}}m68k_incpc(6);
- return (18+retcycles);
-}
-unsigned long CPUFUNC(op_4cd0_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(4);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_4cd8_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 12; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-	m68k_areg(regs, dstreg) = srca;
-}}}m68k_incpc(4);
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_4ce8_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cf0_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 18; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4));
-	BusCyclePenalty += 2;
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (18+retcycles);
-}
-unsigned long CPUFUNC(op_4cf8_4)(uint32_t opcode) /* MVMEL */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cf9_4)(uint32_t opcode) /* MVMEL */
-{
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 20; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = get_ilong(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(8);
- return (20+retcycles);
-}
-unsigned long CPUFUNC(op_4cfa_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = 2;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 16; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t srca = m68k_getpc () + 4;
-	srca += (int32_t)(int16_t)get_iword(4);
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_4cfb_4)(uint32_t opcode) /* MVMEL */
-{
-	uint32_t dstreg = 3;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 37; CurrentInstrCycles = 18; 
-{	uint16_t mask = get_iword(2);
-	unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
-	retcycles = 0;
-{	uint32_t tmppc = m68k_getpc() + 4;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(4));
-	BusCyclePenalty += 2;
-{	while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; }
-	while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; }
-}}}m68k_incpc(6);
- return (18+retcycles);
-}
-unsigned long CPUFUNC(op_4e40_4)(uint32_t opcode) /* TRAP */
-{
-	uint32_t srcreg = (opcode & 15);
-	OpcodeFamily = 39; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-m68k_incpc(2);
-	Exception(src+32,0,M68000_EXC_SRC_CPU);
-}}return 4;
-}
-unsigned long CPUFUNC(op_4e50_4)(uint32_t opcode) /* LINK */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 47; CurrentInstrCycles = 18; 
-{{	uint32_t olda = m68k_areg(regs, 7) - 4;
-	m68k_areg (regs, 7) = olda;
-{	int32_t src = m68k_areg(regs, srcreg);
-	m68k_write_memory_32(olda,src);
-	m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
-{	int16_t offs = get_iword(2);
-	m68k_areg(regs, 7) += offs;
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_4e58_4)(uint32_t opcode) /* UNLK */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 48; CurrentInstrCycles = 12; 
-{{	int32_t src = m68k_areg(regs, srcreg);
-	m68k_areg(regs, 7) = src;
-{	uint32_t olda = m68k_areg(regs, 7);
-{	int32_t old = m68k_read_memory_32(olda);
-	m68k_areg(regs, 7) += 4;
-	m68k_areg(regs, srcreg) = (old);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_4e60_4)(uint32_t opcode) /* MVR2USP */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 40; CurrentInstrCycles = 4;  
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel791; }
-{{	int32_t src = m68k_areg(regs, srcreg);
-	regs.usp = src;
-}}}m68k_incpc(2);
-endlabel791: ;
-return 4;
-}
-unsigned long CPUFUNC(op_4e68_4)(uint32_t opcode) /* MVUSP2R */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 41; CurrentInstrCycles = 4;  
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel792; }
-{{	m68k_areg(regs, srcreg) = (regs.usp);
-}}}m68k_incpc(2);
-endlabel792: ;
-return 4;
-}
-unsigned long CPUFUNC(op_4e70_4)(uint32_t opcode) /* RESET */
-{
-	OpcodeFamily = 42; CurrentInstrCycles = 132;
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel793; }
-{}}m68k_incpc(2);
-endlabel793: ;
-return 132;
-}
-unsigned long CPUFUNC(op_4e71_4)(uint32_t opcode) /* NOP */
-{
-	OpcodeFamily = 43; CurrentInstrCycles = 4;  
-{}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_4e72_4)(uint32_t opcode) /* STOP */
-{
-	OpcodeFamily = 44; CurrentInstrCycles = 4;  
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel795; }
-{{	int16_t src = get_iword(2);
-	regs.sr = src;
-	MakeFromSR();
-	m68k_setstopped(1);
-}}}m68k_incpc(4);
-endlabel795: ;
-return 4;
-}
-unsigned long CPUFUNC(op_4e73_4)(uint32_t opcode) /* RTE */
-{
-	OpcodeFamily = 45; CurrentInstrCycles = 20; 
-{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel796; }
-{{	uint32_t sra = m68k_areg(regs, 7);
-{	int16_t sr = m68k_read_memory_16(sra);
-	m68k_areg(regs, 7) += 2;
-{	uint32_t pca = m68k_areg(regs, 7);
-{	int32_t pc = m68k_read_memory_32(pca);
-	m68k_areg(regs, 7) += 4;
-	regs.sr = sr; m68k_setpc_rte(pc);
-	MakeFromSR();
-}}}}}}endlabel796: ;
-return 20;
-}
-unsigned long CPUFUNC(op_4e74_4)(uint32_t opcode) /* RTD */
-{
-	OpcodeFamily = 46; CurrentInstrCycles = 16; 
-{{	uint32_t pca = m68k_areg(regs, 7);
-{	int32_t pc = m68k_read_memory_32(pca);
-	m68k_areg(regs, 7) += 4;
-{	int16_t offs = get_iword(2);
-	m68k_areg(regs, 7) += offs;
-	m68k_setpc_rte(pc);
-}}}}return 16;
-}
-unsigned long CPUFUNC(op_4e75_4)(uint32_t opcode) /* RTS */
-{
-	OpcodeFamily = 49; CurrentInstrCycles = 16; 
-{	m68k_do_rts();
-}return 16;
-}
-unsigned long CPUFUNC(op_4e76_4)(uint32_t opcode) /* TRAPV */
-{
-	OpcodeFamily = 50; CurrentInstrCycles = 4;  
-{m68k_incpc(2);
-	if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel799; }
-}endlabel799: ;
-return 4;
-}
-unsigned long CPUFUNC(op_4e77_4)(uint32_t opcode) /* RTR */
-{
-	OpcodeFamily = 51; CurrentInstrCycles = 20; 
-{	MakeSR();
-{	uint32_t sra = m68k_areg(regs, 7);
-{	int16_t sr = m68k_read_memory_16(sra);
-	m68k_areg(regs, 7) += 2;
-{	uint32_t pca = m68k_areg(regs, 7);
-{	int32_t pc = m68k_read_memory_32(pca);
-	m68k_areg(regs, 7) += 4;
-	regs.sr &= 0xFF00; sr &= 0xFF;
-	regs.sr |= sr; m68k_setpc(pc);
-	MakeFromSR();
-}}}}}return 20;
-}
-unsigned long CPUFUNC(op_4e90_4)(uint32_t opcode) /* JSR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 52; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	uint32_t oldpc = m68k_getpc () + 2;
-	m68k_do_jsr(m68k_getpc() + 2, srca);
-}}return 16;
-}
-unsigned long CPUFUNC(op_4ea8_4)(uint32_t opcode) /* JSR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 52; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	uint32_t oldpc = m68k_getpc () + 4;
-	m68k_do_jsr(m68k_getpc() + 4, srca);
-}}return 18;
-}
-unsigned long CPUFUNC(op_4eb0_4)(uint32_t opcode) /* JSR */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 52; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	uint32_t oldpc = m68k_getpc () + 4;
-	m68k_do_jsr(m68k_getpc() + 4, srca);
-}}return 22;
-}
-unsigned long CPUFUNC(op_4eb8_4)(uint32_t opcode) /* JSR */
-{
-	OpcodeFamily = 52; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	uint32_t oldpc = m68k_getpc () + 4;
-	m68k_do_jsr(m68k_getpc() + 4, srca);
-}}return 18;
-}
-unsigned long CPUFUNC(op_4eb9_4)(uint32_t opcode) /* JSR */
-{
-	OpcodeFamily = 52; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-	uint32_t oldpc = m68k_getpc () + 6;
-	m68k_do_jsr(m68k_getpc() + 6, srca);
-}}return 20;
-}
-unsigned long CPUFUNC(op_4eba_4)(uint32_t opcode) /* JSR */
-{
-	OpcodeFamily = 52; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-	uint32_t oldpc = m68k_getpc () + 4;
-	m68k_do_jsr(m68k_getpc() + 4, srca);
-}}return 18;
-}
-unsigned long CPUFUNC(op_4ebb_4)(uint32_t opcode) /* JSR */
-{
-	OpcodeFamily = 52; CurrentInstrCycles = 22; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-	uint32_t oldpc = m68k_getpc () + 4;
-	m68k_do_jsr(m68k_getpc() + 4, srca);
-}}return 22;
-}
-unsigned long CPUFUNC(op_4ed0_4)(uint32_t opcode) /* JMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 53; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_setpc(srca);
-}}return 8;
-}
-unsigned long CPUFUNC(op_4ee8_4)(uint32_t opcode) /* JMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 53; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-	m68k_setpc(srca);
-}}return 10;
-}
-unsigned long CPUFUNC(op_4ef0_4)(uint32_t opcode) /* JMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 53; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-	m68k_setpc(srca);
-}}return 14;
-}
-unsigned long CPUFUNC(op_4ef8_4)(uint32_t opcode) /* JMP */
-{
-	OpcodeFamily = 53; CurrentInstrCycles = 10; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-	m68k_setpc(srca);
-}}return 10;
-}
-unsigned long CPUFUNC(op_4ef9_4)(uint32_t opcode) /* JMP */
-{
-	OpcodeFamily = 53; CurrentInstrCycles = 12; 
-{{	uint32_t srca = get_ilong(2);
-	m68k_setpc(srca);
-}}return 12;
-}
-unsigned long CPUFUNC(op_4efa_4)(uint32_t opcode) /* JMP */
-{
-	OpcodeFamily = 53; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-	m68k_setpc(srca);
-}}return 10;
-}
-unsigned long CPUFUNC(op_4efb_4)(uint32_t opcode) /* JMP */
-{
-	OpcodeFamily = 53; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-	m68k_setpc(srca);
-}}return 14;
-}
-unsigned long CPUFUNC(op_5000_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5010_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5018_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-#endif
-
-#ifdef PART_5
-unsigned long CPUFUNC(op_5020_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5028_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5030_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5038_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5039_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5040_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5048_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5050_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5058_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5060_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5068_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5070_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5078_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5079_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5080_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5088_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5090_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_5098_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_50a0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 22; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_50a8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_50b0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 26; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_50b8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_50b9_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 11; CurrentInstrCycles = 28; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_50c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(0) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_50c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(0)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel842: ;
-return 12;
-}
-unsigned long CPUFUNC(op_50d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_50d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_50e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_50e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_50f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_50f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_50f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(0) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5100_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5110_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5118_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5120_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5128_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5130_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5138_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5139_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5140_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5148_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5150_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5158_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5160_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5168_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5170_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5178_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5179_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5180_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5188_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_5190_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_5198_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_51a0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 22; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_51a8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_51b0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 26; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_51b8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_51b9_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	OpcodeFamily = 7; CurrentInstrCycles = 28; 
-{{	uint32_t src = srcreg;
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_51c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(1) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_51c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(1)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel877: ;
-return 12;
-}
-unsigned long CPUFUNC(op_51d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_51d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_51e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_51e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_51f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_51f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_51f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(1) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_52c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(2) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_52c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(2)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel886: ;
-return 12;
-}
-unsigned long CPUFUNC(op_52d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_52d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_52e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_52e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_52f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_52f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_52f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(2) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_53c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(3) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_53c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(3)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel895: ;
-return 12;
-}
-unsigned long CPUFUNC(op_53d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_53d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_53e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_53e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_53f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_53f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_53f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(3) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_54c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(4) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_54c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(4)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel904: ;
-return 12;
-}
-unsigned long CPUFUNC(op_54d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_54d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_54e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_54e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_54f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_54f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_54f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(4) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_55c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(5) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_55c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(5)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel913: ;
-return 12;
-}
-unsigned long CPUFUNC(op_55d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_55d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_55e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_55e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_55f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_55f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_55f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(5) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_56c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(6) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_56c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(6)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel922: ;
-return 12;
-}
-unsigned long CPUFUNC(op_56d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_56d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_56e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_56e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_56f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_56f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_56f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(6) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_57c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(7) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_57c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(7)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel931: ;
-return 12;
-}
-unsigned long CPUFUNC(op_57d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_57d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_57e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_57e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_57f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_57f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_57f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(7) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_58c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(8) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_58c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(8)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel940: ;
-return 12;
-}
-unsigned long CPUFUNC(op_58d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_58d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_58e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_58e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_58f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_58f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_58f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(8) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_59c0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(9) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_59c8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(9)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel949: ;
-return 12;
-}
-unsigned long CPUFUNC(op_59d0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_59d8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_59e0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_59e8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_59f0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_59f8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_59f9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(9) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5ac0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(10) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5ac8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(10)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel958: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5ad0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5ad8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5ae0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5ae8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5af0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5af8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5af9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(10) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5bc0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(11) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5bc8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(11)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel967: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5bd0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5bd8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5be0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5be8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5bf0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5bf8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5bf9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(11) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5cc0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(12) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5cc8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(12)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel976: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5cd0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5cd8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5ce0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5ce8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5cf0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5cf8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5cf9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(12) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5dc0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(13) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5dc8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(13)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel985: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5dd0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5dd8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5de0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5de8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5df0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5df8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5df9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(13) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5ec0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(14) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5ec8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(14)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel994: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5ed0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5ed8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5ee0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_5ee8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5ef0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5ef8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5ef9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(14) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_5fc0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 4;  
-{{{	int val = cctrue(15) ? 0xff : 0;
-	m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
-	if (val) { m68k_incpc(2) ; return 4+2; }
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_5fc8_4)(uint32_t opcode) /* DBcc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 58; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t offs = get_iword(2);
-	if (!cctrue(15)) {
-		m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff);
-		if (src) {
-			m68k_incpc((int32_t)offs + 2);
-			return 10;
-		} else {
-			m68k_incpc(4);
-			return 14;
-		}
-	}
-}}}m68k_incpc(4);
-endlabel1003: ;
-return 12;
-}
-unsigned long CPUFUNC(op_5fd0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5fd8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_5fe0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-	m68k_areg (regs, srcreg) = srca;
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(2);
-return 14;
-}
-#endif
-
-#ifdef PART_6
-unsigned long CPUFUNC(op_5fe8_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5ff0_4)(uint32_t opcode) /* Scc */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 59; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_5ff8_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_5ff9_4)(uint32_t opcode) /* Scc */
-{
-	OpcodeFamily = 59; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int val = cctrue(15) ? 0xff : 0;
-	m68k_write_memory_8(srca,val);
-}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_6000_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(0)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1011: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6001_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(0)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1012: ;
-return 8;
-}
-unsigned long CPUFUNC(op_60ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(0)) goto endlabel1013;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1013;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(0)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1013: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6100_4)(uint32_t opcode) /* BSR */
-{
-	OpcodeFamily = 54; CurrentInstrCycles = 18; 
-{{	int16_t src = get_iword(2);
-	int32_t s = (int32_t)src + 2;
-	m68k_do_bsr(m68k_getpc() + 4, s);
-}}return 18;
-}
-unsigned long CPUFUNC(op_6101_4)(uint32_t opcode) /* BSR */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 54; CurrentInstrCycles = 18; 
-{{	uint32_t src = srcreg;
-	int32_t s = (int32_t)src + 2;
-	m68k_do_bsr(m68k_getpc() + 2, s);
-}}return 18;
-}
-unsigned long CPUFUNC(op_61ff_4)(uint32_t opcode) /* BSR */
-{
-	OpcodeFamily = 54; CurrentInstrCycles = 18; 
-{{	int32_t src = get_ilong(2);
-	int32_t s = (int32_t)src + 2;
-	m68k_do_bsr(m68k_getpc() + 6, s);
-}}return 18;
-}
-unsigned long CPUFUNC(op_6200_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(2)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1017: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6201_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(2)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1018: ;
-return 8;
-}
-unsigned long CPUFUNC(op_62ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(2)) goto endlabel1019;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1019;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(2)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1019: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6300_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(3)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1020: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6301_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(3)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1021: ;
-return 8;
-}
-unsigned long CPUFUNC(op_63ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(3)) goto endlabel1022;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1022;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(3)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1022: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6400_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(4)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1023: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6401_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(4)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1024: ;
-return 8;
-}
-unsigned long CPUFUNC(op_64ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(4)) goto endlabel1025;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1025;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(4)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1025: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6500_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(5)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1026: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6501_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(5)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1027: ;
-return 8;
-}
-unsigned long CPUFUNC(op_65ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(5)) goto endlabel1028;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1028;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(5)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1028: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6600_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(6)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1029: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6601_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(6)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1030: ;
-return 8;
-}
-unsigned long CPUFUNC(op_66ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(6)) goto endlabel1031;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1031;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(6)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1031: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6700_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(7)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1032: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6701_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(7)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1033: ;
-return 8;
-}
-unsigned long CPUFUNC(op_67ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(7)) goto endlabel1034;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1034;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(7)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1034: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6800_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(8)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1035: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6801_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(8)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1036: ;
-return 8;
-}
-unsigned long CPUFUNC(op_68ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(8)) goto endlabel1037;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1037;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(8)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1037: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6900_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(9)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1038: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6901_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(9)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1039: ;
-return 8;
-}
-unsigned long CPUFUNC(op_69ff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(9)) goto endlabel1040;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1040;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(9)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1040: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6a00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(10)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1041: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6a01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(10)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1042: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6aff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(10)) goto endlabel1043;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1043;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(10)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1043: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6b00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(11)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1044: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6b01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(11)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1045: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6bff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(11)) goto endlabel1046;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1046;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(11)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1046: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6c00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(12)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1047: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6c01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(12)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1048: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6cff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(12)) goto endlabel1049;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1049;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(12)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1049: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6d00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(13)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1050: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6d01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(13)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1051: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6dff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(13)) goto endlabel1052;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1052;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(13)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1052: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6e00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(14)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1053: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6e01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(14)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1054: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6eff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(14)) goto endlabel1055;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1055;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(14)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1055: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6f00_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-	if (!cctrue(15)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(4);
-endlabel1056: ;
-return 12;
-}
-unsigned long CPUFUNC(op_6f01_4)(uint32_t opcode) /* Bcc */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	OpcodeFamily = 55; CurrentInstrCycles = 8;  
-{{	uint32_t src = srcreg;
-	if (!cctrue(15)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(2);
-endlabel1057: ;
-return 8;
-}
-unsigned long CPUFUNC(op_6fff_4)(uint32_t opcode) /* Bcc */
-{
-	OpcodeFamily = 55; CurrentInstrCycles = 12; 
-{	m68k_incpc(2);
-	if (!cctrue(15)) goto endlabel1058;
-		last_addr_for_exception_3 = m68k_getpc() + 2;
-		last_fault_for_exception_3 = m68k_getpc() + 1;
-		last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1058;
-{	int32_t src = get_ilong(2);
-	if (!cctrue(15)) goto didnt_jump;
-	m68k_incpc ((int32_t)src + 2);
-	return 10;
-didnt_jump:;
-}}m68k_incpc(6);
-endlabel1058: ;
-return 12;
-}
-unsigned long CPUFUNC(op_7000_4)(uint32_t opcode) /* MOVE */
-{
-	uint32_t srcreg = (int32_t)(int8_t)(opcode & 255);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 30; CurrentInstrCycles = 4;  
-{{	uint32_t src = srcreg;
-{	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_8000_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_8010_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_8018_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_8020_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_8028_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_8030_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_8038_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_8039_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_803a_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_803b_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_803c_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_8040_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_8050_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_8058_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_8060_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_8068_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_8070_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_8078_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_8079_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_807a_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_807b_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_807c_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_8080_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_8090_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_8098_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_80a0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_80a8_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_80b0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_80b8_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_80b9_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_80ba_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_80bb_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_80bc_4)(uint32_t opcode) /* OR */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_80c0_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 4;  
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1093; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}endlabel1093: ;
- return (4+retcycles);
-}
-unsigned long CPUFUNC(op_80d0_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1094; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1094: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_80d8_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1095; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1095: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_80e0_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 10; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1096; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1096: ;
- return (10+retcycles);
-}
-unsigned long CPUFUNC(op_80e8_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1097; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1097: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_80f0_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1098; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1098: ;
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_80f8_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1099; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1099: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_80f9_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 16; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(6);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1100; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1100: ;
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_80fa_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1101; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1101: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_80fb_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1102; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}}endlabel1102: ;
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_80fc_4)(uint32_t opcode) /* DIVU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 60; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1103; } else {
-	uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;
-	uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src;
-	if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);
-}}}endlabel1103: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_8100_4)(uint32_t opcode) /* SBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 10; CurrentInstrCycles = 6;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0);
-	uint16_t newv, tmp_newv;
-	int bcd = 0;
-	newv = tmp_newv = newv_hi + newv_lo;
-	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
-	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
-	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_8108_4)(uint32_t opcode) /* SBCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 10; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0);
-	uint16_t newv, tmp_newv;
-	int bcd = 0;
-	newv = tmp_newv = newv_hi + newv_lo;
-	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
-	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
-	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_8110_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_8118_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_8120_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_8128_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8130_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_8138_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8139_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8150_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_8158_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_8160_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_8168_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8170_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 18; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_8178_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_8179_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_8190_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_8198_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_81a0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 22; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_81a8_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_81b0_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 1; CurrentInstrCycles = 26; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_81b8_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_81b9_4)(uint32_t opcode) /* OR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 1; CurrentInstrCycles = 28; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src |= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_81c0_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 4;  
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1127; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}endlabel1127: ;
- return (4+retcycles);
-}
-unsigned long CPUFUNC(op_81d0_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1128; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1128: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_81d8_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1129; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1129: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_81e0_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 10; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(2);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1130; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1130: ;
- return (10+retcycles);
-}
-unsigned long CPUFUNC(op_81e8_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1131; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1131: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_81f0_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1132; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1132: ;
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_81f8_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1133; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1133: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_81f9_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 16; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(6);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1134; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1134: ;
- return (16+retcycles);
-}
-unsigned long CPUFUNC(op_81fa_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 12; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1135; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1135: ;
- return (12+retcycles);
-}
-unsigned long CPUFUNC(op_81fb_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 14; 
-{	uint32_t oldpc = m68k_getpc();
-{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1136; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}}endlabel1136: ;
- return (14+retcycles);
-}
-unsigned long CPUFUNC(op_81fc_4)(uint32_t opcode) /* DIVS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 61; CurrentInstrCycles = 8;  
-{	uint32_t oldpc = m68k_getpc();
-{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-m68k_incpc(4);
-	if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1137; } else {
-	int32_t newv = (int32_t)dst / (int32_t)(int16_t)src;
-	uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src;
-	if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else
-	{
-	if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_NFLG (((int16_t)(newv)) < 0);
-	newv = (newv & 0xffff) | ((uint32_t)rem << 16);
-	m68k_dreg(regs, dstreg) = (newv);
-	}
-	}
-	retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);
-}}}endlabel1137: ;
- return (8+retcycles);
-}
-unsigned long CPUFUNC(op_9000_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_9010_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9018_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9020_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_9028_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_9030_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_9038_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_9039_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_903a_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_903b_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_903c_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_9040_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_9048_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_9050_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9058_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9060_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_9068_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_9070_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_9078_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_9079_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_907a_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_907b_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_907c_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_9080_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9088_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9090_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_9098_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_90a0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_90a8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_90b0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_90b8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_90b9_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_90ba_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_90bb_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_90bc_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_90c0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_90c8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_90d0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_90d8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_90e0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_90e8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_90f0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_90f8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_90f9_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_90fa_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_90fb_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_90fc_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_9100_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_9108_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_9110_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_9118_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_9120_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_9128_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_9130_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_9138_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_9139_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_9140_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_9148_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_9150_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_9158_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_9160_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_9168_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_9170_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 18; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_9178_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_9179_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_9180_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_9188_4)(uint32_t opcode) /* SUBX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 9; CurrentInstrCycles = 30; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst - src - (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 30;
-}
-unsigned long CPUFUNC(op_9190_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_9198_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_91a0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 22; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_91a8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_91b0_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 7; CurrentInstrCycles = 26; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_91b8_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_91b9_4)(uint32_t opcode) /* SUB */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 7; CurrentInstrCycles = 28; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_91c0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_91c8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_91d0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_91d8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_91e0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_91e8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_91f0_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_91f8_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_91f9_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_91fa_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_91fb_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_91fc_4)(uint32_t opcode) /* SUBA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 8; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst - src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_b000_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_b010_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_b018_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_b020_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_b028_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b030_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b038_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b039_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_b03a_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b03b_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-#endif
-
-#ifdef PART_7
-unsigned long CPUFUNC(op_b03c_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_b040_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_b048_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_b050_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_b058_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_b060_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_b068_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b070_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b078_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b079_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_b07a_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_b07b_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b07c_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_b080_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b088_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b090_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b098_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b0a0_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_b0a8_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b0b0_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_b0b8_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b0b9_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_b0ba_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b0bb_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_b0bc_4)(uint32_t opcode) /* CMP */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 25; CurrentInstrCycles = 14; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(6);
-return 14;
-}
-unsigned long CPUFUNC(op_b0c0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 6;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b0c8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 6;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b0d0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_b0d8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_b0e0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b0e8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b0f0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b0f8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b0f9_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 18;
-}
-unsigned long CPUFUNC(op_b0fa_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_b0fb_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 16; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b0fc_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 10; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(4);
-return 10;
-}
-unsigned long CPUFUNC(op_b100_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_b108_4)(uint32_t opcode) /* CMPM */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 26; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b110_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b118_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b120_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b128_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b130_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b138_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b139_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_b140_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_b148_4)(uint32_t opcode) /* CMPM */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 26; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b150_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b158_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_b160_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b168_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b170_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 18; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b178_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_b179_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_b180_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_b188_4)(uint32_t opcode) /* CMPM */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 26; CurrentInstrCycles = 20; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_b190_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_b198_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_b1a0_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 22; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_b1a8_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_b1b0_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 3; CurrentInstrCycles = 26; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_b1b8_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_b1b9_4)(uint32_t opcode) /* EOR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 3; CurrentInstrCycles = 28; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src ^= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_b1c0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b1c8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_b1d0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b1d8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_b1e0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_b1e8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b1f0_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_b1f8_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b1f9_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_b1fa_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_b1fb_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_b1fc_4)(uint32_t opcode) /* CMPA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 27; CurrentInstrCycles = 14; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs != flgo) && (flgn != flgo));
-	SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst)));
-	SET_NFLG (flgn != 0);
-}}}}}}m68k_incpc(6);
-return 14;
-}
-unsigned long CPUFUNC(op_c000_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_c010_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_c018_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_c020_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_c028_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c030_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c038_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c039_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c03a_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c03b_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c03c_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_c040_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_c050_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_c058_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_c060_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_c068_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c070_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c078_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c079_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c07a_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_c07b_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_c07c_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
-}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_c080_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_c090_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_c098_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_c0a0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_c0a8_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_c0b0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_c0b8_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_c0b9_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_c0ba_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_c0bb_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_c0bc_4)(uint32_t opcode) /* AND */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_c0c0_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 38; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}m68k_incpc(2);
- return (38+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0d0_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 42; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(2);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0d8_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 42; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(2);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0e0_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 44; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(2);
- return (44+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0e8_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 46; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0f0_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 48; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(4);
- return (48+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0f8_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 46; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0f9_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 50; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(6);
- return (50+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0fa_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 46; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0fb_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 48; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}}m68k_incpc(4);
- return (48+retcycles*2);
-}
-unsigned long CPUFUNC(op_c0fc_4)(uint32_t opcode) /* MULU */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 62; CurrentInstrCycles = 42; 
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }
-}}}}m68k_incpc(4);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_c100_4)(uint32_t opcode) /* ABCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 14; CurrentInstrCycles = 6;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0);
-	uint16_t newv, tmp_newv;
-	int cflg;
-	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
-	cflg = (newv & 0x3F0) > 0x90;
-	if (cflg) newv += 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_c108_4)(uint32_t opcode) /* ABCD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 14; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);
-	uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0);
-	uint16_t newv, tmp_newv;
-	int cflg;
-	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
-	cflg = (newv & 0x3F0) > 0x90;
-	if (cflg) newv += 0x60;
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_c110_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_c118_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_c120_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_c128_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_c130_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_c138_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_c139_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int8_t)(src)) == 0);
-	SET_NFLG (((int8_t)(src)) < 0);
-	m68k_write_memory_8(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_c140_4)(uint32_t opcode) /* EXG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 35; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-	m68k_dreg(regs, srcreg) = (dst);
-	m68k_dreg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_c148_4)(uint32_t opcode) /* EXG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 35; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-	m68k_areg(regs, srcreg) = (dst);
-	m68k_areg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_c150_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_c158_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_c160_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_c168_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_c170_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 18; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_c178_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_c179_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(src)) == 0);
-	SET_NFLG (((int16_t)(src)) < 0);
-	m68k_write_memory_16(dsta,src);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_c188_4)(uint32_t opcode) /* EXG */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 35; CurrentInstrCycles = 6;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-	m68k_dreg(regs, srcreg) = (dst);
-	m68k_areg(regs, dstreg) = (src);
-}}}m68k_incpc(2);
-return 6;
-}
-unsigned long CPUFUNC(op_c190_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_c198_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_c1a0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 22; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_c1a8_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_c1b0_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 2; CurrentInstrCycles = 26; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_c1b8_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_c1b9_4)(uint32_t opcode) /* AND */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 2; CurrentInstrCycles = 28; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	src &= dst;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(src)) == 0);
-	SET_NFLG (((int32_t)(src)) < 0);
-	m68k_write_memory_32(dsta,src);
-}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_c1c0_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 38; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}m68k_incpc(2);
- return (38+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1d0_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 42; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(2);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1d8_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 42; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(2);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1e0_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 44; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(2);
- return (44+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1e8_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 46; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1f0_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 48; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(4);
- return (48+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1f8_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 46; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1f9_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 50; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(6);
- return (50+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1fa_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 46; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(4);
- return (46+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1fb_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 48; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}}m68k_incpc(4);
- return (48+retcycles*2);
-}
-unsigned long CPUFUNC(op_c1fc_4)(uint32_t opcode) /* MULS */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 63; CurrentInstrCycles = 42; 
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;
-	uint32_t src2;
-	CLEAR_CZNV;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-	src2 = ((uint32_t)src) << 1;
-	while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }
-}}}}m68k_incpc(4);
- return (42+retcycles*2);
-}
-unsigned long CPUFUNC(op_d000_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_d010_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d018_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d020_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_d028_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d030_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_d038_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d039_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_d03a_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d03b_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t src = m68k_read_memory_8(srca);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_d03c_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int8_t src = get_ibyte(2);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_d040_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_d048_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_d050_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d058_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d060_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 10; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(2);
-return 10;
-}
-unsigned long CPUFUNC(op_d068_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d070_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_d078_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d079_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_d07a_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d07b_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}}m68k_incpc(4);
-return 14;
-}
-unsigned long CPUFUNC(op_d07c_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int16_t src = get_iword(2);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}}m68k_incpc(4);
-return 8;
-}
-unsigned long CPUFUNC(op_d080_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d088_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d090_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d098_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d0a0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_d0a8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d0b0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_d0b8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d0b9_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_d0ba_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d0bb_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_d0bc_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_d0c0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d0c8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	int16_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d0d0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d0d8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 12; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg(regs, srcreg) += 2;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d0e0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d0e8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d0f0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 18; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d0f8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 16; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d0f9_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_ilong(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_d0fa_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d0fb_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 18; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t src = m68k_read_memory_16(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d0fc_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 12; 
-{{	int16_t src = get_iword(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(4);
-return 12;
-}
-unsigned long CPUFUNC(op_d100_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 4;  
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	int8_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_d108_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
-{	int8_t src = m68k_read_memory_8(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0));
-	SET_NFLG (((int8_t)(newv)) < 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_d110_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d118_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d120_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
-{	int8_t dst = m68k_read_memory_8(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d128_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d130_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d138_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d139_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int8_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int8_t dst = m68k_read_memory_8(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src));
-{	int flgs = ((int8_t)(src)) < 0;
-	int flgo = ((int8_t)(dst)) < 0;
-	int flgn = ((int8_t)(newv)) < 0;
-	SET_ZFLG (((int8_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_8(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_d140_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 4;  
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	int16_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
-}}}}}m68k_incpc(2);
-return 4;
-}
-unsigned long CPUFUNC(op_d148_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 2;
-{	int16_t src = m68k_read_memory_16(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0));
-	SET_NFLG (((int16_t)(newv)) < 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 18;
-}
-unsigned long CPUFUNC(op_d150_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d158_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 12; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg(regs, dstreg) += 2;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_d160_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 14; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d168_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d170_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 18; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d178_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 16; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_d179_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int16_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int16_t dst = m68k_read_memory_16(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src));
-{	int flgs = ((int16_t)(src)) < 0;
-	int flgo = ((int16_t)(dst)) < 0;
-	int flgn = ((int16_t)(newv)) < 0;
-	SET_ZFLG (((int16_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_16(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_d180_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_dreg(regs, dstreg);
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_dreg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d188_4)(uint32_t opcode) /* ADDX */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 13; CurrentInstrCycles = 30; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	uint32_t newv = dst + src + (GET_XFLG ? 1 : 0);
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
-	COPY_CARRY;
-	SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0));
-	SET_NFLG (((int32_t)(newv)) < 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 30;
-}
-unsigned long CPUFUNC(op_d190_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_d198_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 20; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg);
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg(regs, dstreg) += 4;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 20;
-}
-unsigned long CPUFUNC(op_d1a0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 22; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) - 4;
-{	int32_t dst = m68k_read_memory_32(dsta);
-	m68k_areg (regs, dstreg) = dsta;
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(2);
-return 22;
-}
-unsigned long CPUFUNC(op_d1a8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_d1b0_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	OpcodeFamily = 11; CurrentInstrCycles = 26; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 26;
-}
-unsigned long CPUFUNC(op_d1b8_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 24; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = (int32_t)(int16_t)get_iword(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(4);
-return 24;
-}
-unsigned long CPUFUNC(op_d1b9_4)(uint32_t opcode) /* ADD */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	OpcodeFamily = 11; CurrentInstrCycles = 28; 
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	uint32_t dsta = get_ilong(2);
-{	int32_t dst = m68k_read_memory_32(dsta);
-{	refill_prefetch (m68k_getpc(), 2);
-{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src));
-{	int flgs = ((int32_t)(src)) < 0;
-	int flgo = ((int32_t)(dst)) < 0;
-	int flgn = ((int32_t)(newv)) < 0;
-	SET_ZFLG (((int32_t)(newv)) == 0);
-	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
-	SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src)));
-	COPY_CARRY;
-	SET_NFLG (flgn != 0);
-	m68k_write_memory_32(dsta,newv);
-}}}}}}}m68k_incpc(6);
-return 28;
-}
-unsigned long CPUFUNC(op_d1c0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_dreg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d1c8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 8;  
-{{	int32_t src = m68k_areg(regs, srcreg);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(2);
-return 8;
-}
-unsigned long CPUFUNC(op_d1d0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-#endif
-
-#ifdef PART_8
-unsigned long CPUFUNC(op_d1d8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 14; 
-{{	uint32_t srca = m68k_areg(regs, srcreg);
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg(regs, srcreg) += 4;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_d1e0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 16; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) - 4;
-{	int32_t src = m68k_read_memory_32(srca);
-	m68k_areg (regs, srcreg) = srca;
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(2);
-return 16;
-}
-unsigned long CPUFUNC(op_d1e8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d1f0_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t srcreg = (opcode & 7);
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 20; 
-{{	uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_d1f8_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 18; 
-{{	uint32_t srca = (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d1f9_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 22; 
-{{	uint32_t srca = get_ilong(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(6);
-return 22;
-}
-unsigned long CPUFUNC(op_d1fa_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 18; 
-{{	uint32_t srca = m68k_getpc () + 2;
-	srca += (int32_t)(int16_t)get_iword(2);
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_d1fb_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 20; 
-{{	uint32_t tmppc = m68k_getpc() + 2;
-	uint32_t srca = get_disp_ea_000(tmppc, get_iword(2));
-	BusCyclePenalty += 2;
-{	int32_t src = m68k_read_memory_32(srca);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}}m68k_incpc(4);
-return 20;
-}
-unsigned long CPUFUNC(op_d1fc_4)(uint32_t opcode) /* ADDA */
-{
-	uint32_t dstreg = (opcode >> 9) & 7;
-	OpcodeFamily = 12; CurrentInstrCycles = 16; 
-{{	int32_t src = get_ilong(2);
-{	int32_t dst = m68k_areg(regs, dstreg);
-{	uint32_t newv = dst + src;
-	m68k_areg(regs, dstreg) = (newv);
-}}}}m68k_incpc(6);
-return 16;
-}
-unsigned long CPUFUNC(op_e000_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	uint32_t sign = (0x80 & val) >> 7;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		val = 0xff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xff << (8 - cnt)) & (uint32_t)-sign;
-		val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e008_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_CFLG ((cnt == 8) & (val >> 7));
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e010_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (7 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e018_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t hival;
-	cnt &= 7;
-	hival = val << (8 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xff;
-	SET_CFLG ((val & 0x80) >> 7);
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e020_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	uint32_t sign = (0x80 & val) >> 7;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		val = 0xff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xff << (8 - cnt)) & (uint32_t)-sign;
-		val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e028_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_CFLG ((cnt == 8) & (val >> 7));
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e030_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 36) cnt -= 36;
-	if (cnt >= 18) cnt -= 18;
-	if (cnt >= 9) cnt -= 9;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (7 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e038_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {	uint32_t hival;
-	cnt &= 7;
-	hival = val << (8 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xff;
-	SET_CFLG ((val & 0x80) >> 7);
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e040_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = (0x8000 & val) >> 15;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		val = 0xffff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xffff << (16 - cnt)) & (uint32_t)-sign;
-		val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e048_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_CFLG ((cnt == 16) & (val >> 15));
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e050_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (15 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e058_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t hival;
-	cnt &= 15;
-	hival = val << (16 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xffff;
-	SET_CFLG ((val & 0x8000) >> 15);
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e060_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = (0x8000 & val) >> 15;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		val = 0xffff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xffff << (16 - cnt)) & (uint32_t)-sign;
-		val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e068_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_CFLG ((cnt == 16) & (val >> 15));
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e070_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 34) cnt -= 34;
-	if (cnt >= 17) cnt -= 17;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (15 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e078_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {	uint32_t hival;
-	cnt &= 15;
-	hival = val << (16 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xffff;
-	SET_CFLG ((val & 0x8000) >> 15);
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e080_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	uint32_t sign = (0x80000000 & val) >> 31;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		val = 0xffffffff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign;
-		val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e088_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_CFLG ((cnt == 32) & (val >> 31));
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e090_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (31 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xffffffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e098_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t hival;
-	cnt &= 31;
-	hival = val << (32 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xffffffff;
-	SET_CFLG ((val & 0x80000000) >> 31);
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e0a0_4)(uint32_t opcode) /* ASR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 64; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	uint32_t sign = (0x80000000 & val) >> 31;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		val = 0xffffffff & (uint32_t)-sign;
-		SET_CFLG (sign);
-	COPY_CARRY;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-		val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign;
-		val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e0a8_4)(uint32_t opcode) /* LSR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 66; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_CFLG ((cnt == 32) & (val >> 31));
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val >>= cnt - 1;
-		SET_CFLG (val & 1);
-	COPY_CARRY;
-		val >>= 1;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e0b0_4)(uint32_t opcode) /* ROXR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 71; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 33) cnt -= 33;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t hival = (val << 1) | GET_XFLG;
-	hival <<= (31 - cnt);
-	val >>= cnt;
-	carry = val & 1;
-	val >>= 1;
-	val |= hival;
-	SET_XFLG (carry);
-	val &= 0xffffffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e0b8_4)(uint32_t opcode) /* ROR */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 69; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {	uint32_t hival;
-	cnt &= 31;
-	hival = val << (32 - cnt);
-	val >>= cnt;
-	val |= hival;
-	val &= 0xffffffff;
-	SET_CFLG ((val & 0x80000000) >> 31);
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e0d0_4)(uint32_t opcode) /* ASRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 72; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e0d8_4)(uint32_t opcode) /* ASRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 72; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e0e0_4)(uint32_t opcode) /* ASRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 72; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e0e8_4)(uint32_t opcode) /* ASRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 72; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e0f0_4)(uint32_t opcode) /* ASRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 72; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e0f8_4)(uint32_t opcode) /* ASRW */
-{
-	OpcodeFamily = 72; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e0f9_4)(uint32_t opcode) /* ASRW */
-{
-	OpcodeFamily = 72; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t cflg = val & 1;
-	val = (val >> 1) | sign;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	SET_CFLG (cflg);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e100_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 8 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		uint32_t mask = (0xff << (7 - cnt)) & 0xff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x80) >> 7);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e108_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_CFLG (cnt == 8 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x80) >> 7);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e110_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (7 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e118_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t loval;
-	cnt &= 7;
-	loval = val >> (8 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e120_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 8 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		uint32_t mask = (0xff << (7 - cnt)) & 0xff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x80) >> 7);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e128_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 8) {
-		SET_CFLG (cnt == 8 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x80) >> 7);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xff;
-	}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e130_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 36) cnt -= 36;
-	if (cnt >= 18) cnt -= 18;
-	if (cnt >= 9) cnt -= 9;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (7 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e138_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	int8_t cnt = m68k_dreg(regs, srcreg);
-{	int8_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint8_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {
-	uint32_t loval;
-	cnt &= 7;
-	loval = val >> (8 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int8_t)(val)) == 0);
-	SET_NFLG (((int8_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e140_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 16 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		uint32_t mask = (0xffff << (15 - cnt)) & 0xffff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x8000) >> 15);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e148_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_CFLG (cnt == 16 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x8000) >> 15);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e150_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (15 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e158_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t loval;
-	cnt &= 15;
-	loval = val >> (16 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xffff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e160_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 16 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		uint32_t mask = (0xffff << (15 - cnt)) & 0xffff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x8000) >> 15);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e168_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 16) {
-		SET_CFLG (cnt == 16 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x8000) >> 15);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xffff;
-	}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e170_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 34) cnt -= 34;
-	if (cnt >= 17) cnt -= 17;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (15 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e178_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	int16_t cnt = m68k_dreg(regs, srcreg);
-{	int16_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = (uint16_t)data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {
-	uint32_t loval;
-	cnt &= 15;
-	loval = val >> (16 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xffff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
-}}}}m68k_incpc(2);
- return (6+retcycles*2);
-}
-unsigned long CPUFUNC(op_e180_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 32 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x80000000) >> 31);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e188_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_CFLG (cnt == 32 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x80000000) >> 31);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e190_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (31 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xffffffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e198_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	uint32_t cnt = srcreg;
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-{	uint32_t loval;
-	cnt &= 31;
-	loval = val >> (32 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xffffffff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e1a0_4)(uint32_t opcode) /* ASL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 65; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_VFLG (val != 0);
-		SET_CFLG (cnt == 32 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
-		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
-		val <<= cnt - 1;
-		SET_CFLG ((val & 0x80000000) >> 31);
-	COPY_CARRY;
-		val <<= 1;
-		val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e1a8_4)(uint32_t opcode) /* LSL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 67; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 32) {
-		SET_CFLG (cnt == 32 ? val & 1 : 0);
-	COPY_CARRY;
-		val = 0;
-	} else if (cnt > 0) {
-		val <<= (cnt - 1);
-		SET_CFLG ((val & 0x80000000) >> 31);
-	COPY_CARRY;
-		val <<= 1;
-	val &= 0xffffffff;
-	}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e1b0_4)(uint32_t opcode) /* ROXL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 70; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt >= 33) cnt -= 33;
-	if (cnt > 0) {
-	cnt--;
-	{
-	uint32_t carry;
-	uint32_t loval = val >> (31 - cnt);
-	carry = loval & 1;
-	val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);
-	SET_XFLG (carry);
-	val &= 0xffffffff;
-	} }
-	SET_CFLG (GET_XFLG);
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e1b8_4)(uint32_t opcode) /* ROL */
-{
-	uint32_t srcreg = ((opcode >> 9) & 7);
-	uint32_t dstreg = opcode & 7;
-	unsigned int retcycles = 0;
-	OpcodeFamily = 68; CurrentInstrCycles = 4;  
-{{	int32_t cnt = m68k_dreg(regs, srcreg);
-{	int32_t data = m68k_dreg(regs, dstreg);
-{	uint32_t val = data;
-	cnt &= 63;
-	retcycles = cnt;
-	CLEAR_CZNV;
-	if (cnt > 0) {
-	uint32_t loval;
-	cnt &= 31;
-	loval = val >> (32 - cnt);
-	val <<= cnt;
-	val |= loval;
-	val &= 0xffffffff;
-	SET_CFLG (val & 1);
-}
-	SET_ZFLG (((int32_t)(val)) == 0);
-	SET_NFLG (((int32_t)(val)) < 0);
-	m68k_dreg(regs, dstreg) = (val);
-}}}}m68k_incpc(2);
- return (8+retcycles*2);
-}
-unsigned long CPUFUNC(op_e1d0_4)(uint32_t opcode) /* ASLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 73; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e1d8_4)(uint32_t opcode) /* ASLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 73; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e1e0_4)(uint32_t opcode) /* ASLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 73; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e1e8_4)(uint32_t opcode) /* ASLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 73; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e1f0_4)(uint32_t opcode) /* ASLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 73; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e1f8_4)(uint32_t opcode) /* ASLW */
-{
-	OpcodeFamily = 73; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e1f9_4)(uint32_t opcode) /* ASLW */
-{
-	OpcodeFamily = 73; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t sign = 0x8000 & val;
-	uint32_t sign2;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-	sign2 = 0x8000 & val;
-	SET_CFLG (sign != 0);
-	COPY_CARRY;
-	SET_VFLG (GET_VFLG | (sign2 != sign));
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e2d0_4)(uint32_t opcode) /* LSRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 74; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e2d8_4)(uint32_t opcode) /* LSRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 74; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e2e0_4)(uint32_t opcode) /* LSRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 74; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e2e8_4)(uint32_t opcode) /* LSRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 74; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e2f0_4)(uint32_t opcode) /* LSRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 74; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e2f8_4)(uint32_t opcode) /* LSRW */
-{
-	OpcodeFamily = 74; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e2f9_4)(uint32_t opcode) /* LSRW */
-{
-	OpcodeFamily = 74; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint32_t val = (uint16_t)data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e3d0_4)(uint32_t opcode) /* LSLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 75; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e3d8_4)(uint32_t opcode) /* LSLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 75; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e3e0_4)(uint32_t opcode) /* LSLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 75; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e3e8_4)(uint32_t opcode) /* LSLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 75; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e3f0_4)(uint32_t opcode) /* LSLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 75; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e3f8_4)(uint32_t opcode) /* LSLW */
-{
-	OpcodeFamily = 75; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e3f9_4)(uint32_t opcode) /* LSLW */
-{
-	OpcodeFamily = 75; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e4d0_4)(uint32_t opcode) /* ROXRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 79; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e4d8_4)(uint32_t opcode) /* ROXRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 79; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e4e0_4)(uint32_t opcode) /* ROXRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 79; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e4e8_4)(uint32_t opcode) /* ROXRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 79; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e4f0_4)(uint32_t opcode) /* ROXRW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 79; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e4f8_4)(uint32_t opcode) /* ROXRW */
-{
-	OpcodeFamily = 79; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e4f9_4)(uint32_t opcode) /* ROXRW */
-{
-	OpcodeFamily = 79; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (GET_XFLG) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e5d0_4)(uint32_t opcode) /* ROXLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 78; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e5d8_4)(uint32_t opcode) /* ROXLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 78; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e5e0_4)(uint32_t opcode) /* ROXLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 78; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e5e8_4)(uint32_t opcode) /* ROXLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 78; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e5f0_4)(uint32_t opcode) /* ROXLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 78; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e5f8_4)(uint32_t opcode) /* ROXLW */
-{
-	OpcodeFamily = 78; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e5f9_4)(uint32_t opcode) /* ROXLW */
-{
-	OpcodeFamily = 78; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (GET_XFLG) val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	COPY_CARRY;
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e6d0_4)(uint32_t opcode) /* RORW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 77; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e6d8_4)(uint32_t opcode) /* RORW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 77; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e6e0_4)(uint32_t opcode) /* RORW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 77; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e6e8_4)(uint32_t opcode) /* RORW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 77; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e6f0_4)(uint32_t opcode) /* RORW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 77; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e6f8_4)(uint32_t opcode) /* RORW */
-{
-	OpcodeFamily = 77; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e6f9_4)(uint32_t opcode) /* RORW */
-{
-	OpcodeFamily = 77; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 1;
-	val >>= 1;
-	if (carry) val |= 0x8000;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-unsigned long CPUFUNC(op_e7d0_4)(uint32_t opcode) /* ROLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 76; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e7d8_4)(uint32_t opcode) /* ROLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 76; CurrentInstrCycles = 12; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg);
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg(regs, srcreg) += 2;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 12;
-}
-unsigned long CPUFUNC(op_e7e0_4)(uint32_t opcode) /* ROLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 76; CurrentInstrCycles = 14; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) - 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-	m68k_areg (regs, srcreg) = dataa;
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(2);
-return 14;
-}
-unsigned long CPUFUNC(op_e7e8_4)(uint32_t opcode) /* ROLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 76; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e7f0_4)(uint32_t opcode) /* ROLW */
-{
-	uint32_t srcreg = (opcode & 7);
-	OpcodeFamily = 76; CurrentInstrCycles = 18; 
-{{	uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2));
-	BusCyclePenalty += 2;
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 18;
-}
-unsigned long CPUFUNC(op_e7f8_4)(uint32_t opcode) /* ROLW */
-{
-	OpcodeFamily = 76; CurrentInstrCycles = 16; 
-{{	uint32_t dataa = (int32_t)(int16_t)get_iword(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(4);
-return 16;
-}
-unsigned long CPUFUNC(op_e7f9_4)(uint32_t opcode) /* ROLW */
-{
-	OpcodeFamily = 76; CurrentInstrCycles = 20; 
-{{	uint32_t dataa = get_ilong(2);
-{	int16_t data = m68k_read_memory_16(dataa);
-{	uint16_t val = data;
-	uint32_t carry = val & 0x8000;
-	val <<= 1;
-	if (carry)  val |= 1;
-	CLEAR_CZNV;
-	SET_ZFLG (((int16_t)(val)) == 0);
-	SET_NFLG (((int16_t)(val)) < 0);
-SET_CFLG (carry >> 15);
-	m68k_write_memory_16(dataa,val);
-}}}}m68k_incpc(6);
-return 20;
-}
-#endif
-
-
-#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
-#define PART_1 1
-#define PART_2 1
-#define PART_3 1
-#define PART_4 1
-#define PART_5 1
-#define PART_6 1
-#define PART_7 1
-#define PART_8 1
-#endif
-
-#ifdef PART_1
 unsigned long CPUFUNC(op_0_5)(uint32_t opcode) /* OR */
 {
 	uint32_t dstreg = opcode & 7;
@@ -29680,9 +3998,6 @@ fill_prefetch_0 ();
 endlabel1784: ;
 return 20;
 }
-#endif
-
-#ifdef PART_2
 unsigned long CPUFUNC(op_a80_5)(uint32_t opcode) /* EOR */
 {
 	uint32_t dstreg = opcode & 7;
@@ -33538,9 +7853,6 @@ fill_prefetch_0 ();
 }}}}}}endlabel1974: ;
 return 24;
 }
-#endif
-
-#ifdef PART_3
 unsigned long CPUFUNC(op_2139_5)(uint32_t opcode) /* MOVE */
 {
 	uint32_t dstreg = (opcode >> 9) & 7;
@@ -39239,9 +13551,6 @@ fill_prefetch_0 ();
 }}}endlabel2197: ;
 return 16;
 }
-#endif
-
-#ifdef PART_4
 unsigned long CPUFUNC(op_4270_5)(uint32_t opcode) /* CLR */
 {
 	uint32_t srcreg = (opcode & 7);
@@ -43193,9 +17502,6 @@ fill_prefetch_2 ();
 	m68k_write_memory_8(dsta,newv);
 }}}}}}}return 12;
 }
-#endif
-
-#ifdef PART_5
 unsigned long CPUFUNC(op_5020_5)(uint32_t opcode) /* ADD */
 {
 	uint32_t srcreg = imm8_table[((opcode >> 9) & 7)];
@@ -46312,9 +20618,6 @@ fill_prefetch_2 ();
 	m68k_write_memory_8(srca,val);
 }}}return 14;
 }
-#endif
-
-#ifdef PART_6
 unsigned long CPUFUNC(op_5fe8_5)(uint32_t opcode) /* Scc */
 {
 	uint32_t srcreg = (opcode & 7);
@@ -51671,9 +25974,6 @@ unsigned long CPUFUNC(op_b03b_5)(uint32_t opcode) /* CMP */
 fill_prefetch_0 ();
 return 14;
 }
-#endif
-
-#ifdef PART_7
 unsigned long CPUFUNC(op_b03c_5)(uint32_t opcode) /* CMP */
 {
 	uint32_t dstreg = (opcode >> 9) & 7;
@@ -57394,9 +31694,6 @@ fill_prefetch_2 ();
 endlabel3047: ;
 return 14;
 }
-#endif
-
-#ifdef PART_8
 unsigned long CPUFUNC(op_d1d8_5)(uint32_t opcode) /* ADDA */
 {
 	uint32_t srcreg = (opcode & 7);
@@ -60604,5 +34901,3 @@ fill_prefetch_0 ();
 }}}}}endlabel3160: ;
 return 20;
 }
-#endif
-
diff --git a/waterbox/virtualjaguar/src/m68000/cpuextra.c b/waterbox/virtualjaguar/src/m68000/cpuextra.c
index e98f1da812..0a8a17d521 100644
--- a/waterbox/virtualjaguar/src/m68000/cpuextra.c
+++ b/waterbox/virtualjaguar/src/m68000/cpuextra.c
@@ -10,18 +10,16 @@
 #include "cpudefs.h"
 #include "inlines.h"
 
+uint16_t last_op_for_exception_3;
+uint32_t last_addr_for_exception_3;
+uint32_t last_fault_for_exception_3;
 
-uint16_t last_op_for_exception_3;		// Opcode of faulting instruction
-uint32_t last_addr_for_exception_3;		// PC at fault time
-uint32_t last_fault_for_exception_3;	// Address that generated the exception
-
-int OpcodeFamily;						// Used by cpuemu.c...
-int BusCyclePenalty = 0;				// Used by cpuemu.c...
+int OpcodeFamily;
+int BusCyclePenalty = 0;
 int CurrentInstrCycles;
 
 struct regstruct regs;
 
-
 //
 // Make displacement effective address for 68000
 //
@@ -30,29 +28,12 @@ uint32_t get_disp_ea_000(uint32_t base, uint32_t dp)
 	int reg = (dp >> 12) & 0x0F;
 	int32_t regd = regs.regs[reg];
 
-#if 1
 	if ((dp & 0x800) == 0)
 		regd = (int32_t)(int16_t)regd;
 
 	return base + (int8_t)dp + regd;
-#else
-	/* Branch-free code... benchmark this again now that
-	 * things are no longer inline.
-	 */
-	int32_t regd16;
-	uint32_t mask;
-	mask = ((dp & 0x800) >> 11) - 1;
-	regd16 = (int32_t)(int16_t)regd;
-	regd16 &= mask;
-	mask = ~mask;
-	base += (int8_t)dp;
-	regd &= mask;
-	regd |= regd16;
-	return base + regd;
-#endif
 }
 
-
 //
 // Create the Status Register from the flags
 //
@@ -62,7 +43,6 @@ void MakeSR(void)
 		| (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1) | GET_CFLG);
 }
 
-
 //
 // Set up the flags from Status Register
 //
@@ -91,107 +71,19 @@ void MakeFromSR(void)
 			m68k_areg(regs, 7) = regs.isp;
 		}
 	}
-
-	/* Pending interrupts can occur again after a write to the SR: */
-//JLH: is this needed?
-//	set_special(SPCFLAG_DOINT);
 }
 
-
-//
-// Rudimentary exception handling. This is really stripped down from what
-// was in Hatari.
-/*
-NB: Seems that when an address exception occurs, it doesn't get handled properly
-    as per test1.cof. Need to figure out why it keeps going when it should wedge. :-P
-*/
 //
 // Handle exceptions. We need a special case to handle MFP exceptions
 // on Atari ST, because it's possible to change the MFP's vector base
 // and get a conflict with 'normal' cpu exceptions.
 //
-#if 0
-/*
-This is the STOP # function. Dunno if exception handling occurs when it hits here or not, because don't know if the regs.s bit is set or not!
-Seems to be...
-
-SR-----------------
-1111 11
-5432 1098 7654 3210
----- ---- ---- ----
-  1    1
-
-
-*/
-unsigned long CPUFUNC(op_4e72_5)(uint32_t opcode) /* STOP */
-{
-	OpcodeFamily = 44;
-	CurrentInstrCycles = 4;
-
-	if (!regs.s)
-	{
-		Exception(8, 0, M68000_EXC_SRC_CPU);
-	}
-	else
-	{
-		int16_t src = get_iword_prefetch(2);
-		regs.sr = src;
-		MakeFromSR();
-		m68k_setstopped(1);
-		m68k_incpc(4);
-		fill_prefetch_0();
-	}
-
-	return 4;
-}
-#endif
-//tmp...
-void WriteLog(const char * text, ...);
 void Exception(int nr, uint32_t oldpc, int ExceptionSource)
 {
 	uint32_t currpc = m68k_getpc(), newpc;
 
-// Need to figure out how to report this stuff without using printf on stdout :-/
-#if 0
-char excNames[33][64] = {
-	"???", "???", "Bus Error", "Address Error",
-	"Illegal Instruction", "Zero Divide", "CHK", "TrapV",
-	"Privilege Violation", "Trace", "Line A", "Line F",
-	"???", "???", "Format Error", "Uninitialized Interrupt",
-	"???", "???", "???", "???",
-	"???", "???", "???", "???",
-	"Spurious/Autovector", "???", "???", "???",
-	"???", "???", "???", "???",
-	"Trap #"
-};
-
-WriteLog("Exception #%i occurred! (%s)\n", nr, (nr < 32 ? excNames[nr] : (nr < 48 ? "Trap #" : "????")));
-WriteLog("Vector @ #%i = %08X\n", nr, m68k_read_memory_32(nr * 4));
-//abort();
-WriteLog("PC = $%08X\n", currpc);
-WriteLog("A0 = $%08X A1 = $%08X A2 = $%08X A3 = $%08X\n", m68k_areg(regs, 0), m68k_areg(regs, 1), m68k_areg(regs, 2), m68k_areg(regs, 3));
-WriteLog("A4 = $%08X A5 = $%08X A6 = $%08X A7 = $%08X\n", m68k_areg(regs, 4), m68k_areg(regs, 5), m68k_areg(regs, 6), m68k_areg(regs, 7));
-WriteLog("D0 = $%08X D1 = $%08X D2 = $%08X D3 = $%08X\n", m68k_dreg(regs, 0), m68k_dreg(regs, 1), m68k_dreg(regs, 2), m68k_dreg(regs, 3));
-WriteLog("D4 = $%08X D5 = $%08X D6 = $%08X D7 = $%08X\n", m68k_dreg(regs, 4), m68k_dreg(regs, 5), m68k_dreg(regs, 6), m68k_dreg(regs, 7));
-WriteLog("\n");
-
-uint32_t disPC = currpc - 10;
-char buffer[128];
-
-do
-{
-	uint32_t oldpc = disPC;
-	disPC += m68k_disassemble(buffer, disPC, 0);
-	WriteLog("%s%08X: %s\n", (oldpc == currpc ? ">" : " "), oldpc, buffer);
-}
-while (disPC < (currpc + 10));
-#endif
-
-/*if( nr>=2 && nr<10 )  fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/
-
 	MakeSR();
 
-	// Change to supervisor mode if necessary
 	if (!regs.s)
 	{
 		regs.usp = m68k_areg(regs, 7);
@@ -199,202 +91,15 @@ while (disPC < (currpc + 10));
 		regs.s = 1;
 	}
 
-	// Create 68000 style stack frame
-	m68k_areg(regs, 7) -= 4;				// Push PC on stack
+	m68k_areg(regs, 7) -= 4;
 	m68k_write_memory_32(m68k_areg(regs, 7), currpc);
-	m68k_areg(regs, 7) -= 2;				// Push SR on stack
+	m68k_areg(regs, 7) -= 2;
 	m68k_write_memory_16(m68k_areg(regs, 7), regs.sr);
 
-//	LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n",
-//	nr, currpc, BusErrorPC, get_long(4 * nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3);
-
-#if 0
-	/* 68000 bus/address errors: */
-	if ((nr == 2 || nr == 3) && ExceptionSource == M68000_EXC_SRC_CPU)
-	{
-		uint16_t specialstatus = 1;
-
-		/* Special status word emulation isn't perfect yet... :-( */
-		if (regs.sr & 0x2000)
-			specialstatus |= 0x4;
-
-		m68k_areg(regs, 7) -= 8;
-
-		if (nr == 3)     /* Address error */
-		{
-			specialstatus |= (last_op_for_exception_3 & (~0x1F));	/* [NP] unused bits of specialstatus are those of the last opcode ! */
-			put_word(m68k_areg(regs, 7), specialstatus);
-			put_long(m68k_areg(regs, 7) + 2, last_fault_for_exception_3);
-			put_word(m68k_areg(regs, 7) + 6, last_op_for_exception_3);
-			put_long(m68k_areg(regs, 7) + 10, last_addr_for_exception_3);
-
-//JLH: Not now...
-#if 0
-			if (bExceptionDebugging)
-			{
-				fprintf(stderr,"Address Error at address $%x, PC=$%x\n", last_fault_for_exception_3, currpc);
-				DebugUI();
-			}
-#endif
-		}
-		else     /* Bus error */
-		{
-			specialstatus |= (get_word(BusErrorPC) & (~0x1F));	/* [NP] unused bits of special status are those of the last opcode ! */
-
-			if (bBusErrorReadWrite)
-				specialstatus |= 0x10;
-
-			put_word(m68k_areg(regs, 7), specialstatus);
-			put_long(m68k_areg(regs, 7) + 2, BusErrorAddress);
-			put_word(m68k_areg(regs, 7) + 6, get_word(BusErrorPC));	/* Opcode */
-
-			/* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */
-			/* FIXME : we should have a proper model for this, in the meantime we handle specific cases */
-			if (get_word(BusErrorPC) == 0x21F8)			/* move.l $0.w,$24.w (Transbeauce 2 loader) */
-				put_long(m68k_areg(regs, 7) + 10, currpc - 2);		/* correct PC is 2 bytes less than usual value */
-
-			/* Check for double bus errors: */
-			if (regs.spcflags & SPCFLAG_BUSERROR)
-			{
-				fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n",
-				BusErrorAddress, (long)currpc);
-				unset_special(SPCFLAG_BUSERROR);
-
-				if (bExceptionDebugging)
-					DebugUI();
-				else
-					DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n");
-
-				regs.intmask = 7;
-				m68k_setstopped(true);
-				return;
-			}
-
-			if (bExceptionDebugging && BusErrorAddress != 0xFF8A00)
-			{
-				fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc);
-				DebugUI();
-			}
-		}
-	}
-
-//Not now...
-#if 0
-	/* Set PC and flags */
-	if (bExceptionDebugging && get_long(4 * nr) == 0)
-	{
-		write_log("Uninitialized exception handler #%i!\n", nr);
-		DebugUI();
-	}
-#endif
-
-	newpc = get_long(4 * nr);
-
-	if (newpc & 1)				/* check new pc is odd */
-	{
-		if (nr == 2 || nr == 3)			/* address error during bus/address error -> stop emulation */
-		{
-			fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n", newpc);
-			DebugUI();
-		}
-		else
-		{
-			fprintf(stderr,"Address Error during exception, new PC=$%x\n", newpc);
-			Exception(3, m68k_getpc(), M68000_EXC_SRC_CPU);
-		}
-
-		return;
-	}
-#endif
-
 	m68k_setpc(m68k_read_memory_32(4 * nr));
 	fill_prefetch_0();
-	/* Handle trace flags depending on current state */
-//JLH:no	exception_trace(nr);
-
-#if 0
-	/* Handle exception cycles (special case for MFP) */
-//	if (ExceptionSource == M68000_EXC_SRC_INT_MFP)
-//	{
-//		M68000_AddCycles(44 + 12);			/* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
-//	}
-//	else
-	if (nr >= 24 && nr <= 31)
-	{
-#if 0
-		if (nr == 26)				/* HBL */
-		{
-			/* store current cycle pos when then interrupt was received (see video.c) */
-			LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO);
-			M68000_AddCycles(44 + 12);		/* Video Interrupt */
-		}
-		else if (nr == 28) 			/* VBL */
-			M68000_AddCycles(44 + 12);		/* Video Interrupt */
-		else
-#endif
-			M68000_AddCycles(44 + 4);			/* Other Interrupts */
-	}
-	else if (nr >= 32 && nr <= 47)
-	{
-		M68000_AddCycles(34 - 4);			/* Trap (total is 34, but cpuemu.c already adds 4) */
-	}
-	else switch(nr)
-	{
-		case 2: M68000_AddCycles(50); break;	/* Bus error */
-		case 3: M68000_AddCycles(50); break;	/* Address error */
-		case 4: M68000_AddCycles(34); break;	/* Illegal instruction */
-		case 5: M68000_AddCycles(38); break;	/* Div by zero */
-		case 6: M68000_AddCycles(40); break;	/* CHK */
-		case 7: M68000_AddCycles(34); break;	/* TRAPV */
-		case 8: M68000_AddCycles(34); break;	/* Privilege violation */
-		case 9: M68000_AddCycles(34); break;	/* Trace */
-		case 10: M68000_AddCycles(34); break;	/* Line-A - probably wrong */
-		case 11: M68000_AddCycles(34); break;	/* Line-F - probably wrong */
-		default:
-		/* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */
-		if (nr < 64)
-			M68000_AddCycles(4);			/* Coprocessor and unassigned exceptions (???) */
-		else
-			M68000_AddCycles(44 + 12);		/* Must be a MFP or DSP interrupt */
-
-		break;
-	}
-#endif
 }
 
-
-/*
- The routines below take dividend and divisor as parameters.
- They return 0 if division by zero, or exact number of cycles otherwise.
-
- The number of cycles returned assumes a register operand.
- Effective address time must be added if memory operand.
-
- For 68000 only (not 68010, 68012, 68020, etc).
- Probably valid for 68008 after adding the extra prefetch cycle.
-
-
- Best and worst cases are for register operand:
- (Note the difference with the documented range.)
-
-
- DIVU:
-
- Overflow (always): 10 cycles.
- Worst case: 136 cycles.
- Best case: 76 cycles.
-
-
- DIVS:
-
- Absolute overflow: 16-18 cycles.
- Signed overflow is not detected prematurely.
-
- Worst case: 156 cycles.
- Best case without signed overflow: 122 cycles.
- Best case with signed overflow: 120 cycles
- */
-
 //
 // DIVU
 // Unsigned division
@@ -408,7 +113,6 @@ STATIC_INLINE int getDivu68kCycles_2 (uint32_t dividend, uint16_t divisor)
 	if (divisor == 0)
 		return 0;
 
-	// Overflow
 	if ((dividend >> 16) >= divisor)
 		return (mcycles = 5) * 2;
 
@@ -422,7 +126,6 @@ STATIC_INLINE int getDivu68kCycles_2 (uint32_t dividend, uint16_t divisor)
 
 		dividend <<= 1;
 
-		// If carry from shift
 		if ((int32_t)temp < 0)
 			dividend -= hdivisor;
 		else
@@ -440,16 +143,12 @@ STATIC_INLINE int getDivu68kCycles_2 (uint32_t dividend, uint16_t divisor)
 	return mcycles * 2;
 }
 
-
-// This is called by cpuemu.c
 int getDivu68kCycles(uint32_t dividend, uint16_t divisor)
 {
 	int v = getDivu68kCycles_2(dividend, divisor) - 4;
-//	write_log ("U%d ", v);
 	return v;
 }
 
-
 //
 // DIVS
 // Signed division
@@ -468,11 +167,9 @@ STATIC_INLINE int getDivs68kCycles_2(int32_t dividend, int16_t divisor)
 	if (dividend < 0)
 		mcycles++;
 
-	// Check for absolute overflow
 	if (((uint32_t)abs(dividend) >> 16) >= (uint16_t)abs(divisor))
 		return (mcycles + 2) * 2;
 
-	// Absolute quotient
 	aquot = (uint32_t)abs(dividend) / (uint16_t)abs(divisor);
 
 	mcycles += 55;
@@ -485,8 +182,6 @@ STATIC_INLINE int getDivs68kCycles_2(int32_t dividend, int16_t divisor)
 			mcycles++;
 	}
 
-	// Count 15 msbits in absolute of quotient
-
 	for(i=0; i<15; i++)
 	{
 		if ((int16_t)aquot >= 0)
@@ -498,12 +193,8 @@ STATIC_INLINE int getDivs68kCycles_2(int32_t dividend, int16_t divisor)
 	return mcycles * 2;
 }
 
-
-// This is called by cpuemu.c
 int getDivs68kCycles(int32_t dividend, int16_t divisor)
 {
 	int v = getDivs68kCycles_2(dividend, divisor) - 4;
-//	write_log ("S%d ", v);
 	return v;
 }
-
diff --git a/waterbox/virtualjaguar/src/m68000/cpuextra.h b/waterbox/virtualjaguar/src/m68000/cpuextra.h
index 0efbbb4d7c..f5504ee5f4 100644
--- a/waterbox/virtualjaguar/src/m68000/cpuextra.h
+++ b/waterbox/virtualjaguar/src/m68000/cpuextra.h
@@ -12,15 +12,12 @@ struct cputbl
 	uint16_t opcode;
 };
 
-extern uint16_t last_op_for_exception_3;	/* Opcode of faulting instruction */
-extern uint32_t last_addr_for_exception_3;	/* PC at fault time */
-extern uint32_t last_fault_for_exception_3;	/* Address that generated the exception */
+extern uint16_t last_op_for_exception_3;
+extern uint32_t last_addr_for_exception_3;
+extern uint32_t last_fault_for_exception_3;
 
-/* Family of the latest instruction executed (to check for pairing) */
-extern int OpcodeFamily;			/* see instrmnem in readcpu.h */
+extern int OpcodeFamily;
 
-/* How many cycles to add to the current instruction in case a "misaligned" bus access is made */
-/* (used when addressing mode is d8(an,ix)) */
 extern int BusCyclePenalty;
 extern int CurrentInstrCycles;
 
diff --git a/waterbox/virtualjaguar/src/m68000/cpustbl.c b/waterbox/virtualjaguar/src/m68000/cpustbl.c
index 91f632682b..80d7f3a7b8 100644
--- a/waterbox/virtualjaguar/src/m68000/cpustbl.c
+++ b/waterbox/virtualjaguar/src/m68000/cpustbl.c
@@ -3,1591 +3,7 @@
 #include "inlines.h"
 #include "cputbl.h"
 #define CPUFUNC(x) x##_ff
-#ifdef NOFLAGS
-#include "noflags.h"
-#endif
-const struct cputbl CPUFUNC(op_smalltbl_4)[] = {
-{ CPUFUNC(op_0_4), 0, 0 }, /* OR */
-{ CPUFUNC(op_10_4), 0, 16 }, /* OR */
-{ CPUFUNC(op_18_4), 0, 24 }, /* OR */
-{ CPUFUNC(op_20_4), 0, 32 }, /* OR */
-{ CPUFUNC(op_28_4), 0, 40 }, /* OR */
-{ CPUFUNC(op_30_4), 0, 48 }, /* OR */
-{ CPUFUNC(op_38_4), 0, 56 }, /* OR */
-{ CPUFUNC(op_39_4), 0, 57 }, /* OR */
-{ CPUFUNC(op_3c_4), 0, 60 }, /* ORSR */
-{ CPUFUNC(op_40_4), 0, 64 }, /* OR */
-{ CPUFUNC(op_50_4), 0, 80 }, /* OR */
-{ CPUFUNC(op_58_4), 0, 88 }, /* OR */
-{ CPUFUNC(op_60_4), 0, 96 }, /* OR */
-{ CPUFUNC(op_68_4), 0, 104 }, /* OR */
-{ CPUFUNC(op_70_4), 0, 112 }, /* OR */
-{ CPUFUNC(op_78_4), 0, 120 }, /* OR */
-{ CPUFUNC(op_79_4), 0, 121 }, /* OR */
-{ CPUFUNC(op_7c_4), 0, 124 }, /* ORSR */
-{ CPUFUNC(op_80_4), 0, 128 }, /* OR */
-{ CPUFUNC(op_90_4), 0, 144 }, /* OR */
-{ CPUFUNC(op_98_4), 0, 152 }, /* OR */
-{ CPUFUNC(op_a0_4), 0, 160 }, /* OR */
-{ CPUFUNC(op_a8_4), 0, 168 }, /* OR */
-{ CPUFUNC(op_b0_4), 0, 176 }, /* OR */
-{ CPUFUNC(op_b8_4), 0, 184 }, /* OR */
-{ CPUFUNC(op_b9_4), 0, 185 }, /* OR */
-{ CPUFUNC(op_100_4), 0, 256 }, /* BTST */
-{ CPUFUNC(op_108_4), 0, 264 }, /* MVPMR */
-{ CPUFUNC(op_110_4), 0, 272 }, /* BTST */
-{ CPUFUNC(op_118_4), 0, 280 }, /* BTST */
-{ CPUFUNC(op_120_4), 0, 288 }, /* BTST */
-{ CPUFUNC(op_128_4), 0, 296 }, /* BTST */
-{ CPUFUNC(op_130_4), 0, 304 }, /* BTST */
-{ CPUFUNC(op_138_4), 0, 312 }, /* BTST */
-{ CPUFUNC(op_139_4), 0, 313 }, /* BTST */
-{ CPUFUNC(op_13a_4), 0, 314 }, /* BTST */
-{ CPUFUNC(op_13b_4), 0, 315 }, /* BTST */
-{ CPUFUNC(op_13c_4), 0, 316 }, /* BTST */
-{ CPUFUNC(op_140_4), 0, 320 }, /* BCHG */
-{ CPUFUNC(op_148_4), 0, 328 }, /* MVPMR */
-{ CPUFUNC(op_150_4), 0, 336 }, /* BCHG */
-{ CPUFUNC(op_158_4), 0, 344 }, /* BCHG */
-{ CPUFUNC(op_160_4), 0, 352 }, /* BCHG */
-{ CPUFUNC(op_168_4), 0, 360 }, /* BCHG */
-{ CPUFUNC(op_170_4), 0, 368 }, /* BCHG */
-{ CPUFUNC(op_178_4), 0, 376 }, /* BCHG */
-{ CPUFUNC(op_179_4), 0, 377 }, /* BCHG */
-{ CPUFUNC(op_17a_4), 0, 378 }, /* BCHG */
-{ CPUFUNC(op_17b_4), 0, 379 }, /* BCHG */
-{ CPUFUNC(op_180_4), 0, 384 }, /* BCLR */
-{ CPUFUNC(op_188_4), 0, 392 }, /* MVPRM */
-{ CPUFUNC(op_190_4), 0, 400 }, /* BCLR */
-{ CPUFUNC(op_198_4), 0, 408 }, /* BCLR */
-{ CPUFUNC(op_1a0_4), 0, 416 }, /* BCLR */
-{ CPUFUNC(op_1a8_4), 0, 424 }, /* BCLR */
-{ CPUFUNC(op_1b0_4), 0, 432 }, /* BCLR */
-{ CPUFUNC(op_1b8_4), 0, 440 }, /* BCLR */
-{ CPUFUNC(op_1b9_4), 0, 441 }, /* BCLR */
-{ CPUFUNC(op_1ba_4), 0, 442 }, /* BCLR */
-{ CPUFUNC(op_1bb_4), 0, 443 }, /* BCLR */
-{ CPUFUNC(op_1c0_4), 0, 448 }, /* BSET */
-{ CPUFUNC(op_1c8_4), 0, 456 }, /* MVPRM */
-{ CPUFUNC(op_1d0_4), 0, 464 }, /* BSET */
-{ CPUFUNC(op_1d8_4), 0, 472 }, /* BSET */
-{ CPUFUNC(op_1e0_4), 0, 480 }, /* BSET */
-{ CPUFUNC(op_1e8_4), 0, 488 }, /* BSET */
-{ CPUFUNC(op_1f0_4), 0, 496 }, /* BSET */
-{ CPUFUNC(op_1f8_4), 0, 504 }, /* BSET */
-{ CPUFUNC(op_1f9_4), 0, 505 }, /* BSET */
-{ CPUFUNC(op_1fa_4), 0, 506 }, /* BSET */
-{ CPUFUNC(op_1fb_4), 0, 507 }, /* BSET */
-{ CPUFUNC(op_200_4), 0, 512 }, /* AND */
-{ CPUFUNC(op_210_4), 0, 528 }, /* AND */
-{ CPUFUNC(op_218_4), 0, 536 }, /* AND */
-{ CPUFUNC(op_220_4), 0, 544 }, /* AND */
-{ CPUFUNC(op_228_4), 0, 552 }, /* AND */
-{ CPUFUNC(op_230_4), 0, 560 }, /* AND */
-{ CPUFUNC(op_238_4), 0, 568 }, /* AND */
-{ CPUFUNC(op_239_4), 0, 569 }, /* AND */
-{ CPUFUNC(op_23c_4), 0, 572 }, /* ANDSR */
-{ CPUFUNC(op_240_4), 0, 576 }, /* AND */
-{ CPUFUNC(op_250_4), 0, 592 }, /* AND */
-{ CPUFUNC(op_258_4), 0, 600 }, /* AND */
-{ CPUFUNC(op_260_4), 0, 608 }, /* AND */
-{ CPUFUNC(op_268_4), 0, 616 }, /* AND */
-{ CPUFUNC(op_270_4), 0, 624 }, /* AND */
-{ CPUFUNC(op_278_4), 0, 632 }, /* AND */
-{ CPUFUNC(op_279_4), 0, 633 }, /* AND */
-{ CPUFUNC(op_27c_4), 0, 636 }, /* ANDSR */
-{ CPUFUNC(op_280_4), 0, 640 }, /* AND */
-{ CPUFUNC(op_290_4), 0, 656 }, /* AND */
-{ CPUFUNC(op_298_4), 0, 664 }, /* AND */
-{ CPUFUNC(op_2a0_4), 0, 672 }, /* AND */
-{ CPUFUNC(op_2a8_4), 0, 680 }, /* AND */
-{ CPUFUNC(op_2b0_4), 0, 688 }, /* AND */
-{ CPUFUNC(op_2b8_4), 0, 696 }, /* AND */
-{ CPUFUNC(op_2b9_4), 0, 697 }, /* AND */
-{ CPUFUNC(op_400_4), 0, 1024 }, /* SUB */
-{ CPUFUNC(op_410_4), 0, 1040 }, /* SUB */
-{ CPUFUNC(op_418_4), 0, 1048 }, /* SUB */
-{ CPUFUNC(op_420_4), 0, 1056 }, /* SUB */
-{ CPUFUNC(op_428_4), 0, 1064 }, /* SUB */
-{ CPUFUNC(op_430_4), 0, 1072 }, /* SUB */
-{ CPUFUNC(op_438_4), 0, 1080 }, /* SUB */
-{ CPUFUNC(op_439_4), 0, 1081 }, /* SUB */
-{ CPUFUNC(op_440_4), 0, 1088 }, /* SUB */
-{ CPUFUNC(op_450_4), 0, 1104 }, /* SUB */
-{ CPUFUNC(op_458_4), 0, 1112 }, /* SUB */
-{ CPUFUNC(op_460_4), 0, 1120 }, /* SUB */
-{ CPUFUNC(op_468_4), 0, 1128 }, /* SUB */
-{ CPUFUNC(op_470_4), 0, 1136 }, /* SUB */
-{ CPUFUNC(op_478_4), 0, 1144 }, /* SUB */
-{ CPUFUNC(op_479_4), 0, 1145 }, /* SUB */
-{ CPUFUNC(op_480_4), 0, 1152 }, /* SUB */
-{ CPUFUNC(op_490_4), 0, 1168 }, /* SUB */
-{ CPUFUNC(op_498_4), 0, 1176 }, /* SUB */
-{ CPUFUNC(op_4a0_4), 0, 1184 }, /* SUB */
-{ CPUFUNC(op_4a8_4), 0, 1192 }, /* SUB */
-{ CPUFUNC(op_4b0_4), 0, 1200 }, /* SUB */
-{ CPUFUNC(op_4b8_4), 0, 1208 }, /* SUB */
-{ CPUFUNC(op_4b9_4), 0, 1209 }, /* SUB */
-{ CPUFUNC(op_600_4), 0, 1536 }, /* ADD */
-{ CPUFUNC(op_610_4), 0, 1552 }, /* ADD */
-{ CPUFUNC(op_618_4), 0, 1560 }, /* ADD */
-{ CPUFUNC(op_620_4), 0, 1568 }, /* ADD */
-{ CPUFUNC(op_628_4), 0, 1576 }, /* ADD */
-{ CPUFUNC(op_630_4), 0, 1584 }, /* ADD */
-{ CPUFUNC(op_638_4), 0, 1592 }, /* ADD */
-{ CPUFUNC(op_639_4), 0, 1593 }, /* ADD */
-{ CPUFUNC(op_640_4), 0, 1600 }, /* ADD */
-{ CPUFUNC(op_650_4), 0, 1616 }, /* ADD */
-{ CPUFUNC(op_658_4), 0, 1624 }, /* ADD */
-{ CPUFUNC(op_660_4), 0, 1632 }, /* ADD */
-{ CPUFUNC(op_668_4), 0, 1640 }, /* ADD */
-{ CPUFUNC(op_670_4), 0, 1648 }, /* ADD */
-{ CPUFUNC(op_678_4), 0, 1656 }, /* ADD */
-{ CPUFUNC(op_679_4), 0, 1657 }, /* ADD */
-{ CPUFUNC(op_680_4), 0, 1664 }, /* ADD */
-{ CPUFUNC(op_690_4), 0, 1680 }, /* ADD */
-{ CPUFUNC(op_698_4), 0, 1688 }, /* ADD */
-{ CPUFUNC(op_6a0_4), 0, 1696 }, /* ADD */
-{ CPUFUNC(op_6a8_4), 0, 1704 }, /* ADD */
-{ CPUFUNC(op_6b0_4), 0, 1712 }, /* ADD */
-{ CPUFUNC(op_6b8_4), 0, 1720 }, /* ADD */
-{ CPUFUNC(op_6b9_4), 0, 1721 }, /* ADD */
-{ CPUFUNC(op_800_4), 0, 2048 }, /* BTST */
-{ CPUFUNC(op_810_4), 0, 2064 }, /* BTST */
-{ CPUFUNC(op_818_4), 0, 2072 }, /* BTST */
-{ CPUFUNC(op_820_4), 0, 2080 }, /* BTST */
-{ CPUFUNC(op_828_4), 0, 2088 }, /* BTST */
-{ CPUFUNC(op_830_4), 0, 2096 }, /* BTST */
-{ CPUFUNC(op_838_4), 0, 2104 }, /* BTST */
-{ CPUFUNC(op_839_4), 0, 2105 }, /* BTST */
-{ CPUFUNC(op_83a_4), 0, 2106 }, /* BTST */
-{ CPUFUNC(op_83b_4), 0, 2107 }, /* BTST */
-{ CPUFUNC(op_83c_4), 0, 2108 }, /* BTST */
-{ CPUFUNC(op_840_4), 0, 2112 }, /* BCHG */
-{ CPUFUNC(op_850_4), 0, 2128 }, /* BCHG */
-{ CPUFUNC(op_858_4), 0, 2136 }, /* BCHG */
-{ CPUFUNC(op_860_4), 0, 2144 }, /* BCHG */
-{ CPUFUNC(op_868_4), 0, 2152 }, /* BCHG */
-{ CPUFUNC(op_870_4), 0, 2160 }, /* BCHG */
-{ CPUFUNC(op_878_4), 0, 2168 }, /* BCHG */
-{ CPUFUNC(op_879_4), 0, 2169 }, /* BCHG */
-{ CPUFUNC(op_87a_4), 0, 2170 }, /* BCHG */
-{ CPUFUNC(op_87b_4), 0, 2171 }, /* BCHG */
-{ CPUFUNC(op_880_4), 0, 2176 }, /* BCLR */
-{ CPUFUNC(op_890_4), 0, 2192 }, /* BCLR */
-{ CPUFUNC(op_898_4), 0, 2200 }, /* BCLR */
-{ CPUFUNC(op_8a0_4), 0, 2208 }, /* BCLR */
-{ CPUFUNC(op_8a8_4), 0, 2216 }, /* BCLR */
-{ CPUFUNC(op_8b0_4), 0, 2224 }, /* BCLR */
-{ CPUFUNC(op_8b8_4), 0, 2232 }, /* BCLR */
-{ CPUFUNC(op_8b9_4), 0, 2233 }, /* BCLR */
-{ CPUFUNC(op_8ba_4), 0, 2234 }, /* BCLR */
-{ CPUFUNC(op_8bb_4), 0, 2235 }, /* BCLR */
-{ CPUFUNC(op_8c0_4), 0, 2240 }, /* BSET */
-{ CPUFUNC(op_8d0_4), 0, 2256 }, /* BSET */
-{ CPUFUNC(op_8d8_4), 0, 2264 }, /* BSET */
-{ CPUFUNC(op_8e0_4), 0, 2272 }, /* BSET */
-{ CPUFUNC(op_8e8_4), 0, 2280 }, /* BSET */
-{ CPUFUNC(op_8f0_4), 0, 2288 }, /* BSET */
-{ CPUFUNC(op_8f8_4), 0, 2296 }, /* BSET */
-{ CPUFUNC(op_8f9_4), 0, 2297 }, /* BSET */
-{ CPUFUNC(op_8fa_4), 0, 2298 }, /* BSET */
-{ CPUFUNC(op_8fb_4), 0, 2299 }, /* BSET */
-{ CPUFUNC(op_a00_4), 0, 2560 }, /* EOR */
-{ CPUFUNC(op_a10_4), 0, 2576 }, /* EOR */
-{ CPUFUNC(op_a18_4), 0, 2584 }, /* EOR */
-{ CPUFUNC(op_a20_4), 0, 2592 }, /* EOR */
-{ CPUFUNC(op_a28_4), 0, 2600 }, /* EOR */
-{ CPUFUNC(op_a30_4), 0, 2608 }, /* EOR */
-{ CPUFUNC(op_a38_4), 0, 2616 }, /* EOR */
-{ CPUFUNC(op_a39_4), 0, 2617 }, /* EOR */
-{ CPUFUNC(op_a3c_4), 0, 2620 }, /* EORSR */
-{ CPUFUNC(op_a40_4), 0, 2624 }, /* EOR */
-{ CPUFUNC(op_a50_4), 0, 2640 }, /* EOR */
-{ CPUFUNC(op_a58_4), 0, 2648 }, /* EOR */
-{ CPUFUNC(op_a60_4), 0, 2656 }, /* EOR */
-{ CPUFUNC(op_a68_4), 0, 2664 }, /* EOR */
-{ CPUFUNC(op_a70_4), 0, 2672 }, /* EOR */
-{ CPUFUNC(op_a78_4), 0, 2680 }, /* EOR */
-{ CPUFUNC(op_a79_4), 0, 2681 }, /* EOR */
-{ CPUFUNC(op_a7c_4), 0, 2684 }, /* EORSR */
-{ CPUFUNC(op_a80_4), 0, 2688 }, /* EOR */
-{ CPUFUNC(op_a90_4), 0, 2704 }, /* EOR */
-{ CPUFUNC(op_a98_4), 0, 2712 }, /* EOR */
-{ CPUFUNC(op_aa0_4), 0, 2720 }, /* EOR */
-{ CPUFUNC(op_aa8_4), 0, 2728 }, /* EOR */
-{ CPUFUNC(op_ab0_4), 0, 2736 }, /* EOR */
-{ CPUFUNC(op_ab8_4), 0, 2744 }, /* EOR */
-{ CPUFUNC(op_ab9_4), 0, 2745 }, /* EOR */
-{ CPUFUNC(op_c00_4), 0, 3072 }, /* CMP */
-{ CPUFUNC(op_c10_4), 0, 3088 }, /* CMP */
-{ CPUFUNC(op_c18_4), 0, 3096 }, /* CMP */
-{ CPUFUNC(op_c20_4), 0, 3104 }, /* CMP */
-{ CPUFUNC(op_c28_4), 0, 3112 }, /* CMP */
-{ CPUFUNC(op_c30_4), 0, 3120 }, /* CMP */
-{ CPUFUNC(op_c38_4), 0, 3128 }, /* CMP */
-{ CPUFUNC(op_c39_4), 0, 3129 }, /* CMP */
-{ CPUFUNC(op_c3a_4), 0, 3130 }, /* CMP */
-{ CPUFUNC(op_c3b_4), 0, 3131 }, /* CMP */
-{ CPUFUNC(op_c40_4), 0, 3136 }, /* CMP */
-{ CPUFUNC(op_c50_4), 0, 3152 }, /* CMP */
-{ CPUFUNC(op_c58_4), 0, 3160 }, /* CMP */
-{ CPUFUNC(op_c60_4), 0, 3168 }, /* CMP */
-{ CPUFUNC(op_c68_4), 0, 3176 }, /* CMP */
-{ CPUFUNC(op_c70_4), 0, 3184 }, /* CMP */
-{ CPUFUNC(op_c78_4), 0, 3192 }, /* CMP */
-{ CPUFUNC(op_c79_4), 0, 3193 }, /* CMP */
-{ CPUFUNC(op_c7a_4), 0, 3194 }, /* CMP */
-{ CPUFUNC(op_c7b_4), 0, 3195 }, /* CMP */
-{ CPUFUNC(op_c80_4), 0, 3200 }, /* CMP */
-{ CPUFUNC(op_c90_4), 0, 3216 }, /* CMP */
-{ CPUFUNC(op_c98_4), 0, 3224 }, /* CMP */
-{ CPUFUNC(op_ca0_4), 0, 3232 }, /* CMP */
-{ CPUFUNC(op_ca8_4), 0, 3240 }, /* CMP */
-{ CPUFUNC(op_cb0_4), 0, 3248 }, /* CMP */
-{ CPUFUNC(op_cb8_4), 0, 3256 }, /* CMP */
-{ CPUFUNC(op_cb9_4), 0, 3257 }, /* CMP */
-{ CPUFUNC(op_cba_4), 0, 3258 }, /* CMP */
-{ CPUFUNC(op_cbb_4), 0, 3259 }, /* CMP */
-{ CPUFUNC(op_1000_4), 0, 4096 }, /* MOVE */
-{ CPUFUNC(op_1008_4), 0, 4104 }, /* MOVE */
-{ CPUFUNC(op_1010_4), 0, 4112 }, /* MOVE */
-{ CPUFUNC(op_1018_4), 0, 4120 }, /* MOVE */
-{ CPUFUNC(op_1020_4), 0, 4128 }, /* MOVE */
-{ CPUFUNC(op_1028_4), 0, 4136 }, /* MOVE */
-{ CPUFUNC(op_1030_4), 0, 4144 }, /* MOVE */
-{ CPUFUNC(op_1038_4), 0, 4152 }, /* MOVE */
-{ CPUFUNC(op_1039_4), 0, 4153 }, /* MOVE */
-{ CPUFUNC(op_103a_4), 0, 4154 }, /* MOVE */
-{ CPUFUNC(op_103b_4), 0, 4155 }, /* MOVE */
-{ CPUFUNC(op_103c_4), 0, 4156 }, /* MOVE */
-{ CPUFUNC(op_1080_4), 0, 4224 }, /* MOVE */
-{ CPUFUNC(op_1088_4), 0, 4232 }, /* MOVE */
-{ CPUFUNC(op_1090_4), 0, 4240 }, /* MOVE */
-{ CPUFUNC(op_1098_4), 0, 4248 }, /* MOVE */
-{ CPUFUNC(op_10a0_4), 0, 4256 }, /* MOVE */
-{ CPUFUNC(op_10a8_4), 0, 4264 }, /* MOVE */
-{ CPUFUNC(op_10b0_4), 0, 4272 }, /* MOVE */
-{ CPUFUNC(op_10b8_4), 0, 4280 }, /* MOVE */
-{ CPUFUNC(op_10b9_4), 0, 4281 }, /* MOVE */
-{ CPUFUNC(op_10ba_4), 0, 4282 }, /* MOVE */
-{ CPUFUNC(op_10bb_4), 0, 4283 }, /* MOVE */
-{ CPUFUNC(op_10bc_4), 0, 4284 }, /* MOVE */
-{ CPUFUNC(op_10c0_4), 0, 4288 }, /* MOVE */
-{ CPUFUNC(op_10c8_4), 0, 4296 }, /* MOVE */
-{ CPUFUNC(op_10d0_4), 0, 4304 }, /* MOVE */
-{ CPUFUNC(op_10d8_4), 0, 4312 }, /* MOVE */
-{ CPUFUNC(op_10e0_4), 0, 4320 }, /* MOVE */
-{ CPUFUNC(op_10e8_4), 0, 4328 }, /* MOVE */
-{ CPUFUNC(op_10f0_4), 0, 4336 }, /* MOVE */
-{ CPUFUNC(op_10f8_4), 0, 4344 }, /* MOVE */
-{ CPUFUNC(op_10f9_4), 0, 4345 }, /* MOVE */
-{ CPUFUNC(op_10fa_4), 0, 4346 }, /* MOVE */
-{ CPUFUNC(op_10fb_4), 0, 4347 }, /* MOVE */
-{ CPUFUNC(op_10fc_4), 0, 4348 }, /* MOVE */
-{ CPUFUNC(op_1100_4), 0, 4352 }, /* MOVE */
-{ CPUFUNC(op_1108_4), 0, 4360 }, /* MOVE */
-{ CPUFUNC(op_1110_4), 0, 4368 }, /* MOVE */
-{ CPUFUNC(op_1118_4), 0, 4376 }, /* MOVE */
-{ CPUFUNC(op_1120_4), 0, 4384 }, /* MOVE */
-{ CPUFUNC(op_1128_4), 0, 4392 }, /* MOVE */
-{ CPUFUNC(op_1130_4), 0, 4400 }, /* MOVE */
-{ CPUFUNC(op_1138_4), 0, 4408 }, /* MOVE */
-{ CPUFUNC(op_1139_4), 0, 4409 }, /* MOVE */
-{ CPUFUNC(op_113a_4), 0, 4410 }, /* MOVE */
-{ CPUFUNC(op_113b_4), 0, 4411 }, /* MOVE */
-{ CPUFUNC(op_113c_4), 0, 4412 }, /* MOVE */
-{ CPUFUNC(op_1140_4), 0, 4416 }, /* MOVE */
-{ CPUFUNC(op_1148_4), 0, 4424 }, /* MOVE */
-{ CPUFUNC(op_1150_4), 0, 4432 }, /* MOVE */
-{ CPUFUNC(op_1158_4), 0, 4440 }, /* MOVE */
-{ CPUFUNC(op_1160_4), 0, 4448 }, /* MOVE */
-{ CPUFUNC(op_1168_4), 0, 4456 }, /* MOVE */
-{ CPUFUNC(op_1170_4), 0, 4464 }, /* MOVE */
-{ CPUFUNC(op_1178_4), 0, 4472 }, /* MOVE */
-{ CPUFUNC(op_1179_4), 0, 4473 }, /* MOVE */
-{ CPUFUNC(op_117a_4), 0, 4474 }, /* MOVE */
-{ CPUFUNC(op_117b_4), 0, 4475 }, /* MOVE */
-{ CPUFUNC(op_117c_4), 0, 4476 }, /* MOVE */
-{ CPUFUNC(op_1180_4), 0, 4480 }, /* MOVE */
-{ CPUFUNC(op_1188_4), 0, 4488 }, /* MOVE */
-{ CPUFUNC(op_1190_4), 0, 4496 }, /* MOVE */
-{ CPUFUNC(op_1198_4), 0, 4504 }, /* MOVE */
-{ CPUFUNC(op_11a0_4), 0, 4512 }, /* MOVE */
-{ CPUFUNC(op_11a8_4), 0, 4520 }, /* MOVE */
-{ CPUFUNC(op_11b0_4), 0, 4528 }, /* MOVE */
-{ CPUFUNC(op_11b8_4), 0, 4536 }, /* MOVE */
-{ CPUFUNC(op_11b9_4), 0, 4537 }, /* MOVE */
-{ CPUFUNC(op_11ba_4), 0, 4538 }, /* MOVE */
-{ CPUFUNC(op_11bb_4), 0, 4539 }, /* MOVE */
-{ CPUFUNC(op_11bc_4), 0, 4540 }, /* MOVE */
-{ CPUFUNC(op_11c0_4), 0, 4544 }, /* MOVE */
-{ CPUFUNC(op_11c8_4), 0, 4552 }, /* MOVE */
-{ CPUFUNC(op_11d0_4), 0, 4560 }, /* MOVE */
-{ CPUFUNC(op_11d8_4), 0, 4568 }, /* MOVE */
-{ CPUFUNC(op_11e0_4), 0, 4576 }, /* MOVE */
-{ CPUFUNC(op_11e8_4), 0, 4584 }, /* MOVE */
-{ CPUFUNC(op_11f0_4), 0, 4592 }, /* MOVE */
-{ CPUFUNC(op_11f8_4), 0, 4600 }, /* MOVE */
-{ CPUFUNC(op_11f9_4), 0, 4601 }, /* MOVE */
-{ CPUFUNC(op_11fa_4), 0, 4602 }, /* MOVE */
-{ CPUFUNC(op_11fb_4), 0, 4603 }, /* MOVE */
-{ CPUFUNC(op_11fc_4), 0, 4604 }, /* MOVE */
-{ CPUFUNC(op_13c0_4), 0, 5056 }, /* MOVE */
-{ CPUFUNC(op_13c8_4), 0, 5064 }, /* MOVE */
-{ CPUFUNC(op_13d0_4), 0, 5072 }, /* MOVE */
-{ CPUFUNC(op_13d8_4), 0, 5080 }, /* MOVE */
-{ CPUFUNC(op_13e0_4), 0, 5088 }, /* MOVE */
-{ CPUFUNC(op_13e8_4), 0, 5096 }, /* MOVE */
-{ CPUFUNC(op_13f0_4), 0, 5104 }, /* MOVE */
-{ CPUFUNC(op_13f8_4), 0, 5112 }, /* MOVE */
-{ CPUFUNC(op_13f9_4), 0, 5113 }, /* MOVE */
-{ CPUFUNC(op_13fa_4), 0, 5114 }, /* MOVE */
-{ CPUFUNC(op_13fb_4), 0, 5115 }, /* MOVE */
-{ CPUFUNC(op_13fc_4), 0, 5116 }, /* MOVE */
-{ CPUFUNC(op_2000_4), 0, 8192 }, /* MOVE */
-{ CPUFUNC(op_2008_4), 0, 8200 }, /* MOVE */
-{ CPUFUNC(op_2010_4), 0, 8208 }, /* MOVE */
-{ CPUFUNC(op_2018_4), 0, 8216 }, /* MOVE */
-{ CPUFUNC(op_2020_4), 0, 8224 }, /* MOVE */
-{ CPUFUNC(op_2028_4), 0, 8232 }, /* MOVE */
-{ CPUFUNC(op_2030_4), 0, 8240 }, /* MOVE */
-{ CPUFUNC(op_2038_4), 0, 8248 }, /* MOVE */
-{ CPUFUNC(op_2039_4), 0, 8249 }, /* MOVE */
-{ CPUFUNC(op_203a_4), 0, 8250 }, /* MOVE */
-{ CPUFUNC(op_203b_4), 0, 8251 }, /* MOVE */
-{ CPUFUNC(op_203c_4), 0, 8252 }, /* MOVE */
-{ CPUFUNC(op_2040_4), 0, 8256 }, /* MOVEA */
-{ CPUFUNC(op_2048_4), 0, 8264 }, /* MOVEA */
-{ CPUFUNC(op_2050_4), 0, 8272 }, /* MOVEA */
-{ CPUFUNC(op_2058_4), 0, 8280 }, /* MOVEA */
-{ CPUFUNC(op_2060_4), 0, 8288 }, /* MOVEA */
-{ CPUFUNC(op_2068_4), 0, 8296 }, /* MOVEA */
-{ CPUFUNC(op_2070_4), 0, 8304 }, /* MOVEA */
-{ CPUFUNC(op_2078_4), 0, 8312 }, /* MOVEA */
-{ CPUFUNC(op_2079_4), 0, 8313 }, /* MOVEA */
-{ CPUFUNC(op_207a_4), 0, 8314 }, /* MOVEA */
-{ CPUFUNC(op_207b_4), 0, 8315 }, /* MOVEA */
-{ CPUFUNC(op_207c_4), 0, 8316 }, /* MOVEA */
-{ CPUFUNC(op_2080_4), 0, 8320 }, /* MOVE */
-{ CPUFUNC(op_2088_4), 0, 8328 }, /* MOVE */
-{ CPUFUNC(op_2090_4), 0, 8336 }, /* MOVE */
-{ CPUFUNC(op_2098_4), 0, 8344 }, /* MOVE */
-{ CPUFUNC(op_20a0_4), 0, 8352 }, /* MOVE */
-{ CPUFUNC(op_20a8_4), 0, 8360 }, /* MOVE */
-{ CPUFUNC(op_20b0_4), 0, 8368 }, /* MOVE */
-{ CPUFUNC(op_20b8_4), 0, 8376 }, /* MOVE */
-{ CPUFUNC(op_20b9_4), 0, 8377 }, /* MOVE */
-{ CPUFUNC(op_20ba_4), 0, 8378 }, /* MOVE */
-{ CPUFUNC(op_20bb_4), 0, 8379 }, /* MOVE */
-{ CPUFUNC(op_20bc_4), 0, 8380 }, /* MOVE */
-{ CPUFUNC(op_20c0_4), 0, 8384 }, /* MOVE */
-{ CPUFUNC(op_20c8_4), 0, 8392 }, /* MOVE */
-{ CPUFUNC(op_20d0_4), 0, 8400 }, /* MOVE */
-{ CPUFUNC(op_20d8_4), 0, 8408 }, /* MOVE */
-{ CPUFUNC(op_20e0_4), 0, 8416 }, /* MOVE */
-{ CPUFUNC(op_20e8_4), 0, 8424 }, /* MOVE */
-{ CPUFUNC(op_20f0_4), 0, 8432 }, /* MOVE */
-{ CPUFUNC(op_20f8_4), 0, 8440 }, /* MOVE */
-{ CPUFUNC(op_20f9_4), 0, 8441 }, /* MOVE */
-{ CPUFUNC(op_20fa_4), 0, 8442 }, /* MOVE */
-{ CPUFUNC(op_20fb_4), 0, 8443 }, /* MOVE */
-{ CPUFUNC(op_20fc_4), 0, 8444 }, /* MOVE */
-{ CPUFUNC(op_2100_4), 0, 8448 }, /* MOVE */
-{ CPUFUNC(op_2108_4), 0, 8456 }, /* MOVE */
-{ CPUFUNC(op_2110_4), 0, 8464 }, /* MOVE */
-{ CPUFUNC(op_2118_4), 0, 8472 }, /* MOVE */
-{ CPUFUNC(op_2120_4), 0, 8480 }, /* MOVE */
-{ CPUFUNC(op_2128_4), 0, 8488 }, /* MOVE */
-{ CPUFUNC(op_2130_4), 0, 8496 }, /* MOVE */
-{ CPUFUNC(op_2138_4), 0, 8504 }, /* MOVE */
-{ CPUFUNC(op_2139_4), 0, 8505 }, /* MOVE */
-{ CPUFUNC(op_213a_4), 0, 8506 }, /* MOVE */
-{ CPUFUNC(op_213b_4), 0, 8507 }, /* MOVE */
-{ CPUFUNC(op_213c_4), 0, 8508 }, /* MOVE */
-{ CPUFUNC(op_2140_4), 0, 8512 }, /* MOVE */
-{ CPUFUNC(op_2148_4), 0, 8520 }, /* MOVE */
-{ CPUFUNC(op_2150_4), 0, 8528 }, /* MOVE */
-{ CPUFUNC(op_2158_4), 0, 8536 }, /* MOVE */
-{ CPUFUNC(op_2160_4), 0, 8544 }, /* MOVE */
-{ CPUFUNC(op_2168_4), 0, 8552 }, /* MOVE */
-{ CPUFUNC(op_2170_4), 0, 8560 }, /* MOVE */
-{ CPUFUNC(op_2178_4), 0, 8568 }, /* MOVE */
-{ CPUFUNC(op_2179_4), 0, 8569 }, /* MOVE */
-{ CPUFUNC(op_217a_4), 0, 8570 }, /* MOVE */
-{ CPUFUNC(op_217b_4), 0, 8571 }, /* MOVE */
-{ CPUFUNC(op_217c_4), 0, 8572 }, /* MOVE */
-{ CPUFUNC(op_2180_4), 0, 8576 }, /* MOVE */
-{ CPUFUNC(op_2188_4), 0, 8584 }, /* MOVE */
-{ CPUFUNC(op_2190_4), 0, 8592 }, /* MOVE */
-{ CPUFUNC(op_2198_4), 0, 8600 }, /* MOVE */
-{ CPUFUNC(op_21a0_4), 0, 8608 }, /* MOVE */
-{ CPUFUNC(op_21a8_4), 0, 8616 }, /* MOVE */
-{ CPUFUNC(op_21b0_4), 0, 8624 }, /* MOVE */
-{ CPUFUNC(op_21b8_4), 0, 8632 }, /* MOVE */
-{ CPUFUNC(op_21b9_4), 0, 8633 }, /* MOVE */
-{ CPUFUNC(op_21ba_4), 0, 8634 }, /* MOVE */
-{ CPUFUNC(op_21bb_4), 0, 8635 }, /* MOVE */
-{ CPUFUNC(op_21bc_4), 0, 8636 }, /* MOVE */
-{ CPUFUNC(op_21c0_4), 0, 8640 }, /* MOVE */
-{ CPUFUNC(op_21c8_4), 0, 8648 }, /* MOVE */
-{ CPUFUNC(op_21d0_4), 0, 8656 }, /* MOVE */
-{ CPUFUNC(op_21d8_4), 0, 8664 }, /* MOVE */
-{ CPUFUNC(op_21e0_4), 0, 8672 }, /* MOVE */
-{ CPUFUNC(op_21e8_4), 0, 8680 }, /* MOVE */
-{ CPUFUNC(op_21f0_4), 0, 8688 }, /* MOVE */
-{ CPUFUNC(op_21f8_4), 0, 8696 }, /* MOVE */
-{ CPUFUNC(op_21f9_4), 0, 8697 }, /* MOVE */
-{ CPUFUNC(op_21fa_4), 0, 8698 }, /* MOVE */
-{ CPUFUNC(op_21fb_4), 0, 8699 }, /* MOVE */
-{ CPUFUNC(op_21fc_4), 0, 8700 }, /* MOVE */
-{ CPUFUNC(op_23c0_4), 0, 9152 }, /* MOVE */
-{ CPUFUNC(op_23c8_4), 0, 9160 }, /* MOVE */
-{ CPUFUNC(op_23d0_4), 0, 9168 }, /* MOVE */
-{ CPUFUNC(op_23d8_4), 0, 9176 }, /* MOVE */
-{ CPUFUNC(op_23e0_4), 0, 9184 }, /* MOVE */
-{ CPUFUNC(op_23e8_4), 0, 9192 }, /* MOVE */
-{ CPUFUNC(op_23f0_4), 0, 9200 }, /* MOVE */
-{ CPUFUNC(op_23f8_4), 0, 9208 }, /* MOVE */
-{ CPUFUNC(op_23f9_4), 0, 9209 }, /* MOVE */
-{ CPUFUNC(op_23fa_4), 0, 9210 }, /* MOVE */
-{ CPUFUNC(op_23fb_4), 0, 9211 }, /* MOVE */
-{ CPUFUNC(op_23fc_4), 0, 9212 }, /* MOVE */
-{ CPUFUNC(op_3000_4), 0, 12288 }, /* MOVE */
-{ CPUFUNC(op_3008_4), 0, 12296 }, /* MOVE */
-{ CPUFUNC(op_3010_4), 0, 12304 }, /* MOVE */
-{ CPUFUNC(op_3018_4), 0, 12312 }, /* MOVE */
-{ CPUFUNC(op_3020_4), 0, 12320 }, /* MOVE */
-{ CPUFUNC(op_3028_4), 0, 12328 }, /* MOVE */
-{ CPUFUNC(op_3030_4), 0, 12336 }, /* MOVE */
-{ CPUFUNC(op_3038_4), 0, 12344 }, /* MOVE */
-{ CPUFUNC(op_3039_4), 0, 12345 }, /* MOVE */
-{ CPUFUNC(op_303a_4), 0, 12346 }, /* MOVE */
-{ CPUFUNC(op_303b_4), 0, 12347 }, /* MOVE */
-{ CPUFUNC(op_303c_4), 0, 12348 }, /* MOVE */
-{ CPUFUNC(op_3040_4), 0, 12352 }, /* MOVEA */
-{ CPUFUNC(op_3048_4), 0, 12360 }, /* MOVEA */
-{ CPUFUNC(op_3050_4), 0, 12368 }, /* MOVEA */
-{ CPUFUNC(op_3058_4), 0, 12376 }, /* MOVEA */
-{ CPUFUNC(op_3060_4), 0, 12384 }, /* MOVEA */
-{ CPUFUNC(op_3068_4), 0, 12392 }, /* MOVEA */
-{ CPUFUNC(op_3070_4), 0, 12400 }, /* MOVEA */
-{ CPUFUNC(op_3078_4), 0, 12408 }, /* MOVEA */
-{ CPUFUNC(op_3079_4), 0, 12409 }, /* MOVEA */
-{ CPUFUNC(op_307a_4), 0, 12410 }, /* MOVEA */
-{ CPUFUNC(op_307b_4), 0, 12411 }, /* MOVEA */
-{ CPUFUNC(op_307c_4), 0, 12412 }, /* MOVEA */
-{ CPUFUNC(op_3080_4), 0, 12416 }, /* MOVE */
-{ CPUFUNC(op_3088_4), 0, 12424 }, /* MOVE */
-{ CPUFUNC(op_3090_4), 0, 12432 }, /* MOVE */
-{ CPUFUNC(op_3098_4), 0, 12440 }, /* MOVE */
-{ CPUFUNC(op_30a0_4), 0, 12448 }, /* MOVE */
-{ CPUFUNC(op_30a8_4), 0, 12456 }, /* MOVE */
-{ CPUFUNC(op_30b0_4), 0, 12464 }, /* MOVE */
-{ CPUFUNC(op_30b8_4), 0, 12472 }, /* MOVE */
-{ CPUFUNC(op_30b9_4), 0, 12473 }, /* MOVE */
-{ CPUFUNC(op_30ba_4), 0, 12474 }, /* MOVE */
-{ CPUFUNC(op_30bb_4), 0, 12475 }, /* MOVE */
-{ CPUFUNC(op_30bc_4), 0, 12476 }, /* MOVE */
-{ CPUFUNC(op_30c0_4), 0, 12480 }, /* MOVE */
-{ CPUFUNC(op_30c8_4), 0, 12488 }, /* MOVE */
-{ CPUFUNC(op_30d0_4), 0, 12496 }, /* MOVE */
-{ CPUFUNC(op_30d8_4), 0, 12504 }, /* MOVE */
-{ CPUFUNC(op_30e0_4), 0, 12512 }, /* MOVE */
-{ CPUFUNC(op_30e8_4), 0, 12520 }, /* MOVE */
-{ CPUFUNC(op_30f0_4), 0, 12528 }, /* MOVE */
-{ CPUFUNC(op_30f8_4), 0, 12536 }, /* MOVE */
-{ CPUFUNC(op_30f9_4), 0, 12537 }, /* MOVE */
-{ CPUFUNC(op_30fa_4), 0, 12538 }, /* MOVE */
-{ CPUFUNC(op_30fb_4), 0, 12539 }, /* MOVE */
-{ CPUFUNC(op_30fc_4), 0, 12540 }, /* MOVE */
-{ CPUFUNC(op_3100_4), 0, 12544 }, /* MOVE */
-{ CPUFUNC(op_3108_4), 0, 12552 }, /* MOVE */
-{ CPUFUNC(op_3110_4), 0, 12560 }, /* MOVE */
-{ CPUFUNC(op_3118_4), 0, 12568 }, /* MOVE */
-{ CPUFUNC(op_3120_4), 0, 12576 }, /* MOVE */
-{ CPUFUNC(op_3128_4), 0, 12584 }, /* MOVE */
-{ CPUFUNC(op_3130_4), 0, 12592 }, /* MOVE */
-{ CPUFUNC(op_3138_4), 0, 12600 }, /* MOVE */
-{ CPUFUNC(op_3139_4), 0, 12601 }, /* MOVE */
-{ CPUFUNC(op_313a_4), 0, 12602 }, /* MOVE */
-{ CPUFUNC(op_313b_4), 0, 12603 }, /* MOVE */
-{ CPUFUNC(op_313c_4), 0, 12604 }, /* MOVE */
-{ CPUFUNC(op_3140_4), 0, 12608 }, /* MOVE */
-{ CPUFUNC(op_3148_4), 0, 12616 }, /* MOVE */
-{ CPUFUNC(op_3150_4), 0, 12624 }, /* MOVE */
-{ CPUFUNC(op_3158_4), 0, 12632 }, /* MOVE */
-{ CPUFUNC(op_3160_4), 0, 12640 }, /* MOVE */
-{ CPUFUNC(op_3168_4), 0, 12648 }, /* MOVE */
-{ CPUFUNC(op_3170_4), 0, 12656 }, /* MOVE */
-{ CPUFUNC(op_3178_4), 0, 12664 }, /* MOVE */
-{ CPUFUNC(op_3179_4), 0, 12665 }, /* MOVE */
-{ CPUFUNC(op_317a_4), 0, 12666 }, /* MOVE */
-{ CPUFUNC(op_317b_4), 0, 12667 }, /* MOVE */
-{ CPUFUNC(op_317c_4), 0, 12668 }, /* MOVE */
-{ CPUFUNC(op_3180_4), 0, 12672 }, /* MOVE */
-{ CPUFUNC(op_3188_4), 0, 12680 }, /* MOVE */
-{ CPUFUNC(op_3190_4), 0, 12688 }, /* MOVE */
-{ CPUFUNC(op_3198_4), 0, 12696 }, /* MOVE */
-{ CPUFUNC(op_31a0_4), 0, 12704 }, /* MOVE */
-{ CPUFUNC(op_31a8_4), 0, 12712 }, /* MOVE */
-{ CPUFUNC(op_31b0_4), 0, 12720 }, /* MOVE */
-{ CPUFUNC(op_31b8_4), 0, 12728 }, /* MOVE */
-{ CPUFUNC(op_31b9_4), 0, 12729 }, /* MOVE */
-{ CPUFUNC(op_31ba_4), 0, 12730 }, /* MOVE */
-{ CPUFUNC(op_31bb_4), 0, 12731 }, /* MOVE */
-{ CPUFUNC(op_31bc_4), 0, 12732 }, /* MOVE */
-{ CPUFUNC(op_31c0_4), 0, 12736 }, /* MOVE */
-{ CPUFUNC(op_31c8_4), 0, 12744 }, /* MOVE */
-{ CPUFUNC(op_31d0_4), 0, 12752 }, /* MOVE */
-{ CPUFUNC(op_31d8_4), 0, 12760 }, /* MOVE */
-{ CPUFUNC(op_31e0_4), 0, 12768 }, /* MOVE */
-{ CPUFUNC(op_31e8_4), 0, 12776 }, /* MOVE */
-{ CPUFUNC(op_31f0_4), 0, 12784 }, /* MOVE */
-{ CPUFUNC(op_31f8_4), 0, 12792 }, /* MOVE */
-{ CPUFUNC(op_31f9_4), 0, 12793 }, /* MOVE */
-{ CPUFUNC(op_31fa_4), 0, 12794 }, /* MOVE */
-{ CPUFUNC(op_31fb_4), 0, 12795 }, /* MOVE */
-{ CPUFUNC(op_31fc_4), 0, 12796 }, /* MOVE */
-{ CPUFUNC(op_33c0_4), 0, 13248 }, /* MOVE */
-{ CPUFUNC(op_33c8_4), 0, 13256 }, /* MOVE */
-{ CPUFUNC(op_33d0_4), 0, 13264 }, /* MOVE */
-{ CPUFUNC(op_33d8_4), 0, 13272 }, /* MOVE */
-{ CPUFUNC(op_33e0_4), 0, 13280 }, /* MOVE */
-{ CPUFUNC(op_33e8_4), 0, 13288 }, /* MOVE */
-{ CPUFUNC(op_33f0_4), 0, 13296 }, /* MOVE */
-{ CPUFUNC(op_33f8_4), 0, 13304 }, /* MOVE */
-{ CPUFUNC(op_33f9_4), 0, 13305 }, /* MOVE */
-{ CPUFUNC(op_33fa_4), 0, 13306 }, /* MOVE */
-{ CPUFUNC(op_33fb_4), 0, 13307 }, /* MOVE */
-{ CPUFUNC(op_33fc_4), 0, 13308 }, /* MOVE */
-{ CPUFUNC(op_4000_4), 0, 16384 }, /* NEGX */
-{ CPUFUNC(op_4010_4), 0, 16400 }, /* NEGX */
-{ CPUFUNC(op_4018_4), 0, 16408 }, /* NEGX */
-{ CPUFUNC(op_4020_4), 0, 16416 }, /* NEGX */
-{ CPUFUNC(op_4028_4), 0, 16424 }, /* NEGX */
-{ CPUFUNC(op_4030_4), 0, 16432 }, /* NEGX */
-{ CPUFUNC(op_4038_4), 0, 16440 }, /* NEGX */
-{ CPUFUNC(op_4039_4), 0, 16441 }, /* NEGX */
-{ CPUFUNC(op_4040_4), 0, 16448 }, /* NEGX */
-{ CPUFUNC(op_4050_4), 0, 16464 }, /* NEGX */
-{ CPUFUNC(op_4058_4), 0, 16472 }, /* NEGX */
-{ CPUFUNC(op_4060_4), 0, 16480 }, /* NEGX */
-{ CPUFUNC(op_4068_4), 0, 16488 }, /* NEGX */
-{ CPUFUNC(op_4070_4), 0, 16496 }, /* NEGX */
-{ CPUFUNC(op_4078_4), 0, 16504 }, /* NEGX */
-{ CPUFUNC(op_4079_4), 0, 16505 }, /* NEGX */
-{ CPUFUNC(op_4080_4), 0, 16512 }, /* NEGX */
-{ CPUFUNC(op_4090_4), 0, 16528 }, /* NEGX */
-{ CPUFUNC(op_4098_4), 0, 16536 }, /* NEGX */
-{ CPUFUNC(op_40a0_4), 0, 16544 }, /* NEGX */
-{ CPUFUNC(op_40a8_4), 0, 16552 }, /* NEGX */
-{ CPUFUNC(op_40b0_4), 0, 16560 }, /* NEGX */
-{ CPUFUNC(op_40b8_4), 0, 16568 }, /* NEGX */
-{ CPUFUNC(op_40b9_4), 0, 16569 }, /* NEGX */
-{ CPUFUNC(op_40c0_4), 0, 16576 }, /* MVSR2 */
-{ CPUFUNC(op_40d0_4), 0, 16592 }, /* MVSR2 */
-{ CPUFUNC(op_40d8_4), 0, 16600 }, /* MVSR2 */
-{ CPUFUNC(op_40e0_4), 0, 16608 }, /* MVSR2 */
-{ CPUFUNC(op_40e8_4), 0, 16616 }, /* MVSR2 */
-{ CPUFUNC(op_40f0_4), 0, 16624 }, /* MVSR2 */
-{ CPUFUNC(op_40f8_4), 0, 16632 }, /* MVSR2 */
-{ CPUFUNC(op_40f9_4), 0, 16633 }, /* MVSR2 */
-{ CPUFUNC(op_4180_4), 0, 16768 }, /* CHK */
-{ CPUFUNC(op_4190_4), 0, 16784 }, /* CHK */
-{ CPUFUNC(op_4198_4), 0, 16792 }, /* CHK */
-{ CPUFUNC(op_41a0_4), 0, 16800 }, /* CHK */
-{ CPUFUNC(op_41a8_4), 0, 16808 }, /* CHK */
-{ CPUFUNC(op_41b0_4), 0, 16816 }, /* CHK */
-{ CPUFUNC(op_41b8_4), 0, 16824 }, /* CHK */
-{ CPUFUNC(op_41b9_4), 0, 16825 }, /* CHK */
-{ CPUFUNC(op_41ba_4), 0, 16826 }, /* CHK */
-{ CPUFUNC(op_41bb_4), 0, 16827 }, /* CHK */
-{ CPUFUNC(op_41bc_4), 0, 16828 }, /* CHK */
-{ CPUFUNC(op_41d0_4), 0, 16848 }, /* LEA */
-{ CPUFUNC(op_41e8_4), 0, 16872 }, /* LEA */
-{ CPUFUNC(op_41f0_4), 0, 16880 }, /* LEA */
-{ CPUFUNC(op_41f8_4), 0, 16888 }, /* LEA */
-{ CPUFUNC(op_41f9_4), 0, 16889 }, /* LEA */
-{ CPUFUNC(op_41fa_4), 0, 16890 }, /* LEA */
-{ CPUFUNC(op_41fb_4), 0, 16891 }, /* LEA */
-{ CPUFUNC(op_4200_4), 0, 16896 }, /* CLR */
-{ CPUFUNC(op_4210_4), 0, 16912 }, /* CLR */
-{ CPUFUNC(op_4218_4), 0, 16920 }, /* CLR */
-{ CPUFUNC(op_4220_4), 0, 16928 }, /* CLR */
-{ CPUFUNC(op_4228_4), 0, 16936 }, /* CLR */
-{ CPUFUNC(op_4230_4), 0, 16944 }, /* CLR */
-{ CPUFUNC(op_4238_4), 0, 16952 }, /* CLR */
-{ CPUFUNC(op_4239_4), 0, 16953 }, /* CLR */
-{ CPUFUNC(op_4240_4), 0, 16960 }, /* CLR */
-{ CPUFUNC(op_4250_4), 0, 16976 }, /* CLR */
-{ CPUFUNC(op_4258_4), 0, 16984 }, /* CLR */
-{ CPUFUNC(op_4260_4), 0, 16992 }, /* CLR */
-{ CPUFUNC(op_4268_4), 0, 17000 }, /* CLR */
-{ CPUFUNC(op_4270_4), 0, 17008 }, /* CLR */
-{ CPUFUNC(op_4278_4), 0, 17016 }, /* CLR */
-{ CPUFUNC(op_4279_4), 0, 17017 }, /* CLR */
-{ CPUFUNC(op_4280_4), 0, 17024 }, /* CLR */
-{ CPUFUNC(op_4290_4), 0, 17040 }, /* CLR */
-{ CPUFUNC(op_4298_4), 0, 17048 }, /* CLR */
-{ CPUFUNC(op_42a0_4), 0, 17056 }, /* CLR */
-{ CPUFUNC(op_42a8_4), 0, 17064 }, /* CLR */
-{ CPUFUNC(op_42b0_4), 0, 17072 }, /* CLR */
-{ CPUFUNC(op_42b8_4), 0, 17080 }, /* CLR */
-{ CPUFUNC(op_42b9_4), 0, 17081 }, /* CLR */
-{ CPUFUNC(op_4400_4), 0, 17408 }, /* NEG */
-{ CPUFUNC(op_4410_4), 0, 17424 }, /* NEG */
-{ CPUFUNC(op_4418_4), 0, 17432 }, /* NEG */
-{ CPUFUNC(op_4420_4), 0, 17440 }, /* NEG */
-{ CPUFUNC(op_4428_4), 0, 17448 }, /* NEG */
-{ CPUFUNC(op_4430_4), 0, 17456 }, /* NEG */
-{ CPUFUNC(op_4438_4), 0, 17464 }, /* NEG */
-{ CPUFUNC(op_4439_4), 0, 17465 }, /* NEG */
-{ CPUFUNC(op_4440_4), 0, 17472 }, /* NEG */
-{ CPUFUNC(op_4450_4), 0, 17488 }, /* NEG */
-{ CPUFUNC(op_4458_4), 0, 17496 }, /* NEG */
-{ CPUFUNC(op_4460_4), 0, 17504 }, /* NEG */
-{ CPUFUNC(op_4468_4), 0, 17512 }, /* NEG */
-{ CPUFUNC(op_4470_4), 0, 17520 }, /* NEG */
-{ CPUFUNC(op_4478_4), 0, 17528 }, /* NEG */
-{ CPUFUNC(op_4479_4), 0, 17529 }, /* NEG */
-{ CPUFUNC(op_4480_4), 0, 17536 }, /* NEG */
-{ CPUFUNC(op_4490_4), 0, 17552 }, /* NEG */
-{ CPUFUNC(op_4498_4), 0, 17560 }, /* NEG */
-{ CPUFUNC(op_44a0_4), 0, 17568 }, /* NEG */
-{ CPUFUNC(op_44a8_4), 0, 17576 }, /* NEG */
-{ CPUFUNC(op_44b0_4), 0, 17584 }, /* NEG */
-{ CPUFUNC(op_44b8_4), 0, 17592 }, /* NEG */
-{ CPUFUNC(op_44b9_4), 0, 17593 }, /* NEG */
-{ CPUFUNC(op_44c0_4), 0, 17600 }, /* MV2SR */
-{ CPUFUNC(op_44d0_4), 0, 17616 }, /* MV2SR */
-{ CPUFUNC(op_44d8_4), 0, 17624 }, /* MV2SR */
-{ CPUFUNC(op_44e0_4), 0, 17632 }, /* MV2SR */
-{ CPUFUNC(op_44e8_4), 0, 17640 }, /* MV2SR */
-{ CPUFUNC(op_44f0_4), 0, 17648 }, /* MV2SR */
-{ CPUFUNC(op_44f8_4), 0, 17656 }, /* MV2SR */
-{ CPUFUNC(op_44f9_4), 0, 17657 }, /* MV2SR */
-{ CPUFUNC(op_44fa_4), 0, 17658 }, /* MV2SR */
-{ CPUFUNC(op_44fb_4), 0, 17659 }, /* MV2SR */
-{ CPUFUNC(op_44fc_4), 0, 17660 }, /* MV2SR */
-{ CPUFUNC(op_4600_4), 0, 17920 }, /* NOT */
-{ CPUFUNC(op_4610_4), 0, 17936 }, /* NOT */
-{ CPUFUNC(op_4618_4), 0, 17944 }, /* NOT */
-{ CPUFUNC(op_4620_4), 0, 17952 }, /* NOT */
-{ CPUFUNC(op_4628_4), 0, 17960 }, /* NOT */
-{ CPUFUNC(op_4630_4), 0, 17968 }, /* NOT */
-{ CPUFUNC(op_4638_4), 0, 17976 }, /* NOT */
-{ CPUFUNC(op_4639_4), 0, 17977 }, /* NOT */
-{ CPUFUNC(op_4640_4), 0, 17984 }, /* NOT */
-{ CPUFUNC(op_4650_4), 0, 18000 }, /* NOT */
-{ CPUFUNC(op_4658_4), 0, 18008 }, /* NOT */
-{ CPUFUNC(op_4660_4), 0, 18016 }, /* NOT */
-{ CPUFUNC(op_4668_4), 0, 18024 }, /* NOT */
-{ CPUFUNC(op_4670_4), 0, 18032 }, /* NOT */
-{ CPUFUNC(op_4678_4), 0, 18040 }, /* NOT */
-{ CPUFUNC(op_4679_4), 0, 18041 }, /* NOT */
-{ CPUFUNC(op_4680_4), 0, 18048 }, /* NOT */
-{ CPUFUNC(op_4690_4), 0, 18064 }, /* NOT */
-{ CPUFUNC(op_4698_4), 0, 18072 }, /* NOT */
-{ CPUFUNC(op_46a0_4), 0, 18080 }, /* NOT */
-{ CPUFUNC(op_46a8_4), 0, 18088 }, /* NOT */
-{ CPUFUNC(op_46b0_4), 0, 18096 }, /* NOT */
-{ CPUFUNC(op_46b8_4), 0, 18104 }, /* NOT */
-{ CPUFUNC(op_46b9_4), 0, 18105 }, /* NOT */
-{ CPUFUNC(op_46c0_4), 0, 18112 }, /* MV2SR */
-{ CPUFUNC(op_46d0_4), 0, 18128 }, /* MV2SR */
-{ CPUFUNC(op_46d8_4), 0, 18136 }, /* MV2SR */
-{ CPUFUNC(op_46e0_4), 0, 18144 }, /* MV2SR */
-{ CPUFUNC(op_46e8_4), 0, 18152 }, /* MV2SR */
-{ CPUFUNC(op_46f0_4), 0, 18160 }, /* MV2SR */
-{ CPUFUNC(op_46f8_4), 0, 18168 }, /* MV2SR */
-{ CPUFUNC(op_46f9_4), 0, 18169 }, /* MV2SR */
-{ CPUFUNC(op_46fa_4), 0, 18170 }, /* MV2SR */
-{ CPUFUNC(op_46fb_4), 0, 18171 }, /* MV2SR */
-{ CPUFUNC(op_46fc_4), 0, 18172 }, /* MV2SR */
-{ CPUFUNC(op_4800_4), 0, 18432 }, /* NBCD */
-{ CPUFUNC(op_4810_4), 0, 18448 }, /* NBCD */
-{ CPUFUNC(op_4818_4), 0, 18456 }, /* NBCD */
-{ CPUFUNC(op_4820_4), 0, 18464 }, /* NBCD */
-{ CPUFUNC(op_4828_4), 0, 18472 }, /* NBCD */
-{ CPUFUNC(op_4830_4), 0, 18480 }, /* NBCD */
-{ CPUFUNC(op_4838_4), 0, 18488 }, /* NBCD */
-{ CPUFUNC(op_4839_4), 0, 18489 }, /* NBCD */
-{ CPUFUNC(op_4840_4), 0, 18496 }, /* SWAP */
-{ CPUFUNC(op_4850_4), 0, 18512 }, /* PEA */
-{ CPUFUNC(op_4868_4), 0, 18536 }, /* PEA */
-{ CPUFUNC(op_4870_4), 0, 18544 }, /* PEA */
-{ CPUFUNC(op_4878_4), 0, 18552 }, /* PEA */
-{ CPUFUNC(op_4879_4), 0, 18553 }, /* PEA */
-{ CPUFUNC(op_487a_4), 0, 18554 }, /* PEA */
-{ CPUFUNC(op_487b_4), 0, 18555 }, /* PEA */
-{ CPUFUNC(op_4880_4), 0, 18560 }, /* EXT */
-{ CPUFUNC(op_4890_4), 0, 18576 }, /* MVMLE */
-{ CPUFUNC(op_48a0_4), 0, 18592 }, /* MVMLE */
-{ CPUFUNC(op_48a8_4), 0, 18600 }, /* MVMLE */
-{ CPUFUNC(op_48b0_4), 0, 18608 }, /* MVMLE */
-{ CPUFUNC(op_48b8_4), 0, 18616 }, /* MVMLE */
-{ CPUFUNC(op_48b9_4), 0, 18617 }, /* MVMLE */
-{ CPUFUNC(op_48c0_4), 0, 18624 }, /* EXT */
-{ CPUFUNC(op_48d0_4), 0, 18640 }, /* MVMLE */
-{ CPUFUNC(op_48e0_4), 0, 18656 }, /* MVMLE */
-{ CPUFUNC(op_48e8_4), 0, 18664 }, /* MVMLE */
-{ CPUFUNC(op_48f0_4), 0, 18672 }, /* MVMLE */
-{ CPUFUNC(op_48f8_4), 0, 18680 }, /* MVMLE */
-{ CPUFUNC(op_48f9_4), 0, 18681 }, /* MVMLE */
-{ CPUFUNC(op_4a00_4), 0, 18944 }, /* TST */
-{ CPUFUNC(op_4a10_4), 0, 18960 }, /* TST */
-{ CPUFUNC(op_4a18_4), 0, 18968 }, /* TST */
-{ CPUFUNC(op_4a20_4), 0, 18976 }, /* TST */
-{ CPUFUNC(op_4a28_4), 0, 18984 }, /* TST */
-{ CPUFUNC(op_4a30_4), 0, 18992 }, /* TST */
-{ CPUFUNC(op_4a38_4), 0, 19000 }, /* TST */
-{ CPUFUNC(op_4a39_4), 0, 19001 }, /* TST */
-{ CPUFUNC(op_4a3a_4), 0, 19002 }, /* TST */
-{ CPUFUNC(op_4a3b_4), 0, 19003 }, /* TST */
-{ CPUFUNC(op_4a3c_4), 0, 19004 }, /* TST */
-{ CPUFUNC(op_4a40_4), 0, 19008 }, /* TST */
-{ CPUFUNC(op_4a48_4), 0, 19016 }, /* TST */
-{ CPUFUNC(op_4a50_4), 0, 19024 }, /* TST */
-{ CPUFUNC(op_4a58_4), 0, 19032 }, /* TST */
-{ CPUFUNC(op_4a60_4), 0, 19040 }, /* TST */
-{ CPUFUNC(op_4a68_4), 0, 19048 }, /* TST */
-{ CPUFUNC(op_4a70_4), 0, 19056 }, /* TST */
-{ CPUFUNC(op_4a78_4), 0, 19064 }, /* TST */
-{ CPUFUNC(op_4a79_4), 0, 19065 }, /* TST */
-{ CPUFUNC(op_4a7a_4), 0, 19066 }, /* TST */
-{ CPUFUNC(op_4a7b_4), 0, 19067 }, /* TST */
-{ CPUFUNC(op_4a7c_4), 0, 19068 }, /* TST */
-{ CPUFUNC(op_4a80_4), 0, 19072 }, /* TST */
-{ CPUFUNC(op_4a88_4), 0, 19080 }, /* TST */
-{ CPUFUNC(op_4a90_4), 0, 19088 }, /* TST */
-{ CPUFUNC(op_4a98_4), 0, 19096 }, /* TST */
-{ CPUFUNC(op_4aa0_4), 0, 19104 }, /* TST */
-{ CPUFUNC(op_4aa8_4), 0, 19112 }, /* TST */
-{ CPUFUNC(op_4ab0_4), 0, 19120 }, /* TST */
-{ CPUFUNC(op_4ab8_4), 0, 19128 }, /* TST */
-{ CPUFUNC(op_4ab9_4), 0, 19129 }, /* TST */
-{ CPUFUNC(op_4aba_4), 0, 19130 }, /* TST */
-{ CPUFUNC(op_4abb_4), 0, 19131 }, /* TST */
-{ CPUFUNC(op_4abc_4), 0, 19132 }, /* TST */
-{ CPUFUNC(op_4ac0_4), 0, 19136 }, /* TAS */
-{ CPUFUNC(op_4ad0_4), 0, 19152 }, /* TAS */
-{ CPUFUNC(op_4ad8_4), 0, 19160 }, /* TAS */
-{ CPUFUNC(op_4ae0_4), 0, 19168 }, /* TAS */
-{ CPUFUNC(op_4ae8_4), 0, 19176 }, /* TAS */
-{ CPUFUNC(op_4af0_4), 0, 19184 }, /* TAS */
-{ CPUFUNC(op_4af8_4), 0, 19192 }, /* TAS */
-{ CPUFUNC(op_4af9_4), 0, 19193 }, /* TAS */
-{ CPUFUNC(op_4c90_4), 0, 19600 }, /* MVMEL */
-{ CPUFUNC(op_4c98_4), 0, 19608 }, /* MVMEL */
-{ CPUFUNC(op_4ca8_4), 0, 19624 }, /* MVMEL */
-{ CPUFUNC(op_4cb0_4), 0, 19632 }, /* MVMEL */
-{ CPUFUNC(op_4cb8_4), 0, 19640 }, /* MVMEL */
-{ CPUFUNC(op_4cb9_4), 0, 19641 }, /* MVMEL */
-{ CPUFUNC(op_4cba_4), 0, 19642 }, /* MVMEL */
-{ CPUFUNC(op_4cbb_4), 0, 19643 }, /* MVMEL */
-{ CPUFUNC(op_4cd0_4), 0, 19664 }, /* MVMEL */
-{ CPUFUNC(op_4cd8_4), 0, 19672 }, /* MVMEL */
-{ CPUFUNC(op_4ce8_4), 0, 19688 }, /* MVMEL */
-{ CPUFUNC(op_4cf0_4), 0, 19696 }, /* MVMEL */
-{ CPUFUNC(op_4cf8_4), 0, 19704 }, /* MVMEL */
-{ CPUFUNC(op_4cf9_4), 0, 19705 }, /* MVMEL */
-{ CPUFUNC(op_4cfa_4), 0, 19706 }, /* MVMEL */
-{ CPUFUNC(op_4cfb_4), 0, 19707 }, /* MVMEL */
-{ CPUFUNC(op_4e40_4), 0, 20032 }, /* TRAP */
-{ CPUFUNC(op_4e50_4), 0, 20048 }, /* LINK */
-{ CPUFUNC(op_4e58_4), 0, 20056 }, /* UNLK */
-{ CPUFUNC(op_4e60_4), 0, 20064 }, /* MVR2USP */
-{ CPUFUNC(op_4e68_4), 0, 20072 }, /* MVUSP2R */
-{ CPUFUNC(op_4e70_4), 0, 20080 }, /* RESET */
-{ CPUFUNC(op_4e71_4), 0, 20081 }, /* NOP */
-{ CPUFUNC(op_4e72_4), 0, 20082 }, /* STOP */
-{ CPUFUNC(op_4e73_4), 0, 20083 }, /* RTE */
-{ CPUFUNC(op_4e74_4), 0, 20084 }, /* RTD */
-{ CPUFUNC(op_4e75_4), 0, 20085 }, /* RTS */
-{ CPUFUNC(op_4e76_4), 0, 20086 }, /* TRAPV */
-{ CPUFUNC(op_4e77_4), 0, 20087 }, /* RTR */
-{ CPUFUNC(op_4e90_4), 0, 20112 }, /* JSR */
-{ CPUFUNC(op_4ea8_4), 0, 20136 }, /* JSR */
-{ CPUFUNC(op_4eb0_4), 0, 20144 }, /* JSR */
-{ CPUFUNC(op_4eb8_4), 0, 20152 }, /* JSR */
-{ CPUFUNC(op_4eb9_4), 0, 20153 }, /* JSR */
-{ CPUFUNC(op_4eba_4), 0, 20154 }, /* JSR */
-{ CPUFUNC(op_4ebb_4), 0, 20155 }, /* JSR */
-{ CPUFUNC(op_4ed0_4), 0, 20176 }, /* JMP */
-{ CPUFUNC(op_4ee8_4), 0, 20200 }, /* JMP */
-{ CPUFUNC(op_4ef0_4), 0, 20208 }, /* JMP */
-{ CPUFUNC(op_4ef8_4), 0, 20216 }, /* JMP */
-{ CPUFUNC(op_4ef9_4), 0, 20217 }, /* JMP */
-{ CPUFUNC(op_4efa_4), 0, 20218 }, /* JMP */
-{ CPUFUNC(op_4efb_4), 0, 20219 }, /* JMP */
-{ CPUFUNC(op_5000_4), 0, 20480 }, /* ADD */
-{ CPUFUNC(op_5010_4), 0, 20496 }, /* ADD */
-{ CPUFUNC(op_5018_4), 0, 20504 }, /* ADD */
-{ CPUFUNC(op_5020_4), 0, 20512 }, /* ADD */
-{ CPUFUNC(op_5028_4), 0, 20520 }, /* ADD */
-{ CPUFUNC(op_5030_4), 0, 20528 }, /* ADD */
-{ CPUFUNC(op_5038_4), 0, 20536 }, /* ADD */
-{ CPUFUNC(op_5039_4), 0, 20537 }, /* ADD */
-{ CPUFUNC(op_5040_4), 0, 20544 }, /* ADD */
-{ CPUFUNC(op_5048_4), 0, 20552 }, /* ADDA */
-{ CPUFUNC(op_5050_4), 0, 20560 }, /* ADD */
-{ CPUFUNC(op_5058_4), 0, 20568 }, /* ADD */
-{ CPUFUNC(op_5060_4), 0, 20576 }, /* ADD */
-{ CPUFUNC(op_5068_4), 0, 20584 }, /* ADD */
-{ CPUFUNC(op_5070_4), 0, 20592 }, /* ADD */
-{ CPUFUNC(op_5078_4), 0, 20600 }, /* ADD */
-{ CPUFUNC(op_5079_4), 0, 20601 }, /* ADD */
-{ CPUFUNC(op_5080_4), 0, 20608 }, /* ADD */
-{ CPUFUNC(op_5088_4), 0, 20616 }, /* ADDA */
-{ CPUFUNC(op_5090_4), 0, 20624 }, /* ADD */
-{ CPUFUNC(op_5098_4), 0, 20632 }, /* ADD */
-{ CPUFUNC(op_50a0_4), 0, 20640 }, /* ADD */
-{ CPUFUNC(op_50a8_4), 0, 20648 }, /* ADD */
-{ CPUFUNC(op_50b0_4), 0, 20656 }, /* ADD */
-{ CPUFUNC(op_50b8_4), 0, 20664 }, /* ADD */
-{ CPUFUNC(op_50b9_4), 0, 20665 }, /* ADD */
-{ CPUFUNC(op_50c0_4), 0, 20672 }, /* Scc */
-{ CPUFUNC(op_50c8_4), 0, 20680 }, /* DBcc */
-{ CPUFUNC(op_50d0_4), 0, 20688 }, /* Scc */
-{ CPUFUNC(op_50d8_4), 0, 20696 }, /* Scc */
-{ CPUFUNC(op_50e0_4), 0, 20704 }, /* Scc */
-{ CPUFUNC(op_50e8_4), 0, 20712 }, /* Scc */
-{ CPUFUNC(op_50f0_4), 0, 20720 }, /* Scc */
-{ CPUFUNC(op_50f8_4), 0, 20728 }, /* Scc */
-{ CPUFUNC(op_50f9_4), 0, 20729 }, /* Scc */
-{ CPUFUNC(op_5100_4), 0, 20736 }, /* SUB */
-{ CPUFUNC(op_5110_4), 0, 20752 }, /* SUB */
-{ CPUFUNC(op_5118_4), 0, 20760 }, /* SUB */
-{ CPUFUNC(op_5120_4), 0, 20768 }, /* SUB */
-{ CPUFUNC(op_5128_4), 0, 20776 }, /* SUB */
-{ CPUFUNC(op_5130_4), 0, 20784 }, /* SUB */
-{ CPUFUNC(op_5138_4), 0, 20792 }, /* SUB */
-{ CPUFUNC(op_5139_4), 0, 20793 }, /* SUB */
-{ CPUFUNC(op_5140_4), 0, 20800 }, /* SUB */
-{ CPUFUNC(op_5148_4), 0, 20808 }, /* SUBA */
-{ CPUFUNC(op_5150_4), 0, 20816 }, /* SUB */
-{ CPUFUNC(op_5158_4), 0, 20824 }, /* SUB */
-{ CPUFUNC(op_5160_4), 0, 20832 }, /* SUB */
-{ CPUFUNC(op_5168_4), 0, 20840 }, /* SUB */
-{ CPUFUNC(op_5170_4), 0, 20848 }, /* SUB */
-{ CPUFUNC(op_5178_4), 0, 20856 }, /* SUB */
-{ CPUFUNC(op_5179_4), 0, 20857 }, /* SUB */
-{ CPUFUNC(op_5180_4), 0, 20864 }, /* SUB */
-{ CPUFUNC(op_5188_4), 0, 20872 }, /* SUBA */
-{ CPUFUNC(op_5190_4), 0, 20880 }, /* SUB */
-{ CPUFUNC(op_5198_4), 0, 20888 }, /* SUB */
-{ CPUFUNC(op_51a0_4), 0, 20896 }, /* SUB */
-{ CPUFUNC(op_51a8_4), 0, 20904 }, /* SUB */
-{ CPUFUNC(op_51b0_4), 0, 20912 }, /* SUB */
-{ CPUFUNC(op_51b8_4), 0, 20920 }, /* SUB */
-{ CPUFUNC(op_51b9_4), 0, 20921 }, /* SUB */
-{ CPUFUNC(op_51c0_4), 0, 20928 }, /* Scc */
-{ CPUFUNC(op_51c8_4), 0, 20936 }, /* DBcc */
-{ CPUFUNC(op_51d0_4), 0, 20944 }, /* Scc */
-{ CPUFUNC(op_51d8_4), 0, 20952 }, /* Scc */
-{ CPUFUNC(op_51e0_4), 0, 20960 }, /* Scc */
-{ CPUFUNC(op_51e8_4), 0, 20968 }, /* Scc */
-{ CPUFUNC(op_51f0_4), 0, 20976 }, /* Scc */
-{ CPUFUNC(op_51f8_4), 0, 20984 }, /* Scc */
-{ CPUFUNC(op_51f9_4), 0, 20985 }, /* Scc */
-{ CPUFUNC(op_52c0_4), 0, 21184 }, /* Scc */
-{ CPUFUNC(op_52c8_4), 0, 21192 }, /* DBcc */
-{ CPUFUNC(op_52d0_4), 0, 21200 }, /* Scc */
-{ CPUFUNC(op_52d8_4), 0, 21208 }, /* Scc */
-{ CPUFUNC(op_52e0_4), 0, 21216 }, /* Scc */
-{ CPUFUNC(op_52e8_4), 0, 21224 }, /* Scc */
-{ CPUFUNC(op_52f0_4), 0, 21232 }, /* Scc */
-{ CPUFUNC(op_52f8_4), 0, 21240 }, /* Scc */
-{ CPUFUNC(op_52f9_4), 0, 21241 }, /* Scc */
-{ CPUFUNC(op_53c0_4), 0, 21440 }, /* Scc */
-{ CPUFUNC(op_53c8_4), 0, 21448 }, /* DBcc */
-{ CPUFUNC(op_53d0_4), 0, 21456 }, /* Scc */
-{ CPUFUNC(op_53d8_4), 0, 21464 }, /* Scc */
-{ CPUFUNC(op_53e0_4), 0, 21472 }, /* Scc */
-{ CPUFUNC(op_53e8_4), 0, 21480 }, /* Scc */
-{ CPUFUNC(op_53f0_4), 0, 21488 }, /* Scc */
-{ CPUFUNC(op_53f8_4), 0, 21496 }, /* Scc */
-{ CPUFUNC(op_53f9_4), 0, 21497 }, /* Scc */
-{ CPUFUNC(op_54c0_4), 0, 21696 }, /* Scc */
-{ CPUFUNC(op_54c8_4), 0, 21704 }, /* DBcc */
-{ CPUFUNC(op_54d0_4), 0, 21712 }, /* Scc */
-{ CPUFUNC(op_54d8_4), 0, 21720 }, /* Scc */
-{ CPUFUNC(op_54e0_4), 0, 21728 }, /* Scc */
-{ CPUFUNC(op_54e8_4), 0, 21736 }, /* Scc */
-{ CPUFUNC(op_54f0_4), 0, 21744 }, /* Scc */
-{ CPUFUNC(op_54f8_4), 0, 21752 }, /* Scc */
-{ CPUFUNC(op_54f9_4), 0, 21753 }, /* Scc */
-{ CPUFUNC(op_55c0_4), 0, 21952 }, /* Scc */
-{ CPUFUNC(op_55c8_4), 0, 21960 }, /* DBcc */
-{ CPUFUNC(op_55d0_4), 0, 21968 }, /* Scc */
-{ CPUFUNC(op_55d8_4), 0, 21976 }, /* Scc */
-{ CPUFUNC(op_55e0_4), 0, 21984 }, /* Scc */
-{ CPUFUNC(op_55e8_4), 0, 21992 }, /* Scc */
-{ CPUFUNC(op_55f0_4), 0, 22000 }, /* Scc */
-{ CPUFUNC(op_55f8_4), 0, 22008 }, /* Scc */
-{ CPUFUNC(op_55f9_4), 0, 22009 }, /* Scc */
-{ CPUFUNC(op_56c0_4), 0, 22208 }, /* Scc */
-{ CPUFUNC(op_56c8_4), 0, 22216 }, /* DBcc */
-{ CPUFUNC(op_56d0_4), 0, 22224 }, /* Scc */
-{ CPUFUNC(op_56d8_4), 0, 22232 }, /* Scc */
-{ CPUFUNC(op_56e0_4), 0, 22240 }, /* Scc */
-{ CPUFUNC(op_56e8_4), 0, 22248 }, /* Scc */
-{ CPUFUNC(op_56f0_4), 0, 22256 }, /* Scc */
-{ CPUFUNC(op_56f8_4), 0, 22264 }, /* Scc */
-{ CPUFUNC(op_56f9_4), 0, 22265 }, /* Scc */
-{ CPUFUNC(op_57c0_4), 0, 22464 }, /* Scc */
-{ CPUFUNC(op_57c8_4), 0, 22472 }, /* DBcc */
-{ CPUFUNC(op_57d0_4), 0, 22480 }, /* Scc */
-{ CPUFUNC(op_57d8_4), 0, 22488 }, /* Scc */
-{ CPUFUNC(op_57e0_4), 0, 22496 }, /* Scc */
-{ CPUFUNC(op_57e8_4), 0, 22504 }, /* Scc */
-{ CPUFUNC(op_57f0_4), 0, 22512 }, /* Scc */
-{ CPUFUNC(op_57f8_4), 0, 22520 }, /* Scc */
-{ CPUFUNC(op_57f9_4), 0, 22521 }, /* Scc */
-{ CPUFUNC(op_58c0_4), 0, 22720 }, /* Scc */
-{ CPUFUNC(op_58c8_4), 0, 22728 }, /* DBcc */
-{ CPUFUNC(op_58d0_4), 0, 22736 }, /* Scc */
-{ CPUFUNC(op_58d8_4), 0, 22744 }, /* Scc */
-{ CPUFUNC(op_58e0_4), 0, 22752 }, /* Scc */
-{ CPUFUNC(op_58e8_4), 0, 22760 }, /* Scc */
-{ CPUFUNC(op_58f0_4), 0, 22768 }, /* Scc */
-{ CPUFUNC(op_58f8_4), 0, 22776 }, /* Scc */
-{ CPUFUNC(op_58f9_4), 0, 22777 }, /* Scc */
-{ CPUFUNC(op_59c0_4), 0, 22976 }, /* Scc */
-{ CPUFUNC(op_59c8_4), 0, 22984 }, /* DBcc */
-{ CPUFUNC(op_59d0_4), 0, 22992 }, /* Scc */
-{ CPUFUNC(op_59d8_4), 0, 23000 }, /* Scc */
-{ CPUFUNC(op_59e0_4), 0, 23008 }, /* Scc */
-{ CPUFUNC(op_59e8_4), 0, 23016 }, /* Scc */
-{ CPUFUNC(op_59f0_4), 0, 23024 }, /* Scc */
-{ CPUFUNC(op_59f8_4), 0, 23032 }, /* Scc */
-{ CPUFUNC(op_59f9_4), 0, 23033 }, /* Scc */
-{ CPUFUNC(op_5ac0_4), 0, 23232 }, /* Scc */
-{ CPUFUNC(op_5ac8_4), 0, 23240 }, /* DBcc */
-{ CPUFUNC(op_5ad0_4), 0, 23248 }, /* Scc */
-{ CPUFUNC(op_5ad8_4), 0, 23256 }, /* Scc */
-{ CPUFUNC(op_5ae0_4), 0, 23264 }, /* Scc */
-{ CPUFUNC(op_5ae8_4), 0, 23272 }, /* Scc */
-{ CPUFUNC(op_5af0_4), 0, 23280 }, /* Scc */
-{ CPUFUNC(op_5af8_4), 0, 23288 }, /* Scc */
-{ CPUFUNC(op_5af9_4), 0, 23289 }, /* Scc */
-{ CPUFUNC(op_5bc0_4), 0, 23488 }, /* Scc */
-{ CPUFUNC(op_5bc8_4), 0, 23496 }, /* DBcc */
-{ CPUFUNC(op_5bd0_4), 0, 23504 }, /* Scc */
-{ CPUFUNC(op_5bd8_4), 0, 23512 }, /* Scc */
-{ CPUFUNC(op_5be0_4), 0, 23520 }, /* Scc */
-{ CPUFUNC(op_5be8_4), 0, 23528 }, /* Scc */
-{ CPUFUNC(op_5bf0_4), 0, 23536 }, /* Scc */
-{ CPUFUNC(op_5bf8_4), 0, 23544 }, /* Scc */
-{ CPUFUNC(op_5bf9_4), 0, 23545 }, /* Scc */
-{ CPUFUNC(op_5cc0_4), 0, 23744 }, /* Scc */
-{ CPUFUNC(op_5cc8_4), 0, 23752 }, /* DBcc */
-{ CPUFUNC(op_5cd0_4), 0, 23760 }, /* Scc */
-{ CPUFUNC(op_5cd8_4), 0, 23768 }, /* Scc */
-{ CPUFUNC(op_5ce0_4), 0, 23776 }, /* Scc */
-{ CPUFUNC(op_5ce8_4), 0, 23784 }, /* Scc */
-{ CPUFUNC(op_5cf0_4), 0, 23792 }, /* Scc */
-{ CPUFUNC(op_5cf8_4), 0, 23800 }, /* Scc */
-{ CPUFUNC(op_5cf9_4), 0, 23801 }, /* Scc */
-{ CPUFUNC(op_5dc0_4), 0, 24000 }, /* Scc */
-{ CPUFUNC(op_5dc8_4), 0, 24008 }, /* DBcc */
-{ CPUFUNC(op_5dd0_4), 0, 24016 }, /* Scc */
-{ CPUFUNC(op_5dd8_4), 0, 24024 }, /* Scc */
-{ CPUFUNC(op_5de0_4), 0, 24032 }, /* Scc */
-{ CPUFUNC(op_5de8_4), 0, 24040 }, /* Scc */
-{ CPUFUNC(op_5df0_4), 0, 24048 }, /* Scc */
-{ CPUFUNC(op_5df8_4), 0, 24056 }, /* Scc */
-{ CPUFUNC(op_5df9_4), 0, 24057 }, /* Scc */
-{ CPUFUNC(op_5ec0_4), 0, 24256 }, /* Scc */
-{ CPUFUNC(op_5ec8_4), 0, 24264 }, /* DBcc */
-{ CPUFUNC(op_5ed0_4), 0, 24272 }, /* Scc */
-{ CPUFUNC(op_5ed8_4), 0, 24280 }, /* Scc */
-{ CPUFUNC(op_5ee0_4), 0, 24288 }, /* Scc */
-{ CPUFUNC(op_5ee8_4), 0, 24296 }, /* Scc */
-{ CPUFUNC(op_5ef0_4), 0, 24304 }, /* Scc */
-{ CPUFUNC(op_5ef8_4), 0, 24312 }, /* Scc */
-{ CPUFUNC(op_5ef9_4), 0, 24313 }, /* Scc */
-{ CPUFUNC(op_5fc0_4), 0, 24512 }, /* Scc */
-{ CPUFUNC(op_5fc8_4), 0, 24520 }, /* DBcc */
-{ CPUFUNC(op_5fd0_4), 0, 24528 }, /* Scc */
-{ CPUFUNC(op_5fd8_4), 0, 24536 }, /* Scc */
-{ CPUFUNC(op_5fe0_4), 0, 24544 }, /* Scc */
-{ CPUFUNC(op_5fe8_4), 0, 24552 }, /* Scc */
-{ CPUFUNC(op_5ff0_4), 0, 24560 }, /* Scc */
-{ CPUFUNC(op_5ff8_4), 0, 24568 }, /* Scc */
-{ CPUFUNC(op_5ff9_4), 0, 24569 }, /* Scc */
-{ CPUFUNC(op_6000_4), 0, 24576 }, /* Bcc */
-{ CPUFUNC(op_6001_4), 0, 24577 }, /* Bcc */
-{ CPUFUNC(op_60ff_4), 0, 24831 }, /* Bcc */
-{ CPUFUNC(op_6100_4), 0, 24832 }, /* BSR */
-{ CPUFUNC(op_6101_4), 0, 24833 }, /* BSR */
-{ CPUFUNC(op_61ff_4), 0, 25087 }, /* BSR */
-{ CPUFUNC(op_6200_4), 0, 25088 }, /* Bcc */
-{ CPUFUNC(op_6201_4), 0, 25089 }, /* Bcc */
-{ CPUFUNC(op_62ff_4), 0, 25343 }, /* Bcc */
-{ CPUFUNC(op_6300_4), 0, 25344 }, /* Bcc */
-{ CPUFUNC(op_6301_4), 0, 25345 }, /* Bcc */
-{ CPUFUNC(op_63ff_4), 0, 25599 }, /* Bcc */
-{ CPUFUNC(op_6400_4), 0, 25600 }, /* Bcc */
-{ CPUFUNC(op_6401_4), 0, 25601 }, /* Bcc */
-{ CPUFUNC(op_64ff_4), 0, 25855 }, /* Bcc */
-{ CPUFUNC(op_6500_4), 0, 25856 }, /* Bcc */
-{ CPUFUNC(op_6501_4), 0, 25857 }, /* Bcc */
-{ CPUFUNC(op_65ff_4), 0, 26111 }, /* Bcc */
-{ CPUFUNC(op_6600_4), 0, 26112 }, /* Bcc */
-{ CPUFUNC(op_6601_4), 0, 26113 }, /* Bcc */
-{ CPUFUNC(op_66ff_4), 0, 26367 }, /* Bcc */
-{ CPUFUNC(op_6700_4), 0, 26368 }, /* Bcc */
-{ CPUFUNC(op_6701_4), 0, 26369 }, /* Bcc */
-{ CPUFUNC(op_67ff_4), 0, 26623 }, /* Bcc */
-{ CPUFUNC(op_6800_4), 0, 26624 }, /* Bcc */
-{ CPUFUNC(op_6801_4), 0, 26625 }, /* Bcc */
-{ CPUFUNC(op_68ff_4), 0, 26879 }, /* Bcc */
-{ CPUFUNC(op_6900_4), 0, 26880 }, /* Bcc */
-{ CPUFUNC(op_6901_4), 0, 26881 }, /* Bcc */
-{ CPUFUNC(op_69ff_4), 0, 27135 }, /* Bcc */
-{ CPUFUNC(op_6a00_4), 0, 27136 }, /* Bcc */
-{ CPUFUNC(op_6a01_4), 0, 27137 }, /* Bcc */
-{ CPUFUNC(op_6aff_4), 0, 27391 }, /* Bcc */
-{ CPUFUNC(op_6b00_4), 0, 27392 }, /* Bcc */
-{ CPUFUNC(op_6b01_4), 0, 27393 }, /* Bcc */
-{ CPUFUNC(op_6bff_4), 0, 27647 }, /* Bcc */
-{ CPUFUNC(op_6c00_4), 0, 27648 }, /* Bcc */
-{ CPUFUNC(op_6c01_4), 0, 27649 }, /* Bcc */
-{ CPUFUNC(op_6cff_4), 0, 27903 }, /* Bcc */
-{ CPUFUNC(op_6d00_4), 0, 27904 }, /* Bcc */
-{ CPUFUNC(op_6d01_4), 0, 27905 }, /* Bcc */
-{ CPUFUNC(op_6dff_4), 0, 28159 }, /* Bcc */
-{ CPUFUNC(op_6e00_4), 0, 28160 }, /* Bcc */
-{ CPUFUNC(op_6e01_4), 0, 28161 }, /* Bcc */
-{ CPUFUNC(op_6eff_4), 0, 28415 }, /* Bcc */
-{ CPUFUNC(op_6f00_4), 0, 28416 }, /* Bcc */
-{ CPUFUNC(op_6f01_4), 0, 28417 }, /* Bcc */
-{ CPUFUNC(op_6fff_4), 0, 28671 }, /* Bcc */
-{ CPUFUNC(op_7000_4), 0, 28672 }, /* MOVE */
-{ CPUFUNC(op_8000_4), 0, 32768 }, /* OR */
-{ CPUFUNC(op_8010_4), 0, 32784 }, /* OR */
-{ CPUFUNC(op_8018_4), 0, 32792 }, /* OR */
-{ CPUFUNC(op_8020_4), 0, 32800 }, /* OR */
-{ CPUFUNC(op_8028_4), 0, 32808 }, /* OR */
-{ CPUFUNC(op_8030_4), 0, 32816 }, /* OR */
-{ CPUFUNC(op_8038_4), 0, 32824 }, /* OR */
-{ CPUFUNC(op_8039_4), 0, 32825 }, /* OR */
-{ CPUFUNC(op_803a_4), 0, 32826 }, /* OR */
-{ CPUFUNC(op_803b_4), 0, 32827 }, /* OR */
-{ CPUFUNC(op_803c_4), 0, 32828 }, /* OR */
-{ CPUFUNC(op_8040_4), 0, 32832 }, /* OR */
-{ CPUFUNC(op_8050_4), 0, 32848 }, /* OR */
-{ CPUFUNC(op_8058_4), 0, 32856 }, /* OR */
-{ CPUFUNC(op_8060_4), 0, 32864 }, /* OR */
-{ CPUFUNC(op_8068_4), 0, 32872 }, /* OR */
-{ CPUFUNC(op_8070_4), 0, 32880 }, /* OR */
-{ CPUFUNC(op_8078_4), 0, 32888 }, /* OR */
-{ CPUFUNC(op_8079_4), 0, 32889 }, /* OR */
-{ CPUFUNC(op_807a_4), 0, 32890 }, /* OR */
-{ CPUFUNC(op_807b_4), 0, 32891 }, /* OR */
-{ CPUFUNC(op_807c_4), 0, 32892 }, /* OR */
-{ CPUFUNC(op_8080_4), 0, 32896 }, /* OR */
-{ CPUFUNC(op_8090_4), 0, 32912 }, /* OR */
-{ CPUFUNC(op_8098_4), 0, 32920 }, /* OR */
-{ CPUFUNC(op_80a0_4), 0, 32928 }, /* OR */
-{ CPUFUNC(op_80a8_4), 0, 32936 }, /* OR */
-{ CPUFUNC(op_80b0_4), 0, 32944 }, /* OR */
-{ CPUFUNC(op_80b8_4), 0, 32952 }, /* OR */
-{ CPUFUNC(op_80b9_4), 0, 32953 }, /* OR */
-{ CPUFUNC(op_80ba_4), 0, 32954 }, /* OR */
-{ CPUFUNC(op_80bb_4), 0, 32955 }, /* OR */
-{ CPUFUNC(op_80bc_4), 0, 32956 }, /* OR */
-{ CPUFUNC(op_80c0_4), 0, 32960 }, /* DIVU */
-{ CPUFUNC(op_80d0_4), 0, 32976 }, /* DIVU */
-{ CPUFUNC(op_80d8_4), 0, 32984 }, /* DIVU */
-{ CPUFUNC(op_80e0_4), 0, 32992 }, /* DIVU */
-{ CPUFUNC(op_80e8_4), 0, 33000 }, /* DIVU */
-{ CPUFUNC(op_80f0_4), 0, 33008 }, /* DIVU */
-{ CPUFUNC(op_80f8_4), 0, 33016 }, /* DIVU */
-{ CPUFUNC(op_80f9_4), 0, 33017 }, /* DIVU */
-{ CPUFUNC(op_80fa_4), 0, 33018 }, /* DIVU */
-{ CPUFUNC(op_80fb_4), 0, 33019 }, /* DIVU */
-{ CPUFUNC(op_80fc_4), 0, 33020 }, /* DIVU */
-{ CPUFUNC(op_8100_4), 0, 33024 }, /* SBCD */
-{ CPUFUNC(op_8108_4), 0, 33032 }, /* SBCD */
-{ CPUFUNC(op_8110_4), 0, 33040 }, /* OR */
-{ CPUFUNC(op_8118_4), 0, 33048 }, /* OR */
-{ CPUFUNC(op_8120_4), 0, 33056 }, /* OR */
-{ CPUFUNC(op_8128_4), 0, 33064 }, /* OR */
-{ CPUFUNC(op_8130_4), 0, 33072 }, /* OR */
-{ CPUFUNC(op_8138_4), 0, 33080 }, /* OR */
-{ CPUFUNC(op_8139_4), 0, 33081 }, /* OR */
-{ CPUFUNC(op_8150_4), 0, 33104 }, /* OR */
-{ CPUFUNC(op_8158_4), 0, 33112 }, /* OR */
-{ CPUFUNC(op_8160_4), 0, 33120 }, /* OR */
-{ CPUFUNC(op_8168_4), 0, 33128 }, /* OR */
-{ CPUFUNC(op_8170_4), 0, 33136 }, /* OR */
-{ CPUFUNC(op_8178_4), 0, 33144 }, /* OR */
-{ CPUFUNC(op_8179_4), 0, 33145 }, /* OR */
-{ CPUFUNC(op_8190_4), 0, 33168 }, /* OR */
-{ CPUFUNC(op_8198_4), 0, 33176 }, /* OR */
-{ CPUFUNC(op_81a0_4), 0, 33184 }, /* OR */
-{ CPUFUNC(op_81a8_4), 0, 33192 }, /* OR */
-{ CPUFUNC(op_81b0_4), 0, 33200 }, /* OR */
-{ CPUFUNC(op_81b8_4), 0, 33208 }, /* OR */
-{ CPUFUNC(op_81b9_4), 0, 33209 }, /* OR */
-{ CPUFUNC(op_81c0_4), 0, 33216 }, /* DIVS */
-{ CPUFUNC(op_81d0_4), 0, 33232 }, /* DIVS */
-{ CPUFUNC(op_81d8_4), 0, 33240 }, /* DIVS */
-{ CPUFUNC(op_81e0_4), 0, 33248 }, /* DIVS */
-{ CPUFUNC(op_81e8_4), 0, 33256 }, /* DIVS */
-{ CPUFUNC(op_81f0_4), 0, 33264 }, /* DIVS */
-{ CPUFUNC(op_81f8_4), 0, 33272 }, /* DIVS */
-{ CPUFUNC(op_81f9_4), 0, 33273 }, /* DIVS */
-{ CPUFUNC(op_81fa_4), 0, 33274 }, /* DIVS */
-{ CPUFUNC(op_81fb_4), 0, 33275 }, /* DIVS */
-{ CPUFUNC(op_81fc_4), 0, 33276 }, /* DIVS */
-{ CPUFUNC(op_9000_4), 0, 36864 }, /* SUB */
-{ CPUFUNC(op_9010_4), 0, 36880 }, /* SUB */
-{ CPUFUNC(op_9018_4), 0, 36888 }, /* SUB */
-{ CPUFUNC(op_9020_4), 0, 36896 }, /* SUB */
-{ CPUFUNC(op_9028_4), 0, 36904 }, /* SUB */
-{ CPUFUNC(op_9030_4), 0, 36912 }, /* SUB */
-{ CPUFUNC(op_9038_4), 0, 36920 }, /* SUB */
-{ CPUFUNC(op_9039_4), 0, 36921 }, /* SUB */
-{ CPUFUNC(op_903a_4), 0, 36922 }, /* SUB */
-{ CPUFUNC(op_903b_4), 0, 36923 }, /* SUB */
-{ CPUFUNC(op_903c_4), 0, 36924 }, /* SUB */
-{ CPUFUNC(op_9040_4), 0, 36928 }, /* SUB */
-{ CPUFUNC(op_9048_4), 0, 36936 }, /* SUB */
-{ CPUFUNC(op_9050_4), 0, 36944 }, /* SUB */
-{ CPUFUNC(op_9058_4), 0, 36952 }, /* SUB */
-{ CPUFUNC(op_9060_4), 0, 36960 }, /* SUB */
-{ CPUFUNC(op_9068_4), 0, 36968 }, /* SUB */
-{ CPUFUNC(op_9070_4), 0, 36976 }, /* SUB */
-{ CPUFUNC(op_9078_4), 0, 36984 }, /* SUB */
-{ CPUFUNC(op_9079_4), 0, 36985 }, /* SUB */
-{ CPUFUNC(op_907a_4), 0, 36986 }, /* SUB */
-{ CPUFUNC(op_907b_4), 0, 36987 }, /* SUB */
-{ CPUFUNC(op_907c_4), 0, 36988 }, /* SUB */
-{ CPUFUNC(op_9080_4), 0, 36992 }, /* SUB */
-{ CPUFUNC(op_9088_4), 0, 37000 }, /* SUB */
-{ CPUFUNC(op_9090_4), 0, 37008 }, /* SUB */
-{ CPUFUNC(op_9098_4), 0, 37016 }, /* SUB */
-{ CPUFUNC(op_90a0_4), 0, 37024 }, /* SUB */
-{ CPUFUNC(op_90a8_4), 0, 37032 }, /* SUB */
-{ CPUFUNC(op_90b0_4), 0, 37040 }, /* SUB */
-{ CPUFUNC(op_90b8_4), 0, 37048 }, /* SUB */
-{ CPUFUNC(op_90b9_4), 0, 37049 }, /* SUB */
-{ CPUFUNC(op_90ba_4), 0, 37050 }, /* SUB */
-{ CPUFUNC(op_90bb_4), 0, 37051 }, /* SUB */
-{ CPUFUNC(op_90bc_4), 0, 37052 }, /* SUB */
-{ CPUFUNC(op_90c0_4), 0, 37056 }, /* SUBA */
-{ CPUFUNC(op_90c8_4), 0, 37064 }, /* SUBA */
-{ CPUFUNC(op_90d0_4), 0, 37072 }, /* SUBA */
-{ CPUFUNC(op_90d8_4), 0, 37080 }, /* SUBA */
-{ CPUFUNC(op_90e0_4), 0, 37088 }, /* SUBA */
-{ CPUFUNC(op_90e8_4), 0, 37096 }, /* SUBA */
-{ CPUFUNC(op_90f0_4), 0, 37104 }, /* SUBA */
-{ CPUFUNC(op_90f8_4), 0, 37112 }, /* SUBA */
-{ CPUFUNC(op_90f9_4), 0, 37113 }, /* SUBA */
-{ CPUFUNC(op_90fa_4), 0, 37114 }, /* SUBA */
-{ CPUFUNC(op_90fb_4), 0, 37115 }, /* SUBA */
-{ CPUFUNC(op_90fc_4), 0, 37116 }, /* SUBA */
-{ CPUFUNC(op_9100_4), 0, 37120 }, /* SUBX */
-{ CPUFUNC(op_9108_4), 0, 37128 }, /* SUBX */
-{ CPUFUNC(op_9110_4), 0, 37136 }, /* SUB */
-{ CPUFUNC(op_9118_4), 0, 37144 }, /* SUB */
-{ CPUFUNC(op_9120_4), 0, 37152 }, /* SUB */
-{ CPUFUNC(op_9128_4), 0, 37160 }, /* SUB */
-{ CPUFUNC(op_9130_4), 0, 37168 }, /* SUB */
-{ CPUFUNC(op_9138_4), 0, 37176 }, /* SUB */
-{ CPUFUNC(op_9139_4), 0, 37177 }, /* SUB */
-{ CPUFUNC(op_9140_4), 0, 37184 }, /* SUBX */
-{ CPUFUNC(op_9148_4), 0, 37192 }, /* SUBX */
-{ CPUFUNC(op_9150_4), 0, 37200 }, /* SUB */
-{ CPUFUNC(op_9158_4), 0, 37208 }, /* SUB */
-{ CPUFUNC(op_9160_4), 0, 37216 }, /* SUB */
-{ CPUFUNC(op_9168_4), 0, 37224 }, /* SUB */
-{ CPUFUNC(op_9170_4), 0, 37232 }, /* SUB */
-{ CPUFUNC(op_9178_4), 0, 37240 }, /* SUB */
-{ CPUFUNC(op_9179_4), 0, 37241 }, /* SUB */
-{ CPUFUNC(op_9180_4), 0, 37248 }, /* SUBX */
-{ CPUFUNC(op_9188_4), 0, 37256 }, /* SUBX */
-{ CPUFUNC(op_9190_4), 0, 37264 }, /* SUB */
-{ CPUFUNC(op_9198_4), 0, 37272 }, /* SUB */
-{ CPUFUNC(op_91a0_4), 0, 37280 }, /* SUB */
-{ CPUFUNC(op_91a8_4), 0, 37288 }, /* SUB */
-{ CPUFUNC(op_91b0_4), 0, 37296 }, /* SUB */
-{ CPUFUNC(op_91b8_4), 0, 37304 }, /* SUB */
-{ CPUFUNC(op_91b9_4), 0, 37305 }, /* SUB */
-{ CPUFUNC(op_91c0_4), 0, 37312 }, /* SUBA */
-{ CPUFUNC(op_91c8_4), 0, 37320 }, /* SUBA */
-{ CPUFUNC(op_91d0_4), 0, 37328 }, /* SUBA */
-{ CPUFUNC(op_91d8_4), 0, 37336 }, /* SUBA */
-{ CPUFUNC(op_91e0_4), 0, 37344 }, /* SUBA */
-{ CPUFUNC(op_91e8_4), 0, 37352 }, /* SUBA */
-{ CPUFUNC(op_91f0_4), 0, 37360 }, /* SUBA */
-{ CPUFUNC(op_91f8_4), 0, 37368 }, /* SUBA */
-{ CPUFUNC(op_91f9_4), 0, 37369 }, /* SUBA */
-{ CPUFUNC(op_91fa_4), 0, 37370 }, /* SUBA */
-{ CPUFUNC(op_91fb_4), 0, 37371 }, /* SUBA */
-{ CPUFUNC(op_91fc_4), 0, 37372 }, /* SUBA */
-{ CPUFUNC(op_b000_4), 0, 45056 }, /* CMP */
-{ CPUFUNC(op_b010_4), 0, 45072 }, /* CMP */
-{ CPUFUNC(op_b018_4), 0, 45080 }, /* CMP */
-{ CPUFUNC(op_b020_4), 0, 45088 }, /* CMP */
-{ CPUFUNC(op_b028_4), 0, 45096 }, /* CMP */
-{ CPUFUNC(op_b030_4), 0, 45104 }, /* CMP */
-{ CPUFUNC(op_b038_4), 0, 45112 }, /* CMP */
-{ CPUFUNC(op_b039_4), 0, 45113 }, /* CMP */
-{ CPUFUNC(op_b03a_4), 0, 45114 }, /* CMP */
-{ CPUFUNC(op_b03b_4), 0, 45115 }, /* CMP */
-{ CPUFUNC(op_b03c_4), 0, 45116 }, /* CMP */
-{ CPUFUNC(op_b040_4), 0, 45120 }, /* CMP */
-{ CPUFUNC(op_b048_4), 0, 45128 }, /* CMP */
-{ CPUFUNC(op_b050_4), 0, 45136 }, /* CMP */
-{ CPUFUNC(op_b058_4), 0, 45144 }, /* CMP */
-{ CPUFUNC(op_b060_4), 0, 45152 }, /* CMP */
-{ CPUFUNC(op_b068_4), 0, 45160 }, /* CMP */
-{ CPUFUNC(op_b070_4), 0, 45168 }, /* CMP */
-{ CPUFUNC(op_b078_4), 0, 45176 }, /* CMP */
-{ CPUFUNC(op_b079_4), 0, 45177 }, /* CMP */
-{ CPUFUNC(op_b07a_4), 0, 45178 }, /* CMP */
-{ CPUFUNC(op_b07b_4), 0, 45179 }, /* CMP */
-{ CPUFUNC(op_b07c_4), 0, 45180 }, /* CMP */
-{ CPUFUNC(op_b080_4), 0, 45184 }, /* CMP */
-{ CPUFUNC(op_b088_4), 0, 45192 }, /* CMP */
-{ CPUFUNC(op_b090_4), 0, 45200 }, /* CMP */
-{ CPUFUNC(op_b098_4), 0, 45208 }, /* CMP */
-{ CPUFUNC(op_b0a0_4), 0, 45216 }, /* CMP */
-{ CPUFUNC(op_b0a8_4), 0, 45224 }, /* CMP */
-{ CPUFUNC(op_b0b0_4), 0, 45232 }, /* CMP */
-{ CPUFUNC(op_b0b8_4), 0, 45240 }, /* CMP */
-{ CPUFUNC(op_b0b9_4), 0, 45241 }, /* CMP */
-{ CPUFUNC(op_b0ba_4), 0, 45242 }, /* CMP */
-{ CPUFUNC(op_b0bb_4), 0, 45243 }, /* CMP */
-{ CPUFUNC(op_b0bc_4), 0, 45244 }, /* CMP */
-{ CPUFUNC(op_b0c0_4), 0, 45248 }, /* CMPA */
-{ CPUFUNC(op_b0c8_4), 0, 45256 }, /* CMPA */
-{ CPUFUNC(op_b0d0_4), 0, 45264 }, /* CMPA */
-{ CPUFUNC(op_b0d8_4), 0, 45272 }, /* CMPA */
-{ CPUFUNC(op_b0e0_4), 0, 45280 }, /* CMPA */
-{ CPUFUNC(op_b0e8_4), 0, 45288 }, /* CMPA */
-{ CPUFUNC(op_b0f0_4), 0, 45296 }, /* CMPA */
-{ CPUFUNC(op_b0f8_4), 0, 45304 }, /* CMPA */
-{ CPUFUNC(op_b0f9_4), 0, 45305 }, /* CMPA */
-{ CPUFUNC(op_b0fa_4), 0, 45306 }, /* CMPA */
-{ CPUFUNC(op_b0fb_4), 0, 45307 }, /* CMPA */
-{ CPUFUNC(op_b0fc_4), 0, 45308 }, /* CMPA */
-{ CPUFUNC(op_b100_4), 0, 45312 }, /* EOR */
-{ CPUFUNC(op_b108_4), 0, 45320 }, /* CMPM */
-{ CPUFUNC(op_b110_4), 0, 45328 }, /* EOR */
-{ CPUFUNC(op_b118_4), 0, 45336 }, /* EOR */
-{ CPUFUNC(op_b120_4), 0, 45344 }, /* EOR */
-{ CPUFUNC(op_b128_4), 0, 45352 }, /* EOR */
-{ CPUFUNC(op_b130_4), 0, 45360 }, /* EOR */
-{ CPUFUNC(op_b138_4), 0, 45368 }, /* EOR */
-{ CPUFUNC(op_b139_4), 0, 45369 }, /* EOR */
-{ CPUFUNC(op_b140_4), 0, 45376 }, /* EOR */
-{ CPUFUNC(op_b148_4), 0, 45384 }, /* CMPM */
-{ CPUFUNC(op_b150_4), 0, 45392 }, /* EOR */
-{ CPUFUNC(op_b158_4), 0, 45400 }, /* EOR */
-{ CPUFUNC(op_b160_4), 0, 45408 }, /* EOR */
-{ CPUFUNC(op_b168_4), 0, 45416 }, /* EOR */
-{ CPUFUNC(op_b170_4), 0, 45424 }, /* EOR */
-{ CPUFUNC(op_b178_4), 0, 45432 }, /* EOR */
-{ CPUFUNC(op_b179_4), 0, 45433 }, /* EOR */
-{ CPUFUNC(op_b180_4), 0, 45440 }, /* EOR */
-{ CPUFUNC(op_b188_4), 0, 45448 }, /* CMPM */
-{ CPUFUNC(op_b190_4), 0, 45456 }, /* EOR */
-{ CPUFUNC(op_b198_4), 0, 45464 }, /* EOR */
-{ CPUFUNC(op_b1a0_4), 0, 45472 }, /* EOR */
-{ CPUFUNC(op_b1a8_4), 0, 45480 }, /* EOR */
-{ CPUFUNC(op_b1b0_4), 0, 45488 }, /* EOR */
-{ CPUFUNC(op_b1b8_4), 0, 45496 }, /* EOR */
-{ CPUFUNC(op_b1b9_4), 0, 45497 }, /* EOR */
-{ CPUFUNC(op_b1c0_4), 0, 45504 }, /* CMPA */
-{ CPUFUNC(op_b1c8_4), 0, 45512 }, /* CMPA */
-{ CPUFUNC(op_b1d0_4), 0, 45520 }, /* CMPA */
-{ CPUFUNC(op_b1d8_4), 0, 45528 }, /* CMPA */
-{ CPUFUNC(op_b1e0_4), 0, 45536 }, /* CMPA */
-{ CPUFUNC(op_b1e8_4), 0, 45544 }, /* CMPA */
-{ CPUFUNC(op_b1f0_4), 0, 45552 }, /* CMPA */
-{ CPUFUNC(op_b1f8_4), 0, 45560 }, /* CMPA */
-{ CPUFUNC(op_b1f9_4), 0, 45561 }, /* CMPA */
-{ CPUFUNC(op_b1fa_4), 0, 45562 }, /* CMPA */
-{ CPUFUNC(op_b1fb_4), 0, 45563 }, /* CMPA */
-{ CPUFUNC(op_b1fc_4), 0, 45564 }, /* CMPA */
-{ CPUFUNC(op_c000_4), 0, 49152 }, /* AND */
-{ CPUFUNC(op_c010_4), 0, 49168 }, /* AND */
-{ CPUFUNC(op_c018_4), 0, 49176 }, /* AND */
-{ CPUFUNC(op_c020_4), 0, 49184 }, /* AND */
-{ CPUFUNC(op_c028_4), 0, 49192 }, /* AND */
-{ CPUFUNC(op_c030_4), 0, 49200 }, /* AND */
-{ CPUFUNC(op_c038_4), 0, 49208 }, /* AND */
-{ CPUFUNC(op_c039_4), 0, 49209 }, /* AND */
-{ CPUFUNC(op_c03a_4), 0, 49210 }, /* AND */
-{ CPUFUNC(op_c03b_4), 0, 49211 }, /* AND */
-{ CPUFUNC(op_c03c_4), 0, 49212 }, /* AND */
-{ CPUFUNC(op_c040_4), 0, 49216 }, /* AND */
-{ CPUFUNC(op_c050_4), 0, 49232 }, /* AND */
-{ CPUFUNC(op_c058_4), 0, 49240 }, /* AND */
-{ CPUFUNC(op_c060_4), 0, 49248 }, /* AND */
-{ CPUFUNC(op_c068_4), 0, 49256 }, /* AND */
-{ CPUFUNC(op_c070_4), 0, 49264 }, /* AND */
-{ CPUFUNC(op_c078_4), 0, 49272 }, /* AND */
-{ CPUFUNC(op_c079_4), 0, 49273 }, /* AND */
-{ CPUFUNC(op_c07a_4), 0, 49274 }, /* AND */
-{ CPUFUNC(op_c07b_4), 0, 49275 }, /* AND */
-{ CPUFUNC(op_c07c_4), 0, 49276 }, /* AND */
-{ CPUFUNC(op_c080_4), 0, 49280 }, /* AND */
-{ CPUFUNC(op_c090_4), 0, 49296 }, /* AND */
-{ CPUFUNC(op_c098_4), 0, 49304 }, /* AND */
-{ CPUFUNC(op_c0a0_4), 0, 49312 }, /* AND */
-{ CPUFUNC(op_c0a8_4), 0, 49320 }, /* AND */
-{ CPUFUNC(op_c0b0_4), 0, 49328 }, /* AND */
-{ CPUFUNC(op_c0b8_4), 0, 49336 }, /* AND */
-{ CPUFUNC(op_c0b9_4), 0, 49337 }, /* AND */
-{ CPUFUNC(op_c0ba_4), 0, 49338 }, /* AND */
-{ CPUFUNC(op_c0bb_4), 0, 49339 }, /* AND */
-{ CPUFUNC(op_c0bc_4), 0, 49340 }, /* AND */
-{ CPUFUNC(op_c0c0_4), 0, 49344 }, /* MULU */
-{ CPUFUNC(op_c0d0_4), 0, 49360 }, /* MULU */
-{ CPUFUNC(op_c0d8_4), 0, 49368 }, /* MULU */
-{ CPUFUNC(op_c0e0_4), 0, 49376 }, /* MULU */
-{ CPUFUNC(op_c0e8_4), 0, 49384 }, /* MULU */
-{ CPUFUNC(op_c0f0_4), 0, 49392 }, /* MULU */
-{ CPUFUNC(op_c0f8_4), 0, 49400 }, /* MULU */
-{ CPUFUNC(op_c0f9_4), 0, 49401 }, /* MULU */
-{ CPUFUNC(op_c0fa_4), 0, 49402 }, /* MULU */
-{ CPUFUNC(op_c0fb_4), 0, 49403 }, /* MULU */
-{ CPUFUNC(op_c0fc_4), 0, 49404 }, /* MULU */
-{ CPUFUNC(op_c100_4), 0, 49408 }, /* ABCD */
-{ CPUFUNC(op_c108_4), 0, 49416 }, /* ABCD */
-{ CPUFUNC(op_c110_4), 0, 49424 }, /* AND */
-{ CPUFUNC(op_c118_4), 0, 49432 }, /* AND */
-{ CPUFUNC(op_c120_4), 0, 49440 }, /* AND */
-{ CPUFUNC(op_c128_4), 0, 49448 }, /* AND */
-{ CPUFUNC(op_c130_4), 0, 49456 }, /* AND */
-{ CPUFUNC(op_c138_4), 0, 49464 }, /* AND */
-{ CPUFUNC(op_c139_4), 0, 49465 }, /* AND */
-{ CPUFUNC(op_c140_4), 0, 49472 }, /* EXG */
-{ CPUFUNC(op_c148_4), 0, 49480 }, /* EXG */
-{ CPUFUNC(op_c150_4), 0, 49488 }, /* AND */
-{ CPUFUNC(op_c158_4), 0, 49496 }, /* AND */
-{ CPUFUNC(op_c160_4), 0, 49504 }, /* AND */
-{ CPUFUNC(op_c168_4), 0, 49512 }, /* AND */
-{ CPUFUNC(op_c170_4), 0, 49520 }, /* AND */
-{ CPUFUNC(op_c178_4), 0, 49528 }, /* AND */
-{ CPUFUNC(op_c179_4), 0, 49529 }, /* AND */
-{ CPUFUNC(op_c188_4), 0, 49544 }, /* EXG */
-{ CPUFUNC(op_c190_4), 0, 49552 }, /* AND */
-{ CPUFUNC(op_c198_4), 0, 49560 }, /* AND */
-{ CPUFUNC(op_c1a0_4), 0, 49568 }, /* AND */
-{ CPUFUNC(op_c1a8_4), 0, 49576 }, /* AND */
-{ CPUFUNC(op_c1b0_4), 0, 49584 }, /* AND */
-{ CPUFUNC(op_c1b8_4), 0, 49592 }, /* AND */
-{ CPUFUNC(op_c1b9_4), 0, 49593 }, /* AND */
-{ CPUFUNC(op_c1c0_4), 0, 49600 }, /* MULS */
-{ CPUFUNC(op_c1d0_4), 0, 49616 }, /* MULS */
-{ CPUFUNC(op_c1d8_4), 0, 49624 }, /* MULS */
-{ CPUFUNC(op_c1e0_4), 0, 49632 }, /* MULS */
-{ CPUFUNC(op_c1e8_4), 0, 49640 }, /* MULS */
-{ CPUFUNC(op_c1f0_4), 0, 49648 }, /* MULS */
-{ CPUFUNC(op_c1f8_4), 0, 49656 }, /* MULS */
-{ CPUFUNC(op_c1f9_4), 0, 49657 }, /* MULS */
-{ CPUFUNC(op_c1fa_4), 0, 49658 }, /* MULS */
-{ CPUFUNC(op_c1fb_4), 0, 49659 }, /* MULS */
-{ CPUFUNC(op_c1fc_4), 0, 49660 }, /* MULS */
-{ CPUFUNC(op_d000_4), 0, 53248 }, /* ADD */
-{ CPUFUNC(op_d010_4), 0, 53264 }, /* ADD */
-{ CPUFUNC(op_d018_4), 0, 53272 }, /* ADD */
-{ CPUFUNC(op_d020_4), 0, 53280 }, /* ADD */
-{ CPUFUNC(op_d028_4), 0, 53288 }, /* ADD */
-{ CPUFUNC(op_d030_4), 0, 53296 }, /* ADD */
-{ CPUFUNC(op_d038_4), 0, 53304 }, /* ADD */
-{ CPUFUNC(op_d039_4), 0, 53305 }, /* ADD */
-{ CPUFUNC(op_d03a_4), 0, 53306 }, /* ADD */
-{ CPUFUNC(op_d03b_4), 0, 53307 }, /* ADD */
-{ CPUFUNC(op_d03c_4), 0, 53308 }, /* ADD */
-{ CPUFUNC(op_d040_4), 0, 53312 }, /* ADD */
-{ CPUFUNC(op_d048_4), 0, 53320 }, /* ADD */
-{ CPUFUNC(op_d050_4), 0, 53328 }, /* ADD */
-{ CPUFUNC(op_d058_4), 0, 53336 }, /* ADD */
-{ CPUFUNC(op_d060_4), 0, 53344 }, /* ADD */
-{ CPUFUNC(op_d068_4), 0, 53352 }, /* ADD */
-{ CPUFUNC(op_d070_4), 0, 53360 }, /* ADD */
-{ CPUFUNC(op_d078_4), 0, 53368 }, /* ADD */
-{ CPUFUNC(op_d079_4), 0, 53369 }, /* ADD */
-{ CPUFUNC(op_d07a_4), 0, 53370 }, /* ADD */
-{ CPUFUNC(op_d07b_4), 0, 53371 }, /* ADD */
-{ CPUFUNC(op_d07c_4), 0, 53372 }, /* ADD */
-{ CPUFUNC(op_d080_4), 0, 53376 }, /* ADD */
-{ CPUFUNC(op_d088_4), 0, 53384 }, /* ADD */
-{ CPUFUNC(op_d090_4), 0, 53392 }, /* ADD */
-{ CPUFUNC(op_d098_4), 0, 53400 }, /* ADD */
-{ CPUFUNC(op_d0a0_4), 0, 53408 }, /* ADD */
-{ CPUFUNC(op_d0a8_4), 0, 53416 }, /* ADD */
-{ CPUFUNC(op_d0b0_4), 0, 53424 }, /* ADD */
-{ CPUFUNC(op_d0b8_4), 0, 53432 }, /* ADD */
-{ CPUFUNC(op_d0b9_4), 0, 53433 }, /* ADD */
-{ CPUFUNC(op_d0ba_4), 0, 53434 }, /* ADD */
-{ CPUFUNC(op_d0bb_4), 0, 53435 }, /* ADD */
-{ CPUFUNC(op_d0bc_4), 0, 53436 }, /* ADD */
-{ CPUFUNC(op_d0c0_4), 0, 53440 }, /* ADDA */
-{ CPUFUNC(op_d0c8_4), 0, 53448 }, /* ADDA */
-{ CPUFUNC(op_d0d0_4), 0, 53456 }, /* ADDA */
-{ CPUFUNC(op_d0d8_4), 0, 53464 }, /* ADDA */
-{ CPUFUNC(op_d0e0_4), 0, 53472 }, /* ADDA */
-{ CPUFUNC(op_d0e8_4), 0, 53480 }, /* ADDA */
-{ CPUFUNC(op_d0f0_4), 0, 53488 }, /* ADDA */
-{ CPUFUNC(op_d0f8_4), 0, 53496 }, /* ADDA */
-{ CPUFUNC(op_d0f9_4), 0, 53497 }, /* ADDA */
-{ CPUFUNC(op_d0fa_4), 0, 53498 }, /* ADDA */
-{ CPUFUNC(op_d0fb_4), 0, 53499 }, /* ADDA */
-{ CPUFUNC(op_d0fc_4), 0, 53500 }, /* ADDA */
-{ CPUFUNC(op_d100_4), 0, 53504 }, /* ADDX */
-{ CPUFUNC(op_d108_4), 0, 53512 }, /* ADDX */
-{ CPUFUNC(op_d110_4), 0, 53520 }, /* ADD */
-{ CPUFUNC(op_d118_4), 0, 53528 }, /* ADD */
-{ CPUFUNC(op_d120_4), 0, 53536 }, /* ADD */
-{ CPUFUNC(op_d128_4), 0, 53544 }, /* ADD */
-{ CPUFUNC(op_d130_4), 0, 53552 }, /* ADD */
-{ CPUFUNC(op_d138_4), 0, 53560 }, /* ADD */
-{ CPUFUNC(op_d139_4), 0, 53561 }, /* ADD */
-{ CPUFUNC(op_d140_4), 0, 53568 }, /* ADDX */
-{ CPUFUNC(op_d148_4), 0, 53576 }, /* ADDX */
-{ CPUFUNC(op_d150_4), 0, 53584 }, /* ADD */
-{ CPUFUNC(op_d158_4), 0, 53592 }, /* ADD */
-{ CPUFUNC(op_d160_4), 0, 53600 }, /* ADD */
-{ CPUFUNC(op_d168_4), 0, 53608 }, /* ADD */
-{ CPUFUNC(op_d170_4), 0, 53616 }, /* ADD */
-{ CPUFUNC(op_d178_4), 0, 53624 }, /* ADD */
-{ CPUFUNC(op_d179_4), 0, 53625 }, /* ADD */
-{ CPUFUNC(op_d180_4), 0, 53632 }, /* ADDX */
-{ CPUFUNC(op_d188_4), 0, 53640 }, /* ADDX */
-{ CPUFUNC(op_d190_4), 0, 53648 }, /* ADD */
-{ CPUFUNC(op_d198_4), 0, 53656 }, /* ADD */
-{ CPUFUNC(op_d1a0_4), 0, 53664 }, /* ADD */
-{ CPUFUNC(op_d1a8_4), 0, 53672 }, /* ADD */
-{ CPUFUNC(op_d1b0_4), 0, 53680 }, /* ADD */
-{ CPUFUNC(op_d1b8_4), 0, 53688 }, /* ADD */
-{ CPUFUNC(op_d1b9_4), 0, 53689 }, /* ADD */
-{ CPUFUNC(op_d1c0_4), 0, 53696 }, /* ADDA */
-{ CPUFUNC(op_d1c8_4), 0, 53704 }, /* ADDA */
-{ CPUFUNC(op_d1d0_4), 0, 53712 }, /* ADDA */
-{ CPUFUNC(op_d1d8_4), 0, 53720 }, /* ADDA */
-{ CPUFUNC(op_d1e0_4), 0, 53728 }, /* ADDA */
-{ CPUFUNC(op_d1e8_4), 0, 53736 }, /* ADDA */
-{ CPUFUNC(op_d1f0_4), 0, 53744 }, /* ADDA */
-{ CPUFUNC(op_d1f8_4), 0, 53752 }, /* ADDA */
-{ CPUFUNC(op_d1f9_4), 0, 53753 }, /* ADDA */
-{ CPUFUNC(op_d1fa_4), 0, 53754 }, /* ADDA */
-{ CPUFUNC(op_d1fb_4), 0, 53755 }, /* ADDA */
-{ CPUFUNC(op_d1fc_4), 0, 53756 }, /* ADDA */
-{ CPUFUNC(op_e000_4), 0, 57344 }, /* ASR */
-{ CPUFUNC(op_e008_4), 0, 57352 }, /* LSR */
-{ CPUFUNC(op_e010_4), 0, 57360 }, /* ROXR */
-{ CPUFUNC(op_e018_4), 0, 57368 }, /* ROR */
-{ CPUFUNC(op_e020_4), 0, 57376 }, /* ASR */
-{ CPUFUNC(op_e028_4), 0, 57384 }, /* LSR */
-{ CPUFUNC(op_e030_4), 0, 57392 }, /* ROXR */
-{ CPUFUNC(op_e038_4), 0, 57400 }, /* ROR */
-{ CPUFUNC(op_e040_4), 0, 57408 }, /* ASR */
-{ CPUFUNC(op_e048_4), 0, 57416 }, /* LSR */
-{ CPUFUNC(op_e050_4), 0, 57424 }, /* ROXR */
-{ CPUFUNC(op_e058_4), 0, 57432 }, /* ROR */
-{ CPUFUNC(op_e060_4), 0, 57440 }, /* ASR */
-{ CPUFUNC(op_e068_4), 0, 57448 }, /* LSR */
-{ CPUFUNC(op_e070_4), 0, 57456 }, /* ROXR */
-{ CPUFUNC(op_e078_4), 0, 57464 }, /* ROR */
-{ CPUFUNC(op_e080_4), 0, 57472 }, /* ASR */
-{ CPUFUNC(op_e088_4), 0, 57480 }, /* LSR */
-{ CPUFUNC(op_e090_4), 0, 57488 }, /* ROXR */
-{ CPUFUNC(op_e098_4), 0, 57496 }, /* ROR */
-{ CPUFUNC(op_e0a0_4), 0, 57504 }, /* ASR */
-{ CPUFUNC(op_e0a8_4), 0, 57512 }, /* LSR */
-{ CPUFUNC(op_e0b0_4), 0, 57520 }, /* ROXR */
-{ CPUFUNC(op_e0b8_4), 0, 57528 }, /* ROR */
-{ CPUFUNC(op_e0d0_4), 0, 57552 }, /* ASRW */
-{ CPUFUNC(op_e0d8_4), 0, 57560 }, /* ASRW */
-{ CPUFUNC(op_e0e0_4), 0, 57568 }, /* ASRW */
-{ CPUFUNC(op_e0e8_4), 0, 57576 }, /* ASRW */
-{ CPUFUNC(op_e0f0_4), 0, 57584 }, /* ASRW */
-{ CPUFUNC(op_e0f8_4), 0, 57592 }, /* ASRW */
-{ CPUFUNC(op_e0f9_4), 0, 57593 }, /* ASRW */
-{ CPUFUNC(op_e100_4), 0, 57600 }, /* ASL */
-{ CPUFUNC(op_e108_4), 0, 57608 }, /* LSL */
-{ CPUFUNC(op_e110_4), 0, 57616 }, /* ROXL */
-{ CPUFUNC(op_e118_4), 0, 57624 }, /* ROL */
-{ CPUFUNC(op_e120_4), 0, 57632 }, /* ASL */
-{ CPUFUNC(op_e128_4), 0, 57640 }, /* LSL */
-{ CPUFUNC(op_e130_4), 0, 57648 }, /* ROXL */
-{ CPUFUNC(op_e138_4), 0, 57656 }, /* ROL */
-{ CPUFUNC(op_e140_4), 0, 57664 }, /* ASL */
-{ CPUFUNC(op_e148_4), 0, 57672 }, /* LSL */
-{ CPUFUNC(op_e150_4), 0, 57680 }, /* ROXL */
-{ CPUFUNC(op_e158_4), 0, 57688 }, /* ROL */
-{ CPUFUNC(op_e160_4), 0, 57696 }, /* ASL */
-{ CPUFUNC(op_e168_4), 0, 57704 }, /* LSL */
-{ CPUFUNC(op_e170_4), 0, 57712 }, /* ROXL */
-{ CPUFUNC(op_e178_4), 0, 57720 }, /* ROL */
-{ CPUFUNC(op_e180_4), 0, 57728 }, /* ASL */
-{ CPUFUNC(op_e188_4), 0, 57736 }, /* LSL */
-{ CPUFUNC(op_e190_4), 0, 57744 }, /* ROXL */
-{ CPUFUNC(op_e198_4), 0, 57752 }, /* ROL */
-{ CPUFUNC(op_e1a0_4), 0, 57760 }, /* ASL */
-{ CPUFUNC(op_e1a8_4), 0, 57768 }, /* LSL */
-{ CPUFUNC(op_e1b0_4), 0, 57776 }, /* ROXL */
-{ CPUFUNC(op_e1b8_4), 0, 57784 }, /* ROL */
-{ CPUFUNC(op_e1d0_4), 0, 57808 }, /* ASLW */
-{ CPUFUNC(op_e1d8_4), 0, 57816 }, /* ASLW */
-{ CPUFUNC(op_e1e0_4), 0, 57824 }, /* ASLW */
-{ CPUFUNC(op_e1e8_4), 0, 57832 }, /* ASLW */
-{ CPUFUNC(op_e1f0_4), 0, 57840 }, /* ASLW */
-{ CPUFUNC(op_e1f8_4), 0, 57848 }, /* ASLW */
-{ CPUFUNC(op_e1f9_4), 0, 57849 }, /* ASLW */
-{ CPUFUNC(op_e2d0_4), 0, 58064 }, /* LSRW */
-{ CPUFUNC(op_e2d8_4), 0, 58072 }, /* LSRW */
-{ CPUFUNC(op_e2e0_4), 0, 58080 }, /* LSRW */
-{ CPUFUNC(op_e2e8_4), 0, 58088 }, /* LSRW */
-{ CPUFUNC(op_e2f0_4), 0, 58096 }, /* LSRW */
-{ CPUFUNC(op_e2f8_4), 0, 58104 }, /* LSRW */
-{ CPUFUNC(op_e2f9_4), 0, 58105 }, /* LSRW */
-{ CPUFUNC(op_e3d0_4), 0, 58320 }, /* LSLW */
-{ CPUFUNC(op_e3d8_4), 0, 58328 }, /* LSLW */
-{ CPUFUNC(op_e3e0_4), 0, 58336 }, /* LSLW */
-{ CPUFUNC(op_e3e8_4), 0, 58344 }, /* LSLW */
-{ CPUFUNC(op_e3f0_4), 0, 58352 }, /* LSLW */
-{ CPUFUNC(op_e3f8_4), 0, 58360 }, /* LSLW */
-{ CPUFUNC(op_e3f9_4), 0, 58361 }, /* LSLW */
-{ CPUFUNC(op_e4d0_4), 0, 58576 }, /* ROXRW */
-{ CPUFUNC(op_e4d8_4), 0, 58584 }, /* ROXRW */
-{ CPUFUNC(op_e4e0_4), 0, 58592 }, /* ROXRW */
-{ CPUFUNC(op_e4e8_4), 0, 58600 }, /* ROXRW */
-{ CPUFUNC(op_e4f0_4), 0, 58608 }, /* ROXRW */
-{ CPUFUNC(op_e4f8_4), 0, 58616 }, /* ROXRW */
-{ CPUFUNC(op_e4f9_4), 0, 58617 }, /* ROXRW */
-{ CPUFUNC(op_e5d0_4), 0, 58832 }, /* ROXLW */
-{ CPUFUNC(op_e5d8_4), 0, 58840 }, /* ROXLW */
-{ CPUFUNC(op_e5e0_4), 0, 58848 }, /* ROXLW */
-{ CPUFUNC(op_e5e8_4), 0, 58856 }, /* ROXLW */
-{ CPUFUNC(op_e5f0_4), 0, 58864 }, /* ROXLW */
-{ CPUFUNC(op_e5f8_4), 0, 58872 }, /* ROXLW */
-{ CPUFUNC(op_e5f9_4), 0, 58873 }, /* ROXLW */
-{ CPUFUNC(op_e6d0_4), 0, 59088 }, /* RORW */
-{ CPUFUNC(op_e6d8_4), 0, 59096 }, /* RORW */
-{ CPUFUNC(op_e6e0_4), 0, 59104 }, /* RORW */
-{ CPUFUNC(op_e6e8_4), 0, 59112 }, /* RORW */
-{ CPUFUNC(op_e6f0_4), 0, 59120 }, /* RORW */
-{ CPUFUNC(op_e6f8_4), 0, 59128 }, /* RORW */
-{ CPUFUNC(op_e6f9_4), 0, 59129 }, /* RORW */
-{ CPUFUNC(op_e7d0_4), 0, 59344 }, /* ROLW */
-{ CPUFUNC(op_e7d8_4), 0, 59352 }, /* ROLW */
-{ CPUFUNC(op_e7e0_4), 0, 59360 }, /* ROLW */
-{ CPUFUNC(op_e7e8_4), 0, 59368 }, /* ROLW */
-{ CPUFUNC(op_e7f0_4), 0, 59376 }, /* ROLW */
-{ CPUFUNC(op_e7f8_4), 0, 59384 }, /* ROLW */
-{ CPUFUNC(op_e7f9_4), 0, 59385 }, /* ROLW */
-{ 0, 0, 0 }};
+
 const struct cputbl CPUFUNC(op_smalltbl_5)[] = {
 { CPUFUNC(op_0_5), 0, 0 }, /* OR */
 { CPUFUNC(op_10_5), 0, 16 }, /* OR */
diff --git a/waterbox/virtualjaguar/src/m68000/cputbl.h b/waterbox/virtualjaguar/src/m68000/cputbl.h
index e5be860448..3e6128825b 100644
--- a/waterbox/virtualjaguar/src/m68000/cputbl.h
+++ b/waterbox/virtualjaguar/src/m68000/cputbl.h
@@ -1,3163 +1,3 @@
-extern cpuop_func op_0_4_nf;
-extern cpuop_func op_0_4_ff;
-extern cpuop_func op_10_4_nf;
-extern cpuop_func op_10_4_ff;
-extern cpuop_func op_18_4_nf;
-extern cpuop_func op_18_4_ff;
-extern cpuop_func op_20_4_nf;
-extern cpuop_func op_20_4_ff;
-extern cpuop_func op_28_4_nf;
-extern cpuop_func op_28_4_ff;
-extern cpuop_func op_30_4_nf;
-extern cpuop_func op_30_4_ff;
-extern cpuop_func op_38_4_nf;
-extern cpuop_func op_38_4_ff;
-extern cpuop_func op_39_4_nf;
-extern cpuop_func op_39_4_ff;
-extern cpuop_func op_3c_4_nf;
-extern cpuop_func op_3c_4_ff;
-extern cpuop_func op_40_4_nf;
-extern cpuop_func op_40_4_ff;
-extern cpuop_func op_50_4_nf;
-extern cpuop_func op_50_4_ff;
-extern cpuop_func op_58_4_nf;
-extern cpuop_func op_58_4_ff;
-extern cpuop_func op_60_4_nf;
-extern cpuop_func op_60_4_ff;
-extern cpuop_func op_68_4_nf;
-extern cpuop_func op_68_4_ff;
-extern cpuop_func op_70_4_nf;
-extern cpuop_func op_70_4_ff;
-extern cpuop_func op_78_4_nf;
-extern cpuop_func op_78_4_ff;
-extern cpuop_func op_79_4_nf;
-extern cpuop_func op_79_4_ff;
-extern cpuop_func op_7c_4_nf;
-extern cpuop_func op_7c_4_ff;
-extern cpuop_func op_80_4_nf;
-extern cpuop_func op_80_4_ff;
-extern cpuop_func op_90_4_nf;
-extern cpuop_func op_90_4_ff;
-extern cpuop_func op_98_4_nf;
-extern cpuop_func op_98_4_ff;
-extern cpuop_func op_a0_4_nf;
-extern cpuop_func op_a0_4_ff;
-extern cpuop_func op_a8_4_nf;
-extern cpuop_func op_a8_4_ff;
-extern cpuop_func op_b0_4_nf;
-extern cpuop_func op_b0_4_ff;
-extern cpuop_func op_b8_4_nf;
-extern cpuop_func op_b8_4_ff;
-extern cpuop_func op_b9_4_nf;
-extern cpuop_func op_b9_4_ff;
-extern cpuop_func op_100_4_nf;
-extern cpuop_func op_100_4_ff;
-extern cpuop_func op_108_4_nf;
-extern cpuop_func op_108_4_ff;
-extern cpuop_func op_110_4_nf;
-extern cpuop_func op_110_4_ff;
-extern cpuop_func op_118_4_nf;
-extern cpuop_func op_118_4_ff;
-extern cpuop_func op_120_4_nf;
-extern cpuop_func op_120_4_ff;
-extern cpuop_func op_128_4_nf;
-extern cpuop_func op_128_4_ff;
-extern cpuop_func op_130_4_nf;
-extern cpuop_func op_130_4_ff;
-extern cpuop_func op_138_4_nf;
-extern cpuop_func op_138_4_ff;
-extern cpuop_func op_139_4_nf;
-extern cpuop_func op_139_4_ff;
-extern cpuop_func op_13a_4_nf;
-extern cpuop_func op_13a_4_ff;
-extern cpuop_func op_13b_4_nf;
-extern cpuop_func op_13b_4_ff;
-extern cpuop_func op_13c_4_nf;
-extern cpuop_func op_13c_4_ff;
-extern cpuop_func op_140_4_nf;
-extern cpuop_func op_140_4_ff;
-extern cpuop_func op_148_4_nf;
-extern cpuop_func op_148_4_ff;
-extern cpuop_func op_150_4_nf;
-extern cpuop_func op_150_4_ff;
-extern cpuop_func op_158_4_nf;
-extern cpuop_func op_158_4_ff;
-extern cpuop_func op_160_4_nf;
-extern cpuop_func op_160_4_ff;
-extern cpuop_func op_168_4_nf;
-extern cpuop_func op_168_4_ff;
-extern cpuop_func op_170_4_nf;
-extern cpuop_func op_170_4_ff;
-extern cpuop_func op_178_4_nf;
-extern cpuop_func op_178_4_ff;
-extern cpuop_func op_179_4_nf;
-extern cpuop_func op_179_4_ff;
-extern cpuop_func op_17a_4_nf;
-extern cpuop_func op_17a_4_ff;
-extern cpuop_func op_17b_4_nf;
-extern cpuop_func op_17b_4_ff;
-extern cpuop_func op_180_4_nf;
-extern cpuop_func op_180_4_ff;
-extern cpuop_func op_188_4_nf;
-extern cpuop_func op_188_4_ff;
-extern cpuop_func op_190_4_nf;
-extern cpuop_func op_190_4_ff;
-extern cpuop_func op_198_4_nf;
-extern cpuop_func op_198_4_ff;
-extern cpuop_func op_1a0_4_nf;
-extern cpuop_func op_1a0_4_ff;
-extern cpuop_func op_1a8_4_nf;
-extern cpuop_func op_1a8_4_ff;
-extern cpuop_func op_1b0_4_nf;
-extern cpuop_func op_1b0_4_ff;
-extern cpuop_func op_1b8_4_nf;
-extern cpuop_func op_1b8_4_ff;
-extern cpuop_func op_1b9_4_nf;
-extern cpuop_func op_1b9_4_ff;
-extern cpuop_func op_1ba_4_nf;
-extern cpuop_func op_1ba_4_ff;
-extern cpuop_func op_1bb_4_nf;
-extern cpuop_func op_1bb_4_ff;
-extern cpuop_func op_1c0_4_nf;
-extern cpuop_func op_1c0_4_ff;
-extern cpuop_func op_1c8_4_nf;
-extern cpuop_func op_1c8_4_ff;
-extern cpuop_func op_1d0_4_nf;
-extern cpuop_func op_1d0_4_ff;
-extern cpuop_func op_1d8_4_nf;
-extern cpuop_func op_1d8_4_ff;
-extern cpuop_func op_1e0_4_nf;
-extern cpuop_func op_1e0_4_ff;
-extern cpuop_func op_1e8_4_nf;
-extern cpuop_func op_1e8_4_ff;
-extern cpuop_func op_1f0_4_nf;
-extern cpuop_func op_1f0_4_ff;
-extern cpuop_func op_1f8_4_nf;
-extern cpuop_func op_1f8_4_ff;
-extern cpuop_func op_1f9_4_nf;
-extern cpuop_func op_1f9_4_ff;
-extern cpuop_func op_1fa_4_nf;
-extern cpuop_func op_1fa_4_ff;
-extern cpuop_func op_1fb_4_nf;
-extern cpuop_func op_1fb_4_ff;
-extern cpuop_func op_200_4_nf;
-extern cpuop_func op_200_4_ff;
-extern cpuop_func op_210_4_nf;
-extern cpuop_func op_210_4_ff;
-extern cpuop_func op_218_4_nf;
-extern cpuop_func op_218_4_ff;
-extern cpuop_func op_220_4_nf;
-extern cpuop_func op_220_4_ff;
-extern cpuop_func op_228_4_nf;
-extern cpuop_func op_228_4_ff;
-extern cpuop_func op_230_4_nf;
-extern cpuop_func op_230_4_ff;
-extern cpuop_func op_238_4_nf;
-extern cpuop_func op_238_4_ff;
-extern cpuop_func op_239_4_nf;
-extern cpuop_func op_239_4_ff;
-extern cpuop_func op_23c_4_nf;
-extern cpuop_func op_23c_4_ff;
-extern cpuop_func op_240_4_nf;
-extern cpuop_func op_240_4_ff;
-extern cpuop_func op_250_4_nf;
-extern cpuop_func op_250_4_ff;
-extern cpuop_func op_258_4_nf;
-extern cpuop_func op_258_4_ff;
-extern cpuop_func op_260_4_nf;
-extern cpuop_func op_260_4_ff;
-extern cpuop_func op_268_4_nf;
-extern cpuop_func op_268_4_ff;
-extern cpuop_func op_270_4_nf;
-extern cpuop_func op_270_4_ff;
-extern cpuop_func op_278_4_nf;
-extern cpuop_func op_278_4_ff;
-extern cpuop_func op_279_4_nf;
-extern cpuop_func op_279_4_ff;
-extern cpuop_func op_27c_4_nf;
-extern cpuop_func op_27c_4_ff;
-extern cpuop_func op_280_4_nf;
-extern cpuop_func op_280_4_ff;
-extern cpuop_func op_290_4_nf;
-extern cpuop_func op_290_4_ff;
-extern cpuop_func op_298_4_nf;
-extern cpuop_func op_298_4_ff;
-extern cpuop_func op_2a0_4_nf;
-extern cpuop_func op_2a0_4_ff;
-extern cpuop_func op_2a8_4_nf;
-extern cpuop_func op_2a8_4_ff;
-extern cpuop_func op_2b0_4_nf;
-extern cpuop_func op_2b0_4_ff;
-extern cpuop_func op_2b8_4_nf;
-extern cpuop_func op_2b8_4_ff;
-extern cpuop_func op_2b9_4_nf;
-extern cpuop_func op_2b9_4_ff;
-extern cpuop_func op_400_4_nf;
-extern cpuop_func op_400_4_ff;
-extern cpuop_func op_410_4_nf;
-extern cpuop_func op_410_4_ff;
-extern cpuop_func op_418_4_nf;
-extern cpuop_func op_418_4_ff;
-extern cpuop_func op_420_4_nf;
-extern cpuop_func op_420_4_ff;
-extern cpuop_func op_428_4_nf;
-extern cpuop_func op_428_4_ff;
-extern cpuop_func op_430_4_nf;
-extern cpuop_func op_430_4_ff;
-extern cpuop_func op_438_4_nf;
-extern cpuop_func op_438_4_ff;
-extern cpuop_func op_439_4_nf;
-extern cpuop_func op_439_4_ff;
-extern cpuop_func op_440_4_nf;
-extern cpuop_func op_440_4_ff;
-extern cpuop_func op_450_4_nf;
-extern cpuop_func op_450_4_ff;
-extern cpuop_func op_458_4_nf;
-extern cpuop_func op_458_4_ff;
-extern cpuop_func op_460_4_nf;
-extern cpuop_func op_460_4_ff;
-extern cpuop_func op_468_4_nf;
-extern cpuop_func op_468_4_ff;
-extern cpuop_func op_470_4_nf;
-extern cpuop_func op_470_4_ff;
-extern cpuop_func op_478_4_nf;
-extern cpuop_func op_478_4_ff;
-extern cpuop_func op_479_4_nf;
-extern cpuop_func op_479_4_ff;
-extern cpuop_func op_480_4_nf;
-extern cpuop_func op_480_4_ff;
-extern cpuop_func op_490_4_nf;
-extern cpuop_func op_490_4_ff;
-extern cpuop_func op_498_4_nf;
-extern cpuop_func op_498_4_ff;
-extern cpuop_func op_4a0_4_nf;
-extern cpuop_func op_4a0_4_ff;
-extern cpuop_func op_4a8_4_nf;
-extern cpuop_func op_4a8_4_ff;
-extern cpuop_func op_4b0_4_nf;
-extern cpuop_func op_4b0_4_ff;
-extern cpuop_func op_4b8_4_nf;
-extern cpuop_func op_4b8_4_ff;
-extern cpuop_func op_4b9_4_nf;
-extern cpuop_func op_4b9_4_ff;
-extern cpuop_func op_600_4_nf;
-extern cpuop_func op_600_4_ff;
-extern cpuop_func op_610_4_nf;
-extern cpuop_func op_610_4_ff;
-extern cpuop_func op_618_4_nf;
-extern cpuop_func op_618_4_ff;
-extern cpuop_func op_620_4_nf;
-extern cpuop_func op_620_4_ff;
-extern cpuop_func op_628_4_nf;
-extern cpuop_func op_628_4_ff;
-extern cpuop_func op_630_4_nf;
-extern cpuop_func op_630_4_ff;
-extern cpuop_func op_638_4_nf;
-extern cpuop_func op_638_4_ff;
-extern cpuop_func op_639_4_nf;
-extern cpuop_func op_639_4_ff;
-extern cpuop_func op_640_4_nf;
-extern cpuop_func op_640_4_ff;
-extern cpuop_func op_650_4_nf;
-extern cpuop_func op_650_4_ff;
-extern cpuop_func op_658_4_nf;
-extern cpuop_func op_658_4_ff;
-extern cpuop_func op_660_4_nf;
-extern cpuop_func op_660_4_ff;
-extern cpuop_func op_668_4_nf;
-extern cpuop_func op_668_4_ff;
-extern cpuop_func op_670_4_nf;
-extern cpuop_func op_670_4_ff;
-extern cpuop_func op_678_4_nf;
-extern cpuop_func op_678_4_ff;
-extern cpuop_func op_679_4_nf;
-extern cpuop_func op_679_4_ff;
-extern cpuop_func op_680_4_nf;
-extern cpuop_func op_680_4_ff;
-extern cpuop_func op_690_4_nf;
-extern cpuop_func op_690_4_ff;
-extern cpuop_func op_698_4_nf;
-extern cpuop_func op_698_4_ff;
-extern cpuop_func op_6a0_4_nf;
-extern cpuop_func op_6a0_4_ff;
-extern cpuop_func op_6a8_4_nf;
-extern cpuop_func op_6a8_4_ff;
-extern cpuop_func op_6b0_4_nf;
-extern cpuop_func op_6b0_4_ff;
-extern cpuop_func op_6b8_4_nf;
-extern cpuop_func op_6b8_4_ff;
-extern cpuop_func op_6b9_4_nf;
-extern cpuop_func op_6b9_4_ff;
-extern cpuop_func op_800_4_nf;
-extern cpuop_func op_800_4_ff;
-extern cpuop_func op_810_4_nf;
-extern cpuop_func op_810_4_ff;
-extern cpuop_func op_818_4_nf;
-extern cpuop_func op_818_4_ff;
-extern cpuop_func op_820_4_nf;
-extern cpuop_func op_820_4_ff;
-extern cpuop_func op_828_4_nf;
-extern cpuop_func op_828_4_ff;
-extern cpuop_func op_830_4_nf;
-extern cpuop_func op_830_4_ff;
-extern cpuop_func op_838_4_nf;
-extern cpuop_func op_838_4_ff;
-extern cpuop_func op_839_4_nf;
-extern cpuop_func op_839_4_ff;
-extern cpuop_func op_83a_4_nf;
-extern cpuop_func op_83a_4_ff;
-extern cpuop_func op_83b_4_nf;
-extern cpuop_func op_83b_4_ff;
-extern cpuop_func op_83c_4_nf;
-extern cpuop_func op_83c_4_ff;
-extern cpuop_func op_840_4_nf;
-extern cpuop_func op_840_4_ff;
-extern cpuop_func op_850_4_nf;
-extern cpuop_func op_850_4_ff;
-extern cpuop_func op_858_4_nf;
-extern cpuop_func op_858_4_ff;
-extern cpuop_func op_860_4_nf;
-extern cpuop_func op_860_4_ff;
-extern cpuop_func op_868_4_nf;
-extern cpuop_func op_868_4_ff;
-extern cpuop_func op_870_4_nf;
-extern cpuop_func op_870_4_ff;
-extern cpuop_func op_878_4_nf;
-extern cpuop_func op_878_4_ff;
-extern cpuop_func op_879_4_nf;
-extern cpuop_func op_879_4_ff;
-extern cpuop_func op_87a_4_nf;
-extern cpuop_func op_87a_4_ff;
-extern cpuop_func op_87b_4_nf;
-extern cpuop_func op_87b_4_ff;
-extern cpuop_func op_880_4_nf;
-extern cpuop_func op_880_4_ff;
-extern cpuop_func op_890_4_nf;
-extern cpuop_func op_890_4_ff;
-extern cpuop_func op_898_4_nf;
-extern cpuop_func op_898_4_ff;
-extern cpuop_func op_8a0_4_nf;
-extern cpuop_func op_8a0_4_ff;
-extern cpuop_func op_8a8_4_nf;
-extern cpuop_func op_8a8_4_ff;
-extern cpuop_func op_8b0_4_nf;
-extern cpuop_func op_8b0_4_ff;
-extern cpuop_func op_8b8_4_nf;
-extern cpuop_func op_8b8_4_ff;
-extern cpuop_func op_8b9_4_nf;
-extern cpuop_func op_8b9_4_ff;
-extern cpuop_func op_8ba_4_nf;
-extern cpuop_func op_8ba_4_ff;
-extern cpuop_func op_8bb_4_nf;
-extern cpuop_func op_8bb_4_ff;
-extern cpuop_func op_8c0_4_nf;
-extern cpuop_func op_8c0_4_ff;
-extern cpuop_func op_8d0_4_nf;
-extern cpuop_func op_8d0_4_ff;
-extern cpuop_func op_8d8_4_nf;
-extern cpuop_func op_8d8_4_ff;
-extern cpuop_func op_8e0_4_nf;
-extern cpuop_func op_8e0_4_ff;
-extern cpuop_func op_8e8_4_nf;
-extern cpuop_func op_8e8_4_ff;
-extern cpuop_func op_8f0_4_nf;
-extern cpuop_func op_8f0_4_ff;
-extern cpuop_func op_8f8_4_nf;
-extern cpuop_func op_8f8_4_ff;
-extern cpuop_func op_8f9_4_nf;
-extern cpuop_func op_8f9_4_ff;
-extern cpuop_func op_8fa_4_nf;
-extern cpuop_func op_8fa_4_ff;
-extern cpuop_func op_8fb_4_nf;
-extern cpuop_func op_8fb_4_ff;
-extern cpuop_func op_a00_4_nf;
-extern cpuop_func op_a00_4_ff;
-extern cpuop_func op_a10_4_nf;
-extern cpuop_func op_a10_4_ff;
-extern cpuop_func op_a18_4_nf;
-extern cpuop_func op_a18_4_ff;
-extern cpuop_func op_a20_4_nf;
-extern cpuop_func op_a20_4_ff;
-extern cpuop_func op_a28_4_nf;
-extern cpuop_func op_a28_4_ff;
-extern cpuop_func op_a30_4_nf;
-extern cpuop_func op_a30_4_ff;
-extern cpuop_func op_a38_4_nf;
-extern cpuop_func op_a38_4_ff;
-extern cpuop_func op_a39_4_nf;
-extern cpuop_func op_a39_4_ff;
-extern cpuop_func op_a3c_4_nf;
-extern cpuop_func op_a3c_4_ff;
-extern cpuop_func op_a40_4_nf;
-extern cpuop_func op_a40_4_ff;
-extern cpuop_func op_a50_4_nf;
-extern cpuop_func op_a50_4_ff;
-extern cpuop_func op_a58_4_nf;
-extern cpuop_func op_a58_4_ff;
-extern cpuop_func op_a60_4_nf;
-extern cpuop_func op_a60_4_ff;
-extern cpuop_func op_a68_4_nf;
-extern cpuop_func op_a68_4_ff;
-extern cpuop_func op_a70_4_nf;
-extern cpuop_func op_a70_4_ff;
-extern cpuop_func op_a78_4_nf;
-extern cpuop_func op_a78_4_ff;
-extern cpuop_func op_a79_4_nf;
-extern cpuop_func op_a79_4_ff;
-extern cpuop_func op_a7c_4_nf;
-extern cpuop_func op_a7c_4_ff;
-extern cpuop_func op_a80_4_nf;
-extern cpuop_func op_a80_4_ff;
-extern cpuop_func op_a90_4_nf;
-extern cpuop_func op_a90_4_ff;
-extern cpuop_func op_a98_4_nf;
-extern cpuop_func op_a98_4_ff;
-extern cpuop_func op_aa0_4_nf;
-extern cpuop_func op_aa0_4_ff;
-extern cpuop_func op_aa8_4_nf;
-extern cpuop_func op_aa8_4_ff;
-extern cpuop_func op_ab0_4_nf;
-extern cpuop_func op_ab0_4_ff;
-extern cpuop_func op_ab8_4_nf;
-extern cpuop_func op_ab8_4_ff;
-extern cpuop_func op_ab9_4_nf;
-extern cpuop_func op_ab9_4_ff;
-extern cpuop_func op_c00_4_nf;
-extern cpuop_func op_c00_4_ff;
-extern cpuop_func op_c10_4_nf;
-extern cpuop_func op_c10_4_ff;
-extern cpuop_func op_c18_4_nf;
-extern cpuop_func op_c18_4_ff;
-extern cpuop_func op_c20_4_nf;
-extern cpuop_func op_c20_4_ff;
-extern cpuop_func op_c28_4_nf;
-extern cpuop_func op_c28_4_ff;
-extern cpuop_func op_c30_4_nf;
-extern cpuop_func op_c30_4_ff;
-extern cpuop_func op_c38_4_nf;
-extern cpuop_func op_c38_4_ff;
-extern cpuop_func op_c39_4_nf;
-extern cpuop_func op_c39_4_ff;
-extern cpuop_func op_c3a_4_nf;
-extern cpuop_func op_c3a_4_ff;
-extern cpuop_func op_c3b_4_nf;
-extern cpuop_func op_c3b_4_ff;
-extern cpuop_func op_c40_4_nf;
-extern cpuop_func op_c40_4_ff;
-extern cpuop_func op_c50_4_nf;
-extern cpuop_func op_c50_4_ff;
-extern cpuop_func op_c58_4_nf;
-extern cpuop_func op_c58_4_ff;
-extern cpuop_func op_c60_4_nf;
-extern cpuop_func op_c60_4_ff;
-extern cpuop_func op_c68_4_nf;
-extern cpuop_func op_c68_4_ff;
-extern cpuop_func op_c70_4_nf;
-extern cpuop_func op_c70_4_ff;
-extern cpuop_func op_c78_4_nf;
-extern cpuop_func op_c78_4_ff;
-extern cpuop_func op_c79_4_nf;
-extern cpuop_func op_c79_4_ff;
-extern cpuop_func op_c7a_4_nf;
-extern cpuop_func op_c7a_4_ff;
-extern cpuop_func op_c7b_4_nf;
-extern cpuop_func op_c7b_4_ff;
-extern cpuop_func op_c80_4_nf;
-extern cpuop_func op_c80_4_ff;
-extern cpuop_func op_c90_4_nf;
-extern cpuop_func op_c90_4_ff;
-extern cpuop_func op_c98_4_nf;
-extern cpuop_func op_c98_4_ff;
-extern cpuop_func op_ca0_4_nf;
-extern cpuop_func op_ca0_4_ff;
-extern cpuop_func op_ca8_4_nf;
-extern cpuop_func op_ca8_4_ff;
-extern cpuop_func op_cb0_4_nf;
-extern cpuop_func op_cb0_4_ff;
-extern cpuop_func op_cb8_4_nf;
-extern cpuop_func op_cb8_4_ff;
-extern cpuop_func op_cb9_4_nf;
-extern cpuop_func op_cb9_4_ff;
-extern cpuop_func op_cba_4_nf;
-extern cpuop_func op_cba_4_ff;
-extern cpuop_func op_cbb_4_nf;
-extern cpuop_func op_cbb_4_ff;
-extern cpuop_func op_1000_4_nf;
-extern cpuop_func op_1000_4_ff;
-extern cpuop_func op_1008_4_nf;
-extern cpuop_func op_1008_4_ff;
-extern cpuop_func op_1010_4_nf;
-extern cpuop_func op_1010_4_ff;
-extern cpuop_func op_1018_4_nf;
-extern cpuop_func op_1018_4_ff;
-extern cpuop_func op_1020_4_nf;
-extern cpuop_func op_1020_4_ff;
-extern cpuop_func op_1028_4_nf;
-extern cpuop_func op_1028_4_ff;
-extern cpuop_func op_1030_4_nf;
-extern cpuop_func op_1030_4_ff;
-extern cpuop_func op_1038_4_nf;
-extern cpuop_func op_1038_4_ff;
-extern cpuop_func op_1039_4_nf;
-extern cpuop_func op_1039_4_ff;
-extern cpuop_func op_103a_4_nf;
-extern cpuop_func op_103a_4_ff;
-extern cpuop_func op_103b_4_nf;
-extern cpuop_func op_103b_4_ff;
-extern cpuop_func op_103c_4_nf;
-extern cpuop_func op_103c_4_ff;
-extern cpuop_func op_1080_4_nf;
-extern cpuop_func op_1080_4_ff;
-extern cpuop_func op_1088_4_nf;
-extern cpuop_func op_1088_4_ff;
-extern cpuop_func op_1090_4_nf;
-extern cpuop_func op_1090_4_ff;
-extern cpuop_func op_1098_4_nf;
-extern cpuop_func op_1098_4_ff;
-extern cpuop_func op_10a0_4_nf;
-extern cpuop_func op_10a0_4_ff;
-extern cpuop_func op_10a8_4_nf;
-extern cpuop_func op_10a8_4_ff;
-extern cpuop_func op_10b0_4_nf;
-extern cpuop_func op_10b0_4_ff;
-extern cpuop_func op_10b8_4_nf;
-extern cpuop_func op_10b8_4_ff;
-extern cpuop_func op_10b9_4_nf;
-extern cpuop_func op_10b9_4_ff;
-extern cpuop_func op_10ba_4_nf;
-extern cpuop_func op_10ba_4_ff;
-extern cpuop_func op_10bb_4_nf;
-extern cpuop_func op_10bb_4_ff;
-extern cpuop_func op_10bc_4_nf;
-extern cpuop_func op_10bc_4_ff;
-extern cpuop_func op_10c0_4_nf;
-extern cpuop_func op_10c0_4_ff;
-extern cpuop_func op_10c8_4_nf;
-extern cpuop_func op_10c8_4_ff;
-extern cpuop_func op_10d0_4_nf;
-extern cpuop_func op_10d0_4_ff;
-extern cpuop_func op_10d8_4_nf;
-extern cpuop_func op_10d8_4_ff;
-extern cpuop_func op_10e0_4_nf;
-extern cpuop_func op_10e0_4_ff;
-extern cpuop_func op_10e8_4_nf;
-extern cpuop_func op_10e8_4_ff;
-extern cpuop_func op_10f0_4_nf;
-extern cpuop_func op_10f0_4_ff;
-extern cpuop_func op_10f8_4_nf;
-extern cpuop_func op_10f8_4_ff;
-extern cpuop_func op_10f9_4_nf;
-extern cpuop_func op_10f9_4_ff;
-extern cpuop_func op_10fa_4_nf;
-extern cpuop_func op_10fa_4_ff;
-extern cpuop_func op_10fb_4_nf;
-extern cpuop_func op_10fb_4_ff;
-extern cpuop_func op_10fc_4_nf;
-extern cpuop_func op_10fc_4_ff;
-extern cpuop_func op_1100_4_nf;
-extern cpuop_func op_1100_4_ff;
-extern cpuop_func op_1108_4_nf;
-extern cpuop_func op_1108_4_ff;
-extern cpuop_func op_1110_4_nf;
-extern cpuop_func op_1110_4_ff;
-extern cpuop_func op_1118_4_nf;
-extern cpuop_func op_1118_4_ff;
-extern cpuop_func op_1120_4_nf;
-extern cpuop_func op_1120_4_ff;
-extern cpuop_func op_1128_4_nf;
-extern cpuop_func op_1128_4_ff;
-extern cpuop_func op_1130_4_nf;
-extern cpuop_func op_1130_4_ff;
-extern cpuop_func op_1138_4_nf;
-extern cpuop_func op_1138_4_ff;
-extern cpuop_func op_1139_4_nf;
-extern cpuop_func op_1139_4_ff;
-extern cpuop_func op_113a_4_nf;
-extern cpuop_func op_113a_4_ff;
-extern cpuop_func op_113b_4_nf;
-extern cpuop_func op_113b_4_ff;
-extern cpuop_func op_113c_4_nf;
-extern cpuop_func op_113c_4_ff;
-extern cpuop_func op_1140_4_nf;
-extern cpuop_func op_1140_4_ff;
-extern cpuop_func op_1148_4_nf;
-extern cpuop_func op_1148_4_ff;
-extern cpuop_func op_1150_4_nf;
-extern cpuop_func op_1150_4_ff;
-extern cpuop_func op_1158_4_nf;
-extern cpuop_func op_1158_4_ff;
-extern cpuop_func op_1160_4_nf;
-extern cpuop_func op_1160_4_ff;
-extern cpuop_func op_1168_4_nf;
-extern cpuop_func op_1168_4_ff;
-extern cpuop_func op_1170_4_nf;
-extern cpuop_func op_1170_4_ff;
-extern cpuop_func op_1178_4_nf;
-extern cpuop_func op_1178_4_ff;
-extern cpuop_func op_1179_4_nf;
-extern cpuop_func op_1179_4_ff;
-extern cpuop_func op_117a_4_nf;
-extern cpuop_func op_117a_4_ff;
-extern cpuop_func op_117b_4_nf;
-extern cpuop_func op_117b_4_ff;
-extern cpuop_func op_117c_4_nf;
-extern cpuop_func op_117c_4_ff;
-extern cpuop_func op_1180_4_nf;
-extern cpuop_func op_1180_4_ff;
-extern cpuop_func op_1188_4_nf;
-extern cpuop_func op_1188_4_ff;
-extern cpuop_func op_1190_4_nf;
-extern cpuop_func op_1190_4_ff;
-extern cpuop_func op_1198_4_nf;
-extern cpuop_func op_1198_4_ff;
-extern cpuop_func op_11a0_4_nf;
-extern cpuop_func op_11a0_4_ff;
-extern cpuop_func op_11a8_4_nf;
-extern cpuop_func op_11a8_4_ff;
-extern cpuop_func op_11b0_4_nf;
-extern cpuop_func op_11b0_4_ff;
-extern cpuop_func op_11b8_4_nf;
-extern cpuop_func op_11b8_4_ff;
-extern cpuop_func op_11b9_4_nf;
-extern cpuop_func op_11b9_4_ff;
-extern cpuop_func op_11ba_4_nf;
-extern cpuop_func op_11ba_4_ff;
-extern cpuop_func op_11bb_4_nf;
-extern cpuop_func op_11bb_4_ff;
-extern cpuop_func op_11bc_4_nf;
-extern cpuop_func op_11bc_4_ff;
-extern cpuop_func op_11c0_4_nf;
-extern cpuop_func op_11c0_4_ff;
-extern cpuop_func op_11c8_4_nf;
-extern cpuop_func op_11c8_4_ff;
-extern cpuop_func op_11d0_4_nf;
-extern cpuop_func op_11d0_4_ff;
-extern cpuop_func op_11d8_4_nf;
-extern cpuop_func op_11d8_4_ff;
-extern cpuop_func op_11e0_4_nf;
-extern cpuop_func op_11e0_4_ff;
-extern cpuop_func op_11e8_4_nf;
-extern cpuop_func op_11e8_4_ff;
-extern cpuop_func op_11f0_4_nf;
-extern cpuop_func op_11f0_4_ff;
-extern cpuop_func op_11f8_4_nf;
-extern cpuop_func op_11f8_4_ff;
-extern cpuop_func op_11f9_4_nf;
-extern cpuop_func op_11f9_4_ff;
-extern cpuop_func op_11fa_4_nf;
-extern cpuop_func op_11fa_4_ff;
-extern cpuop_func op_11fb_4_nf;
-extern cpuop_func op_11fb_4_ff;
-extern cpuop_func op_11fc_4_nf;
-extern cpuop_func op_11fc_4_ff;
-extern cpuop_func op_13c0_4_nf;
-extern cpuop_func op_13c0_4_ff;
-extern cpuop_func op_13c8_4_nf;
-extern cpuop_func op_13c8_4_ff;
-extern cpuop_func op_13d0_4_nf;
-extern cpuop_func op_13d0_4_ff;
-extern cpuop_func op_13d8_4_nf;
-extern cpuop_func op_13d8_4_ff;
-extern cpuop_func op_13e0_4_nf;
-extern cpuop_func op_13e0_4_ff;
-extern cpuop_func op_13e8_4_nf;
-extern cpuop_func op_13e8_4_ff;
-extern cpuop_func op_13f0_4_nf;
-extern cpuop_func op_13f0_4_ff;
-extern cpuop_func op_13f8_4_nf;
-extern cpuop_func op_13f8_4_ff;
-extern cpuop_func op_13f9_4_nf;
-extern cpuop_func op_13f9_4_ff;
-extern cpuop_func op_13fa_4_nf;
-extern cpuop_func op_13fa_4_ff;
-extern cpuop_func op_13fb_4_nf;
-extern cpuop_func op_13fb_4_ff;
-extern cpuop_func op_13fc_4_nf;
-extern cpuop_func op_13fc_4_ff;
-extern cpuop_func op_2000_4_nf;
-extern cpuop_func op_2000_4_ff;
-extern cpuop_func op_2008_4_nf;
-extern cpuop_func op_2008_4_ff;
-extern cpuop_func op_2010_4_nf;
-extern cpuop_func op_2010_4_ff;
-extern cpuop_func op_2018_4_nf;
-extern cpuop_func op_2018_4_ff;
-extern cpuop_func op_2020_4_nf;
-extern cpuop_func op_2020_4_ff;
-extern cpuop_func op_2028_4_nf;
-extern cpuop_func op_2028_4_ff;
-extern cpuop_func op_2030_4_nf;
-extern cpuop_func op_2030_4_ff;
-extern cpuop_func op_2038_4_nf;
-extern cpuop_func op_2038_4_ff;
-extern cpuop_func op_2039_4_nf;
-extern cpuop_func op_2039_4_ff;
-extern cpuop_func op_203a_4_nf;
-extern cpuop_func op_203a_4_ff;
-extern cpuop_func op_203b_4_nf;
-extern cpuop_func op_203b_4_ff;
-extern cpuop_func op_203c_4_nf;
-extern cpuop_func op_203c_4_ff;
-extern cpuop_func op_2040_4_nf;
-extern cpuop_func op_2040_4_ff;
-extern cpuop_func op_2048_4_nf;
-extern cpuop_func op_2048_4_ff;
-extern cpuop_func op_2050_4_nf;
-extern cpuop_func op_2050_4_ff;
-extern cpuop_func op_2058_4_nf;
-extern cpuop_func op_2058_4_ff;
-extern cpuop_func op_2060_4_nf;
-extern cpuop_func op_2060_4_ff;
-extern cpuop_func op_2068_4_nf;
-extern cpuop_func op_2068_4_ff;
-extern cpuop_func op_2070_4_nf;
-extern cpuop_func op_2070_4_ff;
-extern cpuop_func op_2078_4_nf;
-extern cpuop_func op_2078_4_ff;
-extern cpuop_func op_2079_4_nf;
-extern cpuop_func op_2079_4_ff;
-extern cpuop_func op_207a_4_nf;
-extern cpuop_func op_207a_4_ff;
-extern cpuop_func op_207b_4_nf;
-extern cpuop_func op_207b_4_ff;
-extern cpuop_func op_207c_4_nf;
-extern cpuop_func op_207c_4_ff;
-extern cpuop_func op_2080_4_nf;
-extern cpuop_func op_2080_4_ff;
-extern cpuop_func op_2088_4_nf;
-extern cpuop_func op_2088_4_ff;
-extern cpuop_func op_2090_4_nf;
-extern cpuop_func op_2090_4_ff;
-extern cpuop_func op_2098_4_nf;
-extern cpuop_func op_2098_4_ff;
-extern cpuop_func op_20a0_4_nf;
-extern cpuop_func op_20a0_4_ff;
-extern cpuop_func op_20a8_4_nf;
-extern cpuop_func op_20a8_4_ff;
-extern cpuop_func op_20b0_4_nf;
-extern cpuop_func op_20b0_4_ff;
-extern cpuop_func op_20b8_4_nf;
-extern cpuop_func op_20b8_4_ff;
-extern cpuop_func op_20b9_4_nf;
-extern cpuop_func op_20b9_4_ff;
-extern cpuop_func op_20ba_4_nf;
-extern cpuop_func op_20ba_4_ff;
-extern cpuop_func op_20bb_4_nf;
-extern cpuop_func op_20bb_4_ff;
-extern cpuop_func op_20bc_4_nf;
-extern cpuop_func op_20bc_4_ff;
-extern cpuop_func op_20c0_4_nf;
-extern cpuop_func op_20c0_4_ff;
-extern cpuop_func op_20c8_4_nf;
-extern cpuop_func op_20c8_4_ff;
-extern cpuop_func op_20d0_4_nf;
-extern cpuop_func op_20d0_4_ff;
-extern cpuop_func op_20d8_4_nf;
-extern cpuop_func op_20d8_4_ff;
-extern cpuop_func op_20e0_4_nf;
-extern cpuop_func op_20e0_4_ff;
-extern cpuop_func op_20e8_4_nf;
-extern cpuop_func op_20e8_4_ff;
-extern cpuop_func op_20f0_4_nf;
-extern cpuop_func op_20f0_4_ff;
-extern cpuop_func op_20f8_4_nf;
-extern cpuop_func op_20f8_4_ff;
-extern cpuop_func op_20f9_4_nf;
-extern cpuop_func op_20f9_4_ff;
-extern cpuop_func op_20fa_4_nf;
-extern cpuop_func op_20fa_4_ff;
-extern cpuop_func op_20fb_4_nf;
-extern cpuop_func op_20fb_4_ff;
-extern cpuop_func op_20fc_4_nf;
-extern cpuop_func op_20fc_4_ff;
-extern cpuop_func op_2100_4_nf;
-extern cpuop_func op_2100_4_ff;
-extern cpuop_func op_2108_4_nf;
-extern cpuop_func op_2108_4_ff;
-extern cpuop_func op_2110_4_nf;
-extern cpuop_func op_2110_4_ff;
-extern cpuop_func op_2118_4_nf;
-extern cpuop_func op_2118_4_ff;
-extern cpuop_func op_2120_4_nf;
-extern cpuop_func op_2120_4_ff;
-extern cpuop_func op_2128_4_nf;
-extern cpuop_func op_2128_4_ff;
-extern cpuop_func op_2130_4_nf;
-extern cpuop_func op_2130_4_ff;
-extern cpuop_func op_2138_4_nf;
-extern cpuop_func op_2138_4_ff;
-extern cpuop_func op_2139_4_nf;
-extern cpuop_func op_2139_4_ff;
-extern cpuop_func op_213a_4_nf;
-extern cpuop_func op_213a_4_ff;
-extern cpuop_func op_213b_4_nf;
-extern cpuop_func op_213b_4_ff;
-extern cpuop_func op_213c_4_nf;
-extern cpuop_func op_213c_4_ff;
-extern cpuop_func op_2140_4_nf;
-extern cpuop_func op_2140_4_ff;
-extern cpuop_func op_2148_4_nf;
-extern cpuop_func op_2148_4_ff;
-extern cpuop_func op_2150_4_nf;
-extern cpuop_func op_2150_4_ff;
-extern cpuop_func op_2158_4_nf;
-extern cpuop_func op_2158_4_ff;
-extern cpuop_func op_2160_4_nf;
-extern cpuop_func op_2160_4_ff;
-extern cpuop_func op_2168_4_nf;
-extern cpuop_func op_2168_4_ff;
-extern cpuop_func op_2170_4_nf;
-extern cpuop_func op_2170_4_ff;
-extern cpuop_func op_2178_4_nf;
-extern cpuop_func op_2178_4_ff;
-extern cpuop_func op_2179_4_nf;
-extern cpuop_func op_2179_4_ff;
-extern cpuop_func op_217a_4_nf;
-extern cpuop_func op_217a_4_ff;
-extern cpuop_func op_217b_4_nf;
-extern cpuop_func op_217b_4_ff;
-extern cpuop_func op_217c_4_nf;
-extern cpuop_func op_217c_4_ff;
-extern cpuop_func op_2180_4_nf;
-extern cpuop_func op_2180_4_ff;
-extern cpuop_func op_2188_4_nf;
-extern cpuop_func op_2188_4_ff;
-extern cpuop_func op_2190_4_nf;
-extern cpuop_func op_2190_4_ff;
-extern cpuop_func op_2198_4_nf;
-extern cpuop_func op_2198_4_ff;
-extern cpuop_func op_21a0_4_nf;
-extern cpuop_func op_21a0_4_ff;
-extern cpuop_func op_21a8_4_nf;
-extern cpuop_func op_21a8_4_ff;
-extern cpuop_func op_21b0_4_nf;
-extern cpuop_func op_21b0_4_ff;
-extern cpuop_func op_21b8_4_nf;
-extern cpuop_func op_21b8_4_ff;
-extern cpuop_func op_21b9_4_nf;
-extern cpuop_func op_21b9_4_ff;
-extern cpuop_func op_21ba_4_nf;
-extern cpuop_func op_21ba_4_ff;
-extern cpuop_func op_21bb_4_nf;
-extern cpuop_func op_21bb_4_ff;
-extern cpuop_func op_21bc_4_nf;
-extern cpuop_func op_21bc_4_ff;
-extern cpuop_func op_21c0_4_nf;
-extern cpuop_func op_21c0_4_ff;
-extern cpuop_func op_21c8_4_nf;
-extern cpuop_func op_21c8_4_ff;
-extern cpuop_func op_21d0_4_nf;
-extern cpuop_func op_21d0_4_ff;
-extern cpuop_func op_21d8_4_nf;
-extern cpuop_func op_21d8_4_ff;
-extern cpuop_func op_21e0_4_nf;
-extern cpuop_func op_21e0_4_ff;
-extern cpuop_func op_21e8_4_nf;
-extern cpuop_func op_21e8_4_ff;
-extern cpuop_func op_21f0_4_nf;
-extern cpuop_func op_21f0_4_ff;
-extern cpuop_func op_21f8_4_nf;
-extern cpuop_func op_21f8_4_ff;
-extern cpuop_func op_21f9_4_nf;
-extern cpuop_func op_21f9_4_ff;
-extern cpuop_func op_21fa_4_nf;
-extern cpuop_func op_21fa_4_ff;
-extern cpuop_func op_21fb_4_nf;
-extern cpuop_func op_21fb_4_ff;
-extern cpuop_func op_21fc_4_nf;
-extern cpuop_func op_21fc_4_ff;
-extern cpuop_func op_23c0_4_nf;
-extern cpuop_func op_23c0_4_ff;
-extern cpuop_func op_23c8_4_nf;
-extern cpuop_func op_23c8_4_ff;
-extern cpuop_func op_23d0_4_nf;
-extern cpuop_func op_23d0_4_ff;
-extern cpuop_func op_23d8_4_nf;
-extern cpuop_func op_23d8_4_ff;
-extern cpuop_func op_23e0_4_nf;
-extern cpuop_func op_23e0_4_ff;
-extern cpuop_func op_23e8_4_nf;
-extern cpuop_func op_23e8_4_ff;
-extern cpuop_func op_23f0_4_nf;
-extern cpuop_func op_23f0_4_ff;
-extern cpuop_func op_23f8_4_nf;
-extern cpuop_func op_23f8_4_ff;
-extern cpuop_func op_23f9_4_nf;
-extern cpuop_func op_23f9_4_ff;
-extern cpuop_func op_23fa_4_nf;
-extern cpuop_func op_23fa_4_ff;
-extern cpuop_func op_23fb_4_nf;
-extern cpuop_func op_23fb_4_ff;
-extern cpuop_func op_23fc_4_nf;
-extern cpuop_func op_23fc_4_ff;
-extern cpuop_func op_3000_4_nf;
-extern cpuop_func op_3000_4_ff;
-extern cpuop_func op_3008_4_nf;
-extern cpuop_func op_3008_4_ff;
-extern cpuop_func op_3010_4_nf;
-extern cpuop_func op_3010_4_ff;
-extern cpuop_func op_3018_4_nf;
-extern cpuop_func op_3018_4_ff;
-extern cpuop_func op_3020_4_nf;
-extern cpuop_func op_3020_4_ff;
-extern cpuop_func op_3028_4_nf;
-extern cpuop_func op_3028_4_ff;
-extern cpuop_func op_3030_4_nf;
-extern cpuop_func op_3030_4_ff;
-extern cpuop_func op_3038_4_nf;
-extern cpuop_func op_3038_4_ff;
-extern cpuop_func op_3039_4_nf;
-extern cpuop_func op_3039_4_ff;
-extern cpuop_func op_303a_4_nf;
-extern cpuop_func op_303a_4_ff;
-extern cpuop_func op_303b_4_nf;
-extern cpuop_func op_303b_4_ff;
-extern cpuop_func op_303c_4_nf;
-extern cpuop_func op_303c_4_ff;
-extern cpuop_func op_3040_4_nf;
-extern cpuop_func op_3040_4_ff;
-extern cpuop_func op_3048_4_nf;
-extern cpuop_func op_3048_4_ff;
-extern cpuop_func op_3050_4_nf;
-extern cpuop_func op_3050_4_ff;
-extern cpuop_func op_3058_4_nf;
-extern cpuop_func op_3058_4_ff;
-extern cpuop_func op_3060_4_nf;
-extern cpuop_func op_3060_4_ff;
-extern cpuop_func op_3068_4_nf;
-extern cpuop_func op_3068_4_ff;
-extern cpuop_func op_3070_4_nf;
-extern cpuop_func op_3070_4_ff;
-extern cpuop_func op_3078_4_nf;
-extern cpuop_func op_3078_4_ff;
-extern cpuop_func op_3079_4_nf;
-extern cpuop_func op_3079_4_ff;
-extern cpuop_func op_307a_4_nf;
-extern cpuop_func op_307a_4_ff;
-extern cpuop_func op_307b_4_nf;
-extern cpuop_func op_307b_4_ff;
-extern cpuop_func op_307c_4_nf;
-extern cpuop_func op_307c_4_ff;
-extern cpuop_func op_3080_4_nf;
-extern cpuop_func op_3080_4_ff;
-extern cpuop_func op_3088_4_nf;
-extern cpuop_func op_3088_4_ff;
-extern cpuop_func op_3090_4_nf;
-extern cpuop_func op_3090_4_ff;
-extern cpuop_func op_3098_4_nf;
-extern cpuop_func op_3098_4_ff;
-extern cpuop_func op_30a0_4_nf;
-extern cpuop_func op_30a0_4_ff;
-extern cpuop_func op_30a8_4_nf;
-extern cpuop_func op_30a8_4_ff;
-extern cpuop_func op_30b0_4_nf;
-extern cpuop_func op_30b0_4_ff;
-extern cpuop_func op_30b8_4_nf;
-extern cpuop_func op_30b8_4_ff;
-extern cpuop_func op_30b9_4_nf;
-extern cpuop_func op_30b9_4_ff;
-extern cpuop_func op_30ba_4_nf;
-extern cpuop_func op_30ba_4_ff;
-extern cpuop_func op_30bb_4_nf;
-extern cpuop_func op_30bb_4_ff;
-extern cpuop_func op_30bc_4_nf;
-extern cpuop_func op_30bc_4_ff;
-extern cpuop_func op_30c0_4_nf;
-extern cpuop_func op_30c0_4_ff;
-extern cpuop_func op_30c8_4_nf;
-extern cpuop_func op_30c8_4_ff;
-extern cpuop_func op_30d0_4_nf;
-extern cpuop_func op_30d0_4_ff;
-extern cpuop_func op_30d8_4_nf;
-extern cpuop_func op_30d8_4_ff;
-extern cpuop_func op_30e0_4_nf;
-extern cpuop_func op_30e0_4_ff;
-extern cpuop_func op_30e8_4_nf;
-extern cpuop_func op_30e8_4_ff;
-extern cpuop_func op_30f0_4_nf;
-extern cpuop_func op_30f0_4_ff;
-extern cpuop_func op_30f8_4_nf;
-extern cpuop_func op_30f8_4_ff;
-extern cpuop_func op_30f9_4_nf;
-extern cpuop_func op_30f9_4_ff;
-extern cpuop_func op_30fa_4_nf;
-extern cpuop_func op_30fa_4_ff;
-extern cpuop_func op_30fb_4_nf;
-extern cpuop_func op_30fb_4_ff;
-extern cpuop_func op_30fc_4_nf;
-extern cpuop_func op_30fc_4_ff;
-extern cpuop_func op_3100_4_nf;
-extern cpuop_func op_3100_4_ff;
-extern cpuop_func op_3108_4_nf;
-extern cpuop_func op_3108_4_ff;
-extern cpuop_func op_3110_4_nf;
-extern cpuop_func op_3110_4_ff;
-extern cpuop_func op_3118_4_nf;
-extern cpuop_func op_3118_4_ff;
-extern cpuop_func op_3120_4_nf;
-extern cpuop_func op_3120_4_ff;
-extern cpuop_func op_3128_4_nf;
-extern cpuop_func op_3128_4_ff;
-extern cpuop_func op_3130_4_nf;
-extern cpuop_func op_3130_4_ff;
-extern cpuop_func op_3138_4_nf;
-extern cpuop_func op_3138_4_ff;
-extern cpuop_func op_3139_4_nf;
-extern cpuop_func op_3139_4_ff;
-extern cpuop_func op_313a_4_nf;
-extern cpuop_func op_313a_4_ff;
-extern cpuop_func op_313b_4_nf;
-extern cpuop_func op_313b_4_ff;
-extern cpuop_func op_313c_4_nf;
-extern cpuop_func op_313c_4_ff;
-extern cpuop_func op_3140_4_nf;
-extern cpuop_func op_3140_4_ff;
-extern cpuop_func op_3148_4_nf;
-extern cpuop_func op_3148_4_ff;
-extern cpuop_func op_3150_4_nf;
-extern cpuop_func op_3150_4_ff;
-extern cpuop_func op_3158_4_nf;
-extern cpuop_func op_3158_4_ff;
-extern cpuop_func op_3160_4_nf;
-extern cpuop_func op_3160_4_ff;
-extern cpuop_func op_3168_4_nf;
-extern cpuop_func op_3168_4_ff;
-extern cpuop_func op_3170_4_nf;
-extern cpuop_func op_3170_4_ff;
-extern cpuop_func op_3178_4_nf;
-extern cpuop_func op_3178_4_ff;
-extern cpuop_func op_3179_4_nf;
-extern cpuop_func op_3179_4_ff;
-extern cpuop_func op_317a_4_nf;
-extern cpuop_func op_317a_4_ff;
-extern cpuop_func op_317b_4_nf;
-extern cpuop_func op_317b_4_ff;
-extern cpuop_func op_317c_4_nf;
-extern cpuop_func op_317c_4_ff;
-extern cpuop_func op_3180_4_nf;
-extern cpuop_func op_3180_4_ff;
-extern cpuop_func op_3188_4_nf;
-extern cpuop_func op_3188_4_ff;
-extern cpuop_func op_3190_4_nf;
-extern cpuop_func op_3190_4_ff;
-extern cpuop_func op_3198_4_nf;
-extern cpuop_func op_3198_4_ff;
-extern cpuop_func op_31a0_4_nf;
-extern cpuop_func op_31a0_4_ff;
-extern cpuop_func op_31a8_4_nf;
-extern cpuop_func op_31a8_4_ff;
-extern cpuop_func op_31b0_4_nf;
-extern cpuop_func op_31b0_4_ff;
-extern cpuop_func op_31b8_4_nf;
-extern cpuop_func op_31b8_4_ff;
-extern cpuop_func op_31b9_4_nf;
-extern cpuop_func op_31b9_4_ff;
-extern cpuop_func op_31ba_4_nf;
-extern cpuop_func op_31ba_4_ff;
-extern cpuop_func op_31bb_4_nf;
-extern cpuop_func op_31bb_4_ff;
-extern cpuop_func op_31bc_4_nf;
-extern cpuop_func op_31bc_4_ff;
-extern cpuop_func op_31c0_4_nf;
-extern cpuop_func op_31c0_4_ff;
-extern cpuop_func op_31c8_4_nf;
-extern cpuop_func op_31c8_4_ff;
-extern cpuop_func op_31d0_4_nf;
-extern cpuop_func op_31d0_4_ff;
-extern cpuop_func op_31d8_4_nf;
-extern cpuop_func op_31d8_4_ff;
-extern cpuop_func op_31e0_4_nf;
-extern cpuop_func op_31e0_4_ff;
-extern cpuop_func op_31e8_4_nf;
-extern cpuop_func op_31e8_4_ff;
-extern cpuop_func op_31f0_4_nf;
-extern cpuop_func op_31f0_4_ff;
-extern cpuop_func op_31f8_4_nf;
-extern cpuop_func op_31f8_4_ff;
-extern cpuop_func op_31f9_4_nf;
-extern cpuop_func op_31f9_4_ff;
-extern cpuop_func op_31fa_4_nf;
-extern cpuop_func op_31fa_4_ff;
-extern cpuop_func op_31fb_4_nf;
-extern cpuop_func op_31fb_4_ff;
-extern cpuop_func op_31fc_4_nf;
-extern cpuop_func op_31fc_4_ff;
-extern cpuop_func op_33c0_4_nf;
-extern cpuop_func op_33c0_4_ff;
-extern cpuop_func op_33c8_4_nf;
-extern cpuop_func op_33c8_4_ff;
-extern cpuop_func op_33d0_4_nf;
-extern cpuop_func op_33d0_4_ff;
-extern cpuop_func op_33d8_4_nf;
-extern cpuop_func op_33d8_4_ff;
-extern cpuop_func op_33e0_4_nf;
-extern cpuop_func op_33e0_4_ff;
-extern cpuop_func op_33e8_4_nf;
-extern cpuop_func op_33e8_4_ff;
-extern cpuop_func op_33f0_4_nf;
-extern cpuop_func op_33f0_4_ff;
-extern cpuop_func op_33f8_4_nf;
-extern cpuop_func op_33f8_4_ff;
-extern cpuop_func op_33f9_4_nf;
-extern cpuop_func op_33f9_4_ff;
-extern cpuop_func op_33fa_4_nf;
-extern cpuop_func op_33fa_4_ff;
-extern cpuop_func op_33fb_4_nf;
-extern cpuop_func op_33fb_4_ff;
-extern cpuop_func op_33fc_4_nf;
-extern cpuop_func op_33fc_4_ff;
-extern cpuop_func op_4000_4_nf;
-extern cpuop_func op_4000_4_ff;
-extern cpuop_func op_4010_4_nf;
-extern cpuop_func op_4010_4_ff;
-extern cpuop_func op_4018_4_nf;
-extern cpuop_func op_4018_4_ff;
-extern cpuop_func op_4020_4_nf;
-extern cpuop_func op_4020_4_ff;
-extern cpuop_func op_4028_4_nf;
-extern cpuop_func op_4028_4_ff;
-extern cpuop_func op_4030_4_nf;
-extern cpuop_func op_4030_4_ff;
-extern cpuop_func op_4038_4_nf;
-extern cpuop_func op_4038_4_ff;
-extern cpuop_func op_4039_4_nf;
-extern cpuop_func op_4039_4_ff;
-extern cpuop_func op_4040_4_nf;
-extern cpuop_func op_4040_4_ff;
-extern cpuop_func op_4050_4_nf;
-extern cpuop_func op_4050_4_ff;
-extern cpuop_func op_4058_4_nf;
-extern cpuop_func op_4058_4_ff;
-extern cpuop_func op_4060_4_nf;
-extern cpuop_func op_4060_4_ff;
-extern cpuop_func op_4068_4_nf;
-extern cpuop_func op_4068_4_ff;
-extern cpuop_func op_4070_4_nf;
-extern cpuop_func op_4070_4_ff;
-extern cpuop_func op_4078_4_nf;
-extern cpuop_func op_4078_4_ff;
-extern cpuop_func op_4079_4_nf;
-extern cpuop_func op_4079_4_ff;
-extern cpuop_func op_4080_4_nf;
-extern cpuop_func op_4080_4_ff;
-extern cpuop_func op_4090_4_nf;
-extern cpuop_func op_4090_4_ff;
-extern cpuop_func op_4098_4_nf;
-extern cpuop_func op_4098_4_ff;
-extern cpuop_func op_40a0_4_nf;
-extern cpuop_func op_40a0_4_ff;
-extern cpuop_func op_40a8_4_nf;
-extern cpuop_func op_40a8_4_ff;
-extern cpuop_func op_40b0_4_nf;
-extern cpuop_func op_40b0_4_ff;
-extern cpuop_func op_40b8_4_nf;
-extern cpuop_func op_40b8_4_ff;
-extern cpuop_func op_40b9_4_nf;
-extern cpuop_func op_40b9_4_ff;
-extern cpuop_func op_40c0_4_nf;
-extern cpuop_func op_40c0_4_ff;
-extern cpuop_func op_40d0_4_nf;
-extern cpuop_func op_40d0_4_ff;
-extern cpuop_func op_40d8_4_nf;
-extern cpuop_func op_40d8_4_ff;
-extern cpuop_func op_40e0_4_nf;
-extern cpuop_func op_40e0_4_ff;
-extern cpuop_func op_40e8_4_nf;
-extern cpuop_func op_40e8_4_ff;
-extern cpuop_func op_40f0_4_nf;
-extern cpuop_func op_40f0_4_ff;
-extern cpuop_func op_40f8_4_nf;
-extern cpuop_func op_40f8_4_ff;
-extern cpuop_func op_40f9_4_nf;
-extern cpuop_func op_40f9_4_ff;
-extern cpuop_func op_4180_4_nf;
-extern cpuop_func op_4180_4_ff;
-extern cpuop_func op_4190_4_nf;
-extern cpuop_func op_4190_4_ff;
-extern cpuop_func op_4198_4_nf;
-extern cpuop_func op_4198_4_ff;
-extern cpuop_func op_41a0_4_nf;
-extern cpuop_func op_41a0_4_ff;
-extern cpuop_func op_41a8_4_nf;
-extern cpuop_func op_41a8_4_ff;
-extern cpuop_func op_41b0_4_nf;
-extern cpuop_func op_41b0_4_ff;
-extern cpuop_func op_41b8_4_nf;
-extern cpuop_func op_41b8_4_ff;
-extern cpuop_func op_41b9_4_nf;
-extern cpuop_func op_41b9_4_ff;
-extern cpuop_func op_41ba_4_nf;
-extern cpuop_func op_41ba_4_ff;
-extern cpuop_func op_41bb_4_nf;
-extern cpuop_func op_41bb_4_ff;
-extern cpuop_func op_41bc_4_nf;
-extern cpuop_func op_41bc_4_ff;
-extern cpuop_func op_41d0_4_nf;
-extern cpuop_func op_41d0_4_ff;
-extern cpuop_func op_41e8_4_nf;
-extern cpuop_func op_41e8_4_ff;
-extern cpuop_func op_41f0_4_nf;
-extern cpuop_func op_41f0_4_ff;
-extern cpuop_func op_41f8_4_nf;
-extern cpuop_func op_41f8_4_ff;
-extern cpuop_func op_41f9_4_nf;
-extern cpuop_func op_41f9_4_ff;
-extern cpuop_func op_41fa_4_nf;
-extern cpuop_func op_41fa_4_ff;
-extern cpuop_func op_41fb_4_nf;
-extern cpuop_func op_41fb_4_ff;
-extern cpuop_func op_4200_4_nf;
-extern cpuop_func op_4200_4_ff;
-extern cpuop_func op_4210_4_nf;
-extern cpuop_func op_4210_4_ff;
-extern cpuop_func op_4218_4_nf;
-extern cpuop_func op_4218_4_ff;
-extern cpuop_func op_4220_4_nf;
-extern cpuop_func op_4220_4_ff;
-extern cpuop_func op_4228_4_nf;
-extern cpuop_func op_4228_4_ff;
-extern cpuop_func op_4230_4_nf;
-extern cpuop_func op_4230_4_ff;
-extern cpuop_func op_4238_4_nf;
-extern cpuop_func op_4238_4_ff;
-extern cpuop_func op_4239_4_nf;
-extern cpuop_func op_4239_4_ff;
-extern cpuop_func op_4240_4_nf;
-extern cpuop_func op_4240_4_ff;
-extern cpuop_func op_4250_4_nf;
-extern cpuop_func op_4250_4_ff;
-extern cpuop_func op_4258_4_nf;
-extern cpuop_func op_4258_4_ff;
-extern cpuop_func op_4260_4_nf;
-extern cpuop_func op_4260_4_ff;
-extern cpuop_func op_4268_4_nf;
-extern cpuop_func op_4268_4_ff;
-extern cpuop_func op_4270_4_nf;
-extern cpuop_func op_4270_4_ff;
-extern cpuop_func op_4278_4_nf;
-extern cpuop_func op_4278_4_ff;
-extern cpuop_func op_4279_4_nf;
-extern cpuop_func op_4279_4_ff;
-extern cpuop_func op_4280_4_nf;
-extern cpuop_func op_4280_4_ff;
-extern cpuop_func op_4290_4_nf;
-extern cpuop_func op_4290_4_ff;
-extern cpuop_func op_4298_4_nf;
-extern cpuop_func op_4298_4_ff;
-extern cpuop_func op_42a0_4_nf;
-extern cpuop_func op_42a0_4_ff;
-extern cpuop_func op_42a8_4_nf;
-extern cpuop_func op_42a8_4_ff;
-extern cpuop_func op_42b0_4_nf;
-extern cpuop_func op_42b0_4_ff;
-extern cpuop_func op_42b8_4_nf;
-extern cpuop_func op_42b8_4_ff;
-extern cpuop_func op_42b9_4_nf;
-extern cpuop_func op_42b9_4_ff;
-extern cpuop_func op_4400_4_nf;
-extern cpuop_func op_4400_4_ff;
-extern cpuop_func op_4410_4_nf;
-extern cpuop_func op_4410_4_ff;
-extern cpuop_func op_4418_4_nf;
-extern cpuop_func op_4418_4_ff;
-extern cpuop_func op_4420_4_nf;
-extern cpuop_func op_4420_4_ff;
-extern cpuop_func op_4428_4_nf;
-extern cpuop_func op_4428_4_ff;
-extern cpuop_func op_4430_4_nf;
-extern cpuop_func op_4430_4_ff;
-extern cpuop_func op_4438_4_nf;
-extern cpuop_func op_4438_4_ff;
-extern cpuop_func op_4439_4_nf;
-extern cpuop_func op_4439_4_ff;
-extern cpuop_func op_4440_4_nf;
-extern cpuop_func op_4440_4_ff;
-extern cpuop_func op_4450_4_nf;
-extern cpuop_func op_4450_4_ff;
-extern cpuop_func op_4458_4_nf;
-extern cpuop_func op_4458_4_ff;
-extern cpuop_func op_4460_4_nf;
-extern cpuop_func op_4460_4_ff;
-extern cpuop_func op_4468_4_nf;
-extern cpuop_func op_4468_4_ff;
-extern cpuop_func op_4470_4_nf;
-extern cpuop_func op_4470_4_ff;
-extern cpuop_func op_4478_4_nf;
-extern cpuop_func op_4478_4_ff;
-extern cpuop_func op_4479_4_nf;
-extern cpuop_func op_4479_4_ff;
-extern cpuop_func op_4480_4_nf;
-extern cpuop_func op_4480_4_ff;
-extern cpuop_func op_4490_4_nf;
-extern cpuop_func op_4490_4_ff;
-extern cpuop_func op_4498_4_nf;
-extern cpuop_func op_4498_4_ff;
-extern cpuop_func op_44a0_4_nf;
-extern cpuop_func op_44a0_4_ff;
-extern cpuop_func op_44a8_4_nf;
-extern cpuop_func op_44a8_4_ff;
-extern cpuop_func op_44b0_4_nf;
-extern cpuop_func op_44b0_4_ff;
-extern cpuop_func op_44b8_4_nf;
-extern cpuop_func op_44b8_4_ff;
-extern cpuop_func op_44b9_4_nf;
-extern cpuop_func op_44b9_4_ff;
-extern cpuop_func op_44c0_4_nf;
-extern cpuop_func op_44c0_4_ff;
-extern cpuop_func op_44d0_4_nf;
-extern cpuop_func op_44d0_4_ff;
-extern cpuop_func op_44d8_4_nf;
-extern cpuop_func op_44d8_4_ff;
-extern cpuop_func op_44e0_4_nf;
-extern cpuop_func op_44e0_4_ff;
-extern cpuop_func op_44e8_4_nf;
-extern cpuop_func op_44e8_4_ff;
-extern cpuop_func op_44f0_4_nf;
-extern cpuop_func op_44f0_4_ff;
-extern cpuop_func op_44f8_4_nf;
-extern cpuop_func op_44f8_4_ff;
-extern cpuop_func op_44f9_4_nf;
-extern cpuop_func op_44f9_4_ff;
-extern cpuop_func op_44fa_4_nf;
-extern cpuop_func op_44fa_4_ff;
-extern cpuop_func op_44fb_4_nf;
-extern cpuop_func op_44fb_4_ff;
-extern cpuop_func op_44fc_4_nf;
-extern cpuop_func op_44fc_4_ff;
-extern cpuop_func op_4600_4_nf;
-extern cpuop_func op_4600_4_ff;
-extern cpuop_func op_4610_4_nf;
-extern cpuop_func op_4610_4_ff;
-extern cpuop_func op_4618_4_nf;
-extern cpuop_func op_4618_4_ff;
-extern cpuop_func op_4620_4_nf;
-extern cpuop_func op_4620_4_ff;
-extern cpuop_func op_4628_4_nf;
-extern cpuop_func op_4628_4_ff;
-extern cpuop_func op_4630_4_nf;
-extern cpuop_func op_4630_4_ff;
-extern cpuop_func op_4638_4_nf;
-extern cpuop_func op_4638_4_ff;
-extern cpuop_func op_4639_4_nf;
-extern cpuop_func op_4639_4_ff;
-extern cpuop_func op_4640_4_nf;
-extern cpuop_func op_4640_4_ff;
-extern cpuop_func op_4650_4_nf;
-extern cpuop_func op_4650_4_ff;
-extern cpuop_func op_4658_4_nf;
-extern cpuop_func op_4658_4_ff;
-extern cpuop_func op_4660_4_nf;
-extern cpuop_func op_4660_4_ff;
-extern cpuop_func op_4668_4_nf;
-extern cpuop_func op_4668_4_ff;
-extern cpuop_func op_4670_4_nf;
-extern cpuop_func op_4670_4_ff;
-extern cpuop_func op_4678_4_nf;
-extern cpuop_func op_4678_4_ff;
-extern cpuop_func op_4679_4_nf;
-extern cpuop_func op_4679_4_ff;
-extern cpuop_func op_4680_4_nf;
-extern cpuop_func op_4680_4_ff;
-extern cpuop_func op_4690_4_nf;
-extern cpuop_func op_4690_4_ff;
-extern cpuop_func op_4698_4_nf;
-extern cpuop_func op_4698_4_ff;
-extern cpuop_func op_46a0_4_nf;
-extern cpuop_func op_46a0_4_ff;
-extern cpuop_func op_46a8_4_nf;
-extern cpuop_func op_46a8_4_ff;
-extern cpuop_func op_46b0_4_nf;
-extern cpuop_func op_46b0_4_ff;
-extern cpuop_func op_46b8_4_nf;
-extern cpuop_func op_46b8_4_ff;
-extern cpuop_func op_46b9_4_nf;
-extern cpuop_func op_46b9_4_ff;
-extern cpuop_func op_46c0_4_nf;
-extern cpuop_func op_46c0_4_ff;
-extern cpuop_func op_46d0_4_nf;
-extern cpuop_func op_46d0_4_ff;
-extern cpuop_func op_46d8_4_nf;
-extern cpuop_func op_46d8_4_ff;
-extern cpuop_func op_46e0_4_nf;
-extern cpuop_func op_46e0_4_ff;
-extern cpuop_func op_46e8_4_nf;
-extern cpuop_func op_46e8_4_ff;
-extern cpuop_func op_46f0_4_nf;
-extern cpuop_func op_46f0_4_ff;
-extern cpuop_func op_46f8_4_nf;
-extern cpuop_func op_46f8_4_ff;
-extern cpuop_func op_46f9_4_nf;
-extern cpuop_func op_46f9_4_ff;
-extern cpuop_func op_46fa_4_nf;
-extern cpuop_func op_46fa_4_ff;
-extern cpuop_func op_46fb_4_nf;
-extern cpuop_func op_46fb_4_ff;
-extern cpuop_func op_46fc_4_nf;
-extern cpuop_func op_46fc_4_ff;
-extern cpuop_func op_4800_4_nf;
-extern cpuop_func op_4800_4_ff;
-extern cpuop_func op_4810_4_nf;
-extern cpuop_func op_4810_4_ff;
-extern cpuop_func op_4818_4_nf;
-extern cpuop_func op_4818_4_ff;
-extern cpuop_func op_4820_4_nf;
-extern cpuop_func op_4820_4_ff;
-extern cpuop_func op_4828_4_nf;
-extern cpuop_func op_4828_4_ff;
-extern cpuop_func op_4830_4_nf;
-extern cpuop_func op_4830_4_ff;
-extern cpuop_func op_4838_4_nf;
-extern cpuop_func op_4838_4_ff;
-extern cpuop_func op_4839_4_nf;
-extern cpuop_func op_4839_4_ff;
-extern cpuop_func op_4840_4_nf;
-extern cpuop_func op_4840_4_ff;
-extern cpuop_func op_4850_4_nf;
-extern cpuop_func op_4850_4_ff;
-extern cpuop_func op_4868_4_nf;
-extern cpuop_func op_4868_4_ff;
-extern cpuop_func op_4870_4_nf;
-extern cpuop_func op_4870_4_ff;
-extern cpuop_func op_4878_4_nf;
-extern cpuop_func op_4878_4_ff;
-extern cpuop_func op_4879_4_nf;
-extern cpuop_func op_4879_4_ff;
-extern cpuop_func op_487a_4_nf;
-extern cpuop_func op_487a_4_ff;
-extern cpuop_func op_487b_4_nf;
-extern cpuop_func op_487b_4_ff;
-extern cpuop_func op_4880_4_nf;
-extern cpuop_func op_4880_4_ff;
-extern cpuop_func op_4890_4_nf;
-extern cpuop_func op_4890_4_ff;
-extern cpuop_func op_48a0_4_nf;
-extern cpuop_func op_48a0_4_ff;
-extern cpuop_func op_48a8_4_nf;
-extern cpuop_func op_48a8_4_ff;
-extern cpuop_func op_48b0_4_nf;
-extern cpuop_func op_48b0_4_ff;
-extern cpuop_func op_48b8_4_nf;
-extern cpuop_func op_48b8_4_ff;
-extern cpuop_func op_48b9_4_nf;
-extern cpuop_func op_48b9_4_ff;
-extern cpuop_func op_48c0_4_nf;
-extern cpuop_func op_48c0_4_ff;
-extern cpuop_func op_48d0_4_nf;
-extern cpuop_func op_48d0_4_ff;
-extern cpuop_func op_48e0_4_nf;
-extern cpuop_func op_48e0_4_ff;
-extern cpuop_func op_48e8_4_nf;
-extern cpuop_func op_48e8_4_ff;
-extern cpuop_func op_48f0_4_nf;
-extern cpuop_func op_48f0_4_ff;
-extern cpuop_func op_48f8_4_nf;
-extern cpuop_func op_48f8_4_ff;
-extern cpuop_func op_48f9_4_nf;
-extern cpuop_func op_48f9_4_ff;
-extern cpuop_func op_4a00_4_nf;
-extern cpuop_func op_4a00_4_ff;
-extern cpuop_func op_4a10_4_nf;
-extern cpuop_func op_4a10_4_ff;
-extern cpuop_func op_4a18_4_nf;
-extern cpuop_func op_4a18_4_ff;
-extern cpuop_func op_4a20_4_nf;
-extern cpuop_func op_4a20_4_ff;
-extern cpuop_func op_4a28_4_nf;
-extern cpuop_func op_4a28_4_ff;
-extern cpuop_func op_4a30_4_nf;
-extern cpuop_func op_4a30_4_ff;
-extern cpuop_func op_4a38_4_nf;
-extern cpuop_func op_4a38_4_ff;
-extern cpuop_func op_4a39_4_nf;
-extern cpuop_func op_4a39_4_ff;
-extern cpuop_func op_4a3a_4_nf;
-extern cpuop_func op_4a3a_4_ff;
-extern cpuop_func op_4a3b_4_nf;
-extern cpuop_func op_4a3b_4_ff;
-extern cpuop_func op_4a3c_4_nf;
-extern cpuop_func op_4a3c_4_ff;
-extern cpuop_func op_4a40_4_nf;
-extern cpuop_func op_4a40_4_ff;
-extern cpuop_func op_4a48_4_nf;
-extern cpuop_func op_4a48_4_ff;
-extern cpuop_func op_4a50_4_nf;
-extern cpuop_func op_4a50_4_ff;
-extern cpuop_func op_4a58_4_nf;
-extern cpuop_func op_4a58_4_ff;
-extern cpuop_func op_4a60_4_nf;
-extern cpuop_func op_4a60_4_ff;
-extern cpuop_func op_4a68_4_nf;
-extern cpuop_func op_4a68_4_ff;
-extern cpuop_func op_4a70_4_nf;
-extern cpuop_func op_4a70_4_ff;
-extern cpuop_func op_4a78_4_nf;
-extern cpuop_func op_4a78_4_ff;
-extern cpuop_func op_4a79_4_nf;
-extern cpuop_func op_4a79_4_ff;
-extern cpuop_func op_4a7a_4_nf;
-extern cpuop_func op_4a7a_4_ff;
-extern cpuop_func op_4a7b_4_nf;
-extern cpuop_func op_4a7b_4_ff;
-extern cpuop_func op_4a7c_4_nf;
-extern cpuop_func op_4a7c_4_ff;
-extern cpuop_func op_4a80_4_nf;
-extern cpuop_func op_4a80_4_ff;
-extern cpuop_func op_4a88_4_nf;
-extern cpuop_func op_4a88_4_ff;
-extern cpuop_func op_4a90_4_nf;
-extern cpuop_func op_4a90_4_ff;
-extern cpuop_func op_4a98_4_nf;
-extern cpuop_func op_4a98_4_ff;
-extern cpuop_func op_4aa0_4_nf;
-extern cpuop_func op_4aa0_4_ff;
-extern cpuop_func op_4aa8_4_nf;
-extern cpuop_func op_4aa8_4_ff;
-extern cpuop_func op_4ab0_4_nf;
-extern cpuop_func op_4ab0_4_ff;
-extern cpuop_func op_4ab8_4_nf;
-extern cpuop_func op_4ab8_4_ff;
-extern cpuop_func op_4ab9_4_nf;
-extern cpuop_func op_4ab9_4_ff;
-extern cpuop_func op_4aba_4_nf;
-extern cpuop_func op_4aba_4_ff;
-extern cpuop_func op_4abb_4_nf;
-extern cpuop_func op_4abb_4_ff;
-extern cpuop_func op_4abc_4_nf;
-extern cpuop_func op_4abc_4_ff;
-extern cpuop_func op_4ac0_4_nf;
-extern cpuop_func op_4ac0_4_ff;
-extern cpuop_func op_4ad0_4_nf;
-extern cpuop_func op_4ad0_4_ff;
-extern cpuop_func op_4ad8_4_nf;
-extern cpuop_func op_4ad8_4_ff;
-extern cpuop_func op_4ae0_4_nf;
-extern cpuop_func op_4ae0_4_ff;
-extern cpuop_func op_4ae8_4_nf;
-extern cpuop_func op_4ae8_4_ff;
-extern cpuop_func op_4af0_4_nf;
-extern cpuop_func op_4af0_4_ff;
-extern cpuop_func op_4af8_4_nf;
-extern cpuop_func op_4af8_4_ff;
-extern cpuop_func op_4af9_4_nf;
-extern cpuop_func op_4af9_4_ff;
-extern cpuop_func op_4c90_4_nf;
-extern cpuop_func op_4c90_4_ff;
-extern cpuop_func op_4c98_4_nf;
-extern cpuop_func op_4c98_4_ff;
-extern cpuop_func op_4ca8_4_nf;
-extern cpuop_func op_4ca8_4_ff;
-extern cpuop_func op_4cb0_4_nf;
-extern cpuop_func op_4cb0_4_ff;
-extern cpuop_func op_4cb8_4_nf;
-extern cpuop_func op_4cb8_4_ff;
-extern cpuop_func op_4cb9_4_nf;
-extern cpuop_func op_4cb9_4_ff;
-extern cpuop_func op_4cba_4_nf;
-extern cpuop_func op_4cba_4_ff;
-extern cpuop_func op_4cbb_4_nf;
-extern cpuop_func op_4cbb_4_ff;
-extern cpuop_func op_4cd0_4_nf;
-extern cpuop_func op_4cd0_4_ff;
-extern cpuop_func op_4cd8_4_nf;
-extern cpuop_func op_4cd8_4_ff;
-extern cpuop_func op_4ce8_4_nf;
-extern cpuop_func op_4ce8_4_ff;
-extern cpuop_func op_4cf0_4_nf;
-extern cpuop_func op_4cf0_4_ff;
-extern cpuop_func op_4cf8_4_nf;
-extern cpuop_func op_4cf8_4_ff;
-extern cpuop_func op_4cf9_4_nf;
-extern cpuop_func op_4cf9_4_ff;
-extern cpuop_func op_4cfa_4_nf;
-extern cpuop_func op_4cfa_4_ff;
-extern cpuop_func op_4cfb_4_nf;
-extern cpuop_func op_4cfb_4_ff;
-extern cpuop_func op_4e40_4_nf;
-extern cpuop_func op_4e40_4_ff;
-extern cpuop_func op_4e50_4_nf;
-extern cpuop_func op_4e50_4_ff;
-extern cpuop_func op_4e58_4_nf;
-extern cpuop_func op_4e58_4_ff;
-extern cpuop_func op_4e60_4_nf;
-extern cpuop_func op_4e60_4_ff;
-extern cpuop_func op_4e68_4_nf;
-extern cpuop_func op_4e68_4_ff;
-extern cpuop_func op_4e70_4_nf;
-extern cpuop_func op_4e70_4_ff;
-extern cpuop_func op_4e71_4_nf;
-extern cpuop_func op_4e71_4_ff;
-extern cpuop_func op_4e72_4_nf;
-extern cpuop_func op_4e72_4_ff;
-extern cpuop_func op_4e73_4_nf;
-extern cpuop_func op_4e73_4_ff;
-extern cpuop_func op_4e74_4_nf;
-extern cpuop_func op_4e74_4_ff;
-extern cpuop_func op_4e75_4_nf;
-extern cpuop_func op_4e75_4_ff;
-extern cpuop_func op_4e76_4_nf;
-extern cpuop_func op_4e76_4_ff;
-extern cpuop_func op_4e77_4_nf;
-extern cpuop_func op_4e77_4_ff;
-extern cpuop_func op_4e90_4_nf;
-extern cpuop_func op_4e90_4_ff;
-extern cpuop_func op_4ea8_4_nf;
-extern cpuop_func op_4ea8_4_ff;
-extern cpuop_func op_4eb0_4_nf;
-extern cpuop_func op_4eb0_4_ff;
-extern cpuop_func op_4eb8_4_nf;
-extern cpuop_func op_4eb8_4_ff;
-extern cpuop_func op_4eb9_4_nf;
-extern cpuop_func op_4eb9_4_ff;
-extern cpuop_func op_4eba_4_nf;
-extern cpuop_func op_4eba_4_ff;
-extern cpuop_func op_4ebb_4_nf;
-extern cpuop_func op_4ebb_4_ff;
-extern cpuop_func op_4ed0_4_nf;
-extern cpuop_func op_4ed0_4_ff;
-extern cpuop_func op_4ee8_4_nf;
-extern cpuop_func op_4ee8_4_ff;
-extern cpuop_func op_4ef0_4_nf;
-extern cpuop_func op_4ef0_4_ff;
-extern cpuop_func op_4ef8_4_nf;
-extern cpuop_func op_4ef8_4_ff;
-extern cpuop_func op_4ef9_4_nf;
-extern cpuop_func op_4ef9_4_ff;
-extern cpuop_func op_4efa_4_nf;
-extern cpuop_func op_4efa_4_ff;
-extern cpuop_func op_4efb_4_nf;
-extern cpuop_func op_4efb_4_ff;
-extern cpuop_func op_5000_4_nf;
-extern cpuop_func op_5000_4_ff;
-extern cpuop_func op_5010_4_nf;
-extern cpuop_func op_5010_4_ff;
-extern cpuop_func op_5018_4_nf;
-extern cpuop_func op_5018_4_ff;
-extern cpuop_func op_5020_4_nf;
-extern cpuop_func op_5020_4_ff;
-extern cpuop_func op_5028_4_nf;
-extern cpuop_func op_5028_4_ff;
-extern cpuop_func op_5030_4_nf;
-extern cpuop_func op_5030_4_ff;
-extern cpuop_func op_5038_4_nf;
-extern cpuop_func op_5038_4_ff;
-extern cpuop_func op_5039_4_nf;
-extern cpuop_func op_5039_4_ff;
-extern cpuop_func op_5040_4_nf;
-extern cpuop_func op_5040_4_ff;
-extern cpuop_func op_5048_4_nf;
-extern cpuop_func op_5048_4_ff;
-extern cpuop_func op_5050_4_nf;
-extern cpuop_func op_5050_4_ff;
-extern cpuop_func op_5058_4_nf;
-extern cpuop_func op_5058_4_ff;
-extern cpuop_func op_5060_4_nf;
-extern cpuop_func op_5060_4_ff;
-extern cpuop_func op_5068_4_nf;
-extern cpuop_func op_5068_4_ff;
-extern cpuop_func op_5070_4_nf;
-extern cpuop_func op_5070_4_ff;
-extern cpuop_func op_5078_4_nf;
-extern cpuop_func op_5078_4_ff;
-extern cpuop_func op_5079_4_nf;
-extern cpuop_func op_5079_4_ff;
-extern cpuop_func op_5080_4_nf;
-extern cpuop_func op_5080_4_ff;
-extern cpuop_func op_5088_4_nf;
-extern cpuop_func op_5088_4_ff;
-extern cpuop_func op_5090_4_nf;
-extern cpuop_func op_5090_4_ff;
-extern cpuop_func op_5098_4_nf;
-extern cpuop_func op_5098_4_ff;
-extern cpuop_func op_50a0_4_nf;
-extern cpuop_func op_50a0_4_ff;
-extern cpuop_func op_50a8_4_nf;
-extern cpuop_func op_50a8_4_ff;
-extern cpuop_func op_50b0_4_nf;
-extern cpuop_func op_50b0_4_ff;
-extern cpuop_func op_50b8_4_nf;
-extern cpuop_func op_50b8_4_ff;
-extern cpuop_func op_50b9_4_nf;
-extern cpuop_func op_50b9_4_ff;
-extern cpuop_func op_50c0_4_nf;
-extern cpuop_func op_50c0_4_ff;
-extern cpuop_func op_50c8_4_nf;
-extern cpuop_func op_50c8_4_ff;
-extern cpuop_func op_50d0_4_nf;
-extern cpuop_func op_50d0_4_ff;
-extern cpuop_func op_50d8_4_nf;
-extern cpuop_func op_50d8_4_ff;
-extern cpuop_func op_50e0_4_nf;
-extern cpuop_func op_50e0_4_ff;
-extern cpuop_func op_50e8_4_nf;
-extern cpuop_func op_50e8_4_ff;
-extern cpuop_func op_50f0_4_nf;
-extern cpuop_func op_50f0_4_ff;
-extern cpuop_func op_50f8_4_nf;
-extern cpuop_func op_50f8_4_ff;
-extern cpuop_func op_50f9_4_nf;
-extern cpuop_func op_50f9_4_ff;
-extern cpuop_func op_5100_4_nf;
-extern cpuop_func op_5100_4_ff;
-extern cpuop_func op_5110_4_nf;
-extern cpuop_func op_5110_4_ff;
-extern cpuop_func op_5118_4_nf;
-extern cpuop_func op_5118_4_ff;
-extern cpuop_func op_5120_4_nf;
-extern cpuop_func op_5120_4_ff;
-extern cpuop_func op_5128_4_nf;
-extern cpuop_func op_5128_4_ff;
-extern cpuop_func op_5130_4_nf;
-extern cpuop_func op_5130_4_ff;
-extern cpuop_func op_5138_4_nf;
-extern cpuop_func op_5138_4_ff;
-extern cpuop_func op_5139_4_nf;
-extern cpuop_func op_5139_4_ff;
-extern cpuop_func op_5140_4_nf;
-extern cpuop_func op_5140_4_ff;
-extern cpuop_func op_5148_4_nf;
-extern cpuop_func op_5148_4_ff;
-extern cpuop_func op_5150_4_nf;
-extern cpuop_func op_5150_4_ff;
-extern cpuop_func op_5158_4_nf;
-extern cpuop_func op_5158_4_ff;
-extern cpuop_func op_5160_4_nf;
-extern cpuop_func op_5160_4_ff;
-extern cpuop_func op_5168_4_nf;
-extern cpuop_func op_5168_4_ff;
-extern cpuop_func op_5170_4_nf;
-extern cpuop_func op_5170_4_ff;
-extern cpuop_func op_5178_4_nf;
-extern cpuop_func op_5178_4_ff;
-extern cpuop_func op_5179_4_nf;
-extern cpuop_func op_5179_4_ff;
-extern cpuop_func op_5180_4_nf;
-extern cpuop_func op_5180_4_ff;
-extern cpuop_func op_5188_4_nf;
-extern cpuop_func op_5188_4_ff;
-extern cpuop_func op_5190_4_nf;
-extern cpuop_func op_5190_4_ff;
-extern cpuop_func op_5198_4_nf;
-extern cpuop_func op_5198_4_ff;
-extern cpuop_func op_51a0_4_nf;
-extern cpuop_func op_51a0_4_ff;
-extern cpuop_func op_51a8_4_nf;
-extern cpuop_func op_51a8_4_ff;
-extern cpuop_func op_51b0_4_nf;
-extern cpuop_func op_51b0_4_ff;
-extern cpuop_func op_51b8_4_nf;
-extern cpuop_func op_51b8_4_ff;
-extern cpuop_func op_51b9_4_nf;
-extern cpuop_func op_51b9_4_ff;
-extern cpuop_func op_51c0_4_nf;
-extern cpuop_func op_51c0_4_ff;
-extern cpuop_func op_51c8_4_nf;
-extern cpuop_func op_51c8_4_ff;
-extern cpuop_func op_51d0_4_nf;
-extern cpuop_func op_51d0_4_ff;
-extern cpuop_func op_51d8_4_nf;
-extern cpuop_func op_51d8_4_ff;
-extern cpuop_func op_51e0_4_nf;
-extern cpuop_func op_51e0_4_ff;
-extern cpuop_func op_51e8_4_nf;
-extern cpuop_func op_51e8_4_ff;
-extern cpuop_func op_51f0_4_nf;
-extern cpuop_func op_51f0_4_ff;
-extern cpuop_func op_51f8_4_nf;
-extern cpuop_func op_51f8_4_ff;
-extern cpuop_func op_51f9_4_nf;
-extern cpuop_func op_51f9_4_ff;
-extern cpuop_func op_52c0_4_nf;
-extern cpuop_func op_52c0_4_ff;
-extern cpuop_func op_52c8_4_nf;
-extern cpuop_func op_52c8_4_ff;
-extern cpuop_func op_52d0_4_nf;
-extern cpuop_func op_52d0_4_ff;
-extern cpuop_func op_52d8_4_nf;
-extern cpuop_func op_52d8_4_ff;
-extern cpuop_func op_52e0_4_nf;
-extern cpuop_func op_52e0_4_ff;
-extern cpuop_func op_52e8_4_nf;
-extern cpuop_func op_52e8_4_ff;
-extern cpuop_func op_52f0_4_nf;
-extern cpuop_func op_52f0_4_ff;
-extern cpuop_func op_52f8_4_nf;
-extern cpuop_func op_52f8_4_ff;
-extern cpuop_func op_52f9_4_nf;
-extern cpuop_func op_52f9_4_ff;
-extern cpuop_func op_53c0_4_nf;
-extern cpuop_func op_53c0_4_ff;
-extern cpuop_func op_53c8_4_nf;
-extern cpuop_func op_53c8_4_ff;
-extern cpuop_func op_53d0_4_nf;
-extern cpuop_func op_53d0_4_ff;
-extern cpuop_func op_53d8_4_nf;
-extern cpuop_func op_53d8_4_ff;
-extern cpuop_func op_53e0_4_nf;
-extern cpuop_func op_53e0_4_ff;
-extern cpuop_func op_53e8_4_nf;
-extern cpuop_func op_53e8_4_ff;
-extern cpuop_func op_53f0_4_nf;
-extern cpuop_func op_53f0_4_ff;
-extern cpuop_func op_53f8_4_nf;
-extern cpuop_func op_53f8_4_ff;
-extern cpuop_func op_53f9_4_nf;
-extern cpuop_func op_53f9_4_ff;
-extern cpuop_func op_54c0_4_nf;
-extern cpuop_func op_54c0_4_ff;
-extern cpuop_func op_54c8_4_nf;
-extern cpuop_func op_54c8_4_ff;
-extern cpuop_func op_54d0_4_nf;
-extern cpuop_func op_54d0_4_ff;
-extern cpuop_func op_54d8_4_nf;
-extern cpuop_func op_54d8_4_ff;
-extern cpuop_func op_54e0_4_nf;
-extern cpuop_func op_54e0_4_ff;
-extern cpuop_func op_54e8_4_nf;
-extern cpuop_func op_54e8_4_ff;
-extern cpuop_func op_54f0_4_nf;
-extern cpuop_func op_54f0_4_ff;
-extern cpuop_func op_54f8_4_nf;
-extern cpuop_func op_54f8_4_ff;
-extern cpuop_func op_54f9_4_nf;
-extern cpuop_func op_54f9_4_ff;
-extern cpuop_func op_55c0_4_nf;
-extern cpuop_func op_55c0_4_ff;
-extern cpuop_func op_55c8_4_nf;
-extern cpuop_func op_55c8_4_ff;
-extern cpuop_func op_55d0_4_nf;
-extern cpuop_func op_55d0_4_ff;
-extern cpuop_func op_55d8_4_nf;
-extern cpuop_func op_55d8_4_ff;
-extern cpuop_func op_55e0_4_nf;
-extern cpuop_func op_55e0_4_ff;
-extern cpuop_func op_55e8_4_nf;
-extern cpuop_func op_55e8_4_ff;
-extern cpuop_func op_55f0_4_nf;
-extern cpuop_func op_55f0_4_ff;
-extern cpuop_func op_55f8_4_nf;
-extern cpuop_func op_55f8_4_ff;
-extern cpuop_func op_55f9_4_nf;
-extern cpuop_func op_55f9_4_ff;
-extern cpuop_func op_56c0_4_nf;
-extern cpuop_func op_56c0_4_ff;
-extern cpuop_func op_56c8_4_nf;
-extern cpuop_func op_56c8_4_ff;
-extern cpuop_func op_56d0_4_nf;
-extern cpuop_func op_56d0_4_ff;
-extern cpuop_func op_56d8_4_nf;
-extern cpuop_func op_56d8_4_ff;
-extern cpuop_func op_56e0_4_nf;
-extern cpuop_func op_56e0_4_ff;
-extern cpuop_func op_56e8_4_nf;
-extern cpuop_func op_56e8_4_ff;
-extern cpuop_func op_56f0_4_nf;
-extern cpuop_func op_56f0_4_ff;
-extern cpuop_func op_56f8_4_nf;
-extern cpuop_func op_56f8_4_ff;
-extern cpuop_func op_56f9_4_nf;
-extern cpuop_func op_56f9_4_ff;
-extern cpuop_func op_57c0_4_nf;
-extern cpuop_func op_57c0_4_ff;
-extern cpuop_func op_57c8_4_nf;
-extern cpuop_func op_57c8_4_ff;
-extern cpuop_func op_57d0_4_nf;
-extern cpuop_func op_57d0_4_ff;
-extern cpuop_func op_57d8_4_nf;
-extern cpuop_func op_57d8_4_ff;
-extern cpuop_func op_57e0_4_nf;
-extern cpuop_func op_57e0_4_ff;
-extern cpuop_func op_57e8_4_nf;
-extern cpuop_func op_57e8_4_ff;
-extern cpuop_func op_57f0_4_nf;
-extern cpuop_func op_57f0_4_ff;
-extern cpuop_func op_57f8_4_nf;
-extern cpuop_func op_57f8_4_ff;
-extern cpuop_func op_57f9_4_nf;
-extern cpuop_func op_57f9_4_ff;
-extern cpuop_func op_58c0_4_nf;
-extern cpuop_func op_58c0_4_ff;
-extern cpuop_func op_58c8_4_nf;
-extern cpuop_func op_58c8_4_ff;
-extern cpuop_func op_58d0_4_nf;
-extern cpuop_func op_58d0_4_ff;
-extern cpuop_func op_58d8_4_nf;
-extern cpuop_func op_58d8_4_ff;
-extern cpuop_func op_58e0_4_nf;
-extern cpuop_func op_58e0_4_ff;
-extern cpuop_func op_58e8_4_nf;
-extern cpuop_func op_58e8_4_ff;
-extern cpuop_func op_58f0_4_nf;
-extern cpuop_func op_58f0_4_ff;
-extern cpuop_func op_58f8_4_nf;
-extern cpuop_func op_58f8_4_ff;
-extern cpuop_func op_58f9_4_nf;
-extern cpuop_func op_58f9_4_ff;
-extern cpuop_func op_59c0_4_nf;
-extern cpuop_func op_59c0_4_ff;
-extern cpuop_func op_59c8_4_nf;
-extern cpuop_func op_59c8_4_ff;
-extern cpuop_func op_59d0_4_nf;
-extern cpuop_func op_59d0_4_ff;
-extern cpuop_func op_59d8_4_nf;
-extern cpuop_func op_59d8_4_ff;
-extern cpuop_func op_59e0_4_nf;
-extern cpuop_func op_59e0_4_ff;
-extern cpuop_func op_59e8_4_nf;
-extern cpuop_func op_59e8_4_ff;
-extern cpuop_func op_59f0_4_nf;
-extern cpuop_func op_59f0_4_ff;
-extern cpuop_func op_59f8_4_nf;
-extern cpuop_func op_59f8_4_ff;
-extern cpuop_func op_59f9_4_nf;
-extern cpuop_func op_59f9_4_ff;
-extern cpuop_func op_5ac0_4_nf;
-extern cpuop_func op_5ac0_4_ff;
-extern cpuop_func op_5ac8_4_nf;
-extern cpuop_func op_5ac8_4_ff;
-extern cpuop_func op_5ad0_4_nf;
-extern cpuop_func op_5ad0_4_ff;
-extern cpuop_func op_5ad8_4_nf;
-extern cpuop_func op_5ad8_4_ff;
-extern cpuop_func op_5ae0_4_nf;
-extern cpuop_func op_5ae0_4_ff;
-extern cpuop_func op_5ae8_4_nf;
-extern cpuop_func op_5ae8_4_ff;
-extern cpuop_func op_5af0_4_nf;
-extern cpuop_func op_5af0_4_ff;
-extern cpuop_func op_5af8_4_nf;
-extern cpuop_func op_5af8_4_ff;
-extern cpuop_func op_5af9_4_nf;
-extern cpuop_func op_5af9_4_ff;
-extern cpuop_func op_5bc0_4_nf;
-extern cpuop_func op_5bc0_4_ff;
-extern cpuop_func op_5bc8_4_nf;
-extern cpuop_func op_5bc8_4_ff;
-extern cpuop_func op_5bd0_4_nf;
-extern cpuop_func op_5bd0_4_ff;
-extern cpuop_func op_5bd8_4_nf;
-extern cpuop_func op_5bd8_4_ff;
-extern cpuop_func op_5be0_4_nf;
-extern cpuop_func op_5be0_4_ff;
-extern cpuop_func op_5be8_4_nf;
-extern cpuop_func op_5be8_4_ff;
-extern cpuop_func op_5bf0_4_nf;
-extern cpuop_func op_5bf0_4_ff;
-extern cpuop_func op_5bf8_4_nf;
-extern cpuop_func op_5bf8_4_ff;
-extern cpuop_func op_5bf9_4_nf;
-extern cpuop_func op_5bf9_4_ff;
-extern cpuop_func op_5cc0_4_nf;
-extern cpuop_func op_5cc0_4_ff;
-extern cpuop_func op_5cc8_4_nf;
-extern cpuop_func op_5cc8_4_ff;
-extern cpuop_func op_5cd0_4_nf;
-extern cpuop_func op_5cd0_4_ff;
-extern cpuop_func op_5cd8_4_nf;
-extern cpuop_func op_5cd8_4_ff;
-extern cpuop_func op_5ce0_4_nf;
-extern cpuop_func op_5ce0_4_ff;
-extern cpuop_func op_5ce8_4_nf;
-extern cpuop_func op_5ce8_4_ff;
-extern cpuop_func op_5cf0_4_nf;
-extern cpuop_func op_5cf0_4_ff;
-extern cpuop_func op_5cf8_4_nf;
-extern cpuop_func op_5cf8_4_ff;
-extern cpuop_func op_5cf9_4_nf;
-extern cpuop_func op_5cf9_4_ff;
-extern cpuop_func op_5dc0_4_nf;
-extern cpuop_func op_5dc0_4_ff;
-extern cpuop_func op_5dc8_4_nf;
-extern cpuop_func op_5dc8_4_ff;
-extern cpuop_func op_5dd0_4_nf;
-extern cpuop_func op_5dd0_4_ff;
-extern cpuop_func op_5dd8_4_nf;
-extern cpuop_func op_5dd8_4_ff;
-extern cpuop_func op_5de0_4_nf;
-extern cpuop_func op_5de0_4_ff;
-extern cpuop_func op_5de8_4_nf;
-extern cpuop_func op_5de8_4_ff;
-extern cpuop_func op_5df0_4_nf;
-extern cpuop_func op_5df0_4_ff;
-extern cpuop_func op_5df8_4_nf;
-extern cpuop_func op_5df8_4_ff;
-extern cpuop_func op_5df9_4_nf;
-extern cpuop_func op_5df9_4_ff;
-extern cpuop_func op_5ec0_4_nf;
-extern cpuop_func op_5ec0_4_ff;
-extern cpuop_func op_5ec8_4_nf;
-extern cpuop_func op_5ec8_4_ff;
-extern cpuop_func op_5ed0_4_nf;
-extern cpuop_func op_5ed0_4_ff;
-extern cpuop_func op_5ed8_4_nf;
-extern cpuop_func op_5ed8_4_ff;
-extern cpuop_func op_5ee0_4_nf;
-extern cpuop_func op_5ee0_4_ff;
-extern cpuop_func op_5ee8_4_nf;
-extern cpuop_func op_5ee8_4_ff;
-extern cpuop_func op_5ef0_4_nf;
-extern cpuop_func op_5ef0_4_ff;
-extern cpuop_func op_5ef8_4_nf;
-extern cpuop_func op_5ef8_4_ff;
-extern cpuop_func op_5ef9_4_nf;
-extern cpuop_func op_5ef9_4_ff;
-extern cpuop_func op_5fc0_4_nf;
-extern cpuop_func op_5fc0_4_ff;
-extern cpuop_func op_5fc8_4_nf;
-extern cpuop_func op_5fc8_4_ff;
-extern cpuop_func op_5fd0_4_nf;
-extern cpuop_func op_5fd0_4_ff;
-extern cpuop_func op_5fd8_4_nf;
-extern cpuop_func op_5fd8_4_ff;
-extern cpuop_func op_5fe0_4_nf;
-extern cpuop_func op_5fe0_4_ff;
-extern cpuop_func op_5fe8_4_nf;
-extern cpuop_func op_5fe8_4_ff;
-extern cpuop_func op_5ff0_4_nf;
-extern cpuop_func op_5ff0_4_ff;
-extern cpuop_func op_5ff8_4_nf;
-extern cpuop_func op_5ff8_4_ff;
-extern cpuop_func op_5ff9_4_nf;
-extern cpuop_func op_5ff9_4_ff;
-extern cpuop_func op_6000_4_nf;
-extern cpuop_func op_6000_4_ff;
-extern cpuop_func op_6001_4_nf;
-extern cpuop_func op_6001_4_ff;
-extern cpuop_func op_60ff_4_nf;
-extern cpuop_func op_60ff_4_ff;
-extern cpuop_func op_6100_4_nf;
-extern cpuop_func op_6100_4_ff;
-extern cpuop_func op_6101_4_nf;
-extern cpuop_func op_6101_4_ff;
-extern cpuop_func op_61ff_4_nf;
-extern cpuop_func op_61ff_4_ff;
-extern cpuop_func op_6200_4_nf;
-extern cpuop_func op_6200_4_ff;
-extern cpuop_func op_6201_4_nf;
-extern cpuop_func op_6201_4_ff;
-extern cpuop_func op_62ff_4_nf;
-extern cpuop_func op_62ff_4_ff;
-extern cpuop_func op_6300_4_nf;
-extern cpuop_func op_6300_4_ff;
-extern cpuop_func op_6301_4_nf;
-extern cpuop_func op_6301_4_ff;
-extern cpuop_func op_63ff_4_nf;
-extern cpuop_func op_63ff_4_ff;
-extern cpuop_func op_6400_4_nf;
-extern cpuop_func op_6400_4_ff;
-extern cpuop_func op_6401_4_nf;
-extern cpuop_func op_6401_4_ff;
-extern cpuop_func op_64ff_4_nf;
-extern cpuop_func op_64ff_4_ff;
-extern cpuop_func op_6500_4_nf;
-extern cpuop_func op_6500_4_ff;
-extern cpuop_func op_6501_4_nf;
-extern cpuop_func op_6501_4_ff;
-extern cpuop_func op_65ff_4_nf;
-extern cpuop_func op_65ff_4_ff;
-extern cpuop_func op_6600_4_nf;
-extern cpuop_func op_6600_4_ff;
-extern cpuop_func op_6601_4_nf;
-extern cpuop_func op_6601_4_ff;
-extern cpuop_func op_66ff_4_nf;
-extern cpuop_func op_66ff_4_ff;
-extern cpuop_func op_6700_4_nf;
-extern cpuop_func op_6700_4_ff;
-extern cpuop_func op_6701_4_nf;
-extern cpuop_func op_6701_4_ff;
-extern cpuop_func op_67ff_4_nf;
-extern cpuop_func op_67ff_4_ff;
-extern cpuop_func op_6800_4_nf;
-extern cpuop_func op_6800_4_ff;
-extern cpuop_func op_6801_4_nf;
-extern cpuop_func op_6801_4_ff;
-extern cpuop_func op_68ff_4_nf;
-extern cpuop_func op_68ff_4_ff;
-extern cpuop_func op_6900_4_nf;
-extern cpuop_func op_6900_4_ff;
-extern cpuop_func op_6901_4_nf;
-extern cpuop_func op_6901_4_ff;
-extern cpuop_func op_69ff_4_nf;
-extern cpuop_func op_69ff_4_ff;
-extern cpuop_func op_6a00_4_nf;
-extern cpuop_func op_6a00_4_ff;
-extern cpuop_func op_6a01_4_nf;
-extern cpuop_func op_6a01_4_ff;
-extern cpuop_func op_6aff_4_nf;
-extern cpuop_func op_6aff_4_ff;
-extern cpuop_func op_6b00_4_nf;
-extern cpuop_func op_6b00_4_ff;
-extern cpuop_func op_6b01_4_nf;
-extern cpuop_func op_6b01_4_ff;
-extern cpuop_func op_6bff_4_nf;
-extern cpuop_func op_6bff_4_ff;
-extern cpuop_func op_6c00_4_nf;
-extern cpuop_func op_6c00_4_ff;
-extern cpuop_func op_6c01_4_nf;
-extern cpuop_func op_6c01_4_ff;
-extern cpuop_func op_6cff_4_nf;
-extern cpuop_func op_6cff_4_ff;
-extern cpuop_func op_6d00_4_nf;
-extern cpuop_func op_6d00_4_ff;
-extern cpuop_func op_6d01_4_nf;
-extern cpuop_func op_6d01_4_ff;
-extern cpuop_func op_6dff_4_nf;
-extern cpuop_func op_6dff_4_ff;
-extern cpuop_func op_6e00_4_nf;
-extern cpuop_func op_6e00_4_ff;
-extern cpuop_func op_6e01_4_nf;
-extern cpuop_func op_6e01_4_ff;
-extern cpuop_func op_6eff_4_nf;
-extern cpuop_func op_6eff_4_ff;
-extern cpuop_func op_6f00_4_nf;
-extern cpuop_func op_6f00_4_ff;
-extern cpuop_func op_6f01_4_nf;
-extern cpuop_func op_6f01_4_ff;
-extern cpuop_func op_6fff_4_nf;
-extern cpuop_func op_6fff_4_ff;
-extern cpuop_func op_7000_4_nf;
-extern cpuop_func op_7000_4_ff;
-extern cpuop_func op_8000_4_nf;
-extern cpuop_func op_8000_4_ff;
-extern cpuop_func op_8010_4_nf;
-extern cpuop_func op_8010_4_ff;
-extern cpuop_func op_8018_4_nf;
-extern cpuop_func op_8018_4_ff;
-extern cpuop_func op_8020_4_nf;
-extern cpuop_func op_8020_4_ff;
-extern cpuop_func op_8028_4_nf;
-extern cpuop_func op_8028_4_ff;
-extern cpuop_func op_8030_4_nf;
-extern cpuop_func op_8030_4_ff;
-extern cpuop_func op_8038_4_nf;
-extern cpuop_func op_8038_4_ff;
-extern cpuop_func op_8039_4_nf;
-extern cpuop_func op_8039_4_ff;
-extern cpuop_func op_803a_4_nf;
-extern cpuop_func op_803a_4_ff;
-extern cpuop_func op_803b_4_nf;
-extern cpuop_func op_803b_4_ff;
-extern cpuop_func op_803c_4_nf;
-extern cpuop_func op_803c_4_ff;
-extern cpuop_func op_8040_4_nf;
-extern cpuop_func op_8040_4_ff;
-extern cpuop_func op_8050_4_nf;
-extern cpuop_func op_8050_4_ff;
-extern cpuop_func op_8058_4_nf;
-extern cpuop_func op_8058_4_ff;
-extern cpuop_func op_8060_4_nf;
-extern cpuop_func op_8060_4_ff;
-extern cpuop_func op_8068_4_nf;
-extern cpuop_func op_8068_4_ff;
-extern cpuop_func op_8070_4_nf;
-extern cpuop_func op_8070_4_ff;
-extern cpuop_func op_8078_4_nf;
-extern cpuop_func op_8078_4_ff;
-extern cpuop_func op_8079_4_nf;
-extern cpuop_func op_8079_4_ff;
-extern cpuop_func op_807a_4_nf;
-extern cpuop_func op_807a_4_ff;
-extern cpuop_func op_807b_4_nf;
-extern cpuop_func op_807b_4_ff;
-extern cpuop_func op_807c_4_nf;
-extern cpuop_func op_807c_4_ff;
-extern cpuop_func op_8080_4_nf;
-extern cpuop_func op_8080_4_ff;
-extern cpuop_func op_8090_4_nf;
-extern cpuop_func op_8090_4_ff;
-extern cpuop_func op_8098_4_nf;
-extern cpuop_func op_8098_4_ff;
-extern cpuop_func op_80a0_4_nf;
-extern cpuop_func op_80a0_4_ff;
-extern cpuop_func op_80a8_4_nf;
-extern cpuop_func op_80a8_4_ff;
-extern cpuop_func op_80b0_4_nf;
-extern cpuop_func op_80b0_4_ff;
-extern cpuop_func op_80b8_4_nf;
-extern cpuop_func op_80b8_4_ff;
-extern cpuop_func op_80b9_4_nf;
-extern cpuop_func op_80b9_4_ff;
-extern cpuop_func op_80ba_4_nf;
-extern cpuop_func op_80ba_4_ff;
-extern cpuop_func op_80bb_4_nf;
-extern cpuop_func op_80bb_4_ff;
-extern cpuop_func op_80bc_4_nf;
-extern cpuop_func op_80bc_4_ff;
-extern cpuop_func op_80c0_4_nf;
-extern cpuop_func op_80c0_4_ff;
-extern cpuop_func op_80d0_4_nf;
-extern cpuop_func op_80d0_4_ff;
-extern cpuop_func op_80d8_4_nf;
-extern cpuop_func op_80d8_4_ff;
-extern cpuop_func op_80e0_4_nf;
-extern cpuop_func op_80e0_4_ff;
-extern cpuop_func op_80e8_4_nf;
-extern cpuop_func op_80e8_4_ff;
-extern cpuop_func op_80f0_4_nf;
-extern cpuop_func op_80f0_4_ff;
-extern cpuop_func op_80f8_4_nf;
-extern cpuop_func op_80f8_4_ff;
-extern cpuop_func op_80f9_4_nf;
-extern cpuop_func op_80f9_4_ff;
-extern cpuop_func op_80fa_4_nf;
-extern cpuop_func op_80fa_4_ff;
-extern cpuop_func op_80fb_4_nf;
-extern cpuop_func op_80fb_4_ff;
-extern cpuop_func op_80fc_4_nf;
-extern cpuop_func op_80fc_4_ff;
-extern cpuop_func op_8100_4_nf;
-extern cpuop_func op_8100_4_ff;
-extern cpuop_func op_8108_4_nf;
-extern cpuop_func op_8108_4_ff;
-extern cpuop_func op_8110_4_nf;
-extern cpuop_func op_8110_4_ff;
-extern cpuop_func op_8118_4_nf;
-extern cpuop_func op_8118_4_ff;
-extern cpuop_func op_8120_4_nf;
-extern cpuop_func op_8120_4_ff;
-extern cpuop_func op_8128_4_nf;
-extern cpuop_func op_8128_4_ff;
-extern cpuop_func op_8130_4_nf;
-extern cpuop_func op_8130_4_ff;
-extern cpuop_func op_8138_4_nf;
-extern cpuop_func op_8138_4_ff;
-extern cpuop_func op_8139_4_nf;
-extern cpuop_func op_8139_4_ff;
-extern cpuop_func op_8150_4_nf;
-extern cpuop_func op_8150_4_ff;
-extern cpuop_func op_8158_4_nf;
-extern cpuop_func op_8158_4_ff;
-extern cpuop_func op_8160_4_nf;
-extern cpuop_func op_8160_4_ff;
-extern cpuop_func op_8168_4_nf;
-extern cpuop_func op_8168_4_ff;
-extern cpuop_func op_8170_4_nf;
-extern cpuop_func op_8170_4_ff;
-extern cpuop_func op_8178_4_nf;
-extern cpuop_func op_8178_4_ff;
-extern cpuop_func op_8179_4_nf;
-extern cpuop_func op_8179_4_ff;
-extern cpuop_func op_8190_4_nf;
-extern cpuop_func op_8190_4_ff;
-extern cpuop_func op_8198_4_nf;
-extern cpuop_func op_8198_4_ff;
-extern cpuop_func op_81a0_4_nf;
-extern cpuop_func op_81a0_4_ff;
-extern cpuop_func op_81a8_4_nf;
-extern cpuop_func op_81a8_4_ff;
-extern cpuop_func op_81b0_4_nf;
-extern cpuop_func op_81b0_4_ff;
-extern cpuop_func op_81b8_4_nf;
-extern cpuop_func op_81b8_4_ff;
-extern cpuop_func op_81b9_4_nf;
-extern cpuop_func op_81b9_4_ff;
-extern cpuop_func op_81c0_4_nf;
-extern cpuop_func op_81c0_4_ff;
-extern cpuop_func op_81d0_4_nf;
-extern cpuop_func op_81d0_4_ff;
-extern cpuop_func op_81d8_4_nf;
-extern cpuop_func op_81d8_4_ff;
-extern cpuop_func op_81e0_4_nf;
-extern cpuop_func op_81e0_4_ff;
-extern cpuop_func op_81e8_4_nf;
-extern cpuop_func op_81e8_4_ff;
-extern cpuop_func op_81f0_4_nf;
-extern cpuop_func op_81f0_4_ff;
-extern cpuop_func op_81f8_4_nf;
-extern cpuop_func op_81f8_4_ff;
-extern cpuop_func op_81f9_4_nf;
-extern cpuop_func op_81f9_4_ff;
-extern cpuop_func op_81fa_4_nf;
-extern cpuop_func op_81fa_4_ff;
-extern cpuop_func op_81fb_4_nf;
-extern cpuop_func op_81fb_4_ff;
-extern cpuop_func op_81fc_4_nf;
-extern cpuop_func op_81fc_4_ff;
-extern cpuop_func op_9000_4_nf;
-extern cpuop_func op_9000_4_ff;
-extern cpuop_func op_9010_4_nf;
-extern cpuop_func op_9010_4_ff;
-extern cpuop_func op_9018_4_nf;
-extern cpuop_func op_9018_4_ff;
-extern cpuop_func op_9020_4_nf;
-extern cpuop_func op_9020_4_ff;
-extern cpuop_func op_9028_4_nf;
-extern cpuop_func op_9028_4_ff;
-extern cpuop_func op_9030_4_nf;
-extern cpuop_func op_9030_4_ff;
-extern cpuop_func op_9038_4_nf;
-extern cpuop_func op_9038_4_ff;
-extern cpuop_func op_9039_4_nf;
-extern cpuop_func op_9039_4_ff;
-extern cpuop_func op_903a_4_nf;
-extern cpuop_func op_903a_4_ff;
-extern cpuop_func op_903b_4_nf;
-extern cpuop_func op_903b_4_ff;
-extern cpuop_func op_903c_4_nf;
-extern cpuop_func op_903c_4_ff;
-extern cpuop_func op_9040_4_nf;
-extern cpuop_func op_9040_4_ff;
-extern cpuop_func op_9048_4_nf;
-extern cpuop_func op_9048_4_ff;
-extern cpuop_func op_9050_4_nf;
-extern cpuop_func op_9050_4_ff;
-extern cpuop_func op_9058_4_nf;
-extern cpuop_func op_9058_4_ff;
-extern cpuop_func op_9060_4_nf;
-extern cpuop_func op_9060_4_ff;
-extern cpuop_func op_9068_4_nf;
-extern cpuop_func op_9068_4_ff;
-extern cpuop_func op_9070_4_nf;
-extern cpuop_func op_9070_4_ff;
-extern cpuop_func op_9078_4_nf;
-extern cpuop_func op_9078_4_ff;
-extern cpuop_func op_9079_4_nf;
-extern cpuop_func op_9079_4_ff;
-extern cpuop_func op_907a_4_nf;
-extern cpuop_func op_907a_4_ff;
-extern cpuop_func op_907b_4_nf;
-extern cpuop_func op_907b_4_ff;
-extern cpuop_func op_907c_4_nf;
-extern cpuop_func op_907c_4_ff;
-extern cpuop_func op_9080_4_nf;
-extern cpuop_func op_9080_4_ff;
-extern cpuop_func op_9088_4_nf;
-extern cpuop_func op_9088_4_ff;
-extern cpuop_func op_9090_4_nf;
-extern cpuop_func op_9090_4_ff;
-extern cpuop_func op_9098_4_nf;
-extern cpuop_func op_9098_4_ff;
-extern cpuop_func op_90a0_4_nf;
-extern cpuop_func op_90a0_4_ff;
-extern cpuop_func op_90a8_4_nf;
-extern cpuop_func op_90a8_4_ff;
-extern cpuop_func op_90b0_4_nf;
-extern cpuop_func op_90b0_4_ff;
-extern cpuop_func op_90b8_4_nf;
-extern cpuop_func op_90b8_4_ff;
-extern cpuop_func op_90b9_4_nf;
-extern cpuop_func op_90b9_4_ff;
-extern cpuop_func op_90ba_4_nf;
-extern cpuop_func op_90ba_4_ff;
-extern cpuop_func op_90bb_4_nf;
-extern cpuop_func op_90bb_4_ff;
-extern cpuop_func op_90bc_4_nf;
-extern cpuop_func op_90bc_4_ff;
-extern cpuop_func op_90c0_4_nf;
-extern cpuop_func op_90c0_4_ff;
-extern cpuop_func op_90c8_4_nf;
-extern cpuop_func op_90c8_4_ff;
-extern cpuop_func op_90d0_4_nf;
-extern cpuop_func op_90d0_4_ff;
-extern cpuop_func op_90d8_4_nf;
-extern cpuop_func op_90d8_4_ff;
-extern cpuop_func op_90e0_4_nf;
-extern cpuop_func op_90e0_4_ff;
-extern cpuop_func op_90e8_4_nf;
-extern cpuop_func op_90e8_4_ff;
-extern cpuop_func op_90f0_4_nf;
-extern cpuop_func op_90f0_4_ff;
-extern cpuop_func op_90f8_4_nf;
-extern cpuop_func op_90f8_4_ff;
-extern cpuop_func op_90f9_4_nf;
-extern cpuop_func op_90f9_4_ff;
-extern cpuop_func op_90fa_4_nf;
-extern cpuop_func op_90fa_4_ff;
-extern cpuop_func op_90fb_4_nf;
-extern cpuop_func op_90fb_4_ff;
-extern cpuop_func op_90fc_4_nf;
-extern cpuop_func op_90fc_4_ff;
-extern cpuop_func op_9100_4_nf;
-extern cpuop_func op_9100_4_ff;
-extern cpuop_func op_9108_4_nf;
-extern cpuop_func op_9108_4_ff;
-extern cpuop_func op_9110_4_nf;
-extern cpuop_func op_9110_4_ff;
-extern cpuop_func op_9118_4_nf;
-extern cpuop_func op_9118_4_ff;
-extern cpuop_func op_9120_4_nf;
-extern cpuop_func op_9120_4_ff;
-extern cpuop_func op_9128_4_nf;
-extern cpuop_func op_9128_4_ff;
-extern cpuop_func op_9130_4_nf;
-extern cpuop_func op_9130_4_ff;
-extern cpuop_func op_9138_4_nf;
-extern cpuop_func op_9138_4_ff;
-extern cpuop_func op_9139_4_nf;
-extern cpuop_func op_9139_4_ff;
-extern cpuop_func op_9140_4_nf;
-extern cpuop_func op_9140_4_ff;
-extern cpuop_func op_9148_4_nf;
-extern cpuop_func op_9148_4_ff;
-extern cpuop_func op_9150_4_nf;
-extern cpuop_func op_9150_4_ff;
-extern cpuop_func op_9158_4_nf;
-extern cpuop_func op_9158_4_ff;
-extern cpuop_func op_9160_4_nf;
-extern cpuop_func op_9160_4_ff;
-extern cpuop_func op_9168_4_nf;
-extern cpuop_func op_9168_4_ff;
-extern cpuop_func op_9170_4_nf;
-extern cpuop_func op_9170_4_ff;
-extern cpuop_func op_9178_4_nf;
-extern cpuop_func op_9178_4_ff;
-extern cpuop_func op_9179_4_nf;
-extern cpuop_func op_9179_4_ff;
-extern cpuop_func op_9180_4_nf;
-extern cpuop_func op_9180_4_ff;
-extern cpuop_func op_9188_4_nf;
-extern cpuop_func op_9188_4_ff;
-extern cpuop_func op_9190_4_nf;
-extern cpuop_func op_9190_4_ff;
-extern cpuop_func op_9198_4_nf;
-extern cpuop_func op_9198_4_ff;
-extern cpuop_func op_91a0_4_nf;
-extern cpuop_func op_91a0_4_ff;
-extern cpuop_func op_91a8_4_nf;
-extern cpuop_func op_91a8_4_ff;
-extern cpuop_func op_91b0_4_nf;
-extern cpuop_func op_91b0_4_ff;
-extern cpuop_func op_91b8_4_nf;
-extern cpuop_func op_91b8_4_ff;
-extern cpuop_func op_91b9_4_nf;
-extern cpuop_func op_91b9_4_ff;
-extern cpuop_func op_91c0_4_nf;
-extern cpuop_func op_91c0_4_ff;
-extern cpuop_func op_91c8_4_nf;
-extern cpuop_func op_91c8_4_ff;
-extern cpuop_func op_91d0_4_nf;
-extern cpuop_func op_91d0_4_ff;
-extern cpuop_func op_91d8_4_nf;
-extern cpuop_func op_91d8_4_ff;
-extern cpuop_func op_91e0_4_nf;
-extern cpuop_func op_91e0_4_ff;
-extern cpuop_func op_91e8_4_nf;
-extern cpuop_func op_91e8_4_ff;
-extern cpuop_func op_91f0_4_nf;
-extern cpuop_func op_91f0_4_ff;
-extern cpuop_func op_91f8_4_nf;
-extern cpuop_func op_91f8_4_ff;
-extern cpuop_func op_91f9_4_nf;
-extern cpuop_func op_91f9_4_ff;
-extern cpuop_func op_91fa_4_nf;
-extern cpuop_func op_91fa_4_ff;
-extern cpuop_func op_91fb_4_nf;
-extern cpuop_func op_91fb_4_ff;
-extern cpuop_func op_91fc_4_nf;
-extern cpuop_func op_91fc_4_ff;
-extern cpuop_func op_b000_4_nf;
-extern cpuop_func op_b000_4_ff;
-extern cpuop_func op_b010_4_nf;
-extern cpuop_func op_b010_4_ff;
-extern cpuop_func op_b018_4_nf;
-extern cpuop_func op_b018_4_ff;
-extern cpuop_func op_b020_4_nf;
-extern cpuop_func op_b020_4_ff;
-extern cpuop_func op_b028_4_nf;
-extern cpuop_func op_b028_4_ff;
-extern cpuop_func op_b030_4_nf;
-extern cpuop_func op_b030_4_ff;
-extern cpuop_func op_b038_4_nf;
-extern cpuop_func op_b038_4_ff;
-extern cpuop_func op_b039_4_nf;
-extern cpuop_func op_b039_4_ff;
-extern cpuop_func op_b03a_4_nf;
-extern cpuop_func op_b03a_4_ff;
-extern cpuop_func op_b03b_4_nf;
-extern cpuop_func op_b03b_4_ff;
-extern cpuop_func op_b03c_4_nf;
-extern cpuop_func op_b03c_4_ff;
-extern cpuop_func op_b040_4_nf;
-extern cpuop_func op_b040_4_ff;
-extern cpuop_func op_b048_4_nf;
-extern cpuop_func op_b048_4_ff;
-extern cpuop_func op_b050_4_nf;
-extern cpuop_func op_b050_4_ff;
-extern cpuop_func op_b058_4_nf;
-extern cpuop_func op_b058_4_ff;
-extern cpuop_func op_b060_4_nf;
-extern cpuop_func op_b060_4_ff;
-extern cpuop_func op_b068_4_nf;
-extern cpuop_func op_b068_4_ff;
-extern cpuop_func op_b070_4_nf;
-extern cpuop_func op_b070_4_ff;
-extern cpuop_func op_b078_4_nf;
-extern cpuop_func op_b078_4_ff;
-extern cpuop_func op_b079_4_nf;
-extern cpuop_func op_b079_4_ff;
-extern cpuop_func op_b07a_4_nf;
-extern cpuop_func op_b07a_4_ff;
-extern cpuop_func op_b07b_4_nf;
-extern cpuop_func op_b07b_4_ff;
-extern cpuop_func op_b07c_4_nf;
-extern cpuop_func op_b07c_4_ff;
-extern cpuop_func op_b080_4_nf;
-extern cpuop_func op_b080_4_ff;
-extern cpuop_func op_b088_4_nf;
-extern cpuop_func op_b088_4_ff;
-extern cpuop_func op_b090_4_nf;
-extern cpuop_func op_b090_4_ff;
-extern cpuop_func op_b098_4_nf;
-extern cpuop_func op_b098_4_ff;
-extern cpuop_func op_b0a0_4_nf;
-extern cpuop_func op_b0a0_4_ff;
-extern cpuop_func op_b0a8_4_nf;
-extern cpuop_func op_b0a8_4_ff;
-extern cpuop_func op_b0b0_4_nf;
-extern cpuop_func op_b0b0_4_ff;
-extern cpuop_func op_b0b8_4_nf;
-extern cpuop_func op_b0b8_4_ff;
-extern cpuop_func op_b0b9_4_nf;
-extern cpuop_func op_b0b9_4_ff;
-extern cpuop_func op_b0ba_4_nf;
-extern cpuop_func op_b0ba_4_ff;
-extern cpuop_func op_b0bb_4_nf;
-extern cpuop_func op_b0bb_4_ff;
-extern cpuop_func op_b0bc_4_nf;
-extern cpuop_func op_b0bc_4_ff;
-extern cpuop_func op_b0c0_4_nf;
-extern cpuop_func op_b0c0_4_ff;
-extern cpuop_func op_b0c8_4_nf;
-extern cpuop_func op_b0c8_4_ff;
-extern cpuop_func op_b0d0_4_nf;
-extern cpuop_func op_b0d0_4_ff;
-extern cpuop_func op_b0d8_4_nf;
-extern cpuop_func op_b0d8_4_ff;
-extern cpuop_func op_b0e0_4_nf;
-extern cpuop_func op_b0e0_4_ff;
-extern cpuop_func op_b0e8_4_nf;
-extern cpuop_func op_b0e8_4_ff;
-extern cpuop_func op_b0f0_4_nf;
-extern cpuop_func op_b0f0_4_ff;
-extern cpuop_func op_b0f8_4_nf;
-extern cpuop_func op_b0f8_4_ff;
-extern cpuop_func op_b0f9_4_nf;
-extern cpuop_func op_b0f9_4_ff;
-extern cpuop_func op_b0fa_4_nf;
-extern cpuop_func op_b0fa_4_ff;
-extern cpuop_func op_b0fb_4_nf;
-extern cpuop_func op_b0fb_4_ff;
-extern cpuop_func op_b0fc_4_nf;
-extern cpuop_func op_b0fc_4_ff;
-extern cpuop_func op_b100_4_nf;
-extern cpuop_func op_b100_4_ff;
-extern cpuop_func op_b108_4_nf;
-extern cpuop_func op_b108_4_ff;
-extern cpuop_func op_b110_4_nf;
-extern cpuop_func op_b110_4_ff;
-extern cpuop_func op_b118_4_nf;
-extern cpuop_func op_b118_4_ff;
-extern cpuop_func op_b120_4_nf;
-extern cpuop_func op_b120_4_ff;
-extern cpuop_func op_b128_4_nf;
-extern cpuop_func op_b128_4_ff;
-extern cpuop_func op_b130_4_nf;
-extern cpuop_func op_b130_4_ff;
-extern cpuop_func op_b138_4_nf;
-extern cpuop_func op_b138_4_ff;
-extern cpuop_func op_b139_4_nf;
-extern cpuop_func op_b139_4_ff;
-extern cpuop_func op_b140_4_nf;
-extern cpuop_func op_b140_4_ff;
-extern cpuop_func op_b148_4_nf;
-extern cpuop_func op_b148_4_ff;
-extern cpuop_func op_b150_4_nf;
-extern cpuop_func op_b150_4_ff;
-extern cpuop_func op_b158_4_nf;
-extern cpuop_func op_b158_4_ff;
-extern cpuop_func op_b160_4_nf;
-extern cpuop_func op_b160_4_ff;
-extern cpuop_func op_b168_4_nf;
-extern cpuop_func op_b168_4_ff;
-extern cpuop_func op_b170_4_nf;
-extern cpuop_func op_b170_4_ff;
-extern cpuop_func op_b178_4_nf;
-extern cpuop_func op_b178_4_ff;
-extern cpuop_func op_b179_4_nf;
-extern cpuop_func op_b179_4_ff;
-extern cpuop_func op_b180_4_nf;
-extern cpuop_func op_b180_4_ff;
-extern cpuop_func op_b188_4_nf;
-extern cpuop_func op_b188_4_ff;
-extern cpuop_func op_b190_4_nf;
-extern cpuop_func op_b190_4_ff;
-extern cpuop_func op_b198_4_nf;
-extern cpuop_func op_b198_4_ff;
-extern cpuop_func op_b1a0_4_nf;
-extern cpuop_func op_b1a0_4_ff;
-extern cpuop_func op_b1a8_4_nf;
-extern cpuop_func op_b1a8_4_ff;
-extern cpuop_func op_b1b0_4_nf;
-extern cpuop_func op_b1b0_4_ff;
-extern cpuop_func op_b1b8_4_nf;
-extern cpuop_func op_b1b8_4_ff;
-extern cpuop_func op_b1b9_4_nf;
-extern cpuop_func op_b1b9_4_ff;
-extern cpuop_func op_b1c0_4_nf;
-extern cpuop_func op_b1c0_4_ff;
-extern cpuop_func op_b1c8_4_nf;
-extern cpuop_func op_b1c8_4_ff;
-extern cpuop_func op_b1d0_4_nf;
-extern cpuop_func op_b1d0_4_ff;
-extern cpuop_func op_b1d8_4_nf;
-extern cpuop_func op_b1d8_4_ff;
-extern cpuop_func op_b1e0_4_nf;
-extern cpuop_func op_b1e0_4_ff;
-extern cpuop_func op_b1e8_4_nf;
-extern cpuop_func op_b1e8_4_ff;
-extern cpuop_func op_b1f0_4_nf;
-extern cpuop_func op_b1f0_4_ff;
-extern cpuop_func op_b1f8_4_nf;
-extern cpuop_func op_b1f8_4_ff;
-extern cpuop_func op_b1f9_4_nf;
-extern cpuop_func op_b1f9_4_ff;
-extern cpuop_func op_b1fa_4_nf;
-extern cpuop_func op_b1fa_4_ff;
-extern cpuop_func op_b1fb_4_nf;
-extern cpuop_func op_b1fb_4_ff;
-extern cpuop_func op_b1fc_4_nf;
-extern cpuop_func op_b1fc_4_ff;
-extern cpuop_func op_c000_4_nf;
-extern cpuop_func op_c000_4_ff;
-extern cpuop_func op_c010_4_nf;
-extern cpuop_func op_c010_4_ff;
-extern cpuop_func op_c018_4_nf;
-extern cpuop_func op_c018_4_ff;
-extern cpuop_func op_c020_4_nf;
-extern cpuop_func op_c020_4_ff;
-extern cpuop_func op_c028_4_nf;
-extern cpuop_func op_c028_4_ff;
-extern cpuop_func op_c030_4_nf;
-extern cpuop_func op_c030_4_ff;
-extern cpuop_func op_c038_4_nf;
-extern cpuop_func op_c038_4_ff;
-extern cpuop_func op_c039_4_nf;
-extern cpuop_func op_c039_4_ff;
-extern cpuop_func op_c03a_4_nf;
-extern cpuop_func op_c03a_4_ff;
-extern cpuop_func op_c03b_4_nf;
-extern cpuop_func op_c03b_4_ff;
-extern cpuop_func op_c03c_4_nf;
-extern cpuop_func op_c03c_4_ff;
-extern cpuop_func op_c040_4_nf;
-extern cpuop_func op_c040_4_ff;
-extern cpuop_func op_c050_4_nf;
-extern cpuop_func op_c050_4_ff;
-extern cpuop_func op_c058_4_nf;
-extern cpuop_func op_c058_4_ff;
-extern cpuop_func op_c060_4_nf;
-extern cpuop_func op_c060_4_ff;
-extern cpuop_func op_c068_4_nf;
-extern cpuop_func op_c068_4_ff;
-extern cpuop_func op_c070_4_nf;
-extern cpuop_func op_c070_4_ff;
-extern cpuop_func op_c078_4_nf;
-extern cpuop_func op_c078_4_ff;
-extern cpuop_func op_c079_4_nf;
-extern cpuop_func op_c079_4_ff;
-extern cpuop_func op_c07a_4_nf;
-extern cpuop_func op_c07a_4_ff;
-extern cpuop_func op_c07b_4_nf;
-extern cpuop_func op_c07b_4_ff;
-extern cpuop_func op_c07c_4_nf;
-extern cpuop_func op_c07c_4_ff;
-extern cpuop_func op_c080_4_nf;
-extern cpuop_func op_c080_4_ff;
-extern cpuop_func op_c090_4_nf;
-extern cpuop_func op_c090_4_ff;
-extern cpuop_func op_c098_4_nf;
-extern cpuop_func op_c098_4_ff;
-extern cpuop_func op_c0a0_4_nf;
-extern cpuop_func op_c0a0_4_ff;
-extern cpuop_func op_c0a8_4_nf;
-extern cpuop_func op_c0a8_4_ff;
-extern cpuop_func op_c0b0_4_nf;
-extern cpuop_func op_c0b0_4_ff;
-extern cpuop_func op_c0b8_4_nf;
-extern cpuop_func op_c0b8_4_ff;
-extern cpuop_func op_c0b9_4_nf;
-extern cpuop_func op_c0b9_4_ff;
-extern cpuop_func op_c0ba_4_nf;
-extern cpuop_func op_c0ba_4_ff;
-extern cpuop_func op_c0bb_4_nf;
-extern cpuop_func op_c0bb_4_ff;
-extern cpuop_func op_c0bc_4_nf;
-extern cpuop_func op_c0bc_4_ff;
-extern cpuop_func op_c0c0_4_nf;
-extern cpuop_func op_c0c0_4_ff;
-extern cpuop_func op_c0d0_4_nf;
-extern cpuop_func op_c0d0_4_ff;
-extern cpuop_func op_c0d8_4_nf;
-extern cpuop_func op_c0d8_4_ff;
-extern cpuop_func op_c0e0_4_nf;
-extern cpuop_func op_c0e0_4_ff;
-extern cpuop_func op_c0e8_4_nf;
-extern cpuop_func op_c0e8_4_ff;
-extern cpuop_func op_c0f0_4_nf;
-extern cpuop_func op_c0f0_4_ff;
-extern cpuop_func op_c0f8_4_nf;
-extern cpuop_func op_c0f8_4_ff;
-extern cpuop_func op_c0f9_4_nf;
-extern cpuop_func op_c0f9_4_ff;
-extern cpuop_func op_c0fa_4_nf;
-extern cpuop_func op_c0fa_4_ff;
-extern cpuop_func op_c0fb_4_nf;
-extern cpuop_func op_c0fb_4_ff;
-extern cpuop_func op_c0fc_4_nf;
-extern cpuop_func op_c0fc_4_ff;
-extern cpuop_func op_c100_4_nf;
-extern cpuop_func op_c100_4_ff;
-extern cpuop_func op_c108_4_nf;
-extern cpuop_func op_c108_4_ff;
-extern cpuop_func op_c110_4_nf;
-extern cpuop_func op_c110_4_ff;
-extern cpuop_func op_c118_4_nf;
-extern cpuop_func op_c118_4_ff;
-extern cpuop_func op_c120_4_nf;
-extern cpuop_func op_c120_4_ff;
-extern cpuop_func op_c128_4_nf;
-extern cpuop_func op_c128_4_ff;
-extern cpuop_func op_c130_4_nf;
-extern cpuop_func op_c130_4_ff;
-extern cpuop_func op_c138_4_nf;
-extern cpuop_func op_c138_4_ff;
-extern cpuop_func op_c139_4_nf;
-extern cpuop_func op_c139_4_ff;
-extern cpuop_func op_c140_4_nf;
-extern cpuop_func op_c140_4_ff;
-extern cpuop_func op_c148_4_nf;
-extern cpuop_func op_c148_4_ff;
-extern cpuop_func op_c150_4_nf;
-extern cpuop_func op_c150_4_ff;
-extern cpuop_func op_c158_4_nf;
-extern cpuop_func op_c158_4_ff;
-extern cpuop_func op_c160_4_nf;
-extern cpuop_func op_c160_4_ff;
-extern cpuop_func op_c168_4_nf;
-extern cpuop_func op_c168_4_ff;
-extern cpuop_func op_c170_4_nf;
-extern cpuop_func op_c170_4_ff;
-extern cpuop_func op_c178_4_nf;
-extern cpuop_func op_c178_4_ff;
-extern cpuop_func op_c179_4_nf;
-extern cpuop_func op_c179_4_ff;
-extern cpuop_func op_c188_4_nf;
-extern cpuop_func op_c188_4_ff;
-extern cpuop_func op_c190_4_nf;
-extern cpuop_func op_c190_4_ff;
-extern cpuop_func op_c198_4_nf;
-extern cpuop_func op_c198_4_ff;
-extern cpuop_func op_c1a0_4_nf;
-extern cpuop_func op_c1a0_4_ff;
-extern cpuop_func op_c1a8_4_nf;
-extern cpuop_func op_c1a8_4_ff;
-extern cpuop_func op_c1b0_4_nf;
-extern cpuop_func op_c1b0_4_ff;
-extern cpuop_func op_c1b8_4_nf;
-extern cpuop_func op_c1b8_4_ff;
-extern cpuop_func op_c1b9_4_nf;
-extern cpuop_func op_c1b9_4_ff;
-extern cpuop_func op_c1c0_4_nf;
-extern cpuop_func op_c1c0_4_ff;
-extern cpuop_func op_c1d0_4_nf;
-extern cpuop_func op_c1d0_4_ff;
-extern cpuop_func op_c1d8_4_nf;
-extern cpuop_func op_c1d8_4_ff;
-extern cpuop_func op_c1e0_4_nf;
-extern cpuop_func op_c1e0_4_ff;
-extern cpuop_func op_c1e8_4_nf;
-extern cpuop_func op_c1e8_4_ff;
-extern cpuop_func op_c1f0_4_nf;
-extern cpuop_func op_c1f0_4_ff;
-extern cpuop_func op_c1f8_4_nf;
-extern cpuop_func op_c1f8_4_ff;
-extern cpuop_func op_c1f9_4_nf;
-extern cpuop_func op_c1f9_4_ff;
-extern cpuop_func op_c1fa_4_nf;
-extern cpuop_func op_c1fa_4_ff;
-extern cpuop_func op_c1fb_4_nf;
-extern cpuop_func op_c1fb_4_ff;
-extern cpuop_func op_c1fc_4_nf;
-extern cpuop_func op_c1fc_4_ff;
-extern cpuop_func op_d000_4_nf;
-extern cpuop_func op_d000_4_ff;
-extern cpuop_func op_d010_4_nf;
-extern cpuop_func op_d010_4_ff;
-extern cpuop_func op_d018_4_nf;
-extern cpuop_func op_d018_4_ff;
-extern cpuop_func op_d020_4_nf;
-extern cpuop_func op_d020_4_ff;
-extern cpuop_func op_d028_4_nf;
-extern cpuop_func op_d028_4_ff;
-extern cpuop_func op_d030_4_nf;
-extern cpuop_func op_d030_4_ff;
-extern cpuop_func op_d038_4_nf;
-extern cpuop_func op_d038_4_ff;
-extern cpuop_func op_d039_4_nf;
-extern cpuop_func op_d039_4_ff;
-extern cpuop_func op_d03a_4_nf;
-extern cpuop_func op_d03a_4_ff;
-extern cpuop_func op_d03b_4_nf;
-extern cpuop_func op_d03b_4_ff;
-extern cpuop_func op_d03c_4_nf;
-extern cpuop_func op_d03c_4_ff;
-extern cpuop_func op_d040_4_nf;
-extern cpuop_func op_d040_4_ff;
-extern cpuop_func op_d048_4_nf;
-extern cpuop_func op_d048_4_ff;
-extern cpuop_func op_d050_4_nf;
-extern cpuop_func op_d050_4_ff;
-extern cpuop_func op_d058_4_nf;
-extern cpuop_func op_d058_4_ff;
-extern cpuop_func op_d060_4_nf;
-extern cpuop_func op_d060_4_ff;
-extern cpuop_func op_d068_4_nf;
-extern cpuop_func op_d068_4_ff;
-extern cpuop_func op_d070_4_nf;
-extern cpuop_func op_d070_4_ff;
-extern cpuop_func op_d078_4_nf;
-extern cpuop_func op_d078_4_ff;
-extern cpuop_func op_d079_4_nf;
-extern cpuop_func op_d079_4_ff;
-extern cpuop_func op_d07a_4_nf;
-extern cpuop_func op_d07a_4_ff;
-extern cpuop_func op_d07b_4_nf;
-extern cpuop_func op_d07b_4_ff;
-extern cpuop_func op_d07c_4_nf;
-extern cpuop_func op_d07c_4_ff;
-extern cpuop_func op_d080_4_nf;
-extern cpuop_func op_d080_4_ff;
-extern cpuop_func op_d088_4_nf;
-extern cpuop_func op_d088_4_ff;
-extern cpuop_func op_d090_4_nf;
-extern cpuop_func op_d090_4_ff;
-extern cpuop_func op_d098_4_nf;
-extern cpuop_func op_d098_4_ff;
-extern cpuop_func op_d0a0_4_nf;
-extern cpuop_func op_d0a0_4_ff;
-extern cpuop_func op_d0a8_4_nf;
-extern cpuop_func op_d0a8_4_ff;
-extern cpuop_func op_d0b0_4_nf;
-extern cpuop_func op_d0b0_4_ff;
-extern cpuop_func op_d0b8_4_nf;
-extern cpuop_func op_d0b8_4_ff;
-extern cpuop_func op_d0b9_4_nf;
-extern cpuop_func op_d0b9_4_ff;
-extern cpuop_func op_d0ba_4_nf;
-extern cpuop_func op_d0ba_4_ff;
-extern cpuop_func op_d0bb_4_nf;
-extern cpuop_func op_d0bb_4_ff;
-extern cpuop_func op_d0bc_4_nf;
-extern cpuop_func op_d0bc_4_ff;
-extern cpuop_func op_d0c0_4_nf;
-extern cpuop_func op_d0c0_4_ff;
-extern cpuop_func op_d0c8_4_nf;
-extern cpuop_func op_d0c8_4_ff;
-extern cpuop_func op_d0d0_4_nf;
-extern cpuop_func op_d0d0_4_ff;
-extern cpuop_func op_d0d8_4_nf;
-extern cpuop_func op_d0d8_4_ff;
-extern cpuop_func op_d0e0_4_nf;
-extern cpuop_func op_d0e0_4_ff;
-extern cpuop_func op_d0e8_4_nf;
-extern cpuop_func op_d0e8_4_ff;
-extern cpuop_func op_d0f0_4_nf;
-extern cpuop_func op_d0f0_4_ff;
-extern cpuop_func op_d0f8_4_nf;
-extern cpuop_func op_d0f8_4_ff;
-extern cpuop_func op_d0f9_4_nf;
-extern cpuop_func op_d0f9_4_ff;
-extern cpuop_func op_d0fa_4_nf;
-extern cpuop_func op_d0fa_4_ff;
-extern cpuop_func op_d0fb_4_nf;
-extern cpuop_func op_d0fb_4_ff;
-extern cpuop_func op_d0fc_4_nf;
-extern cpuop_func op_d0fc_4_ff;
-extern cpuop_func op_d100_4_nf;
-extern cpuop_func op_d100_4_ff;
-extern cpuop_func op_d108_4_nf;
-extern cpuop_func op_d108_4_ff;
-extern cpuop_func op_d110_4_nf;
-extern cpuop_func op_d110_4_ff;
-extern cpuop_func op_d118_4_nf;
-extern cpuop_func op_d118_4_ff;
-extern cpuop_func op_d120_4_nf;
-extern cpuop_func op_d120_4_ff;
-extern cpuop_func op_d128_4_nf;
-extern cpuop_func op_d128_4_ff;
-extern cpuop_func op_d130_4_nf;
-extern cpuop_func op_d130_4_ff;
-extern cpuop_func op_d138_4_nf;
-extern cpuop_func op_d138_4_ff;
-extern cpuop_func op_d139_4_nf;
-extern cpuop_func op_d139_4_ff;
-extern cpuop_func op_d140_4_nf;
-extern cpuop_func op_d140_4_ff;
-extern cpuop_func op_d148_4_nf;
-extern cpuop_func op_d148_4_ff;
-extern cpuop_func op_d150_4_nf;
-extern cpuop_func op_d150_4_ff;
-extern cpuop_func op_d158_4_nf;
-extern cpuop_func op_d158_4_ff;
-extern cpuop_func op_d160_4_nf;
-extern cpuop_func op_d160_4_ff;
-extern cpuop_func op_d168_4_nf;
-extern cpuop_func op_d168_4_ff;
-extern cpuop_func op_d170_4_nf;
-extern cpuop_func op_d170_4_ff;
-extern cpuop_func op_d178_4_nf;
-extern cpuop_func op_d178_4_ff;
-extern cpuop_func op_d179_4_nf;
-extern cpuop_func op_d179_4_ff;
-extern cpuop_func op_d180_4_nf;
-extern cpuop_func op_d180_4_ff;
-extern cpuop_func op_d188_4_nf;
-extern cpuop_func op_d188_4_ff;
-extern cpuop_func op_d190_4_nf;
-extern cpuop_func op_d190_4_ff;
-extern cpuop_func op_d198_4_nf;
-extern cpuop_func op_d198_4_ff;
-extern cpuop_func op_d1a0_4_nf;
-extern cpuop_func op_d1a0_4_ff;
-extern cpuop_func op_d1a8_4_nf;
-extern cpuop_func op_d1a8_4_ff;
-extern cpuop_func op_d1b0_4_nf;
-extern cpuop_func op_d1b0_4_ff;
-extern cpuop_func op_d1b8_4_nf;
-extern cpuop_func op_d1b8_4_ff;
-extern cpuop_func op_d1b9_4_nf;
-extern cpuop_func op_d1b9_4_ff;
-extern cpuop_func op_d1c0_4_nf;
-extern cpuop_func op_d1c0_4_ff;
-extern cpuop_func op_d1c8_4_nf;
-extern cpuop_func op_d1c8_4_ff;
-extern cpuop_func op_d1d0_4_nf;
-extern cpuop_func op_d1d0_4_ff;
-extern cpuop_func op_d1d8_4_nf;
-extern cpuop_func op_d1d8_4_ff;
-extern cpuop_func op_d1e0_4_nf;
-extern cpuop_func op_d1e0_4_ff;
-extern cpuop_func op_d1e8_4_nf;
-extern cpuop_func op_d1e8_4_ff;
-extern cpuop_func op_d1f0_4_nf;
-extern cpuop_func op_d1f0_4_ff;
-extern cpuop_func op_d1f8_4_nf;
-extern cpuop_func op_d1f8_4_ff;
-extern cpuop_func op_d1f9_4_nf;
-extern cpuop_func op_d1f9_4_ff;
-extern cpuop_func op_d1fa_4_nf;
-extern cpuop_func op_d1fa_4_ff;
-extern cpuop_func op_d1fb_4_nf;
-extern cpuop_func op_d1fb_4_ff;
-extern cpuop_func op_d1fc_4_nf;
-extern cpuop_func op_d1fc_4_ff;
-extern cpuop_func op_e000_4_nf;
-extern cpuop_func op_e000_4_ff;
-extern cpuop_func op_e008_4_nf;
-extern cpuop_func op_e008_4_ff;
-extern cpuop_func op_e010_4_nf;
-extern cpuop_func op_e010_4_ff;
-extern cpuop_func op_e018_4_nf;
-extern cpuop_func op_e018_4_ff;
-extern cpuop_func op_e020_4_nf;
-extern cpuop_func op_e020_4_ff;
-extern cpuop_func op_e028_4_nf;
-extern cpuop_func op_e028_4_ff;
-extern cpuop_func op_e030_4_nf;
-extern cpuop_func op_e030_4_ff;
-extern cpuop_func op_e038_4_nf;
-extern cpuop_func op_e038_4_ff;
-extern cpuop_func op_e040_4_nf;
-extern cpuop_func op_e040_4_ff;
-extern cpuop_func op_e048_4_nf;
-extern cpuop_func op_e048_4_ff;
-extern cpuop_func op_e050_4_nf;
-extern cpuop_func op_e050_4_ff;
-extern cpuop_func op_e058_4_nf;
-extern cpuop_func op_e058_4_ff;
-extern cpuop_func op_e060_4_nf;
-extern cpuop_func op_e060_4_ff;
-extern cpuop_func op_e068_4_nf;
-extern cpuop_func op_e068_4_ff;
-extern cpuop_func op_e070_4_nf;
-extern cpuop_func op_e070_4_ff;
-extern cpuop_func op_e078_4_nf;
-extern cpuop_func op_e078_4_ff;
-extern cpuop_func op_e080_4_nf;
-extern cpuop_func op_e080_4_ff;
-extern cpuop_func op_e088_4_nf;
-extern cpuop_func op_e088_4_ff;
-extern cpuop_func op_e090_4_nf;
-extern cpuop_func op_e090_4_ff;
-extern cpuop_func op_e098_4_nf;
-extern cpuop_func op_e098_4_ff;
-extern cpuop_func op_e0a0_4_nf;
-extern cpuop_func op_e0a0_4_ff;
-extern cpuop_func op_e0a8_4_nf;
-extern cpuop_func op_e0a8_4_ff;
-extern cpuop_func op_e0b0_4_nf;
-extern cpuop_func op_e0b0_4_ff;
-extern cpuop_func op_e0b8_4_nf;
-extern cpuop_func op_e0b8_4_ff;
-extern cpuop_func op_e0d0_4_nf;
-extern cpuop_func op_e0d0_4_ff;
-extern cpuop_func op_e0d8_4_nf;
-extern cpuop_func op_e0d8_4_ff;
-extern cpuop_func op_e0e0_4_nf;
-extern cpuop_func op_e0e0_4_ff;
-extern cpuop_func op_e0e8_4_nf;
-extern cpuop_func op_e0e8_4_ff;
-extern cpuop_func op_e0f0_4_nf;
-extern cpuop_func op_e0f0_4_ff;
-extern cpuop_func op_e0f8_4_nf;
-extern cpuop_func op_e0f8_4_ff;
-extern cpuop_func op_e0f9_4_nf;
-extern cpuop_func op_e0f9_4_ff;
-extern cpuop_func op_e100_4_nf;
-extern cpuop_func op_e100_4_ff;
-extern cpuop_func op_e108_4_nf;
-extern cpuop_func op_e108_4_ff;
-extern cpuop_func op_e110_4_nf;
-extern cpuop_func op_e110_4_ff;
-extern cpuop_func op_e118_4_nf;
-extern cpuop_func op_e118_4_ff;
-extern cpuop_func op_e120_4_nf;
-extern cpuop_func op_e120_4_ff;
-extern cpuop_func op_e128_4_nf;
-extern cpuop_func op_e128_4_ff;
-extern cpuop_func op_e130_4_nf;
-extern cpuop_func op_e130_4_ff;
-extern cpuop_func op_e138_4_nf;
-extern cpuop_func op_e138_4_ff;
-extern cpuop_func op_e140_4_nf;
-extern cpuop_func op_e140_4_ff;
-extern cpuop_func op_e148_4_nf;
-extern cpuop_func op_e148_4_ff;
-extern cpuop_func op_e150_4_nf;
-extern cpuop_func op_e150_4_ff;
-extern cpuop_func op_e158_4_nf;
-extern cpuop_func op_e158_4_ff;
-extern cpuop_func op_e160_4_nf;
-extern cpuop_func op_e160_4_ff;
-extern cpuop_func op_e168_4_nf;
-extern cpuop_func op_e168_4_ff;
-extern cpuop_func op_e170_4_nf;
-extern cpuop_func op_e170_4_ff;
-extern cpuop_func op_e178_4_nf;
-extern cpuop_func op_e178_4_ff;
-extern cpuop_func op_e180_4_nf;
-extern cpuop_func op_e180_4_ff;
-extern cpuop_func op_e188_4_nf;
-extern cpuop_func op_e188_4_ff;
-extern cpuop_func op_e190_4_nf;
-extern cpuop_func op_e190_4_ff;
-extern cpuop_func op_e198_4_nf;
-extern cpuop_func op_e198_4_ff;
-extern cpuop_func op_e1a0_4_nf;
-extern cpuop_func op_e1a0_4_ff;
-extern cpuop_func op_e1a8_4_nf;
-extern cpuop_func op_e1a8_4_ff;
-extern cpuop_func op_e1b0_4_nf;
-extern cpuop_func op_e1b0_4_ff;
-extern cpuop_func op_e1b8_4_nf;
-extern cpuop_func op_e1b8_4_ff;
-extern cpuop_func op_e1d0_4_nf;
-extern cpuop_func op_e1d0_4_ff;
-extern cpuop_func op_e1d8_4_nf;
-extern cpuop_func op_e1d8_4_ff;
-extern cpuop_func op_e1e0_4_nf;
-extern cpuop_func op_e1e0_4_ff;
-extern cpuop_func op_e1e8_4_nf;
-extern cpuop_func op_e1e8_4_ff;
-extern cpuop_func op_e1f0_4_nf;
-extern cpuop_func op_e1f0_4_ff;
-extern cpuop_func op_e1f8_4_nf;
-extern cpuop_func op_e1f8_4_ff;
-extern cpuop_func op_e1f9_4_nf;
-extern cpuop_func op_e1f9_4_ff;
-extern cpuop_func op_e2d0_4_nf;
-extern cpuop_func op_e2d0_4_ff;
-extern cpuop_func op_e2d8_4_nf;
-extern cpuop_func op_e2d8_4_ff;
-extern cpuop_func op_e2e0_4_nf;
-extern cpuop_func op_e2e0_4_ff;
-extern cpuop_func op_e2e8_4_nf;
-extern cpuop_func op_e2e8_4_ff;
-extern cpuop_func op_e2f0_4_nf;
-extern cpuop_func op_e2f0_4_ff;
-extern cpuop_func op_e2f8_4_nf;
-extern cpuop_func op_e2f8_4_ff;
-extern cpuop_func op_e2f9_4_nf;
-extern cpuop_func op_e2f9_4_ff;
-extern cpuop_func op_e3d0_4_nf;
-extern cpuop_func op_e3d0_4_ff;
-extern cpuop_func op_e3d8_4_nf;
-extern cpuop_func op_e3d8_4_ff;
-extern cpuop_func op_e3e0_4_nf;
-extern cpuop_func op_e3e0_4_ff;
-extern cpuop_func op_e3e8_4_nf;
-extern cpuop_func op_e3e8_4_ff;
-extern cpuop_func op_e3f0_4_nf;
-extern cpuop_func op_e3f0_4_ff;
-extern cpuop_func op_e3f8_4_nf;
-extern cpuop_func op_e3f8_4_ff;
-extern cpuop_func op_e3f9_4_nf;
-extern cpuop_func op_e3f9_4_ff;
-extern cpuop_func op_e4d0_4_nf;
-extern cpuop_func op_e4d0_4_ff;
-extern cpuop_func op_e4d8_4_nf;
-extern cpuop_func op_e4d8_4_ff;
-extern cpuop_func op_e4e0_4_nf;
-extern cpuop_func op_e4e0_4_ff;
-extern cpuop_func op_e4e8_4_nf;
-extern cpuop_func op_e4e8_4_ff;
-extern cpuop_func op_e4f0_4_nf;
-extern cpuop_func op_e4f0_4_ff;
-extern cpuop_func op_e4f8_4_nf;
-extern cpuop_func op_e4f8_4_ff;
-extern cpuop_func op_e4f9_4_nf;
-extern cpuop_func op_e4f9_4_ff;
-extern cpuop_func op_e5d0_4_nf;
-extern cpuop_func op_e5d0_4_ff;
-extern cpuop_func op_e5d8_4_nf;
-extern cpuop_func op_e5d8_4_ff;
-extern cpuop_func op_e5e0_4_nf;
-extern cpuop_func op_e5e0_4_ff;
-extern cpuop_func op_e5e8_4_nf;
-extern cpuop_func op_e5e8_4_ff;
-extern cpuop_func op_e5f0_4_nf;
-extern cpuop_func op_e5f0_4_ff;
-extern cpuop_func op_e5f8_4_nf;
-extern cpuop_func op_e5f8_4_ff;
-extern cpuop_func op_e5f9_4_nf;
-extern cpuop_func op_e5f9_4_ff;
-extern cpuop_func op_e6d0_4_nf;
-extern cpuop_func op_e6d0_4_ff;
-extern cpuop_func op_e6d8_4_nf;
-extern cpuop_func op_e6d8_4_ff;
-extern cpuop_func op_e6e0_4_nf;
-extern cpuop_func op_e6e0_4_ff;
-extern cpuop_func op_e6e8_4_nf;
-extern cpuop_func op_e6e8_4_ff;
-extern cpuop_func op_e6f0_4_nf;
-extern cpuop_func op_e6f0_4_ff;
-extern cpuop_func op_e6f8_4_nf;
-extern cpuop_func op_e6f8_4_ff;
-extern cpuop_func op_e6f9_4_nf;
-extern cpuop_func op_e6f9_4_ff;
-extern cpuop_func op_e7d0_4_nf;
-extern cpuop_func op_e7d0_4_ff;
-extern cpuop_func op_e7d8_4_nf;
-extern cpuop_func op_e7d8_4_ff;
-extern cpuop_func op_e7e0_4_nf;
-extern cpuop_func op_e7e0_4_ff;
-extern cpuop_func op_e7e8_4_nf;
-extern cpuop_func op_e7e8_4_ff;
-extern cpuop_func op_e7f0_4_nf;
-extern cpuop_func op_e7f0_4_ff;
-extern cpuop_func op_e7f8_4_nf;
-extern cpuop_func op_e7f8_4_ff;
-extern cpuop_func op_e7f9_4_nf;
-extern cpuop_func op_e7f9_4_ff;
 extern cpuop_func op_0_5_nf;
 extern cpuop_func op_0_5_ff;
 extern cpuop_func op_10_5_nf;
diff --git a/waterbox/virtualjaguar/src/m68000/gencpu.c b/waterbox/virtualjaguar/src/m68000/gencpu.c
deleted file mode 100644
index 88f121ba1b..0000000000
--- a/waterbox/virtualjaguar/src/m68000/gencpu.c
+++ /dev/null
@@ -1,2818 +0,0 @@
-/*
- * UAE - The Un*x Amiga Emulator - CPU core
- *
- * MC68000 emulation generator
- *
- * This is a fairly stupid program that generates a lot of case labels that
- * can be #included in a switch statement.
- * As an alternative, it can generate functions that handle specific
- * MC68000 instructions, plus a prototype header file and a function pointer
- * array to look up the function for an opcode.
- * Error checking is bad, an illegal table68k file will cause the program to
- * call abort().
- * The generated code is sometimes sub-optimal, an optimizing compiler should
- * take care of this.
- *
- * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
- *
- * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
- *
- * Adaptation to Hatari and better cpu timings by Thomas Huth
- * Adaptation to Virtual Jaguar by James Hammons
- *
- * This file is distributed under the GNU Public License, version 3 or at
- * your option any later version. Read the file GPLv3 for details.
- *
- */
-
-
-/* 2007/03/xx	[NP]	Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode.			*/
-/* 2007/04/09	[NP]	Correct CLR : on 68000, CLR reads the memory before clearing it (but we should	*/
-/*			not add cycles for reading). This means CLR can give 2 wait states (one for	*/
-/*			read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu).		*/
-/* 2007/04/14	[NP]	- Although dest -(an) normally takes 2 cycles, this is not the case for move :	*/
-/*			move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi)	*/
-/*			(Syntax Terror Demo Reset).							*/
-/*			- Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader).	*/
-/*			- Store the family of the current opcode into OpcodeFamily : used to check	*/
-/*			instruction pairing on ST into m68000.c						*/
-/* 2007/04/17	[NP]	Add support for cycle accurate MULU (No Cooper Greeting Screen).		*/	
-/* 2007/04/24	[NP]	BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu).		*/
-/* 2007/04/25	[NP]	On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's	*/
-/*			table (ULM Demo Menu).								*/
-/* 2007/11/12	[NP]	Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code.	*/
-/*			Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c)	*/
-/* 2007/11/25	[NP]	In i_DBcc, in case of address error, last_addr_for_exception_3 should be	*/
-/*			pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5').			*/
-/*			This means the value pushed on the frame stack should be the address of the	*/
-/*			instruction following the one generating the address error.			*/
-/*			FIXME : this should be the case for i_BSR and i_BCC too	(need to check on	*/
-/*			a real 68000).									*/
-/* 2007/11/28	[NP]	Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge	*/
-/*			Cwik, pasti@fxatari.com).							*/
-/* 2007/12/08	[NP]	In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the	*/
-/*			next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo).	*/
-/*			We need to call 'sync_m68k_pc' before calling 'Exception'.			*/
-/* 2007/12/09	[NP]	CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/
-/*			instruction (Transbeauce 2 demo) -> change in table68k.				*/
-/* 2008/01/24	[NP]	BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos).	*/
-/* 2008/01/26	[NP]	On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu)	*/
-/*			but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so	*/
-/*			can pair with a lsr) (Anomaly Demo Intro).					*/
-/* 2008/04/26	[NP]	Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible	*/
-/*			on ST (fix Blood Money on Superior 65)						*/
-/* 2010/04/05	[NP]	On ST, d8(An,Xn) takes 2 cycles more (which can generate pairing).		*/
-/*			Use BusCyclePenalty to properly handle the 2/4 cycles added in that case when	*/
-/*			addressing mode	is Ad8r or PC8r	(ULM Demo Menu, Anomaly Demo Intro, DHS		*/
-/*			Sommarhack 2010) (see m68000.h)							*/
-
-
-//const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__;
-
-#include <ctype.h>
-#include <string.h>
-
-#include "sysdeps.h"
-#include "readcpu.h"
-
-#define BOOL_TYPE "int"
-
-static FILE *headerfile;
-static FILE *stblfile;
-
-static int using_prefetch;
-static int using_exception_3;
-static int cpu_level;
-
-char exactCpuCycles[256];   /* Space to store return string for exact cpu cycles */
-
-long nCurInstrCycPos;  /* Stores where we have to patch in the current cycles value */
-
-/* For the current opcode, the next lower level that will have different code.
- * Initialized to -1 for each opcode. If it remains unchanged, indicates we
- * are done with that opcode.  */
-static int next_cpu_level;
-static int *opcode_map;
-static int *opcode_next_clev;
-static int *opcode_last_postfix;
-static unsigned long *counts;
-
-
-static void read_counts (void)
-{
-    FILE *file;
-    unsigned long opcode, count, total;
-    char name[20];
-    int nr = 0;
-    memset (counts, 0, 65536 * sizeof *counts);
-
-    file = fopen ("frequent.68k", "r");
-    if (file) {
-	if (fscanf (file, "Total: %lu\n", &total) == EOF) {
-	    perror("read_counts");
-	}
-	while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
-	    opcode_next_clev[nr] = 4;
-	    opcode_last_postfix[nr] = -1;
-	    opcode_map[nr++] = opcode;
-	    counts[opcode] = count;
-	}
-	fclose (file);
-    }
-    if (nr == nr_cpuop_funcs)
-	return;
-    for (opcode = 0; opcode < 0x10000; opcode++) {
-	if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
-	    && counts[opcode] == 0)
-	{
-	    opcode_next_clev[nr] = 4;
-	    opcode_last_postfix[nr] = -1;
-	    opcode_map[nr++] = opcode;
-	    counts[opcode] = count;
-	}
-    }
-    if (nr != nr_cpuop_funcs)
-	abort ();
-}
-
-static char endlabelstr[80];
-static int endlabelno = 0;
-static int need_endlabel;
-
-static int n_braces = 0;
-static int m68k_pc_offset = 0;
-static int insn_n_cycles;
-
-static void start_brace (void)
-{
-    n_braces++;
-    printf ("{");
-}
-
-static void close_brace (void)
-{
-    assert (n_braces > 0);
-    n_braces--;
-    printf ("}");
-}
-
-static void finish_braces (void)
-{
-    while (n_braces > 0)
-	close_brace ();
-}
-
-static void pop_braces (int to)
-{
-    while (n_braces > to)
-	close_brace ();
-}
-
-static int bit_size (int size)
-{
-    switch (size) {
-     case sz_byte: return 8;
-     case sz_word: return 16;
-     case sz_long: return 32;
-     default: abort ();
-    }
-    return 0;
-}
-
-static const char *bit_mask (int size)
-{
-    switch (size) {
-     case sz_byte: return "0xff";
-     case sz_word: return "0xffff";
-     case sz_long: return "0xffffffff";
-     default: abort ();
-    }
-    return 0;
-}
-
-static const char *gen_nextilong (void)
-{
-    static char buffer[80];
-    int r = m68k_pc_offset;
-    m68k_pc_offset += 4;
-
-    insn_n_cycles += 8;
-
-    if (using_prefetch)
-	sprintf (buffer, "get_ilong_prefetch(%d)", r);
-    else
-	sprintf (buffer, "get_ilong(%d)", r);
-    return buffer;
-}
-
-static const char *gen_nextiword (void)
-{
-    static char buffer[80];
-    int r = m68k_pc_offset;
-    m68k_pc_offset += 2;
-
-    insn_n_cycles += 4;
-
-    if (using_prefetch)
-	sprintf (buffer, "get_iword_prefetch(%d)", r);
-    else
-	sprintf (buffer, "get_iword(%d)", r);
-    return buffer;
-}
-
-static const char *gen_nextibyte (void)
-{
-    static char buffer[80];
-    int r = m68k_pc_offset;
-    m68k_pc_offset += 2;
-
-    insn_n_cycles += 4;
-
-    if (using_prefetch)
-	sprintf (buffer, "get_ibyte_prefetch(%d)", r);
-    else
-	sprintf (buffer, "get_ibyte(%d)", r);
-    return buffer;
-}
-
-static void fill_prefetch_0 (void)
-{
-    if (using_prefetch)
-	printf ("fill_prefetch_0 ();\n");
-}
-
-static void fill_prefetch_2 (void)
-{
-    if (using_prefetch)
-	printf ("fill_prefetch_2 ();\n");
-}
-
-static void sync_m68k_pc(void)
-{
-	if (m68k_pc_offset == 0)
-		return;
-
-	printf("m68k_incpc(%d);\n", m68k_pc_offset);
-
-	switch (m68k_pc_offset)
-	{
-	case 0:
-	/*fprintf (stderr, "refilling prefetch at 0\n"); */
-		break;
-	case 2:
-		fill_prefetch_2();
-		break;
-	default:
-		fill_prefetch_0();
-		break;
-	}
-
-	m68k_pc_offset = 0;
-}
-
-/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
- * the calling routine handles Apdi and Aipi modes.
- * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
-static void genamode(amodes mode, const char * reg, wordsizes size,
-	const char * name, int getv, int movem)
-{
-	start_brace();
-	switch (mode)
-	{
-	case Dreg:
-	if (movem)
-		abort ();
-	if (getv == 1)
-		switch (size) {
-		case sz_byte:
-		printf ("\tint8_t %s = m68k_dreg(regs, %s);\n", name, reg);
-		break;
-		case sz_word:
-		printf ("\tint16_t %s = m68k_dreg(regs, %s);\n", name, reg);
-		break;
-		case sz_long:
-		printf ("\tint32_t %s = m68k_dreg(regs, %s);\n", name, reg);
-		break;
-		default:
-		abort ();
-		}
-	return;
-	case Areg:
-	if (movem)
-		abort ();
-	if (getv == 1)
-		switch (size) {
-		case sz_byte:				// [NP] Areg with .b is possible in MOVE source */
-		printf ("\tint8_t %s = m68k_areg(regs, %s);\n", name, reg);
-		break;
-		case sz_word:
-		printf ("\tint16_t %s = m68k_areg(regs, %s);\n", name, reg);
-		break;
-		case sz_long:
-		printf ("\tint32_t %s = m68k_areg(regs, %s);\n", name, reg);
-		break;
-		default:
-		abort ();
-		}
-	return;
-	case Aind:
-	printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg);
-	break;
-	case Aipi:
-	printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg);
-	break;
-	case Apdi:
-	insn_n_cycles += 2;
-	switch (size) {
-	case sz_byte:
-		if (movem)
-		printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg);
-		else
-		printf ("\tuint32_t %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
-		break;
-	case sz_word:
-		printf ("\tuint32_t %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
-		break;
-	case sz_long:
-		printf ("\tuint32_t %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
-		break;
-	default:
-		abort ();
-	}
-	break;
-	case Ad16:
-	printf ("\tuint32_t %sa = m68k_areg(regs, %s) + (int32_t)(int16_t)%s;\n", name, reg, gen_nextiword ());
-	break;
-	case Ad8r:
-	insn_n_cycles += 2;
-	if (cpu_level > 1) {
-		if (next_cpu_level < 1)
-		next_cpu_level = 1;
-		sync_m68k_pc ();
-		start_brace ();
-		/* This would ordinarily be done in gen_nextiword, which we bypass.  */
-		insn_n_cycles += 4;
-		printf ("\tuint32_t %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg);
-	} else {
-		printf ("\tuint32_t %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ());
-	}
-	printf ("\tBusCyclePenalty += 2;\n");
-
-	break;
-	case PC16:
-	printf ("\tuint32_t %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
-	printf ("\t%sa += (int32_t)(int16_t)%s;\n", name, gen_nextiword ());
-	break;
-	case PC8r:
-	insn_n_cycles += 2;
-	if (cpu_level > 1) {
-		if (next_cpu_level < 1)
-		next_cpu_level = 1;
-		sync_m68k_pc ();
-		start_brace ();
-		/* This would ordinarily be done in gen_nextiword, which we bypass.  */
-		insn_n_cycles += 4;
-		printf ("\tuint32_t tmppc = m68k_getpc();\n");
-		printf ("\tuint32_t %sa = get_disp_ea_020(tmppc, next_iword());\n", name);
-	} else {
-		printf ("\tuint32_t tmppc = m68k_getpc() + %d;\n", m68k_pc_offset);
-		printf ("\tuint32_t %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ());
-	}
-	printf ("\tBusCyclePenalty += 2;\n");
-
-	break;
-	case absw:
-	printf ("\tuint32_t %sa = (int32_t)(int16_t)%s;\n", name, gen_nextiword ());
-	break;
-	case absl:
-	printf ("\tuint32_t %sa = %s;\n", name, gen_nextilong ());
-	break;
-	case imm:
-	if (getv != 1)
-		abort ();
-	switch (size) {
-	case sz_byte:
-		printf ("\tint8_t %s = %s;\n", name, gen_nextibyte ());
-		break;
-	case sz_word:
-		printf ("\tint16_t %s = %s;\n", name, gen_nextiword ());
-		break;
-	case sz_long:
-		printf ("\tint32_t %s = %s;\n", name, gen_nextilong ());
-		break;
-	default:
-		abort ();
-	}
-	return;
-	case imm0:
-	if (getv != 1)
-		abort ();
-	printf ("\tint8_t %s = %s;\n", name, gen_nextibyte ());
-	return;
-	case imm1:
-	if (getv != 1)
-		abort ();
-	printf ("\tint16_t %s = %s;\n", name, gen_nextiword ());
-	return;
-	case imm2:
-	if (getv != 1)
-		abort ();
-	printf ("\tint32_t %s = %s;\n", name, gen_nextilong ());
-	return;
-	case immi:
-	if (getv != 1)
-		abort ();
-	printf ("\tuint32_t %s = %s;\n", name, reg);
-	return;
-	default:
-	abort ();
-	}
-
-	/* We get here for all non-reg non-immediate addressing modes to
-	* actually fetch the value. */
-
-	if (using_exception_3 && getv != 0 && size != sz_byte) {	    
-	printf ("\tif ((%sa & 1) != 0) {\n", name);
-	printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name);
-	printf ("\t\tlast_op_for_exception_3 = opcode;\n");
-	printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset);
-	printf ("\t\tException(3, 0, M68000_EXC_SRC_CPU);\n");
-	printf ("\t\tgoto %s;\n", endlabelstr);
-	printf ("\t}\n");
-	need_endlabel = 1;
-	start_brace ();
-	}
-
-	if (getv == 1) {
-	switch (size) {
-	case sz_byte: insn_n_cycles += 4; break;
-	case sz_word: insn_n_cycles += 4; break;
-	case sz_long: insn_n_cycles += 8; break;
-	default: abort ();
-	}
-	start_brace ();
-	switch (size) {
-	case sz_byte: printf ("\tint8_t %s = m68k_read_memory_8(%sa);\n", name, name); break;
-	case sz_word: printf ("\tint16_t %s = m68k_read_memory_16(%sa);\n", name, name); break;
-	case sz_long: printf ("\tint32_t %s = m68k_read_memory_32(%sa);\n", name, name); break;
-	default: abort ();
-	}
-	}
-
-	/* We now might have to fix up the register for pre-dec or post-inc
-	* addressing modes. */
-	if (!movem)
-	switch (mode) {
-	case Aipi:
-		switch (size) {
-		case sz_byte:
-		printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
-		break;
-		case sz_word:
-		printf ("\tm68k_areg(regs, %s) += 2;\n", reg);
-		break;
-		case sz_long:
-		printf ("\tm68k_areg(regs, %s) += 4;\n", reg);
-		break;
-		default:
-		abort ();
-		}
-		break;
-	case Apdi:
-		printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
-		break;
-	default:
-		break;
-	}
-}
-
-static void genastore (const char *from, amodes mode, const char *reg,
-                       wordsizes size, const char *to)
-{
-    switch (mode) {
-     case Dreg:
-	switch (size) {
-	 case sz_byte:
-	    printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
-	    break;
-	 case sz_word:
-	    printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
-	    break;
-	 case sz_long:
-	    printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
-	    break;
-	 default:
-	    abort ();
-	}
-	break;
-     case Areg:
-	switch (size) {
-	 case sz_word:
-	    fprintf (stderr, "Foo\n");
-	    printf ("\tm68k_areg(regs, %s) = (int32_t)(int16_t)(%s);\n", reg, from);
-	    break;
-	 case sz_long:
-	    printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
-	    break;
-	 default:
-	    abort ();
-	}
-	break;
-     case Aind:
-     case Aipi:
-     case Apdi:
-     case Ad16:
-     case Ad8r:
-     case absw:
-     case absl:
-     case PC16:
-     case PC8r:
-	if (using_prefetch)
-	    sync_m68k_pc ();
-	switch (size) {
-	 case sz_byte:
-	    insn_n_cycles += 4;
-	    printf ("\tm68k_write_memory_8(%sa,%s);\n", to, from);
-	    break;
-	 case sz_word:
-	    insn_n_cycles += 4;
-	    if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
-		abort ();
-	    printf ("\tm68k_write_memory_16(%sa,%s);\n", to, from);
-	    break;
-	 case sz_long:
-	    insn_n_cycles += 8;
-	    if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
-		abort ();
-	    printf ("\tm68k_write_memory_32(%sa,%s);\n", to, from);
-	    break;
-	 default:
-	    abort ();
-	}
-	break;
-     case imm:
-     case imm0:
-     case imm1:
-     case imm2:
-     case immi:
-	abort ();
-	break;
-     default:
-	abort ();
-    }
-}
-
-
-static void genmovemel (uint16_t opcode)
-{
-    char getcode[100];
-    int bMovemLong = (table68k[opcode].size == sz_long);
-    int size = bMovemLong ? 4 : 2;
-
-    if (bMovemLong) {
-	strcpy (getcode, "m68k_read_memory_32(srca)");
-    } else {
-	strcpy (getcode, "(int32_t)(int16_t)m68k_read_memory_16(srca)");
-    }
-
-    printf ("\tuint16_t mask = %s;\n", gen_nextiword ());
-    printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
-    printf ("\tretcycles = 0;\n");
-    genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
-    start_brace ();
-    printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;"
-            " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n",
-	    getcode, size, (bMovemLong ? 8 : 4));
-    printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;"
-            " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n",
-	    getcode, size, (bMovemLong ? 8 : 4));
-
-    if (table68k[opcode].dmode == Aipi)
-	printf ("\tm68k_areg(regs, dstreg) = srca;\n");
-
-    /* Better cycles - experimental! (Thothy) */
-    switch(table68k[opcode].dmode)
-    {
-      case Aind:  insn_n_cycles=12; break;
-      case Aipi:  insn_n_cycles=12; break;
-      case Ad16:  insn_n_cycles=16; break;
-      case Ad8r:  insn_n_cycles=18; break;
-      case absw:  insn_n_cycles=16; break;
-      case absl:  insn_n_cycles=20; break;
-      case PC16:  insn_n_cycles=16; break;
-      case PC8r:  insn_n_cycles=18; break;
-    }
-    sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
-}
-
-static void genmovemle (uint16_t opcode)
-{
-    char putcode[100];
-    int bMovemLong = (table68k[opcode].size == sz_long);
-    int size = bMovemLong ? 4 : 2;
-
-    if (bMovemLong) {
-	strcpy (putcode, "m68k_write_memory_32(srca,");
-    } else {
-	strcpy (putcode, "m68k_write_memory_16(srca,");
-    }
-
-    printf ("\tuint16_t mask = %s;\n", gen_nextiword ());
-    printf ("\tretcycles = 0;\n");
-    genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
-    if (using_prefetch)
-	sync_m68k_pc ();
-
-    start_brace ();
-    if (table68k[opcode].dmode == Apdi) {
-        printf ("\tuint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
-        printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));"
-                " amask = movem_next[amask]; retcycles+=%d; }\n",
-                size, putcode, (bMovemLong ? 8 : 4));
-        printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));"
-                " dmask = movem_next[dmask]; retcycles+=%d; }\n",
-                size, putcode, (bMovemLong ? 8 : 4));
-        printf ("\tm68k_areg(regs, dstreg) = srca;\n");
-    } else {
-        printf ("\tuint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
-        printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;"
-                " dmask = movem_next[dmask]; retcycles+=%d; }\n",
-                putcode, size, (bMovemLong ? 8 : 4));
-        printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;"
-                " amask = movem_next[amask]; retcycles+=%d; }\n",
-                putcode, size, (bMovemLong ? 8 : 4));
-    }
-
-    /* Better cycles - experimental! (Thothy) */
-    switch(table68k[opcode].dmode)
-    {
-      case Aind:  insn_n_cycles=8; break;
-      case Apdi:  insn_n_cycles=8; break;
-      case Ad16:  insn_n_cycles=12; break;
-      case Ad8r:  insn_n_cycles=14; break;
-      case absw:  insn_n_cycles=12; break;
-      case absl:  insn_n_cycles=16; break;
-    }
-    sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
-}
-
-
-static void duplicate_carry (void)
-{
-    printf ("\tCOPY_CARRY;\n");
-}
-
-typedef enum
-{
-  flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
-  flag_av, flag_sv
-}
-flagtypes;
-
-static void genflags_normal (flagtypes type, wordsizes size, const char *value,
-                             const char *src, const char *dst)
-{
-    char vstr[100], sstr[100], dstr[100];
-    char usstr[100], udstr[100];
-    char unsstr[100], undstr[100];
-
-    switch (size) {
-     case sz_byte:
-	strcpy (vstr, "((int8_t)(");
-	strcpy (usstr, "((uint8_t)(");
-	break;
-     case sz_word:
-	strcpy (vstr, "((int16_t)(");
-	strcpy (usstr, "((uint16_t)(");
-	break;
-     case sz_long:
-	strcpy (vstr, "((int32_t)(");
-	strcpy (usstr, "((uint32_t)(");
-	break;
-     default:
-	abort ();
-    }
-    strcpy (unsstr, usstr);
-
-    strcpy (sstr, vstr);
-    strcpy (dstr, vstr);
-    strcat (vstr, value);
-    strcat (vstr, "))");
-    strcat (dstr, dst);
-    strcat (dstr, "))");
-    strcat (sstr, src);
-    strcat (sstr, "))");
-
-    strcpy (udstr, usstr);
-    strcat (udstr, dst);
-    strcat (udstr, "))");
-    strcat (usstr, src);
-    strcat (usstr, "))");
-
-    strcpy (undstr, unsstr);
-    strcat (unsstr, "-");
-    strcat (undstr, "~");
-    strcat (undstr, dst);
-    strcat (undstr, "))");
-    strcat (unsstr, src);
-    strcat (unsstr, "))");
-
-    switch (type) {
-     case flag_logical_noclobber:
-     case flag_logical:
-     case flag_zn:
-     case flag_av:
-     case flag_sv:
-     case flag_addx:
-     case flag_subx:
-	break;
-
-     case flag_add:
-	start_brace ();
-	printf ("uint32_t %s = %s + %s;\n", value, dstr, sstr);
-	break;
-     case flag_sub:
-     case flag_cmp:
-	start_brace ();
-	printf ("uint32_t %s = %s - %s;\n", value, dstr, sstr);
-	break;
-    }
-
-    switch (type) {
-     case flag_logical_noclobber:
-     case flag_logical:
-     case flag_zn:
-	break;
-
-     case flag_add:
-     case flag_sub:
-     case flag_addx:
-     case flag_subx:
-     case flag_cmp:
-     case flag_av:
-     case flag_sv:
-	start_brace ();
-	printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
-	printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
-	printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
-	break;
-    }
-
-    switch (type) {
-     case flag_logical:
-	printf ("\tCLEAR_CZNV;\n");
-	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
-	printf ("\tSET_NFLG (%s < 0);\n", vstr);
-	break;
-     case flag_logical_noclobber:
-	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
-	printf ("\tSET_NFLG (%s < 0);\n", vstr);
-	break;
-     case flag_av:
-	printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
-	break;
-     case flag_sv:
-	printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
-	break;
-     case flag_zn:
-	printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
-	printf ("\tSET_NFLG (%s < 0);\n", vstr);
-	break;
-     case flag_add:
-	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
-	printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
-	printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
-	duplicate_carry ();
-	printf ("\tSET_NFLG (flgn != 0);\n");
-	break;
-     case flag_sub:
-	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
-	printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
-	printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
-	duplicate_carry ();
-	printf ("\tSET_NFLG (flgn != 0);\n");
-	break;
-     case flag_addx:
-	printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
-	printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
-	duplicate_carry ();
-	break;
-     case flag_subx:
-	printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
-	printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
-	duplicate_carry ();
-	break;
-     case flag_cmp:
-	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
-	printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
-	printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
-	printf ("\tSET_NFLG (flgn != 0);\n");
-	break;
-    }
-}
-
-static void genflags (flagtypes type, wordsizes size, const char *value,
-                      const char *src, const char *dst)
-{
-    /* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
-       them in the appropriate m68k.h files and use just one copy of this
-       code here.  The API can be changed if necessary.  */
-#ifdef OPTIMIZED_FLAGS
-    switch (type) {
-     case flag_add:
-     case flag_sub:
-	start_brace ();
-	printf ("\tuint32_t %s;\n", value);
-	break;
-
-     default:
-	break;
-    }
-
-    /* At least some of those casts are fairly important! */
-    switch (type) {
-     case flag_logical_noclobber:
-	printf ("\t{uint32_t oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
-	if (strcmp (value, "0") == 0) {
-	    printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
-	} else {
-	    switch (size) {
-	     case sz_byte: printf ("\toptflag_testb ((int8_t)(%s));\n", value); break;
-	     case sz_word: printf ("\toptflag_testw ((int16_t)(%s));\n", value); break;
-	     case sz_long: printf ("\toptflag_testl ((int32_t)(%s));\n", value); break;
-	    }
-	    printf ("\tIOR_CZNV (oldcznv);\n");
-	}
-	printf ("\t}\n");
-	return;
-     case flag_logical:
-	if (strcmp (value, "0") == 0) {
-	    printf ("\tSET_CZNV (FLAGVAL_Z);\n");
-	} else {
-	    switch (size) {
-	     case sz_byte: printf ("\toptflag_testb ((int8_t)(%s));\n", value); break;
-	     case sz_word: printf ("\toptflag_testw ((int16_t)(%s));\n", value); break;
-	     case sz_long: printf ("\toptflag_testl ((int32_t)(%s));\n", value); break;
-	    }
-	}
-	return;
-
-     case flag_add:
-	switch (size) {
-	 case sz_byte: printf ("\toptflag_addb (%s, (int8_t)(%s), (int8_t)(%s));\n", value, src, dst); break;
-	 case sz_word: printf ("\toptflag_addw (%s, (int16_t)(%s), (int16_t)(%s));\n", value, src, dst); break;
-	 case sz_long: printf ("\toptflag_addl (%s, (int32_t)(%s), (int32_t)(%s));\n", value, src, dst); break;
-	}
-	return;
-
-     case flag_sub:
-	switch (size) {
-	 case sz_byte: printf ("\toptflag_subb (%s, (int8_t)(%s), (int8_t)(%s));\n", value, src, dst); break;
-	 case sz_word: printf ("\toptflag_subw (%s, (int16_t)(%s), (int16_t)(%s));\n", value, src, dst); break;
-	 case sz_long: printf ("\toptflag_subl (%s, (int32_t)(%s), (int32_t)(%s));\n", value, src, dst); break;
-	}
-	return;
-
-     case flag_cmp:
-	switch (size) {
-	 case sz_byte: printf ("\toptflag_cmpb ((int8_t)(%s), (int8_t)(%s));\n", src, dst); break;
-	 case sz_word: printf ("\toptflag_cmpw ((int16_t)(%s), (int16_t)(%s));\n", src, dst); break;
-	 case sz_long: printf ("\toptflag_cmpl ((int32_t)(%s), (int32_t)(%s));\n", src, dst); break;
-	}
-	return;
-	
-     default:
-	break;
-    }
-#endif
-
-    genflags_normal (type, size, value, src, dst);
-}
-
-static void force_range_for_rox (const char *var, wordsizes size)
-{
-    /* Could do a modulo operation here... which one is faster? */
-    switch (size) {
-     case sz_long:
-	printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
-	break;
-     case sz_word:
-	printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
-	printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
-	break;
-     case sz_byte:
-	printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
-	printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
-	printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
-	break;
-    }
-}
-
-static const char *cmask (wordsizes size)
-{
-    switch (size) {
-     case sz_byte: return "0x80";
-     case sz_word: return "0x8000";
-     case sz_long: return "0x80000000";
-     default: abort ();
-    }
-}
-
-static int source_is_imm1_8 (struct instr *i)
-{
-    return i->stype == 3;
-}
-
-
-
-static void gen_opcode (unsigned long int opcode)
-{
-#if 0
-    char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r",
-         "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"};
-#endif
-
-    struct instr *curi = table68k + opcode;
-    insn_n_cycles = 4;
-
-    /* Store the family of the instruction (used to check for pairing on ST)
-     * and leave some space for patching in the current cycles later */
-    printf ("\tOpcodeFamily = %d; CurrentInstrCycles =     \n", curi->mnemo);
-    nCurInstrCycPos = ftell(stdout) - 5;
-
-    start_brace ();
-    m68k_pc_offset = 2;
-
-    switch (curi->plev) {
-    case 0: /* not privileged */
-	break;
-    case 1: /* unprivileged only on 68000 */
-	if (cpu_level == 0)
-	    break;
-	if (next_cpu_level < 0)
-	    next_cpu_level = 0;
-
-	/* fall through */
-    case 2: /* priviledged */
-	printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	need_endlabel = 1;
-	start_brace ();
-	break;
-    case 3: /* privileged if size == word */
-	if (curi->size == sz_byte)
-	    break;
-	printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	need_endlabel = 1;
-	start_brace ();
-	break;
-    }
-
-    /* Build the opcodes: */
-    switch (curi->mnemo) {
-    case i_OR:
-    case i_AND:
-    case i_EOR:
-        genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-        genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-        printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
-        genflags (flag_logical, curi->size, "src", "", "");
-        genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->size==sz_long && curi->dmode==Dreg)
-         {
-          insn_n_cycles += 2;
-          if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
-            insn_n_cycles += 2;
-         }
-#if 0
-        /* Output the CPU cycles: */
-        fprintf(stderr,"MOVE, size %i: ",curi->size);
-        fprintf(stderr," %s ->",amodenames[curi->smode]);
-        fprintf(stderr," %s ",amodenames[curi->dmode]);
-        fprintf(stderr," Cycles: %i\n",insn_n_cycles);
-#endif
-        break;
-    case i_ORSR:
-    case i_EORSR:
-        printf ("\tMakeSR();\n");
-        genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-        if (curi->size == sz_byte) {
-            printf ("\tsrc &= 0xFF;\n");
-        }
-        printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
-        printf ("\tMakeFromSR();\n");
-        insn_n_cycles = 20;
-        break;
-    case i_ANDSR:
-        printf ("\tMakeSR();\n");
-        genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-        if (curi->size == sz_byte) {
-            printf ("\tsrc |= 0xFF00;\n");
-        }
-        printf ("\tregs.sr &= src;\n");
-        printf ("\tMakeFromSR();\n");
-        insn_n_cycles = 20;
-        break;
-    case i_SUB:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	genflags (flag_sub, curi->size, "newv", "src", "dst");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->size==sz_long && curi->dmode==Dreg)
-         {
-          insn_n_cycles += 2;
-          if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
-            insn_n_cycles += 2;
-         }
-	break;
-    case i_SUBA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = dst - src;\n");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-        if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
-          insn_n_cycles += 2;
-         else
-          insn_n_cycles += 4;
-	break;
-    case i_SUBX:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = dst - src - (GET_XFLG ? 1 : 0);\n");
-	genflags (flag_subx, curi->size, "newv", "src", "dst");
-	genflags (flag_zn, curi->size, "newv", "", "");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->smode==Dreg && curi->size==sz_long)
-          insn_n_cycles=8;
-        if(curi->smode==Apdi)
-         {
-          if(curi->size==sz_long)
-            insn_n_cycles=30;
-           else
-            insn_n_cycles=18;
-         }
-	break;
-    case i_SBCD:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
-	printf ("\tuint16_t newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
-	printf ("\tuint16_t newv, tmp_newv;\n");
-	printf ("\tint bcd = 0;\n");
-	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
-	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
-	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
-	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
-	duplicate_carry ();
-	genflags (flag_zn, curi->size, "newv", "", "");
-	printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-	if(curi->smode==Dreg)  insn_n_cycles=6;
-	if(curi->smode==Apdi)  insn_n_cycles=18;
-	break;
-    case i_ADD:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf("\trefill_prefetch (m68k_getpc(), 2);\n");	// FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation
-	genflags (flag_add, curi->size, "newv", "src", "dst");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->size==sz_long && curi->dmode==Dreg)
-         {
-          insn_n_cycles += 2;
-          if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi))
-            insn_n_cycles += 2;
-         }
-	break;
-    case i_ADDA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = dst + src;\n");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-        if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi))
-          insn_n_cycles += 2;
-         else
-          insn_n_cycles += 4;
-	break;
-    case i_ADDX:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = dst + src + (GET_XFLG ? 1 : 0);\n");
-	genflags (flag_addx, curi->size, "newv", "src", "dst");
-	genflags (flag_zn, curi->size, "newv", "", "");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->smode==Dreg && curi->size==sz_long)
-          insn_n_cycles=8;
-        if(curi->smode==Apdi)
-         {
-          if(curi->size==sz_long)
-            insn_n_cycles=30;
-           else
-            insn_n_cycles=18;
-         }
-	break;
-    case i_ABCD:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
-	printf ("\tuint16_t newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
-	printf ("\tuint16_t newv, tmp_newv;\n");
-	printf ("\tint cflg;\n");
-	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
-	printf ("\tif (newv_lo > 9) { newv += 6; }\n");
-	printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
-	printf ("\tif (cflg) newv += 0x60;\n");
-	printf ("\tSET_CFLG (cflg);\n");
-	duplicate_carry ();
-	genflags (flag_zn, curi->size, "newv", "", "");
-	printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
-	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
-	if(curi->smode==Dreg)  insn_n_cycles=6;
-	if(curi->smode==Apdi)  insn_n_cycles=18;
-	break;
-    case i_NEG:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	genflags (flag_sub, curi->size, "dst", "src", "0");
-	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
-        if(curi->size==sz_long && curi->smode==Dreg)  insn_n_cycles += 2;
-	break;
-    case i_NEGX:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
-	genflags (flag_subx, curi->size, "newv", "src", "0");
-	genflags (flag_zn, curi->size, "newv", "", "");
-	genastore ("newv", curi->smode, "srcreg", curi->size, "src");
-        if(curi->size==sz_long && curi->smode==Dreg)  insn_n_cycles += 2;
-	break;
-    case i_NBCD:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	printf ("\tuint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
-	printf ("\tuint16_t newv_hi = - (src & 0xF0);\n");
-	printf ("\tuint16_t newv;\n");
-	printf ("\tint cflg;\n");
-	printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
-	printf ("\tnewv = newv_hi + newv_lo;");
-	printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
-	printf ("\tif (cflg) newv -= 0x60;\n");
-	printf ("\tSET_CFLG (cflg);\n");
-	duplicate_carry();
-	genflags (flag_zn, curi->size, "newv", "", "");
-	genastore ("newv", curi->smode, "srcreg", curi->size, "src");
-	if(curi->smode==Dreg)  insn_n_cycles += 2;
-	break;
-    case i_CLR:
-	genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
-
-	/* [NP] CLR does a read before the write only on 68000 */
-	/* but there's no cycle penalty for doing the read */
-	if ( curi->smode != Dreg )			// only if destination is memory
-	  {
-	    if (curi->size==sz_byte)
-	      printf ("\tint8_t src = m68k_read_memory_8(srca);\n");
-	    else if (curi->size==sz_word)
-	      printf ("\tint16_t src = m68k_read_memory_16(srca);\n");
-	    else if (curi->size==sz_long)
-	      printf ("\tint32_t src = m68k_read_memory_32(srca);\n");
-	  }
-
-	genflags (flag_logical, curi->size, "0", "", "");
-	genastore ("0", curi->smode, "srcreg", curi->size, "src");
-        if(curi->size==sz_long)
-        {
-          if(curi->smode==Dreg)
-            insn_n_cycles += 2;
-           else
-            insn_n_cycles += 4;
-        }
-        if(curi->smode!=Dreg)
-          insn_n_cycles += 4;
-	break;
-    case i_NOT:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t dst = ~src;\n");
-	genflags (flag_logical, curi->size, "dst", "", "");
-	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
-        if(curi->size==sz_long && curi->smode==Dreg)  insn_n_cycles += 2;
-	break;
-    case i_TST:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genflags (flag_logical, curi->size, "src", "", "");
-	break;
-    case i_BTST:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	if (curi->size == sz_byte)
-	    printf ("\tsrc &= 7;\n");
-	else
-	    printf ("\tsrc &= 31;\n");
-	printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
-        if(curi->dmode==Dreg)  insn_n_cycles += 2;
-	break;
-    case i_BCHG:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	if (curi->size == sz_byte)
-	    printf ("\tsrc &= 7;\n");
-	else
-	    printf ("\tsrc &= 31;\n");
-	printf ("\tdst ^= (1 << src);\n");
-	printf ("\tSET_ZFLG (((uint32_t)dst & (1 << src)) >> src);\n");
-	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->dmode==Dreg)  insn_n_cycles += 4;
-	break;
-    case i_BCLR:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	if (curi->size == sz_byte)
-	    printf ("\tsrc &= 7;\n");
-	else
-	    printf ("\tsrc &= 31;\n");
-	printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
-	printf ("\tdst &= ~(1 << src);\n");
-	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->dmode==Dreg)  insn_n_cycles += 6;
-	/* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */
-        if((curi->smode==imm1) && (curi->dmode==Dreg))
-	    printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n");
-	/* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */
-        if((curi->smode==Dreg) && (curi->dmode==Dreg))
-	    printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n");
-	break;
-    case i_BSET:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	if (curi->size == sz_byte)
-	    printf ("\tsrc &= 7;\n");
-	else
-	    printf ("\tsrc &= 31;\n");
-	printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
-	printf ("\tdst |= (1 << src);\n");
-	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->dmode==Dreg)  insn_n_cycles += 4;
-	break;
-    case i_CMPM:
-    case i_CMP:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	genflags (flag_cmp, curi->size, "newv", "src", "dst");
-        if(curi->size==sz_long && curi->dmode==Dreg)
-          insn_n_cycles += 2;
-	break;
-    case i_CMPA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
-	start_brace ();
-	genflags (flag_cmp, sz_long, "newv", "src", "dst");
-        insn_n_cycles += 2;
-	break;
-	/* The next two are coded a little unconventional, but they are doing
-	 * weird things... */
-    case i_MVPRM:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-
-	printf ("\tuint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)%s;\n", gen_nextiword ());
-	if (curi->size == sz_word) {
-	    printf ("\tm68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src);\n");
-	} else {
-	    printf ("\tm68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16);\n");
-	    printf ("\tm68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src);\n");
-	}
-        if(curi->size==sz_long)  insn_n_cycles=24;  else  insn_n_cycles=16;
-	break;
-    case i_MVPMR:
-	printf ("\tuint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)%s;\n", gen_nextiword ());
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-	if (curi->size == sz_word) {
-	    printf ("\tuint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2);\n");
-	} else {
-	    printf ("\tuint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16)\n");
-	    printf ("              + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6);\n");
-	}
-	genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
-        if(curi->size==sz_long)  insn_n_cycles=24;  else  insn_n_cycles=16;
-	break;
-    case i_MOVE:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-
-	/* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */
-	/* For move dest (An), (An)+ and -(An) take the same time */
-	/* (for other instr, dest -(An) really takes 2 cycles more) */
-	if ( curi->dmode == Apdi )
-	  insn_n_cycles -= 2;			/* correct the wrong cycle count for -(An) */
-
-	genflags (flag_logical, curi->size, "src", "", "");
-	genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
-	break;
-    case i_MOVEA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-	if (curi->size == sz_word) {
-	    printf ("\tuint32_t val = (int32_t)(int16_t)src;\n");
-	} else {
-	    printf ("\tuint32_t val = src;\n");
-	}
-	genastore ("val", curi->dmode, "dstreg", sz_long, "dst");
-	break;
-    case i_MVSR2:  /* Move from SR */
-	genamode (curi->smode, "srcreg", sz_word, "src", 2, 0);
-	printf ("\tMakeSR();\n");
-	if (curi->size == sz_byte)
-	    genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
-	else
-	    genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
-        if (curi->smode==Dreg)  insn_n_cycles += 2;  else  insn_n_cycles += 4;
-	break;
-    case i_MV2SR:  /* Move to SR */
-	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
-	if (curi->size == sz_byte)
-	    printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
-	else {
-	    printf ("\tregs.sr = src;\n");
-	}
-	printf ("\tMakeFromSR();\n");
-        insn_n_cycles += 8;
-	break;
-    case i_SWAP:
-	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
-	genflags (flag_logical, sz_long, "dst", "", "");
-	genastore ("dst", curi->smode, "srcreg", sz_long, "src");
-	break;
-    case i_EXG:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
-	genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
-        insn_n_cycles = 6;
-	break;
-    case i_EXT:
-	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t dst = (int32_t)(int8_t)src;\n"); break;
-	case sz_word: printf ("\tuint16_t dst = (int16_t)(int8_t)src;\n"); break;
-	case sz_long: printf ("\tuint32_t dst = (int32_t)(int16_t)src;\n"); break;
-	default: abort ();
-	}
-	genflags (flag_logical,
-		  curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
-	genastore ("dst", curi->smode, "srcreg",
-		   curi->size == sz_word ? sz_word : sz_long, "src");
-	break;
-    case i_MVMEL:
-	genmovemel (opcode);
-	break;
-    case i_MVMLE:
-	genmovemle (opcode);
-	break;
-    case i_TRAP:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tException(src+32,0,M68000_EXC_SRC_CPU);\n");
-	m68k_pc_offset = 0;
-	break;
-    case i_MVR2USP:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	printf ("\tregs.usp = src;\n");
-	break;
-    case i_MVUSP2R:
-	genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
-	genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
-	break;
-    case i_RESET:
-//JLH:Not needed	printf ("\tcustomreset();\n");
-        insn_n_cycles = 132;    /* I am not so sure about this!? - Thothy */
-	break;
-    case i_NOP:
-	break;
-    case i_STOP:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	printf ("\tregs.sr = src;\n");
-	printf ("\tMakeFromSR();\n");
-	printf ("\tm68k_setstopped(1);\n");
-        insn_n_cycles = 4;
-	break;
-    case i_RTE:
-	if (cpu_level == 0) {
-	    genamode (Aipi, "7", sz_word, "sr", 1, 0);
-	    genamode (Aipi, "7", sz_long, "pc", 1, 0);
-	    printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n");
-	    fill_prefetch_0 ();
-	    printf ("\tMakeFromSR();\n");
-	} else {
-	    int old_brace_level = n_braces;
-	    if (next_cpu_level < 0)
-		next_cpu_level = 0;
-	    printf ("\tuint16_t newsr; uint32_t newpc; for (;;) {\n");
-	    genamode (Aipi, "7", sz_word, "sr", 1, 0);
-	    genamode (Aipi, "7", sz_long, "pc", 1, 0);
-	    genamode (Aipi, "7", sz_word, "format", 1, 0);
-	    printf ("\tnewsr = sr; newpc = pc;\n");
-	    printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n");
-	    printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n");
-	    printf ("\telse { Exception(14,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	    printf ("\tregs.sr = newsr; MakeFromSR();\n}\n");
-	    pop_braces (old_brace_level);
-	    printf ("\tregs.sr = newsr; MakeFromSR();\n");
-	    printf ("\tm68k_setpc_rte(newpc);\n");
-	    fill_prefetch_0 ();
-	    need_endlabel = 1;
-	}
-	/* PC is set and prefetch filled. */
-	m68k_pc_offset = 0;
-        insn_n_cycles = 20;
-	break;
-    case i_RTD:
-	genamode (Aipi, "7", sz_long, "pc", 1, 0);
-	genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
-	printf ("\tm68k_areg(regs, 7) += offs;\n");
-	printf ("\tm68k_setpc_rte(pc);\n");
-	fill_prefetch_0 ();
-	/* PC is set and prefetch filled. */
-	m68k_pc_offset = 0;
-	break;
-    case i_LINK:
-	genamode (Apdi, "7", sz_long, "old", 2, 0);
-	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
-	genastore ("src", Apdi, "7", sz_long, "old");
-	genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
-	genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
-	printf ("\tm68k_areg(regs, 7) += offs;\n");
-	break;
-    case i_UNLK:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	printf ("\tm68k_areg(regs, 7) = src;\n");
-	genamode (Aipi, "7", sz_long, "old", 1, 0);
-	genastore ("old", curi->smode, "srcreg", curi->size, "src");
-	break;
-    case i_RTS:
-	printf ("\tm68k_do_rts();\n");
-	fill_prefetch_0 ();
-	m68k_pc_offset = 0;
-        insn_n_cycles = 16;
-	break;
-    case i_TRAPV:
-	sync_m68k_pc ();
-	printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	need_endlabel = 1;
-	break;
-    case i_RTR:
-	printf ("\tMakeSR();\n");
-	genamode (Aipi, "7", sz_word, "sr", 1, 0);
-	genamode (Aipi, "7", sz_long, "pc", 1, 0);
-	printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
-	printf ("\tregs.sr |= sr; m68k_setpc(pc);\n");
-	fill_prefetch_0 ();
-	printf ("\tMakeFromSR();\n");
-	m68k_pc_offset = 0;
-        insn_n_cycles = 20;
-	break;
-    case i_JSR:
-	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
-	printf ("\tuint32_t oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
-	if (using_exception_3) {
-	    printf ("\tif (srca & 1) {\n");
-	    printf ("\t\tlast_addr_for_exception_3 = oldpc;\n");
-	    printf ("\t\tlast_fault_for_exception_3 = srca;\n");
-	    printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-	    printf ("\t}\n");
-	    need_endlabel = 1;
-	}
-	printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset);
-	fill_prefetch_0 ();
-	m68k_pc_offset = 0;
-        switch(curi->smode)
-         {
-          case Aind:  insn_n_cycles=16; break;
-          case Ad16:  insn_n_cycles=18; break;
-          case Ad8r:  insn_n_cycles=22; break;
-          case absw:  insn_n_cycles=18; break;
-          case absl:  insn_n_cycles=20; break;
-          case PC16:  insn_n_cycles=18; break;
-          case PC8r:  insn_n_cycles=22; break;
-         }
-	break;
-    case i_JMP:
-	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
-	if (using_exception_3) {
-	    printf ("\tif (srca & 1) {\n");
-	    printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 6;\n");
-	    printf ("\t\tlast_fault_for_exception_3 = srca;\n");
-	    printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-	    printf ("\t}\n");
-	    need_endlabel = 1;
-	}
-	printf ("\tm68k_setpc(srca);\n");
-	fill_prefetch_0 ();
-	m68k_pc_offset = 0;
-        switch(curi->smode)
-         {
-          case Aind:  insn_n_cycles=8; break;
-          case Ad16:  insn_n_cycles=10; break;
-          case Ad8r:  insn_n_cycles=14; break;
-          case absw:  insn_n_cycles=10; break;
-          case absl:  insn_n_cycles=12; break;
-          case PC16:  insn_n_cycles=10; break;
-          case PC8r:  insn_n_cycles=14; break;
-         }
-	break;
-    case i_BSR:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	printf ("\tint32_t s = (int32_t)src + 2;\n");
-	if (using_exception_3) {
-	    printf ("\tif (src & 1) {\n");
-	    printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");	// [NP] FIXME should be +4, not +2 (same as DBcc) ?
-	    printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n");
-	    printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-	    printf ("\t}\n");
-	    need_endlabel = 1;
-	}
-	printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset);
-	fill_prefetch_0 ();
-	m68k_pc_offset = 0;
-        insn_n_cycles = 18;
-	break;
-    case i_Bcc:
-	if (curi->size == sz_long) {
-	    if (cpu_level < 2) {
-		printf ("\tm68k_incpc(2);\n");
-		printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr);
-		printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");
-		printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n");
-		printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-		need_endlabel = 1;
-	    } else {
-		if (next_cpu_level < 1)
-		    next_cpu_level = 1;
-	    }
-	}
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc);
-	if (using_exception_3) {
-	    printf ("\tif (src & 1) {\n");
-	    printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n");	// [NP] FIXME should be +4, not +2 (same as DBcc) ?
-	    printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src;\n");
-	    printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-	    printf ("\t}\n");
-	    need_endlabel = 1;
-	}
-	printf ("\tm68k_incpc ((int32_t)src + 2);\n");
-	fill_prefetch_0 ();
-	printf ("\treturn 10;\n");
-	printf ("didnt_jump:;\n");
-	need_endlabel = 1;
-	insn_n_cycles = (curi->size == sz_byte) ? 8 : 12;
-	break;
-    case i_LEA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-	genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
-        /* Set correct cycles: According to the M68K User Manual, LEA takes 12
-         * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */
-        if (curi->smode == Ad8r || curi->smode == PC8r)
-          insn_n_cycles = 14;
-	break;
-    case i_PEA:
-	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
-	genamode (Apdi, "7", sz_long, "dst", 2, 0);
-	genastore ("srca", Apdi, "7", sz_long, "dst");
-	/* Set correct cycles: */
-        switch(curi->smode)
-         {
-          case Aind:  insn_n_cycles=12; break;
-          case Ad16:  insn_n_cycles=16; break;
-          /* Note: according to the M68K User Manual, PEA takes 20 cycles for
-           * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */
-          case Ad8r:  insn_n_cycles=22; break;
-          case absw:  insn_n_cycles=16; break;
-          case absl:  insn_n_cycles=20; break;
-          case PC16:  insn_n_cycles=16; break;
-          /* Note: PEA with PC8r takes 20 cycles according to the User Manual,
-           * but it takes 22 (or 24) cycles on a real ST: */
-          case PC8r:  insn_n_cycles=22; break;
-         }
-	break;
-    case i_DBcc:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
-
-	printf ("\tif (!cctrue(%d)) {\n\t", curi->cc);
-	genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src");
-
-	printf ("\t\tif (src) {\n");
-	if (using_exception_3) {
-	    printf ("\t\t\tif (offs & 1) {\n");
-	    printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n");	// [NP] last_addr is pc+4, not pc+2
-	    printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2;\n");
-	    printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr);
-	    printf ("\t\t}\n");
-	    need_endlabel = 1;
-	}
-	printf ("\t\t\tm68k_incpc((int32_t)offs + 2);\n");
-	fill_prefetch_0 ();
-	printf ("\t\t\treturn 10;\n");
-	printf ("\t\t} else {\n\t\t\t");
-        {
-         int tmp_offset = m68k_pc_offset;
-         sync_m68k_pc();              /* not so nice to call it here... */
-         m68k_pc_offset = tmp_offset;
-        }
-        printf ("\t\t\treturn 14;\n");
-        printf ("\t\t}\n");
-	printf ("\t}\n");
-	insn_n_cycles = 12;
-	need_endlabel = 1;
-	break;
-    case i_Scc:
-	genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
-	start_brace ();
-	printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc);
-	genastore ("val", curi->smode, "srcreg", curi->size, "src");
-        if (curi->smode!=Dreg)  insn_n_cycles += 4;
-	else
-	  {					/* [NP] if result is TRUE, we return 6 instead of 4 */
-	    printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n");
-	  }
-	break;
-    case i_DIVU:
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
-	sync_m68k_pc ();
-	/* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
-	 * on this (actually, it's doing a DIVS).  */
-	printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
-	printf ("\tuint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;\n");
-	printf ("\tuint32_t rem = (uint32_t)dst %% (uint32_t)(uint16_t)src;\n");
-	/* The N flag appears to be set each time there is an overflow.
-	 * Weird. */
-	printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
-	genflags (flag_logical, sz_word, "newv", "", "");
-	printf ("\tnewv = (newv & 0xffff) | ((uint32_t)rem << 16);\n");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-	printf ("\t}\n");
-	printf ("\t}\n");
-//	insn_n_cycles += 136;
-	printf ("\tretcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);\n");
-        sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
-	need_endlabel = 1;
-	break;
-    case i_DIVS:
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr);
-	printf ("\tint32_t newv = (int32_t)dst / (int32_t)(int16_t)src;\n");
-	printf ("\tuint16_t rem = (int32_t)dst %% (int32_t)(int16_t)src;\n");
-	printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
-	printf ("\tif (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;\n");
-	genflags (flag_logical, sz_word, "newv", "", "");
-	printf ("\tnewv = (newv & 0xffff) | ((uint32_t)rem << 16);\n");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-	printf ("\t}\n");
-	printf ("\t}\n");
-//	insn_n_cycles += 154;
-	printf ("\tretcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);\n");
-        sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles);
-	need_endlabel = 1;
-	break;
-    case i_MULU:
-	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;\n");
-	genflags (flag_logical, sz_long, "newv", "", "");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-	/* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */
-	insn_n_cycles += 38-4;			/* insn_n_cycles is already initialized to 4 instead of 0 */
-	printf ("\twhile (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }\n");
-        sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
-	break;
-    case i_MULS:
-	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
-	start_brace ();
-	printf ("\tuint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;\n");
-	printf ("\tuint32_t src2;\n");
-	genflags (flag_logical, sz_long, "newv", "", "");
-	genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
-	/* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */
-	insn_n_cycles += 38-4;			/* insn_n_cycles is already initialized to 4 instead of 0 */
-	printf ("\tsrc2 = ((uint32_t)src) << 1;\n");
-	printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n");
-        sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles);
-	break;
-    case i_CHK:
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tif ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
-	need_endlabel = 1;
-        insn_n_cycles += 6;
-	break;
-
-    case i_CHK2:
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-	printf ("\t{int32_t upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
-	switch (curi->size) {
-	case sz_byte:
-	    printf ("\tlower=(int32_t)(int8_t)m68k_read_memory_8(dsta); upper = (int32_t)(int8_t)m68k_read_memory_8(dsta+1);\n");
-	    printf ("\tif ((extra & 0x8000) == 0) reg = (int32_t)(int8_t)reg;\n");
-	    break;
-	case sz_word:
-	    printf ("\tlower=(int32_t)(int16_t)m68k_read_memory_16(dsta); upper = (int32_t)(int16_t)m68k_read_memory_16(dsta+2);\n");
-	    printf ("\tif ((extra & 0x8000) == 0) reg = (int32_t)(int16_t)reg;\n");
-	    break;
-	case sz_long:
-	    printf ("\tlower=m68k_read_memory_32(dsta); upper = m68k_read_memory_32(dsta+4);\n");
-	    break;
-	default:
-	    abort ();
-	}
-	printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
-	printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
-	sync_m68k_pc ();
-	printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n}\n", endlabelstr);
-	need_endlabel = 1;
-	break;
-
-    case i_ASR:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
-	printf ("\t\tval = %s & (uint32_t)-sign;\n", bit_mask (curi->size));
-	printf ("\t\tSET_CFLG (sign);\n");
-	duplicate_carry ();
-	if (source_is_imm1_8 (curi))
-	    printf ("\t} else {\n");
-	else
-	    printf ("\t} else if (cnt > 0) {\n");
-	printf ("\t\tval >>= cnt - 1;\n");
-	printf ("\t\tSET_CFLG (val & 1);\n");
-	duplicate_carry ();
-	printf ("\t\tval >>= 1;\n");
-	printf ("\t\tval |= (%s << (%d - cnt)) & (uint32_t)-sign;\n",
-		bit_mask (curi->size),
-		bit_size (curi->size));
-	printf ("\t\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\t}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ASL:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
-	printf ("\t\tSET_VFLG (val != 0);\n");
-	printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
-		bit_size (curi->size));
-	duplicate_carry ();
-	printf ("\t\tval = 0;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("\t} else {\n");
-	else
-	    printf ("\t} else if (cnt > 0) {\n");
-	printf ("\t\tuint32_t mask = (%s << (%d - cnt)) & %s;\n",
-		bit_mask (curi->size),
-		bit_size (curi->size) - 1,
-		bit_mask (curi->size));
-	printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
-	printf ("\t\tval <<= cnt - 1;\n");
-	printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
-	duplicate_carry ();
-	printf ("\t\tval <<= 1;\n");
-	printf ("\t\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\t}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_LSR:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
-	printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
-		bit_size (curi->size), bit_size (curi->size) - 1);
-	duplicate_carry ();
-	printf ("\t\tval = 0;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("\t} else {\n");
-	else
-	    printf ("\t} else if (cnt > 0) {\n");
-	printf ("\t\tval >>= cnt - 1;\n");
-	printf ("\t\tSET_CFLG (val & 1);\n");
-	duplicate_carry ();
-	printf ("\t\tval >>= 1;\n");
-	printf ("\t}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_LSL:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
-	printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
-		bit_size (curi->size));
-	duplicate_carry ();
-	printf ("\t\tval = 0;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("\t} else {\n");
-	else
-	    printf ("\t} else if (cnt > 0) {\n");
-	printf ("\t\tval <<= (cnt - 1);\n");
-	printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
-	duplicate_carry ();
-	printf ("\t\tval <<= 1;\n");
-	printf ("\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\t}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ROL:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("{");
-	else
-	    printf ("\tif (cnt > 0) {\n");
-	printf ("\tuint32_t loval;\n");
-	printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
-	printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
-	printf ("\tval <<= cnt;\n");
-	printf ("\tval |= loval;\n");
-	printf ("\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\tSET_CFLG (val & 1);\n");
-	printf ("}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ROR:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("{");
-	else
-	    printf ("\tif (cnt > 0) {");
-	printf ("\tuint32_t hival;\n");
-	printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
-	printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
-	printf ("\tval >>= cnt;\n");
-	printf ("\tval |= hival;\n");
-	printf ("\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
-	printf ("\t}\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ROXL:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("{");
-	else {
-	    force_range_for_rox ("cnt", curi->size);
-	    printf ("\tif (cnt > 0) {\n");
-	}
-	printf ("\tcnt--;\n");
-	printf ("\t{\n\tuint32_t carry;\n");
-	printf ("\tuint32_t loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
-	printf ("\tcarry = loval & 1;\n");
-	printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
-	printf ("\tSET_XFLG (carry);\n");
-	printf ("\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\t} }\n");
-	printf ("\tSET_CFLG (GET_XFLG);\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ROXR:
-	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tcnt &= 63;\n");
-        printf ("\tretcycles = cnt;\n");
-	printf ("\tCLEAR_CZNV;\n");
-	if (source_is_imm1_8 (curi))
-	    printf ("{");
-	else {
-	    force_range_for_rox ("cnt", curi->size);
-	    printf ("\tif (cnt > 0) {\n");
-	}
-	printf ("\tcnt--;\n");
-	printf ("\t{\n\tuint32_t carry;\n");
-	printf ("\tuint32_t hival = (val << 1) | GET_XFLG;\n");
-	printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
-	printf ("\tval >>= cnt;\n");
-	printf ("\tcarry = val & 1;\n");
-	printf ("\tval >>= 1;\n");
-	printf ("\tval |= hival;\n");
-	printf ("\tSET_XFLG (carry);\n");
-	printf ("\tval &= %s;\n", bit_mask (curi->size));
-	printf ("\t} }\n");
-	printf ("\tSET_CFLG (GET_XFLG);\n");
-	genflags (flag_logical_noclobber, curi->size, "val", "", "");
-	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
-        if(curi->size==sz_long)
-            strcpy(exactCpuCycles," return (8+retcycles*2);");
-          else
-            strcpy(exactCpuCycles," return (6+retcycles*2);");
-	break;
-    case i_ASRW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t sign = %s & val;\n", cmask (curi->size));
-	printf ("\tuint32_t cflg = val & 1;\n");
-	printf ("\tval = (val >> 1) | sign;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("\tSET_CFLG (cflg);\n");
-	duplicate_carry ();
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_ASLW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t sign = %s & val;\n", cmask (curi->size));
-	printf ("\tuint32_t sign2;\n");
-	printf ("\tval <<= 1;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("\tsign2 = %s & val;\n", cmask (curi->size));
-	printf ("\tSET_CFLG (sign != 0);\n");
-	duplicate_carry ();
-
-	printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_LSRW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break;
-	case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & 1;\n");
-	printf ("\tval >>= 1;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry);\n");
-	duplicate_carry ();
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_LSLW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint8_t val = data;\n"); break;
-	case sz_word: printf ("\tuint16_t val = data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size));
-	printf ("\tval <<= 1;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
-	duplicate_carry ();
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_ROLW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint8_t val = data;\n"); break;
-	case sz_word: printf ("\tuint16_t val = data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size));
-	printf ("\tval <<= 1;\n");
-	printf ("\tif (carry)  val |= 1;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_RORW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint8_t val = data;\n"); break;
-	case sz_word: printf ("\tuint16_t val = data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & 1;\n");
-	printf ("\tval >>= 1;\n");
-	printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry);\n");
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_ROXLW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint8_t val = data;\n"); break;
-	case sz_word: printf ("\tuint16_t val = data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size));
-	printf ("\tval <<= 1;\n");
-	printf ("\tif (GET_XFLG) val |= 1;\n");
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
-	duplicate_carry ();
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_ROXRW:
-	genamode (curi->smode, "srcreg", curi->size, "data", 1, 0);
-	start_brace ();
-	switch (curi->size) {
-	case sz_byte: printf ("\tuint8_t val = data;\n"); break;
-	case sz_word: printf ("\tuint16_t val = data;\n"); break;
-	case sz_long: printf ("\tuint32_t val = data;\n"); break;
-	default: abort ();
-	}
-	printf ("\tuint32_t carry = val & 1;\n");
-	printf ("\tval >>= 1;\n");
-	printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
-	genflags (flag_logical, curi->size, "val", "", "");
-	printf ("SET_CFLG (carry);\n");
-	duplicate_carry ();
-	genastore ("val", curi->smode, "srcreg", curi->size, "data");
-	break;
-    case i_MOVEC2:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	printf ("\tint regno = (src >> 12) & 15;\n");
-	printf ("\tuint32_t *regp = regs.regs + regno;\n");
-	printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
-	break;
-    case i_MOVE2C:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	start_brace ();
-	printf ("\tint regno = (src >> 12) & 15;\n");
-	printf ("\tuint32_t *regp = regs.regs + regno;\n");
-	printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
-	break;
-    case i_CAS:
-    {
-	int old_brace_level;
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	start_brace ();
-	printf ("\tint ru = (src >> 6) & 7;\n");
-	printf ("\tint rc = src & 7;\n");
-	genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
-	printf ("\tif (GET_ZFLG)");
-	old_brace_level = n_braces;
-	start_brace ();
-	genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
-	pop_braces (old_brace_level);
-	printf ("else");
-	start_brace ();
-	printf ("m68k_dreg(regs, rc) = dst;\n");
-	pop_braces (old_brace_level);
-    }
-    break;
-    case i_CAS2:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	printf ("\tuint32_t rn1 = regs.regs[(extra >> 28) & 15];\n");
-	printf ("\tuint32_t rn2 = regs.regs[(extra >> 12) & 15];\n");
-	if (curi->size == sz_word) {
-	    int old_brace_level = n_braces;
-	    printf ("\tuint16_t dst1 = m68k_read_memory_16(rn1), dst2 = m68k_read_memory_16(rn2);\n");
-	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
-	    printf ("\tif (GET_ZFLG) {\n");
-	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
-	    printf ("\tif (GET_ZFLG) {\n");
-	    printf ("\tm68k_write_memory_16(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
-	    printf ("\tm68k_write_memory_16(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
-	    printf ("\t}}\n");
-	    pop_braces (old_brace_level);
-	    printf ("\tif (! GET_ZFLG) {\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
-	    printf ("\t}\n");
-	} else {
-	    int old_brace_level = n_braces;
-	    printf ("\tuint32_t dst1 = m68k_read_memory_32(rn1), dst2 = m68k_read_memory_32(rn2);\n");
-	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
-	    printf ("\tif (GET_ZFLG) {\n");
-	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
-	    printf ("\tif (GET_ZFLG) {\n");
-	    printf ("\tm68k_write_memory_32(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
-	    printf ("\tm68k_write_memory_32(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
-	    printf ("\t}}\n");
-	    pop_braces (old_brace_level);
-	    printf ("\tif (! GET_ZFLG) {\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
-	    printf ("\t}\n");
-	}
-	break;
-    case i_MOVES:		/* ignore DFC and SFC because we have no MMU */
-    {
-	int old_brace_level;
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	printf ("\tif (extra & 0x800)\n");
-	old_brace_level = n_braces;
-	start_brace ();
-	printf ("\tuint32_t src = regs.regs[(extra >> 12) & 15];\n");
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
-	genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
-	pop_braces (old_brace_level);
-	printf ("else");
-	start_brace ();
-	genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0);
-	printf ("\tif (extra & 0x8000) {\n");
-	switch (curi->size) {
-	case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (int32_t)(int8_t)src;\n"); break;
-	case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (int32_t)(int16_t)src;\n"); break;
-	case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
-	default: abort ();
-	}
-	printf ("\t} else {\n");
-	genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
-	printf ("\t}\n");
-	pop_braces (old_brace_level);
-    }
-    break;
-    case i_BKPT:		/* only needed for hardware emulators */
-	sync_m68k_pc ();
-	printf ("\top_illg(opcode);\n");
-	break;
-    case i_CALLM:		/* not present in 68030 */
-	sync_m68k_pc ();
-	printf ("\top_illg(opcode);\n");
-	break;
-    case i_RTM:		/* not present in 68030 */
-	sync_m68k_pc ();
-	printf ("\top_illg(opcode);\n");
-	break;
-    case i_TRAPcc:
-	if (curi->smode != am_unknown && curi->smode != am_illg)
-	    genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
-	printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
-	need_endlabel = 1;
-	break;
-    case i_DIVL:
-	sync_m68k_pc ();
-	start_brace ();
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
-	break;
-    case i_MULL:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tm68k_mull(opcode, dst, extra);\n");
-	break;
-    case i_BFTST:
-    case i_BFEXTU:
-    case i_BFCHG:
-    case i_BFEXTS:
-    case i_BFCLR:
-    case i_BFFFO:
-    case i_BFSET:
-    case i_BFINS:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0);
-	start_brace ();
-	printf ("\tint32_t offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
-	printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
-	if (curi->dmode == Dreg) {
-	    printf ("\tuint32_t tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n");
-	} else {
-	    printf ("\tuint32_t tmp,bf0,bf1;\n");
-	    printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n");
-	    printf ("\tbf0 = m68k_read_memory_32(dsta);bf1 = m68k_read_memory_8(dsta+4) & 0xff;\n");
-	    printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
-	}
-	printf ("\ttmp >>= (32 - width);\n");
-	printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
-	printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
-	switch (curi->mnemo) {
-	case i_BFTST:
-	    break;
-	case i_BFEXTU:
-	    printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
-	    break;
-	case i_BFCHG:
-	    printf ("\ttmp = ~tmp;\n");
-	    break;
-	case i_BFEXTS:
-	    printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
-	    break;
-	case i_BFCLR:
-	    printf ("\ttmp = 0;\n");
-	    break;
-	case i_BFFFO:
-	    printf ("\t{ uint32_t mask = 1 << (width-1);\n");
-	    printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
-	    printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n");
-	    break;
-	case i_BFSET:
-	    printf ("\ttmp = 0xffffffff;\n");
-	    break;
-	case i_BFINS:
-	    printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
-	    printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
-	    printf ("\tSET_ZFLG (tmp == 0);\n");
-	    break;
-	default:
-	    break;
-	}
-	if (curi->mnemo == i_BFCHG
-	    || curi->mnemo == i_BFCLR
-	    || curi->mnemo == i_BFSET
-	    || curi->mnemo == i_BFINS)
-	    {
-		printf ("\ttmp <<= (32 - width);\n");
-		if (curi->dmode == Dreg) {
-		    printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n");
-		    printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n");
-		    printf ("\t\t(tmp >> (offset & 0x1f)) |\n");
-		    printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n");
-		    printf (" (m68k_dreg(regs, dstreg) & ((uint32_t)0xffffffff >> ((offset & 0x1f) + width))));\n");
-		} else {
-		    printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n");
-		    printf ("\t\t(tmp >> (offset & 7)) |\n");
-		    printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n");
-		    printf ("\t\t (bf0 & ((uint32_t)0xffffffff >> ((offset & 7) + width))));\n");
-		    printf ("\tm68k_write_memory_32(dsta,bf0 );\n");
-		    printf ("\tif (((offset & 7) + width) > 32) {\n");
-		    printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n");
-		    printf ("\t\t\t(tmp << (8 - (offset & 7)));\n");
-		    printf ("\t\tm68k_write_memory_8(dsta+4,bf1);\n");
-		    printf ("\t}\n");
-		}
-	    }
-	break;
-    case i_PACK:
-	if (curi->smode == Dreg) {
-	    printf ("\tuint16_t val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ());
-	    printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
-	} else {
-	    printf ("\tuint16_t val;\n");
-	    printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
-	    printf ("\tval = (uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg));\n");
-	    printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
-	    printf ("\tval = (val | ((uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ());
-	    printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
-	    printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n");
-	}
-	break;
-    case i_UNPK:
-	if (curi->smode == Dreg) {
-	    printf ("\tuint16_t val = m68k_dreg(regs, srcreg);\n");
-	    printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
-	    printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
-	} else {
-	    printf ("\tuint16_t val;\n");
-	    printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
-	    printf ("\tval = (uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg));\n");
-	    printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ());
-	    printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
-	    printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),val);\n");
-	    printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
-	    printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),val >> 8);\n");
-	}
-	break;
-    case i_TAS:
-	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
-	genflags (flag_logical, curi->size, "src", "", "");
-	printf ("\tsrc |= 0x80;\n");
-	genastore ("src", curi->smode, "srcreg", curi->size, "src");
-        if( curi->smode!=Dreg )  insn_n_cycles += 2;
-	break;
-    case i_FPP:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tfpp_opp(opcode,extra);\n");
-	break;
-    case i_FDBcc:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tfdbcc_opp(opcode,extra);\n");
-	break;
-    case i_FScc:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tfscc_opp(opcode,extra);\n");
-	break;
-    case i_FTRAPcc:
-	sync_m68k_pc ();
-	start_brace ();
-	printf ("\tuint32_t oldpc = m68k_getpc();\n");
-	if (curi->smode != am_unknown && curi->smode != am_illg)
-	    genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tftrapcc_opp(opcode,oldpc);\n");
-	break;
-    case i_FBcc:
-	sync_m68k_pc ();
-	start_brace ();
-	printf ("\tuint32_t pc = m68k_getpc();\n");
-	genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tfbcc_opp(opcode,pc,extra);\n");
-	break;
-    case i_FSAVE:
-	sync_m68k_pc ();
-	printf ("\tfsave_opp(opcode);\n");
-	break;
-    case i_FRESTORE:
-	sync_m68k_pc ();
-	printf ("\tfrestore_opp(opcode);\n");
-	break;
-
-     case i_CINVL:
-     case i_CINVP:
-     case i_CINVA:
-     case i_CPUSHL:
-     case i_CPUSHP:
-     case i_CPUSHA:
-	break;
-     case i_MOVE16:
-	if ((opcode & 0xfff8) == 0xf620) {
-	    /* MOVE16 (Ax)+,(Ay)+ */
-	    printf ("\tuint32_t mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
-	    printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
-	    printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
-	    printf ("\tm68k_write_memory_32(memd, m68k_read_memory_32(mems));\n");
-	    printf ("\tm68k_write_memory_32(memd+4, m68k_read_memory_32(mems+4));\n");
-	    printf ("\tm68k_write_memory_32(memd+8, m68k_read_memory_32(mems+8));\n");
-	    printf ("\tm68k_write_memory_32(memd+12, m68k_read_memory_32(mems+12));\n");
-	    printf ("\tif (srcreg != dstreg)\n");
-	    printf ("\tm68k_areg(regs, srcreg) += 16;\n");
-	    printf ("\tm68k_areg(regs, dstreg) += 16;\n");
-	} else {
-	    /* Other variants */
-	    genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
-	    genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
-	    printf ("\tmemsa &= ~15;\n");
-	    printf ("\tmemda &= ~15;\n");
-	    printf ("\tm68k_write_memory_32(memda, m68k_read_memory_32(memsa));\n");
-	    printf ("\tm68k_write_memory_32(memda+4, m68k_read_memory_32(memsa+4));\n");
-	    printf ("\tm68k_write_memory_32(memda+8, m68k_read_memory_32(memsa+8));\n");
-	    printf ("\tm68k_write_memory_32(memda+12, m68k_read_memory_32(memsa+12));\n");
-	    if ((opcode & 0xfff8) == 0xf600)
-		printf ("\tm68k_areg(regs, srcreg) += 16;\n");
-	    else if ((opcode & 0xfff8) == 0xf608)
-		printf ("\tm68k_areg(regs, dstreg) += 16;\n");
-	}
-	break;
-
-    case i_MMUOP:
-	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
-	sync_m68k_pc ();
-	printf ("\tmmu_op(opcode,extra);\n");
-	break;
-    default:
-	abort ();
-	break;
-    }
-    finish_braces ();
-    sync_m68k_pc ();
-}
-
-static void generate_includes(FILE * f)
-{
-//JLH:no	fprintf(f, "#include \"sysdeps.h\"\n");
-//JLH:no	fprintf(f, "#include \"hatari-glue.h\"\n");
-//JLH:no	fprintf(f, "#include \"maccess.h\"\n");
-//JLH:no	fprintf(f, "#include \"memory.h\"\n");
-//JLH:no	fprintf(f, "#include \"newcpu.h\"\n");
-	fprintf(f, "#include \"cpudefs.h\"\n");
-	fprintf(f, "#include \"cpuextra.h\"\n");
-	fprintf(f, "#include \"inlines.h\"\n");
-	fprintf(f, "#include \"cputbl.h\"\n");
-	fprintf(f, "#define CPUFUNC(x) x##_ff\n"
-		"#ifdef NOFLAGS\n"
-		"#include \"noflags.h\"\n"
-		"#endif\n");
-}
-
-// JLH: Since this is stuff that should be generated in a file that creates
-// constants, it's in here now. :-P
-static void GenerateTables(FILE * f)
-{
-	int i, j;
-
-	fprintf(f, "\nconst int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };\n");
-	fprintf(f, "const int imm8_table[]   = { 8, 1, 2, 3, 4, 5, 6, 7 };\n\n");
-	fprintf(f, "const int movem_index1[256] = {\n");
-
-	for(i=0; i<256; i++)
-	{
-		for(j=0; j<8; j++)
-			if (i & (1 << j))
-				break;
-
-		fprintf(f, "0x%02X, ", j);
-
-		if ((i % 16) == 15)
-			fprintf(f, "\n");
-	}
-
-	fprintf(f, "};\n\n");
-	fprintf(f, "const int movem_index2[256] = {\n");
-
-	for(i=0; i<256; i++)
-	{
-		for(j=0; j<8; j++)
-			if (i & (1 << j))
-				break;
-
-		fprintf(f, "0x%02X, ", 7 - j);
-
-		if ((i % 16) == 15)
-			fprintf(f, "\n");
-	}
-
-	fprintf(f, "};\n\n");
-	fprintf(f, "const int movem_next[256] = {\n");
-
-	for(i=0; i<256; i++)
-	{
-		for(j=0; j<8; j++)
-			if (i & (1 << j))
-				break;
-
-		fprintf(f, "0x%02X, ", i & (~(1 << j)));
-
-		if ((i % 16) == 15)
-			fprintf(f, "\n");
-	}
-
-	fprintf(f, "};\n\n");
-}
-
-static int postfix;
-
-static void generate_one_opcode (int rp)
-{
-    int i;
-    uint16_t smsk, dmsk;
-    long int opcode = opcode_map[rp];
-
-    exactCpuCycles[0] = 0;  /* Default: not used */
-
-    if (table68k[opcode].mnemo == i_ILLG
-	|| table68k[opcode].clev > cpu_level)
-	return;
-
-    for (i = 0; lookuptab[i].name[0]; i++) {
-	if (table68k[opcode].mnemo == lookuptab[i].mnemo)
-	    break;
-    }
-
-    if (table68k[opcode].handler != -1)
-	return;
-
-    if (opcode_next_clev[rp] != cpu_level) {
-	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
-		 opcode, lookuptab[i].name);
-	return;
-    }
-    fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
-    fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
-    fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
-    printf ("unsigned long CPUFUNC(op_%lx_%d)(uint32_t opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
-
-    switch (table68k[opcode].stype) {
-     case 0: smsk = 7; break;
-     case 1: smsk = 255; break;
-     case 2: smsk = 15; break;
-     case 3: smsk = 7; break;
-     case 4: smsk = 7; break;
-     case 5: smsk = 63; break;
-     case 7: smsk = 3; break;
-     default: abort ();
-    }
-    dmsk = 7;
-
-    next_cpu_level = -1;
-    if (table68k[opcode].suse
-	&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
-	&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
-	&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
-	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
-    {
-	if (table68k[opcode].spos == -1) {
-	    if (((int) table68k[opcode].sreg) >= 128)
-		printf ("\tuint32_t srcreg = (int32_t)(int8_t)%d;\n", (int) table68k[opcode].sreg);
-	    else
-		printf ("\tuint32_t srcreg = %d;\n", (int) table68k[opcode].sreg);
-	} else {
-	    char source[100];
-	    int pos = table68k[opcode].spos;
-
-	    if (pos)
-		sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
-	    else
-		sprintf (source, "(opcode & %d)", smsk);
-
-	    if (table68k[opcode].stype == 3)
-		printf ("\tuint32_t srcreg = imm8_table[%s];\n", source);
-	    else if (table68k[opcode].stype == 1)
-		printf ("\tuint32_t srcreg = (int32_t)(int8_t)%s;\n", source);
-	    else
-		printf ("\tuint32_t srcreg = %s;\n", source);
-	}
-    }
-    if (table68k[opcode].duse
-	/* Yes, the dmode can be imm, in case of LINK or DBcc */
-	&& table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
-	&& table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
-	&& table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
-    {
-	if (table68k[opcode].dpos == -1) {
-	    if (((int) table68k[opcode].dreg) >= 128)
-		printf ("\tuint32_t dstreg = (int32_t)(int8_t)%d;\n", (int) table68k[opcode].dreg);
-	    else
-		printf ("\tuint32_t dstreg = %d;\n", (int) table68k[opcode].dreg);
-	} else {
-	    int pos = table68k[opcode].dpos;
-#if 0
-	    /* Check that we can do the little endian optimization safely.  */
-	    if (pos < 8 && (dmsk >> (8 - pos)) != 0)
-		abort ();
-#endif	    
-	    if (pos)
-		printf ("\tuint32_t dstreg = (opcode >> %d) & %d;\n",
-			pos, dmsk);
-	    else
-		printf ("\tuint32_t dstreg = opcode & %d;\n", dmsk);
-	}
-    }
-    need_endlabel = 0;
-    endlabelno++;
-    sprintf (endlabelstr, "endlabel%d", endlabelno);
-    if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL
-       || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR
-       || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE
-       || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS
-       || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS )
-      printf("\tunsigned int retcycles = 0;\n");
-    gen_opcode (opcode);
-    if (need_endlabel)
-	printf ("%s: ;\n", endlabelstr);
-
-    if (strlen(exactCpuCycles) > 0)
-	printf("%s\n",exactCpuCycles);
-    else
-	printf ("return %d;\n", insn_n_cycles);
-    /* Now patch in the instruction cycles at the beginning of the function: */
-    fseek(stdout, nCurInstrCycPos, SEEK_SET);
-    printf("%d;", insn_n_cycles);
-    fseek(stdout, 0, SEEK_END);
-
-    printf ("}\n");
-    opcode_next_clev[rp] = next_cpu_level;
-    opcode_last_postfix[rp] = postfix;
-}
-
-static void generate_func(void)
-{
-	int i, j, rp;
-
-	using_prefetch = 0;
-	using_exception_3 = 0;
-//JLH:
-//	for(i=0; i<6; i++)
-//For some reason, this doesn't work properly. Seems something is making a bad
-//assumption somewhere.
-//and it's probably in opcode_next_clev[rp]...
-	for(i=4; i<6; i++)
-	{
-		cpu_level = 4 - i;
-
-		//JLH
-		for(rp=0; rp<nr_cpuop_funcs; rp++)
-			opcode_next_clev[rp] = 0;
-
-		if (i == 5)
-		{
-			cpu_level = 0;
-			using_prefetch = 1;
-			using_exception_3 = 1;
-	
-			for(rp=0; rp<nr_cpuop_funcs; rp++)
-				opcode_next_clev[rp] = 0;
-		}
-
-		postfix = i;
-		fprintf(stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
-
-		/* sam: this is for people with low memory (eg. me :)) */
-		printf("\n"
-			"#if !defined(PART_1) && !defined(PART_2) && "
-			"!defined(PART_3) && !defined(PART_4) && "
-			"!defined(PART_5) && !defined(PART_6) && "
-			"!defined(PART_7) && !defined(PART_8)"
-			"\n"
-			"#define PART_1 1\n"
-			"#define PART_2 1\n"
-			"#define PART_3 1\n"
-			"#define PART_4 1\n"
-			"#define PART_5 1\n"
-			"#define PART_6 1\n"
-			"#define PART_7 1\n"
-			"#define PART_8 1\n"
-			"#endif\n\n");
-
-		rp = 0;
-
-		for(j=1; j<=8; ++j)
-		{
-			int k = (j * nr_cpuop_funcs) / 8;
-			printf("#ifdef PART_%d\n", j);
-
-			for(; rp<k; rp++)
-				generate_one_opcode(rp);
-
-			printf ("#endif\n\n");
-		}
-
-		fprintf(stblfile, "{ 0, 0, 0 }};\n");
-	}
-}
-
-int main(int argc, char ** argv)
-{
-	read_table68k();
-	do_merges();
-
-	opcode_map = (int *)malloc(sizeof(int) * nr_cpuop_funcs);
-	opcode_last_postfix = (int *)malloc(sizeof(int) * nr_cpuop_funcs);
-	opcode_next_clev = (int *)malloc(sizeof(int) * nr_cpuop_funcs);
-	counts = (unsigned long *)malloc(65536 * sizeof(unsigned long));
-	read_counts();
-
-	/* It would be a lot nicer to put all in one file (we'd also get rid of
-	 * cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
-	 * I don't dare to touch the 68k version.  */
-
-	headerfile = fopen("cputbl.h", "wb");
-	stblfile = fopen("cpustbl.c", "wb");
-
-	if (freopen("cpuemu.c", "wb", stdout) == NULL)
-	{
-		perror("cpuemu.c");
-		return -1;
-	}
-
-	generate_includes(stdout);
-	generate_includes(stblfile);
-
-	GenerateTables(stdout);
-
-	generate_func();
-
-	free(table68k);
-	return 0;
-}
diff --git a/waterbox/virtualjaguar/src/m68000/inlines.h b/waterbox/virtualjaguar/src/m68000/inlines.h
index 54de9325b9..13801605f6 100644
--- a/waterbox/virtualjaguar/src/m68000/inlines.h
+++ b/waterbox/virtualjaguar/src/m68000/inlines.h
@@ -16,35 +16,32 @@ STATIC_INLINE int cctrue(const int cc)
 {
 	switch (cc)
 	{
-		case 0:  return 1;                       /* T */
-		case 1:  return 0;                       /* F */
-		case 2:  return !CFLG && !ZFLG;          /* HI */
-		case 3:  return CFLG || ZFLG;            /* LS */
-		case 4:  return !CFLG;                   /* CC */
-		case 5:  return CFLG;                    /* CS */
-		case 6:  return !ZFLG;                   /* NE */
-		case 7:  return ZFLG;                    /* EQ */
-		case 8:  return !VFLG;                   /* VC */
-		case 9:  return VFLG;                    /* VS */
-		case 10: return !NFLG;                   /* PL */
-		case 11: return NFLG;                    /* MI */
-		case 12: return NFLG == VFLG;            /* GE */
-		case 13: return NFLG != VFLG;            /* LT */
-		case 14: return !ZFLG && (NFLG == VFLG); /* GT */
-		case 15: return ZFLG || (NFLG != VFLG);  /* LE */
+		case 0:  return 1;
+		case 1:  return 0;
+		case 2:  return !CFLG && !ZFLG;
+		case 3:  return CFLG || ZFLG;
+		case 4:  return !CFLG;
+		case 5:  return CFLG;
+		case 6:  return !ZFLG;
+		case 7:  return ZFLG;
+		case 8:  return !VFLG;
+		case 9:  return VFLG;
+		case 10: return !NFLG;
+		case 11: return NFLG;
+		case 12: return NFLG == VFLG;
+		case 13: return NFLG != VFLG;
+		case 14: return !ZFLG && (NFLG == VFLG);
+		case 15: return ZFLG || (NFLG != VFLG);
 	}
 
 	abort();
 	return 0;
 }
 
-//no #define m68k_incpc(o) (regs.pc_p += (o))
 #define m68k_incpc(o) (regs.pc += (o))
 
 STATIC_INLINE void m68k_setpc(uint32_t newpc)
 {
-	//This is only done here... (get_real_address())
-//	regs.pc_p = regs.pc_oldp = get_real_address(newpc);
 	regs.pc = newpc;
 }
 
@@ -52,29 +49,13 @@ STATIC_INLINE void m68k_setpc(uint32_t newpc)
 
 STATIC_INLINE uint32_t m68k_getpc(void)
 {
-//	return regs.pc + ((char *)regs.pc_p - (char *)regs.pc_oldp);
 	return regs.pc;
 }
 
-#if 0
-STATIC_INLINE uint32_t m68k_getpc_p(uint8_t * p)
-{
-	return regs.pc + ((char *)p - (char *)regs.pc_oldp);
-}
-#endif
-
 STATIC_INLINE void m68k_setstopped(int stop)
 {
 	regs.stopped = stop;
 	regs.remainingCycles = 0;
-
-//But trace instructions are only on >68000 cpus, so this is bogus.
-#if 0
-	/* A traced STOP instruction drops through immediately without
-	actually stopping.  */
-	if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0)
-	regs.spcflags |= SPCFLAG_STOP;
-#endif
 }
 
 STATIC_INLINE void m68k_do_rts(void)
@@ -97,103 +78,27 @@ STATIC_INLINE void m68k_do_jsr(uint32_t oldpc, uint32_t dest)
 	m68k_setpc(dest);
 }
 
-#if 0
-//These do_get_mem_* functions are only used in newcpu...
-//What it does is use a pointer to make instruction fetching quicker,
-//though it probably leads to more problems than it solves. Something to
-//decide using a profiler...
-#define get_ibyte(o) do_get_mem_byte(regs.pc_p + (o) + 1)
-#define get_iword(o) do_get_mem_word(regs.pc_p + (o))
-#define get_ilong(o) do_get_mem_long(regs.pc_p + (o))
-#else
-// For now, we'll punt this crap...
-// (Also, notice that the byte read is at address + 1...)
 #define get_ibyte(o)	m68k_read_memory_8(regs.pc + (o) + 1)
 #define get_iword(o)	m68k_read_memory_16(regs.pc + (o))
 #define get_ilong(o)	m68k_read_memory_32(regs.pc + (o))
-#endif
 
-// We don't use this crap, so let's comment out for now...
 STATIC_INLINE void refill_prefetch(uint32_t currpc, uint32_t offs)
 {
-#if 0
-	uint32_t t = (currpc + offs) & ~1;
-	int32_t pc_p_offs = t - currpc;
-	uint8_t * ptr = regs.pc_p + pc_p_offs;
-	uint32_t r;
-
-#ifdef UNALIGNED_PROFITABLE
-	r = *(uint32_t *)ptr;
-	regs.prefetch = r;
-#else
-	r = do_get_mem_long(ptr);
-	do_put_mem_long(&regs.prefetch, r);
-#endif
-	/* printf ("PC %lx T %lx PCPOFFS %d R %lx\n", currpc, t, pc_p_offs, r); */
-	regs.prefetch_pc = t;
-#endif
 }
 
 STATIC_INLINE uint32_t get_ibyte_prefetch(int32_t o)
 {
-#if 0
-	uint32_t currpc = m68k_getpc();
-	uint32_t addr = currpc + o + 1;
-	uint32_t offs = addr - regs.prefetch_pc;
-
-	if (offs > 3)
-	{
-		refill_prefetch(currpc, o + 1);
-		offs = addr - regs.prefetch_pc;
-	}
-
-	uint32_t v = do_get_mem_byte(((uint8_t *)&regs.prefetch) + offs);
-
-	if (offs >= 2)
-		refill_prefetch(currpc, 2);
-
-	/* printf ("get_ibyte PC %lx ADDR %lx OFFS %lx V %lx\n", currpc, addr, offs, v); */
-	return v;
-#else
 	return get_ibyte(o);
-#endif
 }
 
 STATIC_INLINE uint32_t get_iword_prefetch(int32_t o)
 {
-#if 0
-	uint32_t currpc = m68k_getpc();
-	uint32_t addr = currpc + o;
-	uint32_t offs = addr - regs.prefetch_pc;
-
-	if (offs > 3)
-	{
-		refill_prefetch(currpc, o);
-		offs = addr - regs.prefetch_pc;
-	}
-
-	uint32_t v = do_get_mem_word(((uint8_t *)&regs.prefetch) + offs);
-
-	if (offs >= 2)
-		refill_prefetch(currpc, 2);
-
-/*	printf ("get_iword PC %lx ADDR %lx OFFS %lx V %lx\n", currpc, addr, offs, v); */
-	return v;
-#else
 	return get_iword(o);
-#endif
 }
 
 STATIC_INLINE uint32_t get_ilong_prefetch(int32_t o)
 {
-#if 0
-	uint32_t v = get_iword_prefetch(o);
-	v <<= 16;
-	v |= get_iword_prefetch(o + 2);
-	return v;
-#else
 	return get_ilong(o);
-#endif
 }
 
 STATIC_INLINE void fill_prefetch_0(void)
diff --git a/waterbox/virtualjaguar/src/m68000/m68kdasm.c b/waterbox/virtualjaguar/src/m68000/m68kdasm.c
deleted file mode 100644
index ab31cdb7bb..0000000000
--- a/waterbox/virtualjaguar/src/m68000/m68kdasm.c
+++ /dev/null
@@ -1,421 +0,0 @@
-//
-// m68kdasm.c: 68000 instruction disassembly
-//
-// Originally part of the UAE 68000 cpu core
-// by Bernd Schmidt
-//
-// Adapted to Virtual Jaguar by James Hammons
-//
-// This file is distributed under the GNU Public License, version 3 or at your
-// option any later version. Read the file GPLv3 for details.
-//
-
-#include <string.h>
-#include "cpudefs.h"
-#include "cpuextra.h"
-#include "inlines.h"
-#include "readcpu.h"
-
-
-// Stuff from m68kinterface.c
-extern unsigned long IllegalOpcode(uint32_t opcode);
-extern cpuop_func * cpuFunctionTable[65536];
-
-// Prototypes
-void HandleMovem(char * output, uint16_t data, int direction);
-
-// Local "global" variables
-static long int m68kpc_offset;
-
-#if 0
-#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
-#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
-#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
-#else
-#define get_ibyte_1(o) m68k_read_memory_8(regs.pc + (o) + 1)
-#define get_iword_1(o) m68k_read_memory_16(regs.pc + (o))
-#define get_ilong_1(o) m68k_read_memory_32(regs.pc + (o))
-#endif
-
-
-//int32_t ShowEA(FILE * f, int reg, amodes mode, wordsizes size, char * buf)
-int32_t ShowEA(int mnemonic, int reg, amodes mode, wordsizes size, char * buf)
-{
-	uint16_t dp;
-	int8_t disp8;
-	int16_t disp16;
-	int r;
-	uint32_t dispreg;
-	uint32_t addr;
-	int32_t offset = 0;
-	char buffer[80];
-
-	switch (mode)
-	{
-	case Dreg:
-		sprintf(buffer,"D%d", reg);
-		break;
-	case Areg:
-		sprintf(buffer,"A%d", reg);
-		break;
-	case Aind:
-		sprintf(buffer,"(A%d)", reg);
-		break;
-	case Aipi:
-		sprintf(buffer,"(A%d)+", reg);
-		break;
-	case Apdi:
-		sprintf(buffer,"-(A%d)", reg);
-		break;
-	case Ad16:
-		disp16 = get_iword_1(m68kpc_offset); m68kpc_offset += 2;
-		addr = m68k_areg(regs,reg) + (int16_t)disp16;
-		sprintf(buffer,"(A%d,$%X) == $%lX", reg, disp16 & 0xFFFF,
-			(unsigned long)addr);
-		break;
-	case Ad8r:
-		dp = get_iword_1(m68kpc_offset); m68kpc_offset += 2;
-		disp8 = dp & 0xFF;
-		r = (dp & 0x7000) >> 12;
-		dispreg = (dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r));
-
-		if (!(dp & 0x800))
-			dispreg = (int32_t)(int16_t)(dispreg);
-
-		dispreg <<= (dp >> 9) & 3;
-
-		if (dp & 0x100)
-		{
-			int32_t outer = 0, disp = 0;
-			int32_t base = m68k_areg(regs,reg);
-			char name[10];
-			sprintf (name,"A%d, ",reg);
-			if (dp & 0x80) { base = 0; name[0] = 0; }
-			if (dp & 0x40) dispreg = 0;
-			if ((dp & 0x30) == 0x20) { disp = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; }
-			if ((dp & 0x30) == 0x30) { disp = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; }
-			base += disp;
-
-			if ((dp & 0x3) == 0x2) { outer = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; }
-			if ((dp & 0x3) == 0x3) { outer = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; }
-
-			if (!(dp & 4)) base += dispreg;
-			if (dp & 3) base = m68k_read_memory_32(base);
-			if (dp & 4) base += dispreg;
-
-			addr = base + outer;
-			sprintf(buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%lX", name,
-				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
-				1 << ((dp >> 9) & 3),
-				(long)disp, (long)outer, (unsigned long)addr);
-		}
-		else
-		{
-			addr = m68k_areg(regs,reg) + (int32_t)((int8_t)disp8) + dispreg;
-			sprintf (buffer,"(A%d, %c%d.%c*%d, $%X) == $%lX", reg,
-				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
-				1 << ((dp >> 9) & 3), disp8, (unsigned long)addr);
-		}
-		break;
-	case PC16:
-		addr = m68k_getpc() + m68kpc_offset;
-		disp16 = get_iword_1(m68kpc_offset); m68kpc_offset += 2;
-		addr += (int16_t)disp16;
-		sprintf(buffer,"(PC, $%X) == $%lX", disp16 & 0xFFFF, (unsigned long)addr);
-		break;
-	case PC8r:
-		addr = m68k_getpc() + m68kpc_offset;
-		dp = get_iword_1(m68kpc_offset); m68kpc_offset += 2;
-		disp8 = dp & 0xFF;
-		r = (dp & 0x7000) >> 12;
-		dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
-
-		if (!(dp & 0x800))
-			dispreg = (int32_t)(int16_t)(dispreg);
-
-		dispreg <<= (dp >> 9) & 3;
-
-		if (dp & 0x100)
-		{
-			int32_t outer = 0,disp = 0;
-			int32_t base = addr;
-			char name[10];
-			sprintf (name,"PC, ");
-			if (dp & 0x80) { base = 0; name[0] = 0; }
-			if (dp & 0x40) dispreg = 0;
-			if ((dp & 0x30) == 0x20) { disp = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; }
-			if ((dp & 0x30) == 0x30) { disp = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; }
-			base += disp;
-
-			if ((dp & 0x3) == 0x2)
-			{
-				outer = (int32_t)(int16_t)get_iword_1(m68kpc_offset);
-				m68kpc_offset += 2;
-			}
-
-			if ((dp & 0x3) == 0x3)
-			{
-				outer = get_ilong_1(m68kpc_offset);
-				m68kpc_offset += 4;
-			}
-
-			if (!(dp & 4)) base += dispreg;
-			if (dp & 3) base = m68k_read_memory_32(base);
-			if (dp & 4) base += dispreg;
-
-			addr = base + outer;
-			sprintf(buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%lX", name,
-				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
-				1 << ((dp >> 9) & 3), (long)disp, (long)outer, (unsigned long)addr);
-		}
-		else
-		{
-			addr += (int32_t)((int8_t)disp8) + dispreg;
-			sprintf(buffer,"(PC, %c%d.%c*%d, $%X) == $%lX", dp & 0x8000 ? 'A' : 'D',
-				(int)r, dp & 0x800 ? 'L' : 'W',  1 << ((dp >> 9) & 3),
-				disp8, (unsigned long)addr);
-		}
-		break;
-	case absw:
-		sprintf(buffer,"$%lX", (unsigned long)(int32_t)(int16_t)get_iword_1(m68kpc_offset));
-		m68kpc_offset += 2;
-		break;
-	case absl:
-		sprintf(buffer,"$%lX", (unsigned long)get_ilong_1(m68kpc_offset));
-		m68kpc_offset += 4;
-		break;
-	case imm:
-		switch (size)
-		{
-		case sz_byte:
-			sprintf(buffer,"#$%X", (unsigned int)(get_iword_1(m68kpc_offset) & 0xFF));
-			m68kpc_offset += 2;
-			break;
-		case sz_word:
-			sprintf(buffer,"#$%X", (unsigned int)(get_iword_1(m68kpc_offset) & 0xFFFF));
-			m68kpc_offset += 2;
-			break;
-		case sz_long:
-			sprintf(buffer,"#$%lX", (unsigned long)(get_ilong_1(m68kpc_offset)));
-			m68kpc_offset += 4;
-			break;
-		default:
-			break;
-		}
-		break;
-	case imm0:
-		offset = (int32_t)(int8_t)get_iword_1(m68kpc_offset);
-		m68kpc_offset += 2;
-		sprintf(buffer,"#$%X", (unsigned int)(offset & 0xFF));
-		break;
-	case imm1:
-		offset = (int32_t)(int16_t)get_iword_1(m68kpc_offset);
-		m68kpc_offset += 2;
-
-		if (mnemonic == i_MVMEL)
-			HandleMovem(buffer, offset, 0);
-		else if (mnemonic == i_MVMLE)
-			HandleMovem(buffer, offset, 1);
-		else
-			sprintf(buffer,"#$%X", (unsigned int)(offset & 0xFFFF));
-
-		break;
-	case imm2:
-		offset = (int32_t)get_ilong_1(m68kpc_offset);
-		m68kpc_offset += 4;
-		sprintf(buffer,"#$%lX", (unsigned long)(offset & 0xFFFFFFFF));
-		break;
-	case immi:
-		offset = (int32_t)(int8_t)(reg & 0xFF);
-		sprintf(buffer,"#$%lX", (unsigned long)(offset & 0xFFFFFFFF));
-		break;
-	default:
-		break;
-	}
-
-//	if (buf == 0)
-//		fprintf(f, "%s", buffer);
-//	else
-	strcat(buf, buffer);
-
-	return offset;
-}
-
-
-void HandleMovem(char * output, uint16_t data, int direction)
-{
-	uint16_t ascending[16] = {
-		0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
-		0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 };
-	uint16_t descending[16] = {
-		0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100,
-		0x0080, 0x0040, 0x0020, 0x0010, 0x0008, 0x0004, 0x0002, 0x0001 };
-
-	int i, j, first, runLength, firstPrint = 1;
-	char buf[16];
-	uint16_t * bitMask;
-
-	bitMask = (direction ? descending : ascending);
-	output[0] = 0;
-
-	// Handle D0-D7...
-	for(i=0; i<8; i++)
-	{
-		if (data & bitMask[i])
-		{
-			first = i;
-			runLength = 0;
-
-			for(j=i+1; j<8 && (data & bitMask[j]); j++)
-				runLength++;
-
-			i += runLength;
-
-			if (firstPrint)
-				firstPrint = 0;
-			else
-				strcat(output, "/");
-
-			sprintf(buf, "D%d", first);
-			strcat(output, buf);
-
-			if (runLength > 0)
-			{
-				sprintf(buf, "-D%d", first + runLength);
-				strcat(output, buf);
-			}
-		}
-	}
-
-	// Handle A0-A7...
-	for(i=0; i<8; i++)
-	{
-		if (data & bitMask[i + 8])
-		{
-			first = i;
-			runLength = 0;
-
-			for(j=i+1; j<8 && (data & bitMask[j+8]); j++)
-				runLength++;
-
-			i += runLength;
-
-			if (firstPrint)
-				firstPrint = 0;
-			else
-				strcat(output, "/");
-
-			sprintf(buf, "A%d", first);
-			strcat(output, buf);
-
-			if (runLength > 0)
-			{
-				sprintf(buf, "-A%d", first + runLength);
-				strcat(output, buf);
-			}
-		}
-	}
-}
-
-
-unsigned int M68KDisassemble(char * output, uint32_t addr)
-{
-	char f[256], str[256];
-	char src[256], dst[256];
-	static const char * const ccnames[] =
-		{ "RA","RN","HI","LS","CC","CS","NE","EQ",
-		  "VC","VS","PL","MI","GE","LT","GT","LE" };
-
-	str[0] = 0;
-	output[0] = 0;
-	uint32_t newpc = 0;
-	m68kpc_offset = addr - m68k_getpc();
-	long int pcOffsetSave = m68kpc_offset;
-	int opwords;
-	char instrname[20];
-	const struct mnemolookup * lookup;
-
-	uint32_t opcode = get_iword_1(m68kpc_offset);
-	m68kpc_offset += 2;
-
-	if (cpuFunctionTable[opcode] == IllegalOpcode)
-		opcode = 0x4AFC;
-
-	struct instr * dp = table68k + opcode;
-
-	for(lookup=lookuptab; lookup->mnemo!=dp->mnemo; lookup++)
-		;
-
-	strcpy(instrname, lookup->name);
-	char * ccpt = strstr(instrname, "cc");
-
-	if (ccpt)
-		strncpy(ccpt, ccnames[dp->cc], 2);
-
-	sprintf(f, "%s", instrname);
-	strcat(str, f);
-
-	switch (dp->size)
-	{
-	case sz_byte: strcat(str, ".B\t"); break;
-	case sz_word: strcat(str, ".W\t"); break;
-	case sz_long: strcat(str, ".L\t"); break;
-	default: strcat(str, "\t"); break;
-	}
-
-	// Get source and destination operands (if any)
-	src[0] = dst[0] = f[0] = 0;
-
-	if (dp->suse)
-		newpc = m68k_getpc() + m68kpc_offset
-			+ ShowEA(dp->mnemo, dp->sreg, dp->smode, dp->size, src);
-
-	if (dp->duse)
-		newpc = m68k_getpc() + m68kpc_offset
-			+ ShowEA(dp->mnemo, dp->dreg, dp->dmode, dp->size, dst);
-
-	// Handle execptions to the standard rules
-	if (dp->mnemo == i_BSR || dp->mnemo == i_Bcc)
-		sprintf(f, "$%lX", (long)newpc);
-	else if (dp->mnemo == i_DBcc)
-		sprintf(f, "%s, $%lX", src, (long)newpc);
-	else if (dp->mnemo == i_MVMEL)
-		sprintf(f, "%s, %s", dst, src);
-	else
-		sprintf(f, "%s%s%s", src, (dp->suse && dp->duse ? ", " : ""), dst);
-
-	strcat(str, f);
-
-	if (ccpt)
-	{
-		sprintf(f, " (%s)", (cctrue(dp->cc) ? "true" : "false"));
-		strcat(str, f);
-	}
-
-	// Add byte(s) display to front of disassembly
-	long int numberOfBytes = m68kpc_offset - pcOffsetSave;
-
-	for(opwords=0; opwords<5; opwords++)
-	{
-		if (((opwords + 1) * 2) <= numberOfBytes)
-			sprintf(f, "%04X ", get_iword_1(pcOffsetSave + opwords * 2));
-		else
-			sprintf(f, "     ");
-
-		strcat(output, f);
-	}
-
-	strcat(output, str);
-
-	return numberOfBytes;
-}
-
-
-//
-// Disassemble one instruction at pc and store in str_buff
-//
-unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type)
-{
-	return M68KDisassemble(str_buff, pc);
-}
-
diff --git a/waterbox/virtualjaguar/src/m68000/m68kinterface.c b/waterbox/virtualjaguar/src/m68000/m68kinterface.c
index d896cdfe10..d51fc37b39 100644
--- a/waterbox/virtualjaguar/src/m68000/m68kinterface.c
+++ b/waterbox/virtualjaguar/src/m68000/m68kinterface.c
@@ -12,7 +12,6 @@
 //
 
 #include "m68kinterface.h"
-//#include <pthread.h>
 #include "cpudefs.h"
 #include "inlines.h"
 #include "cpuextra.h"
@@ -35,18 +34,8 @@
 #define EXCEPTION_INTERRUPT_AUTOVECTOR    24
 #define EXCEPTION_TRAP_BASE               32
 
-// These are found in obj/cpustbl.c (generated by gencpu)
-
-//extern const struct cputbl op_smalltbl_0_ff[];	/* 68040 */
-//extern const struct cputbl op_smalltbl_1_ff[];	/* 68020 + 68881 */
-//extern const struct cputbl op_smalltbl_2_ff[];	/* 68020 */
-//extern const struct cputbl op_smalltbl_3_ff[];	/* 68010 */
-extern const struct cputbl op_smalltbl_4_ff[];	/* 68000 */
 extern const struct cputbl op_smalltbl_5_ff[];	/* 68000 slow but compatible.  */
 
-// Externs, supplied by the user...
-//extern int irq_ack_handler(int);
-
 // Function prototypes...
 STATIC_INLINE void m68ki_check_interrupts(void);
 void m68ki_exception_interrupt(uint32_t intLevel);
@@ -60,158 +49,34 @@ void m68k_set_irq2(unsigned int intLevel);
 static int32_t initialCycles;
 cpuop_func * cpuFunctionTable[65536];
 
-// By virtue of the fact that m68k_set_irq() can be called asychronously by
-// another thread, we need something along the lines of this:
 static int checkForIRQToHandle = 0;
-//static pthread_mutex_t executionLock = PTHREAD_MUTEX_INITIALIZER;
 static int IRQLevelToHandle = 0;
 
-#if 0
-#define ADD_CYCLES(A)    m68ki_remaining_cycles += (A)
-#define USE_CYCLES(A)    m68ki_remaining_cycles -= (A)
-#define SET_CYCLES(A)    m68ki_remaining_cycles = A
-#define GET_CYCLES()     m68ki_remaining_cycles
-#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0
-
-#define CPU_INT_LEVEL    m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */
-#define CPU_INT_CYCLES   m68ki_cpu.int_cycles /* ASG */
-#define CPU_STOPPED      m68ki_cpu.stopped
-#define CPU_PREF_ADDR    m68ki_cpu.pref_addr
-#define CPU_PREF_DATA    m68ki_cpu.pref_data
-#define CPU_ADDRESS_MASK m68ki_cpu.address_mask
-#define CPU_SR_MASK      m68ki_cpu.sr_mask
-#endif
-
-#define CPU_DEBUG
-
-
-void Dasm(uint32_t offset, uint32_t qt)
-{
-#ifdef CPU_DEBUG
-// back up a few instructions...
-//offset -= 100;
-	static char buffer[2048];//, mem[64];
-	int pc = offset, oldpc;
-	uint32_t i;
-
-	for(i=0; i<qt; i++)
-	{
-/*		oldpc = pc;
-		for(int j=0; j<64; j++)
-			mem[j^0x01] = jaguar_byte_read(pc + j);
-
-		pc += Dasm68000((char *)mem, buffer, 0);
-		WriteLog("%08X: %s\n", oldpc, buffer);//*/
-		oldpc = pc;
-		pc += m68k_disassemble(buffer, pc, 0);//M68K_CPU_TYPE_68000);
-//		WriteLog("%08X: %s\n", oldpc, buffer);//*/
-		printf("%08X: %s\n", oldpc, buffer);//*/
-	}
-#endif
-}
-
-
-#ifdef CPU_DEBUG
-void DumpRegisters(void)
-{
-	uint32_t i;
-
-	for(i=0; i<16; i++)
-	{
-		printf("%s%i: %08X ", (i < 8 ? "D" : "A"), i & 0x7, regs.regs[i]);
-
-		if ((i & 0x03) == 3)
-			printf("\n");
-	}
-}
-#endif
-
-
-void M68KDebugHalt(void)
-{
-	regs.spcflags |= SPCFLAG_DEBUGGER;
-}
-
-
-void M68KDebugResume(void)
-{
-	regs.spcflags &= ~SPCFLAG_DEBUGGER;
-}
-
-
-void m68k_set_cpu_type(unsigned int type)
-{
-}
-
-
 // Pulse the RESET line on the CPU
 void m68k_pulse_reset(void)
 {
 	static uint32_t emulation_initialized = 0;
 
-	// The first call to this function initializes the opcode handler jump table
 	if (!emulation_initialized)
 	{
-#if 0
-		m68ki_build_opcode_table();
-		m68k_set_int_ack_callback(NULL);
-		m68k_set_bkpt_ack_callback(NULL);
-		m68k_set_reset_instr_callback(NULL);
-		m68k_set_pc_changed_callback(NULL);
-		m68k_set_fc_callback(NULL);
-		m68k_set_instr_hook_callback(NULL);
-#else
-		// Build opcode handler table here...
 		read_table68k();
 		do_merges();
 		BuildCPUFunctionTable();
-#endif
 		emulation_initialized = 1;
 	}
 
-//	if (CPU_TYPE == 0)	/* KW 990319 */
-//		m68k_set_cpu_type(M68K_CPU_TYPE_68000);
-
-#if 0
-	/* Clear all stop levels and eat up all remaining cycles */
-	CPU_STOPPED = 0;
-	SET_CYCLES(0);
-
-	/* Turn off tracing */
-	FLAG_T1 = FLAG_T0 = 0;
-	m68ki_clear_trace();
-	/* Interrupt mask to level 7 */
-	FLAG_INT_MASK = 0x0700;
-	/* Reset VBR */
-	REG_VBR = 0;
-	/* Go to supervisor mode */
-	m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR);
-
-	/* Invalidate the prefetch queue */
-#if M68K_EMULATE_PREFETCH
-	/* Set to arbitrary number since our first fetch is from 0 */
-	CPU_PREF_ADDR = 0x1000;
-#endif /* M68K_EMULATE_PREFETCH */
-
-	/* Read the initial stack pointer and program counter */
-	m68ki_jump(0);
-	REG_SP = m68ki_read_imm_32();
-	REG_PC = m68ki_read_imm_32();
-	m68ki_jump(REG_PC);
-#else
 	checkForIRQToHandle = 0;
 	regs.spcflags = 0;
 	regs.stopped = 0;
 	regs.remainingCycles = 0;
 	
 	regs.intmask = 0x07;
-	regs.s = 1;								// Supervisor mode ON
+	regs.s = 1;
 
 	// Read initial SP and PC
 	m68k_areg(regs, 7) = m68k_read_memory_32(0);
 	m68k_setpc(m68k_read_memory_32(4));
 	refill_prefetch(m68k_getpc(), 0);
-#endif
 }
 
 
@@ -219,392 +84,124 @@ int m68k_execute(int num_cycles)
 {
 	if (regs.stopped)
 	{
-		regs.remainingCycles = 0;	// int32_t
-		regs.interruptCycles = 0;	// uint32_t
+		regs.remainingCycles = 0;
+		regs.interruptCycles = 0;
 
 		return num_cycles;
 	}
 
-#if 0
-	/* Set our pool of clock cycles available */
-	SET_CYCLES(num_cycles);
-	m68ki_initial_cycles = num_cycles;
-
-	/* ASG: update cycles */
-	USE_CYCLES(CPU_INT_CYCLES);
-	CPU_INT_CYCLES = 0;
-
-	/* Return point if we had an address error */
-	m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */
-#else
 	regs.remainingCycles = num_cycles;
-	/*int32_t*/ initialCycles = num_cycles;
+	initialCycles = num_cycles;
 	
 	regs.remainingCycles -= regs.interruptCycles;
 	regs.interruptCycles = 0;
-#endif
 
 	/* Main loop.  Keep going until we run out of clock cycles */
 	do
 	{
-		// This is so our debugging code can break in on a dime.
-		// Otherwise, this is just extra slow down :-P
-		if (regs.spcflags & SPCFLAG_DEBUGGER)
-		{
-			// Not sure this is correct... :-P
-			num_cycles = initialCycles - regs.remainingCycles;
-			regs.remainingCycles = 0;	// int32_t
-			regs.interruptCycles = 0;	// uint32_t
-
-			return num_cycles;
-		}
-#if 0
-		/* Set tracing accodring to T1. (T0 is done inside instruction) */
-		m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
-
-		/* Set the address space for reads */
-		m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */
-
-		/* Call external hook to peek at CPU */
-		m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */
-
-		/* Record previous program counter */
-		REG_PPC = REG_PC;
-
-		/* Read an instruction and call its handler */
-		REG_IR = m68ki_read_imm_16();
-		m68ki_instruction_jump_table[REG_IR]();
-		USE_CYCLES(CYC_INSTRUCTION[REG_IR]);
-
-		/* Trace m68k_exception, if necessary */
-		m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */
-#else
-//Testing Hover Strike...
-#if 0
-//Dasm(regs.pc, 1);
-static int hitCount = 0;
-static int inRoutine = 0;
-static int instSeen;
-
-//if (regs.pc == 0x80340A)
-if (regs.pc == 0x803416)
-{
-	hitCount++;
-	inRoutine = 1;
-	instSeen = 0;
-	printf("%i: $80340A start. A0=%08X, A1=%08X ", hitCount, regs.regs[8], regs.regs[9]);
-}
-else if (regs.pc == 0x803422)
-{
-	inRoutine = 0;
-	printf("(%i instructions)\n", instSeen);
-}
-
-if (inRoutine)
-	instSeen++;
-#endif
-// AvP testing... (problem was: 32 bit addresses on 24 bit address cpu--FIXED)
-#if 0
-	static int go = 0;
-
-	if (regs.pc == 0x94BA)
-	{
-		go = 1;
-		printf("\n");
-	}
-
-	if (regs.pc == 0x94C6)
-		go = 0;
-
-//	if (regs.regs[10] == 0xFFFFFFFF && go)
-	if (go)
-	{
-//		printf("A2=-1, PC=%08X\n", regs.pc);
-//		go = 0;
-//		Dasm(regs.pc, 130);
-		Dasm(regs.pc, 1);
-		DumpRegisters();
-	}
-//94BA: 2468 0000                MOVEA.L	(A0,$0000) == $0002328A, A2
-//94BE: 200A                     MOVE.L	A2, D0
-//94C0: 6A02                     BPL.B	$94C4
-//94C2: 2452                     MOVEA.L	(A2), A2			; <--- HERE
-//94C4: 4283                     CLR.L	D3
-#endif
-//		pthread_mutex_lock(&executionLock);
 		if (checkForIRQToHandle)
 		{
 			checkForIRQToHandle = 0;
 			m68k_set_irq2(IRQLevelToHandle);
 		}
 
-#ifdef M68K_HOOK_FUNCTION
 		M68KInstructionHook();
-#endif
 		uint32_t opcode = get_iword(0);
-//if ((opcode & 0xFFF8) == 0x31C0)
-//{
-//	printf("MOVE.W D%i, EA\n", opcode & 0x07);
-//}
 		int32_t cycles = (int32_t)(*cpuFunctionTable[opcode])(opcode);
 		regs.remainingCycles -= cycles;
-//		pthread_mutex_unlock(&executionLock);
-
-//printf("Executed opcode $%04X (%i cycles)...\n", opcode, cycles);
-#endif
 	}
 	while (regs.remainingCycles > 0);
 
-#if 0
-	/* set previous PC to current PC for the next entry into the loop */
-	REG_PPC = REG_PC;
-
-	/* ASG: update cycles */
-	USE_CYCLES(CPU_INT_CYCLES);
-	CPU_INT_CYCLES = 0;
-
-	/* return how many clocks we used */
-	return m68ki_initial_cycles - GET_CYCLES();
-#else
 	regs.remainingCycles -= regs.interruptCycles;
 	regs.interruptCycles = 0;
 
 	// Return # of clock cycles used
 	return initialCycles - regs.remainingCycles;
-#endif
 }
 
-
 void m68k_set_irq(unsigned int intLevel)
 {
-	// We need to check for stopped state as well...
 	if (regs.stopped)
 	{
 		m68k_set_irq2(intLevel);
 		return;
 	}
 
-	// Since this can be called asynchronously, we need to fix it so that it
-	// doesn't fuck up the main execution loop.
 	IRQLevelToHandle = intLevel;
 	checkForIRQToHandle = 1;
 }
 
-
 /* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */
 void m68k_set_irq2(unsigned int intLevel)
 {
-//	pthread_mutex_lock(&executionLock);
-//		printf("m68k_set_irq: Could not get the lock!!!\n");
-
 	int oldLevel = regs.intLevel;
 	regs.intLevel = intLevel;
 
-	// A transition from < 7 to 7 always interrupts (NMI)
-	// Note: Level 7 can also level trigger like a normal IRQ
 	if (oldLevel != 0x07 && regs.intLevel == 0x07)
-		m68ki_exception_interrupt(7);		// Edge triggered level 7 (NMI)
+		m68ki_exception_interrupt(7);
 	else
-		m68ki_check_interrupts();			// Level triggered (IRQ)
-
-//	pthread_mutex_unlock(&executionLock);
+		m68ki_check_interrupts();
 }
 
-
 // Check for interrupts
 STATIC_INLINE void m68ki_check_interrupts(void)
 {
-#if 0
-	if(CPU_INT_LEVEL > FLAG_INT_MASK)
-		m68ki_exception_interrupt(CPU_INT_LEVEL>>8);
-#else
 	if (regs.intLevel > regs.intmask)
 		m68ki_exception_interrupt(regs.intLevel);
-#endif
 }
 
-
 // Service an interrupt request and start exception processing
 void m68ki_exception_interrupt(uint32_t intLevel)
 {
-#if 0
-	uint vector;
-	uint sr;
-	uint new_pc;
-
-	/* Turn off the stopped state */
-	CPU_STOPPED &= ~STOP_LEVEL_STOP;
-
-	/* If we are halted, don't do anything */
-	if(CPU_STOPPED)
-		return;
-
-	/* Acknowledge the interrupt */
-	vector = m68ki_int_ack(int_level);
-
-	/* Get the interrupt vector */
-	if(vector == M68K_INT_ACK_AUTOVECTOR)
-		/* Use the autovectors.  This is the most commonly used implementation */
-		vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
-	else if(vector == M68K_INT_ACK_SPURIOUS)
-		/* Called if no devices respond to the interrupt acknowledge */
-		vector = EXCEPTION_SPURIOUS_INTERRUPT;
-	else if(vector > 255)
-	{
-		M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",
-			 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector));
-		return;
-	}
-
-	/* Start exception processing */
-	sr = m68ki_init_exception();
-
-	/* Set the interrupt mask to the level of the one being serviced */
-	FLAG_INT_MASK = int_level<<8;
-
-	/* Get the new PC */
-	new_pc = m68ki_read_data_32((vector<<2) + REG_VBR);
-
-	/* If vector is uninitialized, call the uninitialized interrupt vector */
-	if(new_pc == 0)
-		new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR);
-
-	/* Generate a stack frame */
-	m68ki_stack_frame_0000(REG_PC, sr, vector);
-
-	if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
-	{
-		/* Create throwaway frame */
-		m68ki_set_sm_flag(FLAG_S);	/* clear M */
-		sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */
-		m68ki_stack_frame_0001(REG_PC, sr, vector);
-	}
-
-	m68ki_jump(new_pc);
-
-	/* Defer cycle counting until later */
-	CPU_INT_CYCLES += CYC_EXCEPTION[vector];
-
-#if !M68K_EMULATE_INT_ACK
-	/* Automatically clear IRQ if we are not using an acknowledge scheme */
-	CPU_INT_LEVEL = 0;
-#endif /* M68K_EMULATE_INT_ACK */
-#else
-	// Turn off the stopped state (N.B.: normal 68K behavior!)
 	regs.stopped = 0;
 
-//JLH: need to add halt state?
-// prolly, for debugging/alpine mode... :-/
-// but then again, this should be handled already by the main execution loop :-P
-	// If we are halted, don't do anything
-//	if (regs.halted)
-//		return;
-
-	// Acknowledge the interrupt (NOTE: This is a user supplied function!)
 	uint32_t vector = irq_ack_handler(intLevel);
 
-	// Get the interrupt vector
 	if (vector == M68K_INT_ACK_AUTOVECTOR)
-		// Use the autovectors.  This is the most commonly used implementation
 		vector = EXCEPTION_INTERRUPT_AUTOVECTOR + intLevel;
 	else if (vector == M68K_INT_ACK_SPURIOUS)
-		// Called if no devices respond to the interrupt acknowledge
 		vector = EXCEPTION_SPURIOUS_INTERRUPT;
 	else if (vector > 255)
 	{
-//		M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",
-//			 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector));
 		return;
 	}
 
-	// Start exception processing
 	uint32_t sr = m68ki_init_exception();
 
-	// Set the interrupt mask to the level of the one being serviced
 	regs.intmask = intLevel;
 
-#if 0
-extern int startM68KTracing;
-if (startM68KTracing)
-{
-	printf("IRQ: old PC=%06X, ", regs.pc);
-}
-#endif
-
-	// Get the new PC
 	uint32_t newPC = m68k_read_memory_32(vector << 2);
 
-#if 0
-if (startM68KTracing)
-{
-	printf("new PC=%06X, vector=%u, ", newPC, vector);
-}
-#endif
-
-	// If vector is uninitialized, call the uninitialized interrupt vector
 	if (newPC == 0)
 		newPC = m68k_read_memory_32(EXCEPTION_UNINITIALIZED_INTERRUPT << 2);
 
-	// Generate a stack frame
 	m68ki_stack_frame_3word(regs.pc, sr);
 
 	m68k_setpc(newPC);
-#if 0
-if (startM68KTracing)
-{
-	printf("(PC=%06X)\n", regs.pc);
-}
-#endif
 
-	// Defer cycle counting until later
-	regs.interruptCycles += 56;	// NOT ACCURATE-- !!! FIX !!!
-//	CPU_INT_CYCLES += CYC_EXCEPTION[vector];
-#endif
+	regs.interruptCycles += 56;
 }
 
-
 // Initiate exception processing
 STATIC_INLINE uint32_t m68ki_init_exception(void)
 {
-#if 0
-	/* Save the old status register */
-	uint sr = m68ki_get_sr();
-
-	/* Turn off trace flag, clear pending traces */
-	FLAG_T1 = FLAG_T0 = 0;
-	m68ki_clear_trace();
-	/* Enter supervisor mode */
-	m68ki_set_s_flag(SFLAG_SET);
-
-	return sr;
-#else
 	MakeSR();
-	uint32_t sr = regs.sr;					// Save old status register
-	regs.s = 1;								// Set supervisor mode
+	uint32_t sr = regs.sr;
+	regs.s = 1;
 
 	return sr;
-#endif
 }
 
-
 // 3 word stack frame (68000 only)
 STATIC_INLINE void m68ki_stack_frame_3word(uint32_t pc, uint32_t sr)
 {
-#if 0
-	m68ki_push_32(pc);
-	m68ki_push_16(sr);
-#else
-	// Push PC on stack:
 	m68k_areg(regs, 7) -= 4;
 	m68k_write_memory_32(m68k_areg(regs, 7), pc);
-	// Push SR on stack:
 	m68k_areg(regs, 7) -= 2;
 	m68k_write_memory_16(m68k_areg(regs, 7), sr);
-#endif
 }
 
-
-unsigned int m68k_get_reg(void * context, m68k_register_t reg)
+unsigned int m68k_get_reg(m68k_register_t reg)
 {
 	if (reg <= M68K_REG_A7)
 		return regs.regs[reg];
@@ -621,7 +218,6 @@ unsigned int m68k_get_reg(void * context, m68k_register_t reg)
 	return 0;
 }
 
-
 void m68k_set_reg(m68k_register_t reg, unsigned int value)
 {
 	if (reg <= M68K_REG_A7)
@@ -637,7 +233,6 @@ void m68k_set_reg(m68k_register_t reg, unsigned int value)
 		regs.regs[15] = value;
 }
 
-
 //
 // Check if the instruction is a valid one
 //
@@ -651,106 +246,54 @@ unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cp
 	return 1;
 }
 
-
-// Dummy functions, for now, until we prove the concept here. :-)
-
-// Temp, while we're using the Musashi disassembler...
-#if 0
-unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type)
-{
-	return 0;
-}
-#endif
-
-int m68k_cycles_run(void) {}              /* Number of cycles run so far */
-int m68k_cycles_remaining(void) {}        /* Number of cycles left */
-//void m68k_modify_timeslice(int cycles) {} /* Modify cycles left */
-//void m68k_end_timeslice(void) {}          /* End timeslice now */
-
-
 void m68k_modify_timeslice(int cycles)
 {
 	regs.remainingCycles = cycles;
 }
 
-
 void m68k_end_timeslice(void)
 {
-#if 0
-	m68ki_initial_cycles = GET_CYCLES();
-	SET_CYCLES(0);
-#else
 	initialCycles = regs.remainingCycles;
 	regs.remainingCycles = 0;
-#endif
 }
 
-
 unsigned long IllegalOpcode(uint32_t opcode)
 {
-#if 0
-	uint32_t pc = m68k_getpc ();
-#endif
 	if ((opcode & 0xF000) == 0xF000)
 	{
-		Exception(0x0B, 0, M68000_EXC_SRC_CPU);	// LineF exception...
+		Exception(0x0B, 0, M68000_EXC_SRC_CPU);
 		return 4;
 	}
 	else if ((opcode & 0xF000) == 0xA000)
 	{
-		Exception(0x0A, 0, M68000_EXC_SRC_CPU);	// LineA exception...
+		Exception(0x0A, 0, M68000_EXC_SRC_CPU);
 		return 4;
 	}
 
-#if 0
-	write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
-#endif
-
-	Exception(0x04, 0, M68000_EXC_SRC_CPU);		// Illegal opcode exception...
+	Exception(0x04, 0, M68000_EXC_SRC_CPU);
 	return 4;
 }
 
-
 void BuildCPUFunctionTable(void)
 {
 	int i;
 	unsigned long opcode;
 
-	// We're only using the "fast" 68000 emulation here, not the "compatible"
-	// ("fast" doesn't throw exceptions, so we're using "compatible" now :-P)
-#if 0
-	const struct cputbl * tbl = (currprefs.cpu_compatible
-		? op_smalltbl_5_ff : op_smalltbl_4_ff);
-#else
-//let's try "compatible" and see what happens here...
-//	const struct cputbl * tbl = op_smalltbl_4_ff;
 	const struct cputbl * tbl = op_smalltbl_5_ff;
-#endif
 
-//	Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n",
-//		currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
-
-	// Set all instructions to Illegal...
 	for(opcode=0; opcode<65536; opcode++)
 		cpuFunctionTable[opcode] = IllegalOpcode;
 
-	// Move functions from compact table into our full function table...
 	for(i=0; tbl[i].handler!=NULL; i++)
 		cpuFunctionTable[tbl[i].opcode] = tbl[i].handler;
 
-//JLH: According to readcpu.c, handler is set to -1 and never changes.
-// Actually, it does read this crap in readcpu.c, do_merges() does it... :-P
-// Again, seems like a build time thing could be done here...
-#if 1
 	for(opcode=0; opcode<65536; opcode++)
 	{
-//		if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
 		if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > 0)
 			continue;
 
 		if (table68k[opcode].handler != -1)
 		{
-//printf("Relocate: $%04X->$%04X\n", table68k[opcode].handler, opcode);
 			cpuop_func * f = cpuFunctionTable[table68k[opcode].handler];
 
 			if (f == IllegalOpcode)
@@ -759,5 +302,4 @@ void BuildCPUFunctionTable(void)
 			cpuFunctionTable[opcode] = f;
 		}
 	}
-#endif
 }
diff --git a/waterbox/virtualjaguar/src/m68000/m68kinterface.h b/waterbox/virtualjaguar/src/m68000/m68kinterface.h
index 84c87af9f3..1b7bfada59 100644
--- a/waterbox/virtualjaguar/src/m68000/m68kinterface.h
+++ b/waterbox/virtualjaguar/src/m68000/m68kinterface.h
@@ -69,7 +69,6 @@ typedef enum
  */
 #define M68K_INT_ACK_SPURIOUS      0xFFFFFFFE
 
-void m68k_set_cpu_type(unsigned int);
 void m68k_pulse_reset(void);
 int m68k_execute(int num_cycles);
 void m68k_set_irq(unsigned int int_level);
@@ -90,45 +89,24 @@ int irq_ack_handler(int);
 
 // Convenience functions
 
-// Uncomment this to have the emulated CPU call a hook function after every instruction
-// NB: This must be implemented by the user!
-#define M68K_HOOK_FUNCTION
-#ifdef M68K_HOOK_FUNCTION
 void M68KInstructionHook(void);
-#endif
 
-// Functions to allow debugging
-void M68KDebugHalt(void);
-void M68KDebugResume(void);
-
-/* Peek at the internals of a CPU context.  This can either be a context
- * retrieved using m68k_get_context() or the currently running context.
- * If context is NULL, the currently running CPU context will be used.
- */
-unsigned int m68k_get_reg(void * context, m68k_register_t reg);
+/* Peek at the internals of the currently running CPU context */
+unsigned int m68k_get_reg(m68k_register_t reg);
 
 /* Poke values into the internals of the currently running CPU context */
 void m68k_set_reg(m68k_register_t reg, unsigned int value);
 
-// Dummy functions, for now...
-
 /* Check if an instruction is valid for the specified CPU type */
 unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type);
 
-/* Disassemble 1 instruction using the epecified CPU type at pc.  Stores
- * disassembly in str_buff and returns the size of the instruction in bytes.
- */
-unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type);
-
 /* These functions let you read/write/modify the number of cycles left to run
  * while m68k_execute() is running.
  * These are useful if the 68k accesses a memory-mapped port on another device
  * that requires immediate processing by another CPU.
  */
-int m68k_cycles_run(void);              // Number of cycles run so far
-int m68k_cycles_remaining(void);        // Number of cycles left
-void m68k_modify_timeslice(int cycles); // Modify cycles left
-void m68k_end_timeslice(void);          // End timeslice now
+void m68k_modify_timeslice(int cycles);
+void m68k_end_timeslice(void);
 
 #ifdef __cplusplus
 }
diff --git a/waterbox/virtualjaguar/src/m68000/readcpu.c b/waterbox/virtualjaguar/src/m68000/readcpu.c
index 4fcb100926..4fb529dcfb 100644
--- a/waterbox/virtualjaguar/src/m68000/readcpu.c
+++ b/waterbox/virtualjaguar/src/m68000/readcpu.c
@@ -16,9 +16,6 @@
 /* 2008/04/26	[NP]	Handle sz_byte for Areg as a valid srcmode if current instruction is a MOVE	*/
 /*			(e.g. move.b a1,(a0) ($1089)) (fix Blood Money on Superior 65)			*/
 
-
-//const char ReadCpu_fileid[] = "Hatari readcpu.c : " __DATE__ " " __TIME__;
-
 #include <ctype.h>
 #include <string.h>
 
@@ -219,12 +216,6 @@ static void build_insn(int insn)
 	int flaglive = 0, flagdead = 0;
 	id = defs68k[insn];
 
-	/* Note: We treat anything with unknown flags as a jump. That
-	   is overkill, but "the programmer" was lazy quite often, and
-	   *this* programmer can't be bothered to work out what can and
-	   can't trap. Usually, this will be overwritten with the gencomp
-	   based information, anyway. */
-
 	for(j=0; j<5; j++)
 	{
 		switch (id.flaginfo[j].flagset)
@@ -304,14 +295,12 @@ out1:
 		if (bitval[bitj] == 0)
 			bitval[bitj] = 8;
 
-		/* first check whether this one does not match after all */
 		if (bitval[bitz] == 3 || bitval[bitC] == 1)
 			continue;
 
 		if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
 			continue;
 
-		/* bitI and bitC get copied to biti and bitc */
 		if (bitcnt[bitI])
 		{
 			bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
@@ -367,15 +356,12 @@ out1:
 
 		mnemonic[mnp] = 0;
 
-		/* now, we have read the mnemonic and the size */
 		while (opcstr[pos] && isspace((unsigned)opcstr[pos]))
 			pos++;
 
-		/* A goto a day keeps the D******a away. */
 		if (opcstr[pos] == 0)
 			goto endofline;
 
-		/* parse the source address */
 		usesrc = 1;
 		switch (opcstr[pos++])
 		{
@@ -422,7 +408,6 @@ out1:
 
 				if (CPU_EMU_SIZE < 4)
 				{
-					/* Used for branch instructions */
 					srctype = 1;
 					srcgather = 1;
 					srcpos = bitpos[biti];
@@ -434,7 +419,6 @@ out1:
 
 				if (CPU_EMU_SIZE < 3)
 				{
-					/* 1..8 for ADDQ/SUBQ and rotshi insns */
 					srcgather = 1;
 					srctype = 3;
 					srcpos = bitpos[bitj];
@@ -446,7 +430,6 @@ out1:
 
 				if (CPU_EMU_SIZE < 5)
 				{
-					/* 0..15 */
 					srcgather = 1;
 					srctype = 2;
 					srcpos = bitpos[bitJ];
@@ -469,7 +452,6 @@ out1:
 
 				if (CPU_EMU_SIZE < 5)
 				{
-					/* 0..15 */
 					srcgather = 1;
 					srctype = 5;
 					srcpos = bitpos[bitK];
@@ -481,7 +463,6 @@ out1:
 
 				if (CPU_EMU_SIZE < 5)
 				{
-					/* 0..3 */
 					srcgather = 1;
 					srctype = 7;
 					srcpos = bitpos[bitp];
@@ -514,7 +495,6 @@ out1:
 
 				if (opcstr[pos] == '!')
 				{
-					/* exclusion */
 					do
 					{
 						pos++;
@@ -532,7 +512,6 @@ out1:
 				{
 					if (opcstr[pos + 4] == '-')
 					{
-						/* replacement */
 						if (mode_from_str(opcstr + pos) == srcmode)
 							srcmode = mode_from_str(opcstr + pos + 5);
 						else
@@ -542,7 +521,6 @@ out1:
 					}
 					else
 					{
-						/* normal */
 						while(mode_from_str(opcstr + pos) != srcmode)
 						{
 							pos += 4;
@@ -562,7 +540,6 @@ out1:
 				}
 			}
 
-			/* Some addressing modes are invalid as destination */
 			if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
 				goto nomatch;
 
@@ -589,7 +566,6 @@ out1:
 
 				if (opcstr[pos] == '!')
 				{
-					/* exclusion */
 					do
 					{
 						pos++;
@@ -607,7 +583,6 @@ out1:
 				{
 					if (opcstr[pos + 4] == '-')
 					{
-						/* replacement */
 						if (mode_from_str(opcstr + pos) == srcmode)
 							srcmode = mode_from_str(opcstr + pos + 5);
 						else
@@ -617,7 +592,6 @@ out1:
 					}
 					else
 					{
-						/* normal */
 						while(mode_from_str(opcstr+pos) != srcmode)
 						{
 							pos += 4;
@@ -639,7 +613,6 @@ out1:
 		default: abort();
 		}
 
-		/* safety check - might have changed */
 		if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
 			&& srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
 			&& srcmode != Apdi && srcmode != immi)
@@ -647,8 +620,7 @@ out1:
 			srcgather = 0;
 		}
 
-//		if (srcmode == Areg && sz == sz_byte)
-		if (srcmode == Areg && sz == sz_byte && strcmp(mnemonic, "MOVE") != 0 )	// [NP] move.b is valid on 68000
+		if (srcmode == Areg && sz == sz_byte && strcmp(mnemonic, "MOVE") != 0 )
 			goto nomatch;
 
 		if (opcstr[pos] != ',')
@@ -656,7 +628,6 @@ out1:
 
 		pos++;
 
-		/* parse the destination address */
 		usedst = 1;
 
 		switch (opcstr[pos++])
@@ -736,7 +707,6 @@ out1:
 
 				if (opcstr[pos] == '!')
 				{
-					/* exclusion */
 					do
 					{
 						pos++;
@@ -754,7 +724,6 @@ out1:
 				{
 					if (opcstr[pos+4] == '-')
 					{
-						/* replacement */
 						if (mode_from_str(opcstr + pos) == destmode)
 							destmode = mode_from_str(opcstr + pos + 5);
 						else
@@ -764,7 +733,6 @@ out1:
 					}
 					else
 					{
-						/* normal */
 						while(mode_from_str(opcstr + pos) != destmode)
 						{
 							pos += 4;
@@ -784,7 +752,6 @@ out1:
 				}
 			}
 
-			/* Some addressing modes are invalid as destination */
 			if (destmode == imm || destmode == PC16 || destmode == PC8r)
 				goto nomatch;
 
@@ -810,7 +777,6 @@ out1:
 
 				if (opcstr[pos] == '!')
 				{
-					/* exclusion */
 					do
 					{
 						pos++;
@@ -828,7 +794,6 @@ out1:
 				{
 					if (opcstr[pos+4] == '-')
 					{
-						/* replacement */
 						if (mode_from_str(opcstr + pos) == destmode)
 							destmode = mode_from_str(opcstr + pos + 5);
 						else
@@ -838,7 +803,6 @@ out1:
 					}
 					else
 					{
-						/* normal */
 						while (mode_from_str(opcstr + pos) != destmode)
 						{
 							pos += 4;
@@ -860,7 +824,6 @@ out1:
 		default: abort();
 		}
 
-		/* safety check - might have changed */
 		if (destmode != Areg && destmode != Dreg && destmode != Aind
 			&& destmode != Ad16 && destmode != Ad8r && destmode != Aipi
 			&& destmode != Apdi)
@@ -870,13 +833,7 @@ out1:
 
 		if (destmode == Areg && sz == sz_byte)
 			goto nomatch;
-#if 0
-		if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
-			dstgather = 0;
-		}
-#endif
 endofline:
-		/* now, we have a match */
 		if (table68k[opc].mnemo != i_ILLG)
 			fprintf(stderr, "Double match: %x: %s\n", opc, opcstr);
 
@@ -921,22 +878,15 @@ endofline:
 		table68k[opc].stype = srctype;
 		table68k[opc].plev = id.plevel;
 		table68k[opc].clev = id.cpulevel;
-#if 0
-		for (i = 0; i < 5; i++) {
-			table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
-			table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
-		}
-#endif
 		table68k[opc].flagdead = flagdead;
 		table68k[opc].flaglive = flaglive;
 		table68k[opc].isjmp = isjmp;
 
 nomatch:
-	/* FOO! */;
+		;
     }
 }
 
-
 void read_table68k(void)
 {
 	int i;
@@ -952,21 +902,15 @@ void read_table68k(void)
 		build_insn(i);
 }
 
-
 static int mismatch;
 
-
-static void handle_merges (long int opcode)
+static void handle_merges(long int opcode)
 {
 	uint16_t smsk;
 	uint16_t dmsk;
 	int sbitdst, dstend;
 	int srcreg, dstreg;
 
-//0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W  s,d[!Areg]
-//31C3 ->
-//0011 0001 1100 0011 : DDD = 0, ddd = 7, sss = 0, SSS = 3
-
 	if (table68k[opcode].spos == -1)
 	{
 		sbitdst = 1;
@@ -1019,9 +963,6 @@ static void handle_merges (long int opcode)
 			code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
 			code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
 
-			/* Check whether this is in fact the same instruction.
-			* The instructions should never differ, except for the
-			* Bcc.(BW) case. */
 			if (table68k[code].mnemo != table68k[opcode].mnemo
 				|| table68k[code].size != table68k[opcode].size
 				|| table68k[code].suse != table68k[opcode].suse
@@ -1051,52 +992,11 @@ static void handle_merges (long int opcode)
 			if (code != opcode)
 			{
 				table68k[code].handler = opcode;
-
-#if 0
-if (opcode == 0x31C3 || code == 0x31C3)
-{
-	printf("Relocate... ($%04X->$%04X)\n", (uint16_t)opcode, code);
-	printf(" handler: %08X\n", table68k[code].handler);
-	printf("    dreg: %i\n", table68k[code].dreg);
-	printf("    sreg: %i\n", table68k[code].sreg);
-	printf("    dpos: %i\n", table68k[code].dpos);
-	printf("    spos: %i\n", table68k[code].spos);
-	printf("   sduse: %i\n", table68k[code].sduse);
-	printf("flagdead: %i\n", table68k[code].flagdead);
-	printf("flaglive: %i\n", table68k[code].flaglive);
-}
-#endif
-/*
-    long int handler;
-    unsigned char dreg;
-    unsigned char sreg;
-    signed char dpos;
-    signed char spos;
-    unsigned char sduse;
-    int flagdead:8, flaglive:8;
-    unsigned int mnemo:8;
-    unsigned int cc:4;
-    unsigned int plev:2;
-    unsigned int size:2;
-    unsigned int smode:5;
-    unsigned int stype:3;
-    unsigned int dmode:5;
-    unsigned int suse:1;
-    unsigned int duse:1;
-    unsigned int unused1:1;
-    unsigned int clev:3;
-    unsigned int isjmp:1;
-    unsigned int unused2:4;
-*/
 			}
 		}
 	}
 }
 
-
-// What this really does is expand the # of handlers, which is why the
-// opcode has to be passed into the opcode handler...
-// E.g., $F620 maps into $F621-F627 as well; this code does this expansion.
 void do_merges(void)
 {
 	long int opcode;
@@ -1115,9 +1015,7 @@ void do_merges(void)
 	nr_cpuop_funcs = nr;
 }
 
-
 int get_no_mismatches(void)
 {
 	return mismatch;
 }
-
diff --git a/waterbox/virtualjaguar/src/m68000/readcpu.h b/waterbox/virtualjaguar/src/m68000/readcpu.h
index 5fe0d495b6..ff4b37d0df 100644
--- a/waterbox/virtualjaguar/src/m68000/readcpu.h
+++ b/waterbox/virtualjaguar/src/m68000/readcpu.h
@@ -11,7 +11,6 @@
 
 #include "sysdeps.h"
 
-
 ENUMDECL {
   Dreg, Areg, Aind, Aipi, Apdi, Ad16, Ad8r,
   absw, absl, PC16, PC8r, imm, imm0, imm1, imm2, immi, am_unknown, am_illg
@@ -44,7 +43,7 @@ ENUMDECL {
     i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16,
     i_MMUOP,
 
-    MAX_OPCODE_FAMILY				/* should always be last of the list */
+    MAX_OPCODE_FAMILY
 } ENUMNAME (instrmnem);
 
 extern const struct mnemolookup {
diff --git a/waterbox/virtualjaguar/src/m68000/sysdeps.h b/waterbox/virtualjaguar/src/m68000/sysdeps.h
index d927b8dbaa..b99beaa9a1 100644
--- a/waterbox/virtualjaguar/src/m68000/sysdeps.h
+++ b/waterbox/virtualjaguar/src/m68000/sysdeps.h
@@ -27,67 +27,11 @@
 #include <assert.h>
 #include <limits.h>
 
-#ifndef __STDC__
-#error "Your compiler is not ANSI. Get a real one."
-#endif
-
 #include <stdarg.h>
 #include <stdint.h>
 
-
-#if EEXIST == ENOTEMPTY
-#define BROKEN_OS_PROBABLY_AIX
-#endif
-
-#ifdef __NeXT__
-#define S_IRUSR S_IREAD
-#define S_IWUSR S_IWRITE
-#define S_IXUSR S_IEXEC
-#define S_ISDIR(val) (S_IFDIR & val)
-struct utimbuf
-{
-    time_t actime;
-    time_t modtime;
-};
-#endif
-
-
-#if defined(WARPUP)
-#include "devices/timer.h"
-#include "osdep/posixemu.h"
-#define RETSIGTYPE
-#define USE_ZFILE
-#define strcasecmp stricmp
-#define memcpy q_memcpy
-#define memset q_memset
-#define strdup my_strdup
-#define random rand
-#define creat(x,y) open("T:creat",O_CREAT|O_RDWR|O_TRUNC,777)
-extern void * q_memset(void *, int, size_t);
-extern void * q_memcpy(void *, const void *, size_t);
-#endif
-
-
-/* Acorn specific stuff */
-#ifdef ACORN
-
-#define S_IRUSR S_IREAD
-#define S_IWUSR S_IWRITE
-#define S_IXUSR S_IEXEC
-
-#define strcasecmp stricmp
-
-#endif
-
-/* We can only rely on GNU C getting enums right. Mickeysoft VSC++ is known
- * to have problems, and it's likely that other compilers choke too. */
-#ifdef __GNUC__
 #define ENUMDECL typedef enum
 #define ENUMNAME(name) name
-#else
-#define ENUMDECL enum
-#define ENUMNAME(name) ; typedef int name
-#endif
 
 /* When using GNU C, make abort more useful.  */
 #ifdef __GNUC__
@@ -98,11 +42,6 @@ extern void * q_memcpy(void *, const void *, size_t);
 } while (0)
 #endif
 
-
-#ifndef O_BINARY
-#define O_BINARY 0
-#endif
-
 #ifndef STATIC_INLINE
 #define STATIC_INLINE static __inline__
 #endif
diff --git a/waterbox/virtualjaguar/src/m68000/table68k b/waterbox/virtualjaguar/src/m68000/table68k
deleted file mode 100644
index 9605d6e3e2..0000000000
--- a/waterbox/virtualjaguar/src/m68000/table68k
+++ /dev/null
@@ -1,260 +0,0 @@
-% 0: bit 0
-% 1: bit 1
-% c: condition code
-% C: condition codes, except F
-% f: direction
-% i: immediate
-% I: immediate, except 00 and ff
-% j: immediate 1..8
-% J: immediate 0..15
-% k: immediate 0..7
-% K: immediate 0..63
-% p: immediate 0..3 (CINV and CPUSH: cache field)
-% s: source mode
-% S: source reg
-% d: dest mode
-% D: dest reg
-% r: reg
-% z: size
-%
-% Actually, a sssSSS may appear as a destination, and
-% vice versa. The only difference between sssSSS and
-% dddDDD are the valid addressing modes. There is
-% no match for immediate and pc-rel. addressing modes
-% in case of dddDDD.
-%
-% Arp: --> -(Ar)
-% ArP: --> (Ar)+
-% L: (xxx.L)
-%
-% Fields on a line: 
-% 16 chars bitpattern : 
-% CPU level / privilege level :
-%   CPU level 0: 68000
-%             1: 68010
-%             2: 68020
-%   privilege level 0: not privileged
-%                   1: unprivileged only on 68000 (check regs.s)
-%                   2: privileged                 (check regs.s)
-%                   3: privileged if size == word (check regs.s)
-% Flags set by instruction: XNZVC :
-% Flags used by instruction: XNZVC :
-%   - means flag unaffected / unused
-%   0 means flag reset
-%   1 means flag set
-%   ? means programmer was too lazy to check or instruction may trap
-%   + means instruction is conditional branch 
-%     everything else means flag set/used
-%   / means instruction is unconditional branch/call
-%   x means flag is unknown and well-behaved programs shouldn't check it
-% srcaddr status destaddr status :
-%   bitmasks of
-%   1 means fetched
-%   2 means stored
-%   4 means jump offset
-%   8 means jump address
-% instruction
-%
-
-0000 0000 0011 1100:00:XNZVC:XNZVC:10: ORSR.B  #1
-0000 0000 0111 1100:02:?????:?????:10: ORSR.W  #1
-0000 0zz0 11ss sSSS:20:?????:?????:11: CHK2.z  #1,s[!Dreg,Areg,Aipi,Apdi,Immd]
-0000 0000 zzdd dDDD:00:-NZ00:-----:13: OR.z    #z,d[!Areg]
-0000 0010 0011 1100:00:XNZVC:XNZVC:10: ANDSR.B #1
-0000 0010 0111 1100:02:?????:?????:10: ANDSR.W #1
-0000 0010 zzdd dDDD:00:-NZ00:-----:13: AND.z   #z,d[!Areg]
-0000 0100 zzdd dDDD:00:XNZVC:-----:13: SUB.z   #z,d[!Areg]
-0000 0110 zzdd dDDD:00:XNZVC:-----:13: ADD.z   #z,d[!Areg]
-0000 0110 11ss sSSS:20:?????:?????:10: CALLM   s[!Dreg,Areg,Aipi,Apdi,Immd]
-0000 0110 11ss sSSS:20:?????:?????:10: RTM     s[Dreg,Areg]
-0000 1000 00ss sSSS:00:--Z--:-----:11: BTST    #1,s[!Areg]
-0000 1000 01ss sSSS:00:--Z--:-----:13: BCHG    #1,s[!Areg,Immd]
-0000 1000 10ss sSSS:00:--Z--:-----:13: BCLR    #1,s[!Areg,Immd]
-0000 1000 11ss sSSS:00:--Z--:-----:13: BSET    #1,s[!Areg,Immd]
-0000 1010 0011 1100:00:XNZVC:XNZVC:10: EORSR.B #1
-0000 1010 0111 1100:02:?????:?????:10: EORSR.W #1
-0000 1010 zzdd dDDD:00:-NZ00:-----:13: EOR.z   #z,d[!Areg]
-0000 1100 zzss sSSS:00:-NZVC:-----:11: CMP.z   #z,s[!Areg,Immd]
-
-0000 1010 11ss sSSS:20:?????:?????:13: CAS.B   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
-0000 1100 11ss sSSS:20:?????:?????:13: CAS.W   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
-0000 1100 1111 1100:20:?????:?????:10: CAS2.W  #2
-0000 1110 zzss sSSS:22:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]
-0000 1110 11ss sSSS:20:?????:?????:13: CAS.L   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
-0000 1110 1111 1100:20:?????:?????:10: CAS2.L  #2
-
-0000 rrr1 00dd dDDD:00:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
-0000 rrr1 01dd dDDD:00:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
-0000 rrr1 10dd dDDD:00:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
-0000 rrr1 11dd dDDD:00:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
-0000 rrr1 00ss sSSS:00:--Z--:-----:11: BTST    Dr,s[!Areg]
-0000 rrr1 01ss sSSS:00:--Z--:-----:13: BCHG    Dr,s[!Areg,Immd]
-0000 rrr1 10ss sSSS:00:--Z--:-----:13: BCLR    Dr,s[!Areg,Immd]
-0000 rrr1 11ss sSSS:00:--Z--:-----:13: BSET    Dr,s[!Areg,Immd]
-
-0001 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.B  s,d[!Areg]
-0010 DDDd ddss sSSS:00:-----:-----:12: MOVEA.L s,d[Areg]
-0010 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.L  s,d[!Areg]
-0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg]
-0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W  s,d[!Areg]
-
-0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z  d[!Areg]
-0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg]
-0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z   d[!Areg]
-0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg]
-0100 0100 zzdd dDDD:00:XNZVC:-----:30: NEG.z   d[!Areg]
-0100 0100 11ss sSSS:00:XNZVC:-----:10: MV2SR.B s[!Areg]
-0100 0110 zzdd dDDD:00:-NZ00:-----:30: NOT.z   d[!Areg]
-0100 0110 11ss sSSS:02:?????:?????:10: MV2SR.W s[!Areg]
-0100 1000 0000 1rrr:20:-----:-----:31: LINK.L  Ar,#2
-0100 1000 00dd dDDD:00:X?Z?C:X-Z--:30: NBCD.B  d[!Areg]
-0100 1000 0100 1kkk:20:?????:?????:10: BKPT    #k
-0100 1000 01ss sSSS:00:-NZ00:-----:30: SWAP.W  s[Dreg]         
-0100 1000 01ss sSSS:00:-----:-----:00: PEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
-0100 1000 10dd dDDD:00:-NZ00:-----:30: EXT.W   d[Dreg]         
-0100 1000 10dd dDDD:00:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
-0100 1000 11dd dDDD:00:-NZ00:-----:30: EXT.L   d[Dreg]         
-0100 1000 11dd dDDD:00:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
-0100 1001 11dd dDDD:20:-NZ00:-----:30: EXT.B   d[Dreg]         
-0100 1010 zzss sSSS:00:-NZ00:-----:10: TST.z   s
-0100 1010 11dd dDDD:00:?????:?????:30: TAS.B   d[!Areg]
-0100 1010 1111 1100:00:?????:?????:00: ILLEGAL
-0100 1100 00ss sSSS:20:-NZVC:-----:13: MULL.L  #1,s[!Areg]
-0100 1100 01ss sSSS:20:?????:?????:13: DIVL.L  #1,s[!Areg]
-0100 1100 10ss sSSS:00:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
-0100 1100 11ss sSSS:00:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
-0100 1110 0100 JJJJ:00:-----:XNZVC:10: TRAP    #J
-0100 1110 0101 0rrr:00:-----:-----:31: LINK.W  Ar,#1
-0100 1110 0101 1rrr:00:-----:-----:30: UNLK.L  Ar
-0100 1110 0110 0rrr:02:-----:-----:10: MVR2USP.L Ar
-0100 1110 0110 1rrr:02:-----:-----:20: MVUSP2R.L Ar
-0100 1110 0111 0000:02:-----:-----:00: RESET
-0100 1110 0111 0001:00:-----:-----:00: NOP
-0100 1110 0111 0010:02:XNZVC:-----:10: STOP    #1
-0100 1110 0111 0011:02:XNZVC:-----:00: RTE
-0100 1110 0111 0100:00:?????:?????:10: RTD     #1
-0100 1110 0111 0101:00:-----:-----:00: RTS
-0100 1110 0111 0110:00:-----:XNZVC:00: TRAPV
-0100 1110 0111 0111:00:XNZVC:-----:00: RTR
-0100 1110 0111 1010:12:?????:?????:10: MOVEC2  #1
-0100 1110 0111 1011:12:?????:?????:10: MOVE2C  #1
-0100 1110 10ss sSSS:00://///://///:80: JSR.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
-0100 rrr1 00ss sSSS:20:?????:?????:11: CHK.L   s[!Areg],Dr
-0100 rrr1 10ss sSSS:00:?????:?????:11: CHK.W   s[!Areg],Dr
-0100 1110 11ss sSSS:00://///://///:80: JMP.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
-0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
-
-0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W  #j,d[Areg]
-0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L  #j,d[Areg]
-0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z   #j,d[!Areg]
-0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W  #j,d[Areg]
-0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L  #j,d[Areg]
-0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z   #j,d[!Areg]
-0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W  Dr,#1
-0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B   d[!Areg]
-0101 cccc 1111 1010:20:?????:?????:10: TRAPcc  #1
-0101 cccc 1111 1011:20:?????:?????:10: TRAPcc  #2
-0101 cccc 1111 1100:20:?????:?????:00: TRAPcc
-
-% Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
-% instruction exceptions when compiling a 68000 only emulation, which isn't
-% what we want either.
-0110 0001 0000 0000:00://///://///:40: BSR.W   #1
-0110 0001 IIII IIII:00://///://///:40: BSR.B   #i
-0110 0001 1111 1111:00://///://///:40: BSR.L   #2
-0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W   #1
-0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B   #i
-0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L   #2
-
-0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L  #i,Dr
-
-1000 rrr0 zzss sSSS:00:-NZ00:-----:13: OR.z    s[!Areg],Dr
-1000 rrr0 11ss sSSS:00:?????:?????:13: DIVU.W  s[!Areg],Dr
-1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B  d[Dreg],Dr      
-1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B  d[Areg-Apdi],Arp      
-1000 rrr1 zzdd dDDD:00:-NZ00:-----:13: OR.z    Dr,d[!Areg,Dreg]
-1000 rrr1 01dd dDDD:20:?????:?????:12: PACK    d[Dreg],Dr      
-1000 rrr1 01dd dDDD:20:?????:?????:12: PACK    d[Areg-Apdi],Arp      
-1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK    d[Dreg],Dr      
-1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK    d[Areg-Apdi],Arp      
-1000 rrr1 11ss sSSS:00:?????:?????:13: DIVS.W  s[!Areg],Dr
-
-1001 rrr0 zzss sSSS:00:XNZVC:-----:13: SUB.z   s,Dr
-1001 rrr0 11ss sSSS:00:-----:-----:13: SUBA.W  s,Ar
-1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z  d[Dreg],Dr      
-1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z  d[Areg-Apdi],Arp      
-1001 rrr1 zzdd dDDD:00:XNZVC:-----:13: SUB.z   Dr,d[!Areg,Dreg]
-1001 rrr1 11ss sSSS:00:-----:-----:13: SUBA.L  s,Ar
-
-1011 rrr0 zzss sSSS:00:-NZVC:-----:11: CMP.z   s,Dr
-1011 rrr0 11ss sSSS:00:-NZVC:-----:11: CMPA.W  s,Ar
-1011 rrr1 11ss sSSS:00:-NZVC:-----:11: CMPA.L  s,Ar
-1011 rrr1 zzdd dDDD:00:-NZVC:-----:11: CMPM.z  d[Areg-Aipi],ArP
-1011 rrr1 zzdd dDDD:00:-NZ00:-----:13: EOR.z   Dr,d[!Areg]
-
-1100 rrr0 zzss sSSS:00:-NZ00:-----:13: AND.z   s[!Areg],Dr
-1100 rrr0 11ss sSSS:00:-NZ00:-----:13: MULU.W  s[!Areg],Dr
-1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B  d[Dreg],Dr      
-1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B  d[Areg-Apdi],Arp      
-1100 rrr1 zzdd dDDD:00:-NZ00:-----:13: AND.z   Dr,d[!Areg,Dreg]
-1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L   Dr,d[Dreg]      
-1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L   Ar,d[Areg]            
-1100 rrr1 10dd dDDD:00:-----:-----:33: EXG.L   Dr,d[Areg]      
-1100 rrr1 11ss sSSS:00:-NZ00:-----:13: MULS.W  s[!Areg],Dr
-
-1101 rrr0 zzss sSSS:00:XNZVC:-----:13: ADD.z   s,Dr
-1101 rrr0 11ss sSSS:00:-----:-----:13: ADDA.W  s,Ar
-1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z  d[Dreg],Dr      
-1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z  d[Areg-Apdi],Arp      
-1101 rrr1 zzdd dDDD:00:XNZVC:-----:13: ADD.z   Dr,d[!Areg,Dreg]
-1101 rrr1 11ss sSSS:00:-----:-----:13: ADDA.L  s,Ar
-
-1110 jjjf zz00 0RRR:00:XNZVC:-----:13: ASf.z   #j,DR
-1110 jjjf zz00 1RRR:00:XNZ0C:-----:13: LSf.z   #j,DR
-1110 jjjf zz01 0RRR:00:XNZ0C:X----:13: ROXf.z  #j,DR
-1110 jjjf zz01 1RRR:00:-NZ0C:-----:13: ROf.z   #j,DR
-1110 rrrf zz10 0RRR:00:XNZVC:X----:13: ASf.z   Dr,DR
-1110 rrrf zz10 1RRR:00:XNZ0C:X----:13: LSf.z   Dr,DR
-1110 rrrf zz11 0RRR:00:XNZ0C:X----:13: ROXf.z  Dr,DR
-1110 rrrf zz11 1RRR:00:-NZ0C:-----:13: ROf.z   Dr,DR
-1110 000f 11dd dDDD:00:XNZVC:-----:13: ASfW.W  d[!Dreg,Areg]
-1110 001f 11dd dDDD:00:XNZ0C:-----:13: LSfW.W  d[!Dreg,Areg]
-1110 010f 11dd dDDD:00:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg]
-1110 011f 11dd dDDD:00:-NZ0C:-----:13: ROfW.W  d[!Dreg,Areg]
-
-1110 1000 11ss sSSS:20:?????:?????:11: BFTST   #1,s[!Areg,Apdi,Aipi,Immd]
-1110 1001 11ss sSSS:20:?????:?????:11: BFEXTU  #1,s[!Areg,Apdi,Aipi,Immd]
-1110 1010 11ss sSSS:20:?????:?????:13: BFCHG   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
-1110 1011 11ss sSSS:20:?????:?????:11: BFEXTS  #1,s[!Areg,Apdi,Aipi,Immd]
-1110 1100 11ss sSSS:20:?????:?????:13: BFCLR   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
-1110 1101 11ss sSSS:20:?????:?????:11: BFFFO   #1,s[!Areg,Apdi,Aipi,Immd]
-1110 1110 11ss sSSS:20:?????:?????:13: BFSET   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
-1110 1111 11ss sSSS:20:?????:?????:13: BFINS   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
-
-% floating point co processor
-1111 0010 00ss sSSS:30:?????:?????:11: FPP      #1,s
-1111 0010 01ss sSSS:30:?????:?????:11: FDBcc    #1,s[Areg-Dreg]
-1111 0010 01ss sSSS:30:?????:?????:11: FScc     #1,s[!Areg,Immd,PC8r,PC16]
-1111 0010 0111 1010:30:?????:?????:10: FTRAPcc  #1
-1111 0010 0111 1011:30:?????:?????:10: FTRAPcc  #2
-1111 0010 0111 1100:30:?????:?????:00: FTRAPcc
-1111 0010 10KK KKKK:30:?????:?????:11: FBcc     #K,#1
-1111 0010 11KK KKKK:30:?????:?????:11: FBcc     #K,#2
-1111 0011 00ss sSSS:32:?????:?????:20: FSAVE    s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
-1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
-
-1111 0101 iiii iSSS:40:?????:?????:11: MMUOP    #i,s
-
-% 68040 instructions
-1111 0100 pp00 1rrr:42:-----:-----:02: CINVL    #p,Ar
-1111 0100 pp01 0rrr:42:-----:-----:02: CINVP    #p,Ar
-1111 0100 pp01 1rrr:42:-----:-----:00: CINVA    #p
-1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL   #p,Ar
-1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP   #p,Ar
-1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA   #p
-% destination register number is encoded in the following word
-1111 0110 0010 0rrr:40:-----:-----:12: MOVE16   ArP,AxP
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Dreg-Aipi],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Areg-Aipi]
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Aind],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Aipi-Aind]