update psx core to 0.9.38.7
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zeromus
parent
29767ba522
commit
5cfc1dae2a
Binary file not shown.
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@ -81,3 +81,11 @@
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[OK] psx/memcard : change to debug output
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0.9.38.4 -> 0.9.38.6
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[OK] psx/gpu & gpu_sprite : Fixed GPU emulation timing bugs that caused graphical glitches in "Mr. Driller G".
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0.9.38.5 -> 0.9.38.7
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[OK] psx/cpu : Revisions to exception handling
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[OK] psx/cpu : Many revisions and cleanups to branch and exception handling in opcode implementations
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[OK] psx/dis : Just some basic disassembly changes
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[OK] psx/gte : Cleanup
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[OK] psx/psx : Cleanup
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[OK] psx/timer : Major functional changes
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[NO] psx/timer : Added loadstate sanity checks
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File diff suppressed because it is too large
Load Diff
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@ -123,13 +123,13 @@ class PS_CPU
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CP0REG_BDA = 5, // Data load/store breakpoint address.
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CP0REG_TAR = 6, // Target address(???)
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CP0REG_DCIC = 7, // Cache control
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CP0REG_BADVA = 8,
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CP0REG_BDAM = 9, // Data load/store address mask.
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CP0REG_BPCM = 11, // PC breakpoint address mask.
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CP0REG_SR = 12,
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CP0REG_CAUSE = 13,
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CP0REG_EPC = 14,
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CP0REG_PRID = 15, // Product ID
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CP0REG_ERREG = 16
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CP0REG_PRID = 15 // Product ID
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};
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struct
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@ -145,9 +145,9 @@ class PS_CPU
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uint32 BPC; // RW
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uint32 Unused04;
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uint32 BDA; // RW
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uint32 TAR;
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uint32 TAR; // R
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uint32 DCIC; // RW
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uint32 Unused08;
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uint32 BADVA; // R
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uint32 BDAM; // R/W
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uint32 Unused0A;
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uint32 BPCM; // R/W
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@ -155,7 +155,6 @@ class PS_CPU
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uint32 CAUSE; // R/W(partial)
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uint32 EPC; // R
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uint32 PRID; // R
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uint32 ERREG; // ?(may not exist, test)
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};
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};
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} CP0;
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@ -209,7 +208,7 @@ class PS_CPU
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EXCEPTION_OV = 12 // Arithmetic overflow
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};
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uint32 Exception(uint32 code, uint32 PC, const uint32 NPM) MDFN_WARN_UNUSED_RESULT;
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uint32 Exception(uint32 code, uint32 PC, const uint32 NP, const uint32 NPM, const uint32 instr) MDFN_WARN_UNUSED_RESULT;
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template<bool DebugMode, bool BIOSPrintMode, bool ILHMode> pscpu_timestamp_t RunReal(pscpu_timestamp_t timestamp_in) NO_INLINE;
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@ -128,13 +128,15 @@ struct OpEntry
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#define MK_OP(mnemonic, format, op, func, extra_mask) { MASK_OP | (op ? 0 : MASK_FUNC) | extra_mask, ((unsigned)op << 26) | func, mnemonic, format }
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#define MK_OP_REGIMM(mnemonic, regop) { MASK_OP | MASK_RT, (0x01U << 26) | (regop << 16), mnemonic, "s, p" }
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#define MK_OP_REGIMM(mnemonic, regop_mask, regop) { MASK_OP | (regop_mask << 16), (0x01U << 26) | (regop << 16), mnemonic, "s, p" }
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#define MK_COPZ(z) { MASK_OP | (0x1U << 25), (0x1U << 25) | ((0x10U | z) << 26), "cop" #z, "F" }
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#define MK_COP0_FUNC(mnemonic, func) { MASK_OP | (0x1U << 25) | MASK_FUNC, (0x10U << 26) | (0x1U << 25) | func, mnemonic, "" }
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#define MK_COPZ_XFER(z, mnemonic, format, xf) { MASK_OP | (0x1FU << 21), ((0x10U | z) << 26) | (xf << 21), mnemonic, format }
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#define MK_COPZ_BCzx(z, x) { MASK_OP | (0x1BU << 21) | (0x01 << 16), ((0x10U | z) << 26) | (0x08 << 21) | (x << 16), (x ? "bc" #z "t" : "bc" #z "f"), "p" }
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#define MK_COPZ_BC(z) MK_COPZ_BCzx(z, 0), MK_COPZ_BCzx(z, 1)
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#define MK_GTE(mnemonic, format, func) { MASK_OP | (0x1U << 25) | MASK_FUNC, (0x1U << 25) | (0x12U << 26) | func, mnemonic, format }
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@ -180,10 +182,12 @@ static OpEntry ops[] =
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MK_OP("slt", "d, s, t", 0, 42, 0),
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MK_OP("sltu", "d, s, t", 0, 43, 0),
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MK_OP_REGIMM("bgez", 0x01),
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MK_OP_REGIMM("bgezal", 0x11),
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MK_OP_REGIMM("bltz", 0x00),
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MK_OP_REGIMM("bltzal", 0x10),
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// keep *al before the non-linking versions, due to mask setup.
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MK_OP_REGIMM("bgezal", 0x1F, 0x11),
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MK_OP_REGIMM("bltzal", 0x1F, 0x10),
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MK_OP_REGIMM("bgez", 0x01, 0x01),
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MK_OP_REGIMM("bltz", 0x00, 0x00),
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MK_OP("j", "P", 2, 0, 0),
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@ -225,6 +229,11 @@ static OpEntry ops[] =
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MK_COPZ_XFER(2, "ctc2", "t, G", 0x06),
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MK_COPZ_XFER(3, "ctc3", "t, ?", 0x06),
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MK_COPZ_BC(0),
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MK_COPZ_BC(1),
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MK_COPZ_BC(2),
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MK_COPZ_BC(3),
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// COP0 stuff here
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MK_COP0_FUNC("rfe", 0x10),
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@ -316,8 +325,8 @@ EW_EXPORT s32 shock_Util_DisassembleMIPS(u32 PC, u32 instr, void* outbuf, s32 bu
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static const char *cop0_names[32] =
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{
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"CPR0", "CPR1", "CPR2", "BPC", "CPR4", "BDA", "TAR", "DCIC", "CPR8", "BDAM", "CPR10", "BPCM", "SR", "CAUSE", "EPC", "PRID",
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"ERREG", "CPR17", "CPR18", "CPR19", "CPR20", "CPR21", "CPR22", "CPR23", "CPR24", "CPR25", "CPR26", "CPR27", "CPR28", "CPR29", "CPR30", "CPR31"
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"CPR0", "CPR1", "CPR2", "BPC", "CPR4", "BDA", "TAR", "DCIC", "BADVA", "BDAM", "CPR10", "BPCM", "SR", "CAUSE", "EPC", "PRID",
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"CPR16", "CPR17", "CPR18", "CPR19", "CPR20", "CPR21", "CPR22", "CPR23", "CPR24", "CPR25", "CPR26", "CPR27", "CPR28", "CPR29", "CPR30", "CPR31"
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};
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static const char *gte_cr_names[32] =
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@ -796,22 +796,6 @@ static INLINE int32 Lm_G(unsigned int which, int32 value)
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// limit to 4096, not 4095
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static INLINE int32 Lm_H(int32 value)
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{
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#if 0
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if(FLAGS & (1 << 15))
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{
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value = 0;
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FLAGS |= 1 << 12;
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return value;
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}
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if(FLAGS & (1 << 16))
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{
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value = 4096;
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FLAGS |= 1 << 12;
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return value;
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}
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#endif
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if(value < 0)
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{
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value = 0;
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@ -272,7 +272,6 @@ static void RebaseTS(const pscpu_timestamp_t timestamp)
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void PSX_SetEventNT(const int type, const pscpu_timestamp_t next_timestamp)
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{
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assert(type > PSX_EVENT__SYNFIRST && type < PSX_EVENT__SYNLAST);
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event_list_entry *e = &events[type];
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if(next_timestamp < e->event_time)
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@ -31,9 +31,9 @@
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For timer2:
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0x1 = timer stopped(TODO: confirm on real system)
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Target mode enabled 0x008
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IRQ enable 0x010
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--?Affects 0x400 status flag?-- 0x020
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Target match counter reset enable 0x008
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Target match IRQ enable 0x010
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Overflow IRQ enable 0x020
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IRQ evaluation auto-reset 0x040
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--unknown-- 0x080
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Clock selection 0x100
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@ -43,11 +43,10 @@
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Reset to 0 on writes to the mode/status register.
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Status flags:
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Unknown flag 0x0400
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Current IRQ line status? 0x0400
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Compare flag 0x0800
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Cleared on mode/status read.
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Set when: //ever Counter == 0(proooobably, need to investigate lower 3 bits in relation to this).
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Set repeatedly while counter == target.
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Overflow/Carry flag 0x1000
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Cleared on mode/status read.
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@ -58,20 +57,17 @@
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Cleared on writes to the mode/status register, on writes to the count register, and apparently automatically when the counter
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increments if (Mode & 0x40) [Note: If target mode is enabled, and target is 0, IRQ done flag won't be automatically reset]
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There seems to be a brief period(edge condition?) where, if count to target is enabled, you can (sometimes?) read the target value in the count
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register before it's reset to 0. I doubt any games rely on this, but who knows. Maybe a PSX equivalent of the PC Engine "Battle Royale"? ;)
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There seems to be a brief period(edge condition?) where, if target match reset mode is enabled, you can (sometimes?) read the target value in the count
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register before it's reset to 0. Currently not emulated; I doubt any games rely on this, but who knows. Maybe a PSX equivalent
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of the PC Engine "Battle Royale"? ;)
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When the counter == 0, the compare flag is set. An IRQ will be generated if (Mode & 0x10), and the hidden IRQ done flag will be set.
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*/
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A timer is somewhat unreliable when target match reset mode is enabled and the 33MHz clock is used. Average 2.4 counts seem to be
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skipped for that timer every target match reset, but oddly subtracting only 2 from the desired target match value seems to effectively
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negate the loss...wonder if my test program is faulty in some way. Currently not emulated.
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/*
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Dec. 26, 2011 Note
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Due to problems I've had with my GPU timing test program, timer2 appears to be unreliable(clocks are skipped?) when target mode is enabled and the full
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33MHz clock is used(rather than 33MHz / 8). TODO: Investigate further and confirm(or not).
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Jan. 15, 2013 Note:
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Counters using GPU clock sources(hretrace,dot clock) reportedly will with a low probability return wrong count values on an actual PS1, so keep this in mind
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when writing test programs(IE keep reading the count value until two consecutive reads return the same value).
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Counters using GPU clock sources(hretrace,dot clock) reportedly will with a low probability return wrong count values on an actual PS1,
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so keep this in mind when writing test programs(IE keep reading the count value until two consecutive reads return the same value).
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Currently not emulated.
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*/
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/*
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@ -86,10 +82,10 @@ namespace MDFN_IEN_PSX
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struct Timer
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{
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uint32 Mode;
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int32 Counter; // Only 16-bit, but 32-bit here for detecting counting past target.
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int32 Target;
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uint32 Counter; // Only 16-bit, but 32-bit here for detecting counting past target.
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uint32 Target;
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int32 Div8Counter;
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uint32 Div8Counter;
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bool IRQDone;
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int32 DoZeCounting;
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@ -100,17 +96,13 @@ static bool hretrace;
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static Timer Timers[3];
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static pscpu_timestamp_t lastts;
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static int32 CalcNextEvent(int32 next_event)
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static uint32 CalcNextEvent(void)
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{
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for(int i = 0; i < 3; i++)
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uint32 next_event = 1024; //
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for(unsigned i = 0; i < 3; i++)
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{
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int32 target;
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int32 count_delta;
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if((i == 0 || i == 1) && (Timers[i].Mode & 0x100)) // If clocked by GPU, abort for this timer(will result in poor granularity for pixel-clock-derived timer IRQs, but whatever).
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continue;
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if(!(Timers[i].Mode & 0x10)) // If IRQ is disabled, abort for this timer.
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if(!(Timers[i].Mode & 0x30)) // If IRQ is disabled, abort for this timer(don't look at IRQDone for this test, or things will break since its resetting is deferred!).
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continue;
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if((Timers[i].Mode & 0x8) && (Timers[i].Counter == 0) && (Timers[i].Target == 0) && !Timers[i].IRQDone)
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@ -119,17 +111,10 @@ static int32 CalcNextEvent(int32 next_event)
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continue;
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}
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target = ((Timers[i].Mode & 0x8) && (Timers[i].Counter < Timers[i].Target)) ? Timers[i].Target : 0x10000;
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count_delta = target - Timers[i].Counter;
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if(count_delta <= 0)
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{
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PSX_DBG(PSX_DBG_ERROR, "timer %d count_delta <= 0!!! %d %d\n", i, target, Timers[i].Counter);
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//
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//
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if((i == 0 || i == 1) && (Timers[i].Mode & 0x100)) // If clocked by GPU, abort for this timer(will result in poor granularity for pixel-clock-derived timer IRQs, but whatever).
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continue;
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}
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{
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int32 tmp_clocks;
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if(Timers[i].DoZeCounting <= 0)
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continue;
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@ -137,30 +122,83 @@ static int32 CalcNextEvent(int32 next_event)
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if((i == 0x2) && (Timers[i].Mode & 0x1))
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continue;
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//
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//
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//
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const uint32 target = ((Timers[i].Mode & 0x18) && (Timers[i].Counter < Timers[i].Target)) ? Timers[i].Target : 0x10000;
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const uint32 count_delta = target - Timers[i].Counter;
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uint32 tmp_clocks;
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if((i == 0x2) && (Timers[i].Mode & 0x200))
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{
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assert(Timers[i].Div8Counter >= 0 && Timers[i].Div8Counter < 8);
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tmp_clocks = ((count_delta - 1) * 8) + (8 - Timers[i].Div8Counter);
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}
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tmp_clocks = (count_delta * 8) - Timers[i].Div8Counter;
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else
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tmp_clocks = count_delta;
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assert(tmp_clocks > 0);
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if(next_event > tmp_clocks)
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next_event = tmp_clocks;
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}
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}
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return(next_event);
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}
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static bool TimerMatch(unsigned i)
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{
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bool irq_exact = false;
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Timers[i].Mode |= 0x0800;
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if(Timers[i].Mode & 0x008)
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Timers[i].Counter %= std::max<uint32>(1, Timers[i].Target);
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if((Timers[i].Mode & 0x10) && !Timers[i].IRQDone)
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{
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if(Timers[i].Counter == 0 || Timers[i].Counter == Timers[i].Target)
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irq_exact = true;
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#if 1
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{
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const uint16 lateness = (Timers[i].Mode & 0x008) ? Timers[i].Counter : (Timers[i].Counter - Timers[i].Target);
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if(lateness > ((i == 1 && (Timers[i].Mode & 0x100)) ? 0 : 3))
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PSX_DBG(PSX_DBG_WARNING, "[TIMER] Timer %d match IRQ trigger late: %u\n", i, lateness);
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}
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#endif
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Timers[i].IRQDone = true;
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IRQ_Assert(IRQ_TIMER_0 + i, true);
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IRQ_Assert(IRQ_TIMER_0 + i, false);
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}
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return irq_exact;
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}
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static bool TimerOverflow(unsigned i)
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{
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bool irq_exact = false;
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Timers[i].Mode |= 0x1000;
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Timers[i].Counter &= 0xFFFF;
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if((Timers[i].Mode & 0x20) && !Timers[i].IRQDone)
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{
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if(Timers[i].Counter == 0)
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irq_exact = true;
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#if 1
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if(Timers[i].Counter > ((i == 1 && (Timers[i].Mode & 0x100)) ? 0 : 3))
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PSX_DBG(PSX_DBG_WARNING, "[TIMER] Timer %d overflow IRQ trigger late: %u\n", i, Timers[i].Counter);
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#endif
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Timers[i].IRQDone = true;
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IRQ_Assert(IRQ_TIMER_0 + i, true);
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IRQ_Assert(IRQ_TIMER_0 + i, false);
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}
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return irq_exact;
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}
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static void ClockTimer(int i, uint32 clocks)
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{
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int32 before = Timers[i].Counter;
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int32 target = 0x10000;
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bool zero_tm = false;
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if(Timers[i].DoZeCounting <= 0)
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clocks = 0;
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@ -170,7 +208,7 @@ static void ClockTimer(int i, uint32 clocks)
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Timers[i].Div8Counter += clocks;
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d8_clocks = Timers[i].Div8Counter >> 3;
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Timers[i].Div8Counter -= d8_clocks << 3;
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Timers[i].Div8Counter &= 0x7;
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if(Timers[i].Mode & 0x200) // Divide by 8, at least for timer 0x2
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clocks = d8_clocks;
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@ -179,57 +217,35 @@ static void ClockTimer(int i, uint32 clocks)
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clocks = 0;
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}
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if(Timers[i].Mode & 0x008)
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target = Timers[i].Target;
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if((Timers[i].Mode & 0x008) && Timers[i].Target == 0 && Timers[i].Counter == 0)
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TimerMatch(i);
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else if(clocks)
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{
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uint32 before = Timers[i].Counter;
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if(target == 0 && Timers[i].Counter == 0)
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zero_tm = true;
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else
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Timers[i].Counter += clocks;
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if(clocks && (Timers[i].Mode & 0x40))
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if(Timers[i].Mode & 0x40)
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Timers[i].IRQDone = false;
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if((before < target && Timers[i].Counter >= target) || zero_tm || Timers[i].Counter > 0xFFFF)
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{
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#if 1
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if(Timers[i].Mode & 0x10)
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{
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if((Timers[i].Counter - target) > 3)
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PSX_WARNING("Timer %d IRQ trigger error: %d", i, Timers[i].Counter - target);
|
||||
}
|
||||
bool irq_exact = false;
|
||||
|
||||
#endif
|
||||
//
|
||||
// Target match handling
|
||||
//
|
||||
if((before < Timers[i].Target && Timers[i].Counter >= Timers[i].Target) || (Timers[i].Counter >= Timers[i].Target + 0x10000))
|
||||
irq_exact |= TimerMatch(i);
|
||||
|
||||
//
|
||||
// Overflow handling
|
||||
//
|
||||
if(Timers[i].Counter >= 0x10000)
|
||||
irq_exact |= TimerOverflow(i);
|
||||
|
||||
Timers[i].Mode |= 0x0800;
|
||||
|
||||
if(Timers[i].Counter > 0xFFFF)
|
||||
{
|
||||
Timers[i].Counter -= 0x10000;
|
||||
|
||||
if(target == 0x10000)
|
||||
Timers[i].Mode |= 0x1000;
|
||||
|
||||
if(!target)
|
||||
Timers[i].Counter = 0;
|
||||
}
|
||||
|
||||
if(target)
|
||||
Timers[i].Counter -= (Timers[i].Counter / target) * target;
|
||||
|
||||
if((Timers[i].Mode & 0x10) && !Timers[i].IRQDone)
|
||||
{
|
||||
Timers[i].IRQDone = true;
|
||||
|
||||
IRQ_Assert(IRQ_TIMER_0 + i, true);
|
||||
IRQ_Assert(IRQ_TIMER_0 + i, false);
|
||||
}
|
||||
|
||||
if(Timers[i].Counter && (Timers[i].Mode & 0x40))
|
||||
//
|
||||
if((Timers[i].Mode & 0x40) && !irq_exact)
|
||||
Timers[i].IRQDone = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void TIMER_SetVBlank(bool status)
|
||||
|
|
@ -242,13 +258,21 @@ void TIMER_SetVBlank(bool status)
|
|||
|
||||
case 0x3:
|
||||
if(vblank && !status)
|
||||
{
|
||||
Timers[1].Counter = 0;
|
||||
if(Timers[1].Counter == Timers[1].Target)
|
||||
TimerMatch(1);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x5:
|
||||
Timers[1].DoZeCounting = status;
|
||||
if(vblank && !status)
|
||||
{
|
||||
Timers[1].Counter = 0;
|
||||
if(Timers[1].Counter == Timers[1].Target)
|
||||
TimerMatch(1);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x7:
|
||||
|
|
@ -272,7 +296,12 @@ void TIMER_SetHRetrace(bool status)
|
|||
if(hretrace && !status)
|
||||
{
|
||||
if((Timers[0].Mode & 0x7) == 0x3)
|
||||
{
|
||||
Timers[0].Counter = 0;
|
||||
|
||||
if(Timers[0].Counter == Timers[0].Target)
|
||||
TimerMatch(0);
|
||||
}
|
||||
}
|
||||
|
||||
hretrace = status;
|
||||
|
|
@ -306,7 +335,7 @@ pscpu_timestamp_t TIMER_Update(const pscpu_timestamp_t timestamp)
|
|||
|
||||
lastts = timestamp;
|
||||
|
||||
return(timestamp + CalcNextEvent(1024));
|
||||
return(timestamp + CalcNextEvent());
|
||||
}
|
||||
|
||||
static void CalcCountingStart(unsigned which)
|
||||
|
|
@ -349,40 +378,16 @@ void TIMER_Write(const pscpu_timestamp_t timestamp, uint32 A, uint16 V)
|
|||
if(which >= 3)
|
||||
return;
|
||||
|
||||
// TODO: See if the "Timers[which].Counter" part of the IRQ if() statements below is what a real PSX does.
|
||||
switch(A & 0xC)
|
||||
{
|
||||
case 0x0: Timers[which].IRQDone = false;
|
||||
#if 1
|
||||
if(Timers[which].Counter && (V & 0xFFFF) == 0)
|
||||
{
|
||||
Timers[which].Mode |= 0x0800;
|
||||
if((Timers[which].Mode & 0x10) && !Timers[which].IRQDone)
|
||||
{
|
||||
Timers[which].IRQDone = true;
|
||||
IRQ_Assert(IRQ_TIMER_0 + which, true);
|
||||
IRQ_Assert(IRQ_TIMER_0 + which, false);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Timers[which].Counter = V & 0xFFFF;
|
||||
break;
|
||||
|
||||
case 0x4: Timers[which].Mode = (V & 0x3FF) | (Timers[which].Mode & 0x1C00);
|
||||
Timers[which].IRQDone = false;
|
||||
#if 1
|
||||
if(Timers[which].Counter)
|
||||
{
|
||||
Timers[which].Mode |= 0x0800;
|
||||
if((Timers[which].Mode & 0x10) && !Timers[which].IRQDone)
|
||||
{
|
||||
Timers[which].IRQDone = true;
|
||||
IRQ_Assert(IRQ_TIMER_0 + which, true);
|
||||
IRQ_Assert(IRQ_TIMER_0 + which, false);
|
||||
}
|
||||
}
|
||||
Timers[which].Counter = 0;
|
||||
#endif
|
||||
|
||||
CalcCountingStart(which); // Call after setting .Mode
|
||||
break;
|
||||
|
||||
|
|
@ -393,9 +398,10 @@ void TIMER_Write(const pscpu_timestamp_t timestamp, uint32 A, uint16 V)
|
|||
break;
|
||||
}
|
||||
|
||||
// TIMER_Update(timestamp);
|
||||
if(Timers[which].Counter == Timers[which].Target)
|
||||
TimerMatch(which);
|
||||
|
||||
PSX_SetEventNT(PSX_EVENT_TIMER, timestamp + CalcNextEvent(1024));
|
||||
PSX_SetEventNT(PSX_EVENT_TIMER, timestamp + CalcNextEvent());
|
||||
}
|
||||
|
||||
uint16 TIMER_Read(const pscpu_timestamp_t timestamp, uint32 A)
|
||||
|
|
@ -418,7 +424,9 @@ uint16 TIMER_Read(const pscpu_timestamp_t timestamp, uint32 A)
|
|||
break;
|
||||
|
||||
case 0x4: ret = Timers[which].Mode;
|
||||
Timers[which].Mode &= ~0x1800;
|
||||
Timers[which].Mode &= ~0x1000;
|
||||
if(Timers[which].Counter != Timers[which].Target)
|
||||
Timers[which].Mode &= ~0x0800;
|
||||
break;
|
||||
|
||||
case 0x8: ret = Timers[which].Target;
|
||||
|
|
@ -496,6 +504,9 @@ void TIMER_SetRegister(unsigned int which, uint32 value)
|
|||
break;
|
||||
}
|
||||
|
||||
if (Timers[tw].Counter == Timers[tw].Target)
|
||||
TimerMatch(tw);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue