fix ares64 tracer, pull in some more commits from upstream

This commit is contained in:
CasualPokePlayer 2022-05-27 21:14:04 -07:00
parent 3fe168ad0f
commit 59d011334f
5 changed files with 15 additions and 15 deletions

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@ -28,9 +28,9 @@ struct Instruction : Tracer {
}
auto address(u64 address) -> bool {
address &= (1ull << _addressBits) - 1; //mask upper bits of address
address &= (u128(1) << _addressBits) - 1; //mask upper bits of address
_address = address;
address >>= _addressMask; //clip unneeded alignment bits (to reduce _masks size)
/*address >>= _addressMask; //clip unneeded alignment bits (to reduce _masks size)
if(_mask && updateMasks()) {
if(_masks[address >> 3] & 1 << (address & 7)) return false; //do not trace twice
@ -48,7 +48,7 @@ struct Instruction : Tracer {
_history[index] = _history[index + 1];
}
_history.last() = _address;
}
}*/
return true;
}
@ -56,11 +56,11 @@ struct Instruction : Tracer {
//mark an already-executed address as not executed yet for trace masking.
//call when writing to executable RAM to support self-modifying code.
auto invalidate(u64 address) -> void {
if(unlikely(_mask && updateMasks())) {
address &= (1ull << _addressBits) - 1;
/*if(unlikely(_mask && updateMasks())) {
address &= (u128(1) << _addressBits) - 1;
address >>= _addressMask;
_masks[address >> 3] &= ~(1 << (address & 7));
}
}*/
}
auto notify(const string& instruction, const string& context, const string& extra = {}) -> void {
@ -72,7 +72,6 @@ struct Instruction : Tracer {
);
_omitted = 0;
}
string output{
_component, " ",
hex(_address, _addressBits + 3 >> 2), " ",

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@ -314,11 +314,12 @@ auto RSP::SFV(cr128& vt, cr32& rs, s8 imm) -> void {
template<u8 e>
auto RSP::SHV(cr128& vt, cr32& rs, s8 imm) -> void {
auto address = rs.u32 + imm * 16;
auto index = address & 7;
address &= ~7;
for(u32 offset = 0; offset < 8; offset++) {
auto byte = e + offset * 2;
auto value = vt.byte(byte + 0 & 15) << 1 | vt.byte(byte + 1 & 15) >> 7;
dmem.write<Byte>(address, value);
address += 2;
dmem.write<Byte>(address + (index + offset * 2 & 15), value);
}
}
@ -411,8 +412,8 @@ auto RSP::SWV(cr128& vt, cr32& rs, s8 imm) -> void {
auto address = rs.u32 + imm * 16;
auto start = e;
auto end = start + 16;
auto base = address & 15;
address &= ~15;
auto base = address & 7;
address &= ~7;
for(u32 offset = start; offset < end; offset++) {
dmem.write<Byte>(address + (base++ & 15), vt.byte(offset & 15));
}

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@ -1,14 +1,14 @@
auto RSP::Recompiler::pool() -> Pool* {
if(context) return context;
u32 hashcode = 0;
nall::Hash::CRC32 hashcode;
for(u32 offset : range(4096)) {
hashcode = (hashcode << 5) + hashcode + self.imem.read<Byte>(offset);
hashcode.input(self.imem.read<Byte>(offset));
}
PoolHashPair pair;
pair.pool = (Pool*)allocator.acquire();
pair.hashcode = hashcode;
pair.hashcode = hashcode.value();
if(auto result = pools.find(pair)) {
return context = result->pool;
}

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@ -90,7 +90,7 @@ auto VI::main() -> void {
#if defined(VULKAN)
}
#endif
#endif
#endif
refreshed = true;
screen->frame();