Revert ""cheat" around the lack of pipeline emulation, delaying bankswitches/imask clears (note: branching resets the pipeline)"
This reverts commit d5a47490ff.
This commit is contained in:
CasualPokePlayer
parent
d5a47490ff
commit
5382d4d345
Binary file not shown.
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@ -186,7 +186,6 @@ static uint32_t dsp_opcode_first_parameter;
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static uint32_t dsp_opcode_second_parameter;
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static bool IMASKCleared;
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static uint32_t dsp_pipeline_countdown;
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static uint32_t dsp_inhibit_interrupt;
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#define DSP_RUNNING (dsp_control & 0x01)
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@ -246,8 +245,6 @@ static void DSPUpdateRegisterBanks(void)
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dsp_reg = dsp_reg_bank_1, dsp_alternate_reg = dsp_reg_bank_0;
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else
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dsp_reg = dsp_reg_bank_0, dsp_alternate_reg = dsp_reg_bank_1;
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dsp_pipeline_countdown = 0;
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}
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//
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@ -455,23 +452,14 @@ void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who)
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case 0x00:
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{
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IMASKCleared |= (dsp_flags & IMASK) && !(data & IMASK);
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dsp_flags = data & (~IMASK);
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dsp_flag_z = dsp_flags & 0x01;
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dsp_flag_c = (dsp_flags >> 1) & 0x01;
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dsp_flag_n = (dsp_flags >> 2) & 0x01;
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DSPUpdateRegisterBanks();
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dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3);
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dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1);
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if (who == DSP)
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{
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if (dsp_pipeline_countdown == 0)
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{
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dsp_pipeline_countdown = 2;
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}
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}
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else
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{
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DSPUpdateRegisterBanks();
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}
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break;
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}
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case 0x04:
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@ -577,8 +565,6 @@ void DSPReset(void)
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dsp_flag_z = dsp_flag_n = dsp_flag_c = 0;
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IMASKCleared = false;
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dsp_inhibit_interrupt = 0;
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dsp_pipeline_countdown = 0;
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for(uint32_t i=0; i<8192; i+=4)
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*((uint32_t *)(&dsp_ram_8[i])) = rand();
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@ -593,17 +579,10 @@ void DSPExec(int32_t cycles)
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{
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MAYBE_CALLBACK(DSPTraceCallback, dsp_pc, dsp_reg);
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if (dsp_pipeline_countdown == 0)
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if (IMASKCleared && !dsp_inhibit_interrupt)
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{
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if (IMASKCleared && !dsp_inhibit_interrupt)
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{
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DSPHandleIRQs();
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IMASKCleared = false;
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}
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}
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else if (--dsp_pipeline_countdown == 0)
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{
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DSPUpdateRegisterBanks();
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DSPHandleIRQs();
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IMASKCleared = false;
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}
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dsp_inhibit_interrupt = 0;
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@ -178,7 +178,6 @@ static uint32_t gpu_opcode_second_parameter;
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static bool IMASKCleared;
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static uint32_t gpu_inhibit_interrupt;
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static uint32_t gpu_pipeline_countdown;
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#define GPU_RUNNING (gpu_control & 0x01)
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@ -223,8 +222,6 @@ static void GPUUpdateRegisterBanks(void)
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gpu_reg = gpu_reg_bank_1, gpu_alternate_reg = gpu_reg_bank_0;
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else
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gpu_reg = gpu_reg_bank_0, gpu_alternate_reg = gpu_reg_bank_1;
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gpu_pipeline_countdown = 0;
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}
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static void GPUHandleIRQs(void)
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@ -463,18 +460,8 @@ void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who)
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gpu_flag_z = gpu_flags & ZERO_FLAG;
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gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1;
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gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2;
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GPUUpdateRegisterBanks();
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gpu_control &= ~((gpu_flags & CINT04FLAGS) >> 3);
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if (who == GPU)
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{
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if (gpu_pipeline_countdown == 0)
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{
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gpu_pipeline_countdown = 2;
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}
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}
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else
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{
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GPUUpdateRegisterBanks();
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}
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break;
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}
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case 0x04:
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@ -575,8 +562,7 @@ void GPUReset(void)
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gpu_flag_z = gpu_flag_n = gpu_flag_c = 0;
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IMASKCleared = false;
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gpu_inhibit_interrupt = 0;
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gpu_pipeline_countdown = 0;
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memset(gpu_ram_8, 0xFF, 0x1000);
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for(uint32_t i=0; i<4096; i+=4)
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*((uint32_t *)(&gpu_ram_8[i])) = rand();
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@ -597,19 +583,6 @@ void GPUExec(int32_t cycles)
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IMASKCleared = false;
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}
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if (gpu_pipeline_countdown == 0)
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{
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if (IMASKCleared && !gpu_inhibit_interrupt)
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{
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GPUHandleIRQs();
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IMASKCleared = false;
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}
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}
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else if (--gpu_pipeline_countdown == 0)
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{
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GPUUpdateRegisterBanks();
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}
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gpu_inhibit_interrupt = 0;
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uint16_t opcode = GPUReadWord(gpu_pc, GPU);
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uint32_t index = opcode >> 10;
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@ -22,7 +22,6 @@
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#define RISCReadWord(x, y) GPUReadWord(x, y)
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#define RISCReadLong(x, y) GPUReadLong(x, y)
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#define RISCWriteLong(x, y, z) GPUWriteLong(x, y, z)
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#define RISCUpdateRegisterBanks GPUUpdateRegisterBanks()
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#elif RISC == 2
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#define RISC_OPCODE(op) static void dsp_opcode_##op(void)
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#define risc_inhibit_interrupt dsp_inhibit_interrupt
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@ -45,7 +44,6 @@
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#define RISCReadWord(x, y) DSPReadWord(x, y)
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#define RISCReadLong(x, y) DSPReadLong(x, y)
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#define RISCWriteLong(x, y, z) DSPWriteLong(x, y, z)
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#define RISCUpdateRegisterBanks DSPUpdateRegisterBanks()
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#else
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#error RISC improperly defined
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#endif
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@ -92,7 +90,6 @@ RISC_OPCODE(jump)
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risc_inhibit_interrupt = 1;
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RISCExec(1);
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risc_pc = delayed_pc;
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RISCUpdateRegisterBanks;
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}
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}
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@ -107,7 +104,6 @@ RISC_OPCODE(jr)
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risc_inhibit_interrupt = 1;
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RISCExec(1);
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risc_pc = delayed_pc;
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RISCUpdateRegisterBanks;
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}
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}
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