NES: add proper WRAM to Taito X1-005. should fix saveram on Kyonshiizu 2, Kyuukyoku Harikiri Stadium, Minelvaton Saga: Ragon no Fukkatsu, Mirai Shinwa Jarvas, Taito Grand Prix: Eikou e no License.
also fold mapper 207 into mapper 80 for simplicity
This commit is contained in:
goyuken
parent
5be10ff8d5
commit
508a60c737
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@ -297,7 +297,6 @@
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper200.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper201.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper203.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper207.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper218.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper222.cs" />
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<Compile Include="Consoles\Nintendo\NES\Boards\Mapper225.cs" />
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@ -1,189 +0,0 @@
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using BizHawk.Common;
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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/*
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* Here are Disch's original notes:
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========================
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= Mapper 207 =
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========================
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Example Game:
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--------------------------
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Fudou Myouou Den
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Notes:
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---------------------------
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Regs appear at $7EFx, I'm unsure whether or not PRG-RAM can exist at $6000-7FFF
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Registers:
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---------------------------
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$7EF0: [MCCC CCCC]
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M = Mirroring 0
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C = CHR Reg 0
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$7EF1: [MCCC CCCC]
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M = Mirroring 1
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C = CHR Reg 1
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$7EF2-7EF5: CHR Regs 2-5
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$7EFA,7EFB: PRG Reg 0 (8k @ $8000)
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$7EFC,7EFD: PRG Reg 1 (8k @ $A000)
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$7EFE,7EFF: PRG Reg 2 (8k @ $C000)
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CHR Setup:
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---------------------------
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$0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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+---------------+---------------+-------+-------+-------+-------+
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| <$7EF0> | <$7EF1> | $7EF2 | $7EF3 | $7EF4 | $7EF5 |
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+---------------+---------------+-------+-------+-------+-------+
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PRG Setup:
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---------------------------
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$8000 $A000 $C000 $E000
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+-------+-------+-------+-------+
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| $7EFA | $7EFC | $7EFE | { -1} |
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+-------+-------+-------+-------+
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Mirroring:
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---------------------------
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[ $7EF0 ][ $7EF0 ]
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[ $7EF1 ][ $7EF1 ]
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Mirroring bit of appropriate reg selects NTA or NTB
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*/
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public sealed class Mapper207 : NES.NESBoardBase
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{
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int prg_bank_mask, chr_bank_mask;
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ByteBuffer chr_regs_1k = new ByteBuffer(8);
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ByteBuffer prg_regs_8k = new ByteBuffer(4);
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bool mirror0 = false;
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bool mirror1 = false;
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("chr_regs_1k", ref chr_regs_1k);
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ser.Sync("prg_regs_8k", ref prg_regs_8k);
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ser.Sync("mirror0", ref mirror0);
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ser.Sync("mirror1", ref mirror1);
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DoMirroring();
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}
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public override void Dispose()
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{
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base.Dispose();
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chr_regs_1k.Dispose();
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prg_regs_8k.Dispose();
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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//configure
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switch (Cart.board_type)
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{
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case "MAPPER207":
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break;
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case "TAITO-X1-005":
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if (Cart.mapper == 207)
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{
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break;
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}
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return false;
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default:
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return false;
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}
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SetMirrorType(EMirrorType.Horizontal);
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chr_bank_mask = Cart.chr_size / 1 - 1;
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prg_bank_mask = Cart.prg_size / 8 - 1;
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prg_regs_8k[3] = 0xFF;
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return true;
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}
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public override void WriteWRAM(int addr, byte value)
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{
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switch (addr)
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{
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case 0x1EF0:
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mirror0 = value.Bit(7);
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int val1 = value & 0x7F;
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chr_regs_1k[0] = (byte)(val1/2*2);
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chr_regs_1k[1] = (byte)(val1/2*2+1);
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break;
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case 0x1EF1:
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mirror1 = value.Bit(7);
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int val2 = value & 0x7F;
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chr_regs_1k[2] = (byte)(val2/2*2);
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chr_regs_1k[3] = (byte)(val2/2*2+1);
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break;
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case 0x1EF2:
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chr_regs_1k[4] = value;
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break;
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case 0x1EF3:
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chr_regs_1k[5] = value;
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break;
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case 0x1EF4:
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chr_regs_1k[6] = value;
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break;
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case 0X1EF5:
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chr_regs_1k[7] = value;
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break;
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case 0x1EFA: //PRG Reg 0
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case 0x1EFB:
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prg_regs_8k[0] = value;
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break;
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case 0x1EFC: //PRG Reg 1
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case 0x1EFD:
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prg_regs_8k[1] = value;
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break;
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case 0x1EFE: //PRG Reg 2
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case 0x1EFF:
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prg_regs_8k[2] = value;
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break;
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}
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DoMirroring();
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}
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private void DoMirroring()
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{
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int m0 = mirror0?1:0;
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int m1 = mirror1?1:0;
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SetMirroring(m0, m0, m1, m1);
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}
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public override byte ReadPRG(int addr)
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{
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int bank_8k = addr >> 13;
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int ofs = addr & ((1 << 13) - 1);
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bank_8k = prg_regs_8k[bank_8k];
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bank_8k &= prg_bank_mask;
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addr = (bank_8k << 13) | ofs;
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return ROM[addr];
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = chr_regs_1k[bank_1k];
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bank_1k &= chr_bank_mask;
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addr = (bank_1k << 10) | ofs;
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return VROM[addr];
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}
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else return base.ReadPPU(addr);
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}
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}
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}
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@ -2,55 +2,58 @@
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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//AKA mapper 80
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//Minelvaton Saga
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//Taito Grand Prix - Eikou heno License
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//Kyuukyoku Harikiri Stadium
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// Mapper 80. TLSROM variant is Mapper 207
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/*
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* Registers:
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---------------------------
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* Bakushou!! Jinsei Gekijou 2 爆笑！！人生劇場２
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* Fudou Myouou Den 不動明王伝 <=== TLSROM VARIANT!!!
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* Kyonshiizu 2 キョンシーズ２
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* Kyuukyoku Harikiri Stadium 究極ハリキリスタジアム
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* Minelvaton Saga: Ragon no Fukkatsu ミネルバトンサーガ ラゴンの復活
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* Mirai Shinwa Jarvas 未来神話ジャーヴァス
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* Taito Grand Prix: Eikou e no License タイトーグランプリ 栄光へのライセンス
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* Yamamura Misa Suspense: Kyouto Ryuu no Tera Satsujin Jiken 山村美紗サスペンス 京都龍の寺殺人事件
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*/
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$7EF0-7EF5: CHR Regs
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$7EF6: [.... ...M] Mirroring
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0 = Horz
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1 = Vert
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$7EFA,7EFB: PRG Reg 0 (8k @ $8000)
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$7EFC,7EFD: PRG Reg 1 (8k @ $A000)
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$7EFE,7EFF: PRG Reg 2 (8k @ $C000)
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CHR Setup:
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---------------------------
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$0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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+---------------+---------------+-------+-------+-------+-------+
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| <$7EF0> | <$7EF1> | $7EF2 | $7EF3 | $7EF4 | $7EF5 |
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+---------------+---------------+-------+-------+-------+-------+
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PRG Setup:
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---------------------------
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$8000 $A000 $C000 $E000
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+-------+-------+-------+-------+
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| $7EFA | $7EFC | $7EFE | { -1} |
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+-------+-------+-------+-------+
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*/
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/*
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* Registers should be masked with $ff7f.
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*
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* $7e70: 2k chr @ PPU $0000 (lsb ignored)
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* $7e71: 2k chr @ PPU $0800 (lsb ignored)
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* $7e72: 1k chr @ PPU $1000
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* $7e73: 1k chr @ PPU $1400
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* $7e74: 1k chr @ PPU $1800
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* $7e75: 1k chr @ PPU $1c00
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* $7e76,$7e77: mirroring. bit0: 0 = H, 1 = V
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* $7e78,$7e79: prg wram protect. must be $a3 to enable read+write
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* $7e7a,$7e7b: 8k prg @ cpu $8000
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* $7e7c,$7e7d: 8k prg @ cpu $a000
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* $7e7e,$7e7f: 8k prg @ cpu $c000
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*
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* $7f00:$7f7f: 128 bytes internal prg ram, mirrored on CPU A7
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*
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* 8k prg @ cpu $e000 is fixed to last 8k of rom.
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* in TLSROM-like mode (mapper 207), mirroring reg is ignored,
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* and top bit of CHR regs (normally CHRROM A17) is used as CIRAM A10
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*
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*/
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public sealed class TAITO_X1_005 : NES.NESBoardBase
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{
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// config
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int prg_bank_mask, chr_bank_mask;
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bool tlsrewire = false;
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// state
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ByteBuffer chr_regs_1k = new ByteBuffer(8);
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ByteBuffer prg_regs_8k = new ByteBuffer(4);
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bool wramenable = false;
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("chr_regs_1k", ref chr_regs_1k);
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ser.Sync("prg_regs_8k", ref prg_regs_8k);
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ser.Sync("wramenable", ref wramenable);
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}
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public override void Dispose()
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@ -67,11 +70,12 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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{
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case "MAPPER080":
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break;
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case "MAPPER207":
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tlsrewire = true;
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break;
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case "TAITO-X1-005":
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if (Cart.mapper == 207)
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{
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return false;
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}
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if (Cart.pcb == "アシユラー")
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tlsrewire = true;
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break;
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default:
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return false;
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@ -80,58 +84,91 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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SetMirrorType(EMirrorType.Vertical);
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chr_bank_mask = Cart.chr_size / 1 - 1;
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prg_bank_mask = Cart.prg_size / 8 - 1;
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// the chip has 128 bytes of WRAM built into it, which we have to instantiate ourselves
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Cart.wram_size = 0;
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prg_regs_8k[3] = 0xFF;
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return true;
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}
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public override void PostConfigure()
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{
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WRAM = new byte[128];
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base.PostConfigure();
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}
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public override void WriteWRAM(int addr, byte value)
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{
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addr &= 0x1f7f;
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if (addr >= 0x1f00)
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{
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if (wramenable)
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WRAM[addr & 0x7f] = value;
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return;
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}
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switch (addr)
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{
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case 0x1EF6:
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case 0x1E76:
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case 0x1E77:
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if (value.Bit(0))
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SetMirrorType(EMirrorType.Vertical);
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else
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SetMirrorType(EMirrorType.Horizontal);
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break;
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case 0x1EF0:
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chr_regs_1k[0] = (byte)(value/2*2);
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chr_regs_1k[1] = (byte)(value/2*2+1);
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case 0x1E70:
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chr_regs_1k[0] = (byte)(value & ~1);
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chr_regs_1k[1] = (byte)(value | 1);
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break;
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case 0x1EF1:
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chr_regs_1k[2] = (byte)(value/2*2);
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chr_regs_1k[3] = (byte)(value/2*2+1);
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case 0x1E71:
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chr_regs_1k[2] = (byte)(value & ~1);
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chr_regs_1k[3] = (byte)(value | 1);
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break;
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case 0x1EF2:
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case 0x1E72:
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chr_regs_1k[4] = value;
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break;
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case 0x1EF3:
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case 0x1E73:
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chr_regs_1k[5] = value;
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break;
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case 0x1EF4:
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case 0x1E74:
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chr_regs_1k[6] = value;
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break;
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case 0X1EF5:
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case 0X1E75:
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chr_regs_1k[7] = value;
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break;
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case 0x1EFA: //PRG Reg 0
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case 0x1EFB:
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case 0x1E78:
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case 0x1E79:
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wramenable = value == 0xa3;
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break;
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case 0x1E7A: //PRG Reg 0
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case 0x1E7B:
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prg_regs_8k[0] = value;
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break;
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case 0x1EFC: //PRG Reg 1
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case 0x1EFD:
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case 0x1E7C: //PRG Reg 1
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case 0x1E7D:
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prg_regs_8k[1] = value;
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break;
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case 0x1EFE: //PRG Reg 2
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case 0x1EFF:
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case 0x1E7E: //PRG Reg 2
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case 0x1E7F:
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prg_regs_8k[2] = value;
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break;
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}
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}
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public override byte ReadWRAM(int addr)
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{
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if (addr >= 0x1f00 && wramenable)
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return WRAM[addr & 0x7f];
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else
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return NES.DB;
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}
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public override byte ReadPRG(int addr)
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{
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int bank_8k = addr >> 13;
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@ -153,24 +190,39 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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addr = (bank_1k << 10) | ofs;
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return VROM[addr];
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}
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else return base.ReadPPU(addr);
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else if (tlsrewire)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = chr_regs_1k[bank_1k & 7]; // ignore PPU A13
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bank_1k >>= 7; // top bit is used
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addr = (bank_1k << 10) | ofs;
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return NES.CIRAM[addr];
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}
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else
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{
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return base.ReadPPU(addr);
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}
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}
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public override void WritePPU(int addr, byte value)
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{
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if (addr >= 0x2000)
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{
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if (tlsrewire)
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{
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int bank_1k = addr >> 10;
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int ofs = addr & ((1 << 10) - 1);
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bank_1k = chr_regs_1k[bank_1k & 7]; // ignore PPU A13
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bank_1k >>= 7; // top bit is used
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addr = (bank_1k << 10) | ofs;
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NES.CIRAM[addr] = value;
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}
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else
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{
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base.WritePPU(addr, value);
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}
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}
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}
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}
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}
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/*
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CHR Setup:
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||||
---------------------------
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$0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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+---------------+---------------+-------+-------+-------+-------+
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CHR Mode 0: | <$7EF0> | <$7EF1> | $7EF2 | $7EF3 | $7EF4 | $7EF5 |
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+---------------+---------------+---------------+---------------+
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CHR Mode 1: | $7EF2 | $7EF3 | $7EF4 | $7EF5 | <$7EF0> | <$7EF1> |
|
||||
+-------+-------+-------+-------+---------------+---------------+
|
||||
*/
|
||||
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Reference in New Issue