diff --git a/Assets/dll/virtualjaguar.wbx.zst b/Assets/dll/virtualjaguar.wbx.zst new file mode 100644 index 0000000000..b2de670a4b Binary files /dev/null and b/Assets/dll/virtualjaguar.wbx.zst differ diff --git a/src/BizHawk.Client.Common/RomLoader.cs b/src/BizHawk.Client.Common/RomLoader.cs index d22b4eff2e..0864b02ffc 100644 --- a/src/BizHawk.Client.Common/RomLoader.cs +++ b/src/BizHawk.Client.Common/RomLoader.cs @@ -788,6 +788,8 @@ namespace BizHawk.Client.Common public static readonly IReadOnlyCollection INTV = new[] { "int", "bin", "rom" }; + public static readonly IReadOnlyCollection Jaguar = new[] { "j64", "jag" }; + public static readonly IReadOnlyCollection Lynx = new[] { "lnx" }; public static readonly IReadOnlyCollection MSX = new[] { "cas", "dsk", "mx1", "rom" }; @@ -832,6 +834,7 @@ namespace BizHawk.Client.Common .Concat(GBA) .Concat(GEN) .Concat(INTV) + .Concat(Jaguar) .Concat(Lynx) .Concat(MSX) .Concat(N64) @@ -870,6 +873,7 @@ namespace BizHawk.Client.Common new FilesystemFilter("PC Engine", RomFileExtensions.PCE.Concat(new[] { "cue", "ccd", "mds" }).ToList(), addArchiveExts: true), new FilesystemFilter("Atari 2600", RomFileExtensions.A26, devBuildExtraExts: new[] { "bin" }, addArchiveExts: true), new FilesystemFilter("Atari 7800", RomFileExtensions.A78, devBuildExtraExts: new[] { "bin" }, addArchiveExts: true), + new FilesystemFilter("Atari Jaguar", RomFileExtensions.Jaguar, addArchiveExts: true), new FilesystemFilter("Atari Lynx", RomFileExtensions.Lynx, addArchiveExts: true), new FilesystemFilter("ColecoVision", RomFileExtensions.Coleco, addArchiveExts: true), new FilesystemFilter("IntelliVision", RomFileExtensions.INTV, addArchiveExts: true), diff --git a/src/BizHawk.Client.Common/config/PathEntryCollection.cs b/src/BizHawk.Client.Common/config/PathEntryCollection.cs index b3fd7db916..8d1448763f 100644 --- a/src/BizHawk.Client.Common/config/PathEntryCollection.cs +++ b/src/BizHawk.Client.Common/config/PathEntryCollection.cs @@ -44,6 +44,7 @@ namespace BizHawk.Client.Common [VSystemID.Raw.N64] = "N64", [VSystemID.Raw.SAT] = "Saturn", [VSystemID.Raw.WSWAN] = "WonderSwan", + [VSystemID.Raw.JAG] = "Jaguar", [VSystemID.Raw.Lynx] = "Lynx", [VSystemID.Raw.AppleII] = "Apple II", [VSystemID.Raw.Libretro] = "Libretro", @@ -226,6 +227,8 @@ namespace BizHawk.Client.Common PalettesEntryFor(VSystemID.Raw.INTV), }, + CommonEntriesFor(VSystemID.Raw.JAG, basePath: Path.Combine(".", "Jaguar")), + new[] { BaseEntryFor(VSystemID.Raw.Libretro, Path.Combine(".", "Libretro")), // It doesn't make much sense to have a ROM dir for libretro, but a lot of stuff is built around the assumption of a ROM dir existing diff --git a/src/BizHawk.Client.Common/movie/bk2/Bk2MnemonicLookup.cs b/src/BizHawk.Client.Common/movie/bk2/Bk2MnemonicLookup.cs index 859e010362..dc5cd6d32b 100644 --- a/src/BizHawk.Client.Common/movie/bk2/Bk2MnemonicLookup.cs +++ b/src/BizHawk.Client.Common/movie/bk2/Bk2MnemonicLookup.cs @@ -391,6 +391,11 @@ namespace BizHawk.Client.Common ["Toggle Link Shift"] = 'F', ["Toggle Link Spacing"] = 'C', }, + [VSystemID.Raw.JAG] = new() + { + ["Option"] = 'O', + ["Asterisk"] = '*', + }, [VSystemID.Raw.Lynx] = new() { ["Option 1"] = '1', diff --git a/src/BizHawk.Client.EmuHawk/MainForm.Events.cs b/src/BizHawk.Client.EmuHawk/MainForm.Events.cs index b630fe7337..08ebb519ca 100644 --- a/src/BizHawk.Client.EmuHawk/MainForm.Events.cs +++ b/src/BizHawk.Client.EmuHawk/MainForm.Events.cs @@ -18,6 +18,7 @@ using BizHawk.Emulation.Cores; using BizHawk.Emulation.Cores.Arcades.MAME; using BizHawk.Emulation.Cores.Atari.A7800Hawk; using BizHawk.Emulation.Cores.Atari.Atari2600; +using BizHawk.Emulation.Cores.Atari.Jaguar; using BizHawk.Emulation.Cores.Atari.Lynx; using BizHawk.Emulation.Cores.Calculators.Emu83; using BizHawk.Emulation.Cores.Calculators.TI83; @@ -3042,6 +3043,9 @@ namespace BizHawk.Client.EmuHawk // Virtual Boyee items.Add(CreateCoreSubmenu(VSystemCategory.Consoles, CoreNames.VirtualBoyee, CreateGenericNymaCoreConfigItem(CoreNames.VirtualBoyee, VirtualBoyee.CachedSettingsInfo))); + // Virtual Jaguar + items.Add(CreateCoreSubmenu(VSystemCategory.Consoles, CoreNames.VirtualJaguar, CreateGenericCoreConfigItem(CoreNames.VirtualJaguar))); + // ZXHawk items.Add(CreateCoreSubmenu( VSystemCategory.PCs, diff --git a/src/BizHawk.Client.EmuHawk/config/FirmwaresConfig.cs b/src/BizHawk.Client.EmuHawk/config/FirmwaresConfig.cs index cf00427e4f..365faee181 100644 --- a/src/BizHawk.Client.EmuHawk/config/FirmwaresConfig.cs +++ b/src/BizHawk.Client.EmuHawk/config/FirmwaresConfig.cs @@ -76,6 +76,7 @@ namespace BizHawk.Client.EmuHawk ["GEN"] = "Genesis", ["SMS"] = "Sega Master System", ["PSX"] = "PlayStation", + ["JAG"] = "Jaguar", ["Lynx"] = "Lynx", ["AppleII"] = "Apple II", ["O2"] = "Odyssey 2 / Philips Videopac+ G7400", diff --git a/src/BizHawk.Emulation.Common/Database/Database.cs b/src/BizHawk.Emulation.Common/Database/Database.cs index e35a8d347c..3258fda3fe 100644 --- a/src/BizHawk.Emulation.Common/Database/Database.cs +++ b/src/BizHawk.Emulation.Common/Database/Database.cs @@ -358,6 +358,11 @@ namespace BizHawk.Emulation.Common game.System = VSystemID.Raw.WSWAN; break; + case ".J64": + case ".JAG": + game.System = VSystemID.Raw.JAG; + break; + case ".LNX": game.System = VSystemID.Raw.Lynx; break; diff --git a/src/BizHawk.Emulation.Common/Database/FirmwareDatabase.cs b/src/BizHawk.Emulation.Common/Database/FirmwareDatabase.cs index a4419e8b37..a7cbb7db63 100644 --- a/src/BizHawk.Emulation.Common/Database/FirmwareDatabase.cs +++ b/src/BizHawk.Emulation.Common/Database/FirmwareDatabase.cs @@ -143,6 +143,12 @@ namespace BizHawk.Emulation.Common FirmwareAndOption(SHA1Checksum.Dummy, 131072, "NDS", "firmwarei", "DSi_Firmware.bin", "DSi Firmware"); FirmwareAndOption(SHA1Checksum.Dummy, 251658304, "NDS", "nand", "DSi_Nand.bin", "DSi NAND"); + Firmware("JAG", "Bios", "Bios"); + var kseries = File("F8991B0C385F4E5002FA2A7E2F5E61E8C5213356", 131072, "JAG_bios_k.bin", "Bios (K Series)"); + var mseries = File("AF643900FEA84234E08B616A6D27F03F0A61DB96", 131072, "JAG_bios_m.bin", "Bios (M Series)"); + Option("JAG", "Bios", in kseries); + Option("JAG", "Bios", in mseries); + FirmwareAndOption("E4ED47FAE31693E016B081C6BDA48DA5B70D7CCB", 512, "Lynx", "Boot", "LYNX_boot.img", "Boot Rom"); FirmwareAndOption("5A65B922B562CB1F57DAB51B73151283F0E20C7A", 8192, "INTV", "EROM", "INTV_EROM.bin", "Executive Rom"); diff --git a/src/BizHawk.Emulation.Common/Extensions.cs b/src/BizHawk.Emulation.Common/Extensions.cs index 5a34237cbb..f84e899b28 100644 --- a/src/BizHawk.Emulation.Common/Extensions.cs +++ b/src/BizHawk.Emulation.Common/Extensions.cs @@ -35,6 +35,7 @@ namespace BizHawk.Emulation.Common [VSystemID.Raw.GG] = "Game Gear", [VSystemID.Raw.GGL] = "Game Gear Link", [VSystemID.Raw.INTV] = "Intellivision", + [VSystemID.Raw.JAG] = "Jaguar", [VSystemID.Raw.Libretro] = "Libretro", [VSystemID.Raw.Lynx] = "Lynx", [VSystemID.Raw.MAME] = "MAME", diff --git a/src/BizHawk.Emulation.Common/SystemLookup.cs b/src/BizHawk.Emulation.Common/SystemLookup.cs index 096b916003..48ca9d862d 100644 --- a/src/BizHawk.Emulation.Common/SystemLookup.cs +++ b/src/BizHawk.Emulation.Common/SystemLookup.cs @@ -9,6 +9,7 @@ namespace BizHawk.Emulation.Common { new(VSystemID.Raw.A26, "Atari 2600"), new(VSystemID.Raw.A78, "Atari 7800"), + new(VSystemID.Raw.JAG, "Atari Jaguar"), new(VSystemID.Raw.Lynx, "Atari Lynx"), new(VSystemID.Raw.NES, "NES"), new(VSystemID.Raw.SNES, "Super NES"), diff --git a/src/BizHawk.Emulation.Common/VSystemID.cs b/src/BizHawk.Emulation.Common/VSystemID.cs index 7ae233eeac..3c4ab0a503 100644 --- a/src/BizHawk.Emulation.Common/VSystemID.cs +++ b/src/BizHawk.Emulation.Common/VSystemID.cs @@ -33,6 +33,7 @@ namespace BizHawk.Emulation.Common public const string GG = "GG"; public const string GGL = "GGL"; public const string INTV = "INTV"; + public const string JAG = "JAG"; public const string Libretro = "Libretro"; public const string Lynx = "Lynx"; public const string MAME = "MAME"; diff --git a/src/BizHawk.Emulation.Cores/BizHawk.Emulation.Cores.csproj b/src/BizHawk.Emulation.Cores/BizHawk.Emulation.Cores.csproj index b383cab16d..bb6356be48 100644 --- a/src/BizHawk.Emulation.Cores/BizHawk.Emulation.Cores.csproj +++ b/src/BizHawk.Emulation.Cores/BizHawk.Emulation.Cores.csproj @@ -35,6 +35,7 @@ + diff --git a/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/LibVirtualJaguar.cs b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/LibVirtualJaguar.cs new file mode 100644 index 0000000000..fc1975d770 --- /dev/null +++ b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/LibVirtualJaguar.cs @@ -0,0 +1,65 @@ +using System; +using System.Runtime.InteropServices; + +using BizHawk.BizInvoke; +using BizHawk.Emulation.Cores.Waterbox; + +namespace BizHawk.Emulation.Cores.Atari.Jaguar +{ + public abstract class LibVirtualJaguar : LibWaterboxCore + { + [StructLayout(LayoutKind.Sequential)] + public struct Settings + { + public bool NTSC; + public bool UseBIOS; + public bool UseFastBlitter; + } + + [StructLayout(LayoutKind.Sequential)] + public new class FrameInfo : LibWaterboxCore.FrameInfo + { + public Buttons Player1; + public Buttons Player2; + public bool Reset; + } + + [BizImport(CC)] + public abstract bool Init(ref Settings s, IntPtr bios, IntPtr rom, int romsize); + + [BizImport(CC)] + public abstract bool SaveRamIsDirty(); + + [BizImport(CC)] + public abstract void GetSaveRam(byte[] dst); + + [BizImport(CC)] + public abstract void PutSaveRam(byte[] src); + + [Flags] + public enum Buttons : uint + { + Up = 1 << 0, + Down = 1 << 1, + Left = 1 << 2, + Right = 1 << 3, + Asterisk = 1 << 4, + _7 = 1 << 5, + _4 = 1 << 6, + _1 = 1 << 7, + _0 = 1 << 8, + _8 = 1 << 9, + _5 = 1 << 10, + _2 = 1 << 11, + Pound = 1 << 12, + _9 = 1 << 13, + _6 = 1 << 14, + _3 = 1 << 15, + A = 1 << 16, + B = 1 << 17, + C = 1 << 18, + Option = 1 << 19, + Pause = 1 << 20, + } + } +} diff --git a/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISaveRam.cs b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISaveRam.cs new file mode 100644 index 0000000000..9f23cd6f9d --- /dev/null +++ b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISaveRam.cs @@ -0,0 +1,28 @@ +using System; + +using BizHawk.Emulation.Common; + +namespace BizHawk.Emulation.Cores.Atari.Jaguar +{ + public partial class VirtualJaguar : ISaveRam + { + public new bool SaveRamModified => _core.SaveRamIsDirty(); + + public new byte[] CloneSaveRam() + { + byte[] ret = new byte[128]; + _core.GetSaveRam(ret); + return ret; + } + + public new void StoreSaveRam(byte[] data) + { + if (data.Length != 128) + { + throw new ArgumentException(message: "buffer wrong size", paramName: nameof(data)); + } + + _core.PutSaveRam(data); + } + } +} diff --git a/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISettable.cs b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISettable.cs new file mode 100644 index 0000000000..bcfb4dafbb --- /dev/null +++ b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.ISettable.cs @@ -0,0 +1,65 @@ +using System.ComponentModel; + +using BizHawk.Common; +using BizHawk.Emulation.Common; + +namespace BizHawk.Emulation.Cores.Atari.Jaguar +{ + public partial class VirtualJaguar : ISettable + { + private VirtualJaguarSyncSettings _syncSettings; + + public object GetSettings() + => null; + + public PutSettingsDirtyBits PutSettings(object o) + => PutSettingsDirtyBits.None; + + public VirtualJaguarSyncSettings GetSyncSettings() + => _syncSettings.Clone(); + + public PutSettingsDirtyBits PutSyncSettings(VirtualJaguarSyncSettings o) + { + var ret = VirtualJaguarSyncSettings.NeedsReboot(_syncSettings, o); + _syncSettings = o; + return ret ? PutSettingsDirtyBits.RebootCore : PutSettingsDirtyBits.None; + } + + public class VirtualJaguarSyncSettings + { + [DisplayName("Player 1 Controller Connected")] + [Description("")] + [DefaultValue(true)] + public bool P1Active { get; set; } + + [DisplayName("Player 2 Controller Connected")] + [Description("")] + [DefaultValue(false)] + public bool P2Active { get; set; } + + [DisplayName("NTSC")] + [Description("")] + [DefaultValue(true)] + public bool NTSC { get; set; } + + [DisplayName("Skip BIOS")] + [Description("BIOS file must still be present")] + [DefaultValue(true)] + public bool SkipBIOS { get; set; } + + [DisplayName("Use Fast Blitter")] + [Description("")] + [DefaultValue(true)] + public bool UseFastBlitter { get; set; } + + public VirtualJaguarSyncSettings() + => SettingsUtil.SetDefaultValues(this); + + public VirtualJaguarSyncSettings Clone() + => (VirtualJaguarSyncSettings)MemberwiseClone(); + + public static bool NeedsReboot(VirtualJaguarSyncSettings x, VirtualJaguarSyncSettings y) + => !DeepEquality.DeepEquals(x, y); + } + } +} diff --git a/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.cs b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.cs new file mode 100644 index 0000000000..25d0d4036d --- /dev/null +++ b/src/BizHawk.Emulation.Cores/Consoles/Atari/jaguar/VirtualJaguar.cs @@ -0,0 +1,163 @@ +using System; +using System.Collections.Generic; +using System.Linq; + +using BizHawk.Common.CollectionExtensions; +using BizHawk.Emulation.Common; +using BizHawk.Emulation.Cores.Waterbox; + +namespace BizHawk.Emulation.Cores.Atari.Jaguar +{ + [PortedCore(CoreNames.VirtualJaguar, "Niels Wagenaar, Carwin Jones, Adam Green, James L. Hammons", "2.1.3", "https://icculus.org/virtualjaguar/", isReleased: false)] + [ServiceNotApplicable(new[] { typeof(IDriveLight) })] + public partial class VirtualJaguar : WaterboxCore, IRegionable + { + private readonly LibVirtualJaguar _core; + + [CoreConstructor(VSystemID.Raw.JAG)] + public VirtualJaguar(CoreLoadParameters lp) + : base(lp.Comm, new Configuration + { + DefaultWidth = 326, + DefaultHeight = 240, + MaxWidth = 1304, + MaxHeight = 256, + MaxSamples = 1024, + DefaultFpsNumerator = 60, + DefaultFpsDenominator = 1, + SystemId = VSystemID.Raw.JAG, + }) + { + _syncSettings = lp.SyncSettings ?? new(); + + ControllerDefinition = CreateControllerDefinition(_syncSettings.P1Active, _syncSettings.P2Active); + Region = _syncSettings.NTSC ? DisplayType.NTSC : DisplayType.PAL; + VsyncNumerator = _syncSettings.NTSC ? 60 : 50; + + _core = PreInit(new WaterboxOptions + { + Filename = "virtualjaguar.wbx", + SbrkHeapSizeKB = 64 * 1024, + SealedHeapSizeKB = 4, + InvisibleHeapSizeKB = 4, + PlainHeapSizeKB = 4, + MmapHeapSizeKB = 64 * 1024, + SkipCoreConsistencyCheck = CoreComm.CorePreferences.HasFlag(CoreComm.CorePreferencesFlags.WaterboxCoreConsistencyCheck), + SkipMemoryConsistencyCheck = CoreComm.CorePreferences.HasFlag(CoreComm.CorePreferencesFlags.WaterboxMemoryConsistencyCheck), + }); + + var bios = CoreComm.CoreFileProvider.GetFirmwareOrThrow(new("JAG", "Bios")); + if (bios.Length != 0x20000) + { + throw new MissingFirmwareException("Jaguar Bios must be 131072 bytes!"); + } + + var settings = new LibVirtualJaguar.Settings() + { + NTSC = _syncSettings.NTSC, + UseBIOS = !_syncSettings.SkipBIOS, + UseFastBlitter = _syncSettings.UseFastBlitter, + }; + + var rom = lp.Roms[0].FileData; + unsafe + { + fixed (byte* rp = rom, bp = bios) + { + if (!_core.Init(ref settings, (IntPtr)bp, (IntPtr)rp, rom.Length)) + { + throw new Exception("Core rejected the rom!"); + } + } + } + + PostInit(); + } + + private static readonly IReadOnlyList JaguarButtonsOrdered = new[] + { + "Up", "Down", "Left", "Right", "A", "B", "C", "Option", "Pause", + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "Asterisk", "Pound", + }; + + private static ControllerDefinition CreateControllerDefinition(bool p1, bool p2) + { + var ret = new ControllerDefinition("Jaguar Controller"); + + if (p1) + { + ret.BoolButtons.AddRange(JaguarButtonsOrdered.Select(s => $"P1 {s}")); + } + + if (p2) + { + ret.BoolButtons.AddRange(JaguarButtonsOrdered.Select(s => $"P2 {s}")); + } + + ret.BoolButtons.Add("Power"); + return ret.MakeImmutable(); + } + + private LibVirtualJaguar.Buttons GetButtons(IController controller, int n) + { + LibVirtualJaguar.Buttons ret = 0; + + if (controller.IsPressed($"P{n} Up")) + ret |= LibVirtualJaguar.Buttons.Up; + if (controller.IsPressed($"P{n} Down")) + ret |= LibVirtualJaguar.Buttons.Down; + if (controller.IsPressed($"P{n} Left")) + ret |= LibVirtualJaguar.Buttons.Left; + if (controller.IsPressed($"P{n} Right")) + ret |= LibVirtualJaguar.Buttons.Right; + if (controller.IsPressed($"P{n} 0")) + ret |= LibVirtualJaguar.Buttons._0; + if (controller.IsPressed($"P{n} 1")) + ret |= LibVirtualJaguar.Buttons._1; + if (controller.IsPressed($"P{n} 2")) + ret |= LibVirtualJaguar.Buttons._2; + if (controller.IsPressed($"P{n} 3")) + ret |= LibVirtualJaguar.Buttons._3; + if (controller.IsPressed($"P{n} 4")) + ret |= LibVirtualJaguar.Buttons._4; + if (controller.IsPressed($"P{n} 5")) + ret |= LibVirtualJaguar.Buttons._5; + if (controller.IsPressed($"P{n} 6")) + ret |= LibVirtualJaguar.Buttons._6; + if (controller.IsPressed($"P{n} 7")) + ret |= LibVirtualJaguar.Buttons._7; + if (controller.IsPressed($"P{n} 8")) + ret |= LibVirtualJaguar.Buttons._8; + if (controller.IsPressed($"P{n} 9")) + ret |= LibVirtualJaguar.Buttons._9; + if (controller.IsPressed($"P{n} Asterisk")) + ret |= LibVirtualJaguar.Buttons.Asterisk; + if (controller.IsPressed($"P{n} Pound")) + ret |= LibVirtualJaguar.Buttons.Pound; + if (controller.IsPressed($"P{n} A")) + ret |= LibVirtualJaguar.Buttons.A; + if (controller.IsPressed($"P{n} B")) + ret |= LibVirtualJaguar.Buttons.B; + if (controller.IsPressed($"P{n} C")) + ret |= LibVirtualJaguar.Buttons.C; + if (controller.IsPressed($"P{n} Option")) + ret |= LibVirtualJaguar.Buttons.Option; + if (controller.IsPressed($"P{n} Pause")) + ret |= LibVirtualJaguar.Buttons.Pause; + + return ret; + } + + protected override LibWaterboxCore.FrameInfo FrameAdvancePrep(IController controller, bool render, bool rendersound) + { + return new LibVirtualJaguar.FrameInfo() + { + Player1 = GetButtons(controller, 1), + Player2 = GetButtons(controller, 2), + Reset = controller.IsPressed("Power"), + }; + } + + public DisplayType Region { get; } + } +} diff --git a/src/BizHawk.Emulation.Cores/CoreNames.cs b/src/BizHawk.Emulation.Cores/CoreNames.cs index 9c4b9de7e7..6858567c57 100644 --- a/src/BizHawk.Emulation.Cores/CoreNames.cs +++ b/src/BizHawk.Emulation.Cores/CoreNames.cs @@ -61,6 +61,7 @@ namespace BizHawk.Emulation.Cores public const string VectrexHawk = "VectrexHawk"; public const string Virtu = "Virtu"; public const string VirtualBoyee = "Virtual Boyee"; + public const string VirtualJaguar = "Virtual Jaguar"; public const string ZXHawk = "ZXHawk"; } } diff --git a/src/BizHawk.Emulation.Cores/FileID.cs b/src/BizHawk.Emulation.Cores/FileID.cs index f7a4c1a360..4c2699a7ae 100644 --- a/src/BizHawk.Emulation.Cores/FileID.cs +++ b/src/BizHawk.Emulation.Cores/FileID.cs @@ -43,7 +43,7 @@ namespace BizHawk.Emulation.Cores ZXSpectrum, AmstradCPC, INT, - A26, A52, A78, LNX, + A26, A52, A78, JAG, LNX, JAD, SBI, M3U, @@ -349,6 +349,7 @@ namespace BizHawk.Emulation.Cores { "INT", new ExtensionInfo(FileIDType.INT, null) }, { "SFC", new ExtensionInfo(FileIDType.SFC, null) }, { "SMC", new ExtensionInfo(FileIDType.SFC, null) }, + { "JAG", new ExtensionInfo(FileIDType.JAG, null ) }, { "LNX", new ExtensionInfo(FileIDType.LNX, null ) }, { "SG", new ExtensionInfo(FileIDType.SG, null ) }, { "SGX", new ExtensionInfo(FileIDType.SGX, null ) }, diff --git a/waterbox/virtualjaguar/BizInterface.cpp b/waterbox/virtualjaguar/BizInterface.cpp new file mode 100644 index 0000000000..dbbb21579c --- /dev/null +++ b/waterbox/virtualjaguar/BizInterface.cpp @@ -0,0 +1,205 @@ +#include "jaguar.h" +#include "file.h" +#include "settings.h" +#include "memory.h" +#include "tom.h" +#include "joystick.h" +#include "blip_buf.h" + +#include +#include + +#include + +#define EXPORT extern "C" ECL_EXPORT + +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +struct BizSettings +{ + u8 hardwareTypeNTSC; + u8 useJaguarBIOS; + u8 useFastBlitter; +}; + +void SoundCallback(u16 * buffer, int length); +static u16* soundBuf; +static blip_t* blipL; +static blip_t* blipR; +static s16 latchL, latchR; + +EXPORT bool Init(BizSettings* bizSettings, u8* boot, u8* rom, u32 sz) +{ + vjs.GPUEnabled = true; + vjs.DSPEnabled = true; + vjs.usePipelinedDSP = false; + vjs.renderType = RT_NORMAL; + vjs.hardwareTypeNTSC = bizSettings->hardwareTypeNTSC; + vjs.useJaguarBIOS = bizSettings->useJaguarBIOS; + vjs.useFastBlitter = bizSettings->useFastBlitter; + soundBuf = alloc_invisible(2048); + blipL = blip_new(1024); + blipR = blip_new(1024); + blip_set_rates(blipL, 48000, 44100); + blip_set_rates(blipR, 48000, 44100); + + JaguarInit(); + + if (!JaguarLoadFile(rom, sz)) + { + if (!AlpineLoadFile(rom, sz)) + { + return false; + } + + vjs.hardwareTypeAlpine = true; + } + else + { + vjs.hardwareTypeAlpine = ParseFileType(rom, sz) == JST_ALPINE; + } + + SET32(jaguarMainRAM, 0, 0x00200000); + memcpy(jagMemSpace + 0xE00000, boot, 0x20000); + + JaguarReset(); + + return true; +} + +extern uint16_t eeprom_ram[64]; +extern bool eeprom_dirty; + +EXPORT bool SaveRamIsDirty() +{ + return eeprom_dirty; +} + +EXPORT void GetSaveRam(u8* dst) +{ + memcpy(dst, eeprom_ram, sizeof(eeprom_ram)); + eeprom_dirty = false; +} + +EXPORT void PutSaveRam(u8* src) +{ + memcpy(eeprom_ram, src, sizeof(eeprom_ram)); + eeprom_dirty = false; +} + +EXPORT void GetMemoryAreas(MemoryArea* m) +{ + m[0].Data = jaguarMainRAM; + m[0].Name = "Main RAM"; + m[0].Size = 0x200000; + m[0].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE | MEMORYAREA_FLAGS_PRIMARY; + + m[1].Data = eeprom_ram; + m[1].Name = "EEPROM"; + m[1].Size = sizeof(eeprom_ram); + m[1].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE | MEMORYAREA_FLAGS_SAVERAMMABLE; + + m[2].Data = gpuRAM; + m[2].Name = "GPU RAM"; + m[2].Size = 0x18000; + m[2].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; + + m[3].Data = dspRAM; + m[3].Name = "DSP RAM"; + m[3].Size = 0x5000; + m[3].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; + + m[4].Data = TOMGetRamPointer(); + m[4].Name = "TOM RAM"; + m[4].Size = 0x4000; + m[4].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; + + m[5].Data = jaguarMainROM; + m[5].Name = "ROM"; + m[5].Size = jaguarROMSize; + m[5].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; + + m[6].Data = jagMemSpace + 0xE00000; + m[6].Name = "BIOS"; + m[6].Size = 0x20000; + m[6].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; + + m[7].Data = jagMemSpace; + m[7].Name = "System Bus"; + m[7].Size = 0xF20000; + m[7].Flags = MEMORYAREA_FLAGS_WORDSIZE1 | MEMORYAREA_FLAGS_WRITABLE; +} + +struct MyFrameInfo : public FrameInfo +{ + u32 player1, player2; + bool reset; +}; + +bool lagged; +void (*inputcb)() = 0; + +EXPORT void FrameAdvance(MyFrameInfo* f) +{ + if (f->reset) + { + JaguarReset(); + } + + for (u32 i = 0; i < 21; i++) + { + joypad0Buttons[i] = (f->player1 >> i) & 1; + joypad1Buttons[i] = (f->player2 >> i) & 1; + } + + lagged = true; + JaguarSetScreenPitch(TOMGetVideoModeWidth()); + JaguarSetScreenBuffer(f->VideoBuffer); + + JaguarExecuteNew(); + + JaguarSetScreenBuffer(nullptr); + f->Width = TOMGetVideoModeWidth(); + f->Height = TOMGetVideoModeHeight(); + f->Lagged = lagged; + + u32 samples = 48000 / (vjs.hardwareTypeNTSC ? 60 : 50); + SoundCallback(soundBuf, samples * 4); + s16* sb = reinterpret_cast(soundBuf); + for (u32 i = 0; i < samples; i++) + { + s16 l = *sb++; + if (latchL != l) + { + blip_add_delta(blipL, i, latchL - l); + latchL = l; + } + + s16 r = *sb++; + if (latchR != r) + { + blip_add_delta(blipR, i, latchR - r); + latchR = r; + } + } + + blip_end_frame(blipL, samples); + blip_end_frame(blipR, samples); + + f->Samples = blip_samples_avail(blipL); + blip_read_samples(blipL, f->SoundBuffer + 0, f->Samples, 1); + blip_read_samples(blipR, f->SoundBuffer + 1, f->Samples, 1); +} + +EXPORT void SetInputCallback(void (*callback)()) +{ + inputcb = callback; +} diff --git a/waterbox/virtualjaguar/Makefile b/waterbox/virtualjaguar/Makefile new file mode 100644 index 0000000000..4a8481255d --- /dev/null +++ b/waterbox/virtualjaguar/Makefile @@ -0,0 +1,14 @@ +COMMON_FLAGS := -fno-strict-aliasing -fwrapv -I./src/ -I./src/m68000 \ + -Werror=int-to-pointer-cast -Wno-unused-variable -Wno-cpp \ + -Wno-unused-but-set-variable -Wno-return-type -Wno-misleading-indentation \ + -Wno-parentheses -Wno-unused-label + +CCFLAGS := -std=c11 $(COMMON_FLAGS) -Wno-implicit-function-declaration + +CXXFLAGS := -std=c++11 $(COMMON_FLAGS) + +TARGET = virtualjaguar.wbx + +SRCS = $(shell find ./ -type f -name '*.c') $(shell find ./ -type f -name '*.cpp') + +include ../common.mak diff --git a/waterbox/virtualjaguar/blip_buf.c b/waterbox/virtualjaguar/blip_buf.c new file mode 100644 index 0000000000..362eede49a --- /dev/null +++ b/waterbox/virtualjaguar/blip_buf.c @@ -0,0 +1,344 @@ +/* blip_buf 1.1.0. http://www.slack.net/~ant/ */ + +#include "blip_buf.h" + +#include +#include +#include +#include + +/* Library Copyright (C) 2003-2009 Shay Green. This library is free software; +you can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +library is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +#if defined (BLARGG_TEST) && BLARGG_TEST + #include "blargg_test.h" +#endif + +/* Equivalent to ULONG_MAX >= 0xFFFFFFFF00000000. +Avoids constants that don't fit in 32 bits. */ +#if ULONG_MAX/0xFFFFFFFF > 0xFFFFFFFF + typedef unsigned long fixed_t; + enum { pre_shift = 32 }; + +#elif defined(ULLONG_MAX) + typedef unsigned long long fixed_t; + enum { pre_shift = 32 }; + +#else + typedef unsigned fixed_t; + enum { pre_shift = 0 }; + +#endif + +enum { time_bits = pre_shift + 20 }; + +static fixed_t const time_unit = (fixed_t) 1 << time_bits; + +enum { bass_shift = 9 }; /* affects high-pass filter breakpoint frequency */ +enum { end_frame_extra = 2 }; /* allows deltas slightly after frame length */ + +enum { half_width = 8 }; +enum { buf_extra = half_width*2 + end_frame_extra }; +enum { phase_bits = 5 }; +enum { phase_count = 1 << phase_bits }; +enum { delta_bits = 15 }; +enum { delta_unit = 1 << delta_bits }; +enum { frac_bits = time_bits - pre_shift }; + +/* We could eliminate avail and encode whole samples in offset, but that would +limit the total buffered samples to blip_max_frame. That could only be +increased by decreasing time_bits, which would reduce resample ratio accuracy. +*/ + +/** Sample buffer that resamples to output rate and accumulates samples +until they're read out */ +struct blip_t +{ + fixed_t factor; + fixed_t offset; + int avail; + int size; + int integrator; +}; + +typedef int buf_t; + +/* probably not totally portable */ +#define SAMPLES( buf ) ((buf_t*) ((buf) + 1)) + +/* Arithmetic (sign-preserving) right shift */ +#define ARITH_SHIFT( n, shift ) \ + ((n) >> (shift)) + +enum { max_sample = +32767 }; +enum { min_sample = -32768 }; + +#define CLAMP( n ) \ + {\ + if ( (short) n != n )\ + n = ARITH_SHIFT( n, 16 ) ^ max_sample;\ + } + +static void check_assumptions( void ) +{ + int n; + + #if INT_MAX < 0x7FFFFFFF || UINT_MAX < 0xFFFFFFFF + #error "int must be at least 32 bits" + #endif + + assert( (-3 >> 1) == -2 ); /* right shift must preserve sign */ + + n = max_sample * 2; + CLAMP( n ); + assert( n == max_sample ); + + n = min_sample * 2; + CLAMP( n ); + assert( n == min_sample ); + + assert( blip_max_ratio <= time_unit ); + assert( blip_max_frame <= (fixed_t) -1 >> time_bits ); +} + +blip_t* blip_new( int size ) +{ + blip_t* m; + assert( size >= 0 ); + + m = (blip_t*) malloc( sizeof *m + (size + buf_extra) * sizeof (buf_t) ); + if ( m ) + { + m->factor = time_unit / blip_max_ratio; + m->size = size; + blip_clear( m ); + check_assumptions(); + } + return m; +} + +void blip_delete( blip_t* m ) +{ + if ( m != NULL ) + { + /* Clear fields in case user tries to use after freeing */ + memset( m, 0, sizeof *m ); + free( m ); + } +} + +void blip_set_rates( blip_t* m, double clock_rate, double sample_rate ) +{ + double factor = time_unit * sample_rate / clock_rate; + m->factor = (fixed_t) factor; + + /* Fails if clock_rate exceeds maximum, relative to sample_rate */ + assert( 0 <= factor - m->factor && factor - m->factor < 1 ); + + /* Avoid requiring math.h. Equivalent to + m->factor = (int) ceil( factor ) */ + if ( m->factor < factor ) + m->factor++; + + /* At this point, factor is most likely rounded up, but could still + have been rounded down in the floating-point calculation. */ +} + +void blip_clear( blip_t* m ) +{ + /* We could set offset to 0, factor/2, or factor-1. 0 is suitable if + factor is rounded up. factor-1 is suitable if factor is rounded down. + Since we don't know rounding direction, factor/2 accommodates either, + with the slight loss of showing an error in half the time. Since for + a 64-bit factor this is years, the halving isn't a problem. */ + + m->offset = m->factor / 2; + m->avail = 0; + m->integrator = 0; + memset( SAMPLES( m ), 0, (m->size + buf_extra) * sizeof (buf_t) ); +} + +int blip_clocks_needed( const blip_t* m, int samples ) +{ + fixed_t needed; + + /* Fails if buffer can't hold that many more samples */ + assert( samples >= 0 && m->avail + samples <= m->size ); + + needed = (fixed_t) samples * time_unit; + if ( needed < m->offset ) + return 0; + + return (needed - m->offset + m->factor - 1) / m->factor; +} + +void blip_end_frame( blip_t* m, unsigned t ) +{ + fixed_t off = t * m->factor + m->offset; + m->avail += off >> time_bits; + m->offset = off & (time_unit - 1); + + /* Fails if buffer size was exceeded */ + assert( m->avail <= m->size ); +} + +int blip_samples_avail( const blip_t* m ) +{ + return m->avail; +} + +static void remove_samples( blip_t* m, int count ) +{ + buf_t* buf = SAMPLES( m ); + int remain = m->avail + buf_extra - count; + m->avail -= count; + + memmove( &buf [0], &buf [count], remain * sizeof buf [0] ); + memset( &buf [remain], 0, count * sizeof buf [0] ); +} + +int blip_read_samples( blip_t* m, short out [], int count, int stereo ) +{ + assert( count >= 0 ); + + if ( count > m->avail ) + count = m->avail; + + if ( count ) + { + int const step = stereo ? 2 : 1; + buf_t const* in = SAMPLES( m ); + buf_t const* end = in + count; + int sum = m->integrator; + do + { + /* Eliminate fraction */ + int s = ARITH_SHIFT( sum, delta_bits ); + + sum += *in++; + + CLAMP( s ); + + *out = s; + out += step; + + /* High-pass filter */ + sum -= s << (delta_bits - bass_shift); + } + while ( in != end ); + m->integrator = sum; + + remove_samples( m, count ); + } + + return count; +} + +/* Things that didn't help performance on x86: + __attribute__((aligned(128))) + #define short int + restrict +*/ + +/* Sinc_Generator( 0.9, 0.55, 4.5 ) */ +static short const bl_step [phase_count + 1] [half_width] = +{ +{ 43, -115, 350, -488, 1136, -914, 5861,21022}, +{ 44, -118, 348, -473, 1076, -799, 5274,21001}, +{ 45, -121, 344, -454, 1011, -677, 4706,20936}, +{ 46, -122, 336, -431, 942, -549, 4156,20829}, +{ 47, -123, 327, -404, 868, -418, 3629,20679}, +{ 47, -122, 316, -375, 792, -285, 3124,20488}, +{ 47, -120, 303, -344, 714, -151, 2644,20256}, +{ 46, -117, 289, -310, 634, -17, 2188,19985}, +{ 46, -114, 273, -275, 553, 117, 1758,19675}, +{ 44, -108, 255, -237, 471, 247, 1356,19327}, +{ 43, -103, 237, -199, 390, 373, 981,18944}, +{ 42, -98, 218, -160, 310, 495, 633,18527}, +{ 40, -91, 198, -121, 231, 611, 314,18078}, +{ 38, -84, 178, -81, 153, 722, 22,17599}, +{ 36, -76, 157, -43, 80, 824, -241,17092}, +{ 34, -68, 135, -3, 8, 919, -476,16558}, +{ 32, -61, 115, 34, -60, 1006, -683,16001}, +{ 29, -52, 94, 70, -123, 1083, -862,15422}, +{ 27, -44, 73, 106, -184, 1152,-1015,14824}, +{ 25, -36, 53, 139, -239, 1211,-1142,14210}, +{ 22, -27, 34, 170, -290, 1261,-1244,13582}, +{ 20, -20, 16, 199, -335, 1301,-1322,12942}, +{ 18, -12, -3, 226, -375, 1331,-1376,12293}, +{ 15, -4, -19, 250, -410, 1351,-1408,11638}, +{ 13, 3, -35, 272, -439, 1361,-1419,10979}, +{ 11, 9, -49, 292, -464, 1362,-1410,10319}, +{ 9, 16, -63, 309, -483, 1354,-1383, 9660}, +{ 7, 22, -75, 322, -496, 1337,-1339, 9005}, +{ 6, 26, -85, 333, -504, 1312,-1280, 8355}, +{ 4, 31, -94, 341, -507, 1278,-1205, 7713}, +{ 3, 35, -102, 347, -506, 1238,-1119, 7082}, +{ 1, 40, -110, 350, -499, 1190,-1021, 6464}, +{ 0, 43, -115, 350, -488, 1136, -914, 5861} +}; + +/* Shifting by pre_shift allows calculation using unsigned int rather than +possibly-wider fixed_t. On 32-bit platforms, this is likely more efficient. +And by having pre_shift 32, a 32-bit platform can easily do the shift by +simply ignoring the low half. */ + +void blip_add_delta( blip_t* m, unsigned time, int delta ) +{ + unsigned fixed = (unsigned) ((time * m->factor + m->offset) >> pre_shift); + buf_t* out = SAMPLES( m ) + m->avail + (fixed >> frac_bits); + + int const phase_shift = frac_bits - phase_bits; + int phase = fixed >> phase_shift & (phase_count - 1); + short const* in = bl_step [phase]; + short const* rev = bl_step [phase_count - phase]; + + int interp = fixed >> (phase_shift - delta_bits) & (delta_unit - 1); + int delta2 = (delta * interp) >> delta_bits; + delta -= delta2; + + /* Fails if buffer size was exceeded */ + assert( out <= &SAMPLES( m ) [m->size + end_frame_extra] ); + + out [0] += in[0]*delta + in[half_width+0]*delta2; + out [1] += in[1]*delta + in[half_width+1]*delta2; + out [2] += in[2]*delta + in[half_width+2]*delta2; + out [3] += in[3]*delta + in[half_width+3]*delta2; + out [4] += in[4]*delta + in[half_width+4]*delta2; + out [5] += in[5]*delta + in[half_width+5]*delta2; + out [6] += in[6]*delta + in[half_width+6]*delta2; + out [7] += in[7]*delta + in[half_width+7]*delta2; + + in = rev; + out [ 8] += in[7]*delta + in[7-half_width]*delta2; + out [ 9] += in[6]*delta + in[6-half_width]*delta2; + out [10] += in[5]*delta + in[5-half_width]*delta2; + out [11] += in[4]*delta + in[4-half_width]*delta2; + out [12] += in[3]*delta + in[3-half_width]*delta2; + out [13] += in[2]*delta + in[2-half_width]*delta2; + out [14] += in[1]*delta + in[1-half_width]*delta2; + out [15] += in[0]*delta + in[0-half_width]*delta2; +} + +void blip_add_delta_fast( blip_t* m, unsigned time, int delta ) +{ + unsigned fixed = (unsigned) ((time * m->factor + m->offset) >> pre_shift); + buf_t* out = SAMPLES( m ) + m->avail + (fixed >> frac_bits); + + int interp = fixed >> (frac_bits - delta_bits) & (delta_unit - 1); + int delta2 = delta * interp; + + /* Fails if buffer size was exceeded */ + assert( out <= &SAMPLES( m ) [m->size + end_frame_extra] ); + + out [7] += delta * delta_unit - delta2; + out [8] += delta2; +} diff --git a/waterbox/virtualjaguar/blip_buf.h b/waterbox/virtualjaguar/blip_buf.h new file mode 100644 index 0000000000..52703643c4 --- /dev/null +++ b/waterbox/virtualjaguar/blip_buf.h @@ -0,0 +1,72 @@ +/** \file +Sample buffer that resamples from input clock rate to output sample rate */ + +/* blip_buf 1.1.0 */ +#ifndef BLIP_BUF_H +#define BLIP_BUF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** First parameter of most functions is blip_t*, or const blip_t* if nothing +is changed. */ +typedef struct blip_t blip_t; + +/** Creates new buffer that can hold at most sample_count samples. Sets rates +so that there are blip_max_ratio clocks per sample. Returns pointer to new +buffer, or NULL if insufficient memory. */ +blip_t* blip_new( int sample_count ); + +/** Sets approximate input clock rate and output sample rate. For every +clock_rate input clocks, approximately sample_rate samples are generated. */ +void blip_set_rates( blip_t*, double clock_rate, double sample_rate ); + +enum { /** Maximum clock_rate/sample_rate ratio. For a given sample_rate, +clock_rate must not be greater than sample_rate*blip_max_ratio. */ +blip_max_ratio = 1 << 20 }; + +/** Clears entire buffer. Afterwards, blip_samples_avail() == 0. */ +void blip_clear( blip_t* ); + +/** Adds positive/negative delta into buffer at specified clock time. */ +void blip_add_delta( blip_t*, unsigned int clock_time, int delta ); + +/** Same as blip_add_delta(), but uses faster, lower-quality synthesis. */ +void blip_add_delta_fast( blip_t*, unsigned int clock_time, int delta ); + +/** Length of time frame, in clocks, needed to make sample_count additional +samples available. */ +int blip_clocks_needed( const blip_t*, int sample_count ); + +enum { /** Maximum number of samples that can be generated from one time frame. */ +blip_max_frame = 4000 }; + +/** Makes input clocks before clock_duration available for reading as output +samples. Also begins new time frame at clock_duration, so that clock time 0 in +the new time frame specifies the same clock as clock_duration in the old time +frame specified. Deltas can have been added slightly past clock_duration (up to +however many clocks there are in two output samples). */ +void blip_end_frame( blip_t*, unsigned int clock_duration ); + +/** Number of buffered samples available for reading. */ +int blip_samples_avail( const blip_t* ); + +/** Reads and removes at most 'count' samples and writes them to 'out'. If +'stereo' is true, writes output to every other element of 'out', allowing easy +interleaving of two buffers into a stereo sample stream. Outputs 16-bit signed +samples. Returns number of samples actually read. */ +int blip_read_samples( blip_t*, short out [], int count, int stereo ); + +/** Frees buffer. No effect if NULL is passed. */ +void blip_delete( blip_t* ); + + +/* Deprecated */ +typedef blip_t blip_buffer_t; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/waterbox/virtualjaguar/src/blitter.cpp b/waterbox/virtualjaguar/src/blitter.cpp new file mode 100644 index 0000000000..7193daf19c --- /dev/null +++ b/waterbox/virtualjaguar/src/blitter.cpp @@ -0,0 +1,6232 @@ +// +// Blitter core +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ----------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +// +// I owe a debt of gratitude to Curt Vendel and to John Mathieson--to Curt +// for supplying the Oberon ASIC nets and to John for making them available +// to Curt. ;-) Without that excellent documentation which shows *exactly* +// what's going on inside the TOM chip, we'd all still be guessing as to how +// the wily blitter and other pieces of the Jaguar puzzle actually work. +// + +#include "blitter.h" + +#include +#include +#include +#include "jaguar.h" +#include "log.h" +//#include "memory.h" +#include "settings.h" + +// Various conditional compilation goodies... + +//#define LOG_BLITS + +#define USE_ORIGINAL_BLITTER +//#define USE_MIDSUMMER_BLITTER +#define USE_MIDSUMMER_BLITTER_MKII + +#ifdef USE_ORIGINAL_BLITTER +#ifdef USE_MIDSUMMER_BLITTER_MKII +#define USE_BOTH_BLITTERS +#endif +#endif + + +// External global variables + +extern int jaguar_active_memory_dumps; + +// Local global variables + +int start_logging = 0; +uint8_t blitter_working = 0; +bool startConciseBlitLogging = false; +bool logBlit = false; + +// Blitter register RAM (most of it is hidden from the user) + +static uint8_t blitter_ram[0x100]; + +// Other crapola + +bool specialLog = false; +extern int effect_start; +extern int blit_start_log; +void BlitterMidsummer(uint32_t cmd); +void BlitterMidsummer2(void); + +#define REG(A) (((uint32_t)blitter_ram[(A)] << 24) | ((uint32_t)blitter_ram[(A)+1] << 16) \ + | ((uint32_t)blitter_ram[(A)+2] << 8) | (uint32_t)blitter_ram[(A)+3]) +#define WREG(A,D) (blitter_ram[(A)] = ((D)>>24)&0xFF, blitter_ram[(A)+1] = ((D)>>16)&0xFF, \ + blitter_ram[(A)+2] = ((D)>>8)&0xFF, blitter_ram[(A)+3] = (D)&0xFF) + +// Blitter registers (offsets from F02200) + +#define A1_BASE ((uint32_t)0x00) +#define A1_FLAGS ((uint32_t)0x04) +#define A1_CLIP ((uint32_t)0x08) // Height and width values for clipping +#define A1_PIXEL ((uint32_t)0x0C) // Integer part of the pixel (Y.i and X.i) +#define A1_STEP ((uint32_t)0x10) // Integer part of the step +#define A1_FSTEP ((uint32_t)0x14) // Fractional part of the step +#define A1_FPIXEL ((uint32_t)0x18) // Fractional part of the pixel (Y.f and X.f) +#define A1_INC ((uint32_t)0x1C) // Integer part of the increment +#define A1_FINC ((uint32_t)0x20) // Fractional part of the increment +#define A2_BASE ((uint32_t)0x24) +#define A2_FLAGS ((uint32_t)0x28) +#define A2_MASK ((uint32_t)0x2C) // Modulo values for x and y (M.y and M.x) +#define A2_PIXEL ((uint32_t)0x30) // Integer part of the pixel (no fractional part for A2) +#define A2_STEP ((uint32_t)0x34) // Integer part of the step (no fractional part for A2) +#define COMMAND ((uint32_t)0x38) +#define PIXLINECOUNTER ((uint32_t)0x3C) // Inner & outer loop values +#define SRCDATA ((uint32_t)0x40) +#define DSTDATA ((uint32_t)0x48) +#define DSTZ ((uint32_t)0x50) +#define SRCZINT ((uint32_t)0x58) +#define SRCZFRAC ((uint32_t)0x60) +#define PATTERNDATA ((uint32_t)0x68) +#define INTENSITYINC ((uint32_t)0x70) +#define ZINC ((uint32_t)0x74) +#define COLLISIONCTRL ((uint32_t)0x78) +#define PHRASEINT0 ((uint32_t)0x7C) +#define PHRASEINT1 ((uint32_t)0x80) +#define PHRASEINT2 ((uint32_t)0x84) +#define PHRASEINT3 ((uint32_t)0x88) +#define PHRASEZ0 ((uint32_t)0x8C) +#define PHRASEZ1 ((uint32_t)0x90) +#define PHRASEZ2 ((uint32_t)0x94) +#define PHRASEZ3 ((uint32_t)0x98) + +// Blitter command bits + +#define SRCEN (cmd & 0x00000001) +#define SRCENZ (cmd & 0x00000002) +#define SRCENX (cmd & 0x00000004) +#define DSTEN (cmd & 0x00000008) +#define DSTENZ (cmd & 0x00000010) +#define DSTWRZ (cmd & 0x00000020) +#define CLIPA1 (cmd & 0x00000040) + +#define UPDA1F (cmd & 0x00000100) +#define UPDA1 (cmd & 0x00000200) +#define UPDA2 (cmd & 0x00000400) + +#define DSTA2 (cmd & 0x00000800) + +#define Z_OP_INF (cmd & 0x00040000) +#define Z_OP_EQU (cmd & 0x00080000) +#define Z_OP_SUP (cmd & 0x00100000) + +#define LFU_NAN (cmd & 0x00200000) +#define LFU_NA (cmd & 0x00400000) +#define LFU_AN (cmd & 0x00800000) +#define LFU_A (cmd & 0x01000000) + +#define CMPDST (cmd & 0x02000000) +#define BCOMPEN (cmd & 0x04000000) +#define DCOMPEN (cmd & 0x08000000) + +#define PATDSEL (cmd & 0x00010000) +#define ADDDSEL (cmd & 0x00020000) +#define TOPBEN (cmd & 0x00004000) +#define TOPNEN (cmd & 0x00008000) +#define BKGWREN (cmd & 0x10000000) +#define GOURD (cmd & 0x00001000) +#define GOURZ (cmd & 0x00002000) +#define SRCSHADE (cmd & 0x40000000) + + +#define XADDPHR 0 +#define XADDPIX 1 +#define XADD0 2 +#define XADDINC 3 + +#define XSIGNSUB_A1 (REG(A1_FLAGS)&0x080000) +#define XSIGNSUB_A2 (REG(A2_FLAGS)&0x080000) + +#define YSIGNSUB_A1 (REG(A1_FLAGS)&0x100000) +#define YSIGNSUB_A2 (REG(A2_FLAGS)&0x100000) + +#define YADD1_A1 (REG(A1_FLAGS)&0x040000) +#define YADD1_A2 (REG(A2_FLAGS)&0x040000) + +/******************************************************************************* +********************** STUFF CUT BELOW THIS LINE! ****************************** +*******************************************************************************/ +#ifdef USE_ORIGINAL_BLITTER // We're ditching this crap for now... + +//Put 'em back, once we fix the problem!!! [KO] +// 1 bpp pixel read +#define PIXEL_SHIFT_1(a) (((~a##_x) >> 16) & 7) +#define PIXEL_OFFSET_1(a) (((((uint32_t)a##_y >> 16) * a##_width / 8) + (((uint32_t)a##_x >> 19) & ~7)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 19) & 7)) +#define READ_PIXEL_1(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a), BLITTER) >> PIXEL_SHIFT_1(a)) & 0x01) +//#define READ_PIXEL_1(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a)) >> PIXEL_SHIFT_1(a)) & 0x01) + +// 2 bpp pixel read +#define PIXEL_SHIFT_2(a) (((~a##_x) >> 15) & 6) +#define PIXEL_OFFSET_2(a) (((((uint32_t)a##_y >> 16) * a##_width / 4) + (((uint32_t)a##_x >> 18) & ~7)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 18) & 7)) +#define READ_PIXEL_2(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a), BLITTER) >> PIXEL_SHIFT_2(a)) & 0x03) +//#define READ_PIXEL_2(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_2(a)) >> PIXEL_SHIFT_2(a)) & 0x03) + +// 4 bpp pixel read +#define PIXEL_SHIFT_4(a) (((~a##_x) >> 14) & 4) +#define PIXEL_OFFSET_4(a) (((((uint32_t)a##_y >> 16) * (a##_width/2)) + (((uint32_t)a##_x >> 17) & ~7)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 17) & 7)) +#define READ_PIXEL_4(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a), BLITTER) >> PIXEL_SHIFT_4(a)) & 0x0f) +//#define READ_PIXEL_4(a) ((JaguarReadByte(a##_addr+PIXEL_OFFSET_4(a)) >> PIXEL_SHIFT_4(a)) & 0x0f) + +// 8 bpp pixel read +#define PIXEL_OFFSET_8(a) (((((uint32_t)a##_y >> 16) * a##_width) + (((uint32_t)a##_x >> 16) & ~7)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 16) & 7)) +#define READ_PIXEL_8(a) (JaguarReadByte(a##_addr+PIXEL_OFFSET_8(a), BLITTER)) +//#define READ_PIXEL_8(a) (JaguarReadByte(a##_addr+PIXEL_OFFSET_8(a))) + +// 16 bpp pixel read +#define PIXEL_OFFSET_16(a) (((((uint32_t)a##_y >> 16) * a##_width) + (((uint32_t)a##_x >> 16) & ~3)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 16) & 3)) +#define READ_PIXEL_16(a) (JaguarReadWord(a##_addr+(PIXEL_OFFSET_16(a)<<1), BLITTER)) +//#define READ_PIXEL_16(a) (JaguarReadWord(a##_addr+(PIXEL_OFFSET_16(a)<<1))) + +// 32 bpp pixel read +#define PIXEL_OFFSET_32(a) (((((uint32_t)a##_y >> 16) * a##_width) + (((uint32_t)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 16) & 1)) +#define READ_PIXEL_32(a) (JaguarReadLong(a##_addr+(PIXEL_OFFSET_32(a)<<2), BLITTER)) +//#define READ_PIXEL_32(a) (JaguarReadLong(a##_addr+(PIXEL_OFFSET_32(a)<<2))) + +// pixel read +#define READ_PIXEL(a,f) (\ + (((f>>3)&0x07) == 0) ? (READ_PIXEL_1(a)) : \ + (((f>>3)&0x07) == 1) ? (READ_PIXEL_2(a)) : \ + (((f>>3)&0x07) == 2) ? (READ_PIXEL_4(a)) : \ + (((f>>3)&0x07) == 3) ? (READ_PIXEL_8(a)) : \ + (((f>>3)&0x07) == 4) ? (READ_PIXEL_16(a)) : \ + (((f>>3)&0x07) == 5) ? (READ_PIXEL_32(a)) : 0) + +// 16 bpp z data read +#define ZDATA_OFFSET_16(a) (PIXEL_OFFSET_16(a) + a##_zoffs * 4) +#define READ_ZDATA_16(a) (JaguarReadWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), BLITTER)) +//#define READ_ZDATA_16(a) (JaguarReadWord(a##_addr+(ZDATA_OFFSET_16(a)<<1))) + +// z data read +#define READ_ZDATA(a,f) (READ_ZDATA_16(a)) + +// 16 bpp z data write +#define WRITE_ZDATA_16(a,d) { JaguarWriteWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), d, BLITTER); } +//#define WRITE_ZDATA_16(a,d) { JaguarWriteWord(a##_addr+(ZDATA_OFFSET_16(a)<<1), d); } + +// z data write +#define WRITE_ZDATA(a,f,d) WRITE_ZDATA_16(a,d); + +// 1 bpp r data read +#define READ_RDATA_1(r,a,p) ((p) ? ((REG(r+(((uint32_t)a##_x >> 19) & 0x04))) >> (((uint32_t)a##_x >> 16) & 0x1F)) & 0x0001 : (REG(r) & 0x0001)) + +// 2 bpp r data read +#define READ_RDATA_2(r,a,p) ((p) ? ((REG(r+(((uint32_t)a##_x >> 18) & 0x04))) >> (((uint32_t)a##_x >> 15) & 0x3E)) & 0x0003 : (REG(r) & 0x0003)) + +// 4 bpp r data read +#define READ_RDATA_4(r,a,p) ((p) ? ((REG(r+(((uint32_t)a##_x >> 17) & 0x04))) >> (((uint32_t)a##_x >> 14) & 0x28)) & 0x000F : (REG(r) & 0x000F)) + +// 8 bpp r data read +#define READ_RDATA_8(r,a,p) ((p) ? ((REG(r+(((uint32_t)a##_x >> 16) & 0x04))) >> (((uint32_t)a##_x >> 13) & 0x18)) & 0x00FF : (REG(r) & 0x00FF)) + +// 16 bpp r data read +#define READ_RDATA_16(r,a,p) ((p) ? ((REG(r+(((uint32_t)a##_x >> 15) & 0x04))) >> (((uint32_t)a##_x >> 12) & 0x10)) & 0xFFFF : (REG(r) & 0xFFFF)) + +// 32 bpp r data read +#define READ_RDATA_32(r,a,p) ((p) ? REG(r+(((uint32_t)a##_x >> 14) & 0x04)) : REG(r)) + +// register data read +#define READ_RDATA(r,a,f,p) (\ + (((f>>3)&0x07) == 0) ? (READ_RDATA_1(r,a,p)) : \ + (((f>>3)&0x07) == 1) ? (READ_RDATA_2(r,a,p)) : \ + (((f>>3)&0x07) == 2) ? (READ_RDATA_4(r,a,p)) : \ + (((f>>3)&0x07) == 3) ? (READ_RDATA_8(r,a,p)) : \ + (((f>>3)&0x07) == 4) ? (READ_RDATA_16(r,a,p)) : \ + (((f>>3)&0x07) == 5) ? (READ_RDATA_32(r,a,p)) : 0) + +// 1 bpp pixel write +#define WRITE_PIXEL_1(a,d) { JaguarWriteByte(a##_addr+PIXEL_OFFSET_1(a), (JaguarReadByte(a##_addr+PIXEL_OFFSET_1(a), BLITTER)&(~(0x01 << PIXEL_SHIFT_1(a))))|(d<>3)&0x07) { \ + case 0: WRITE_PIXEL_1(a,d); break; \ + case 1: WRITE_PIXEL_2(a,d); break; \ + case 2: WRITE_PIXEL_4(a,d); break; \ + case 3: WRITE_PIXEL_8(a,d); break; \ + case 4: WRITE_PIXEL_16(a,d); break; \ + case 5: WRITE_PIXEL_32(a,d); break; \ + }} + +// Width in Pixels of a Scanline +// This is a pretranslation of the value found in the A1 & A2 flags: It's really a floating point value +// of the form EEEEMM where MM is the mantissa with an implied "1." in front of it and the EEEE value is +// the exponent. Valid values for the exponent range from 0 to 11 (decimal). It's easiest to think of it +// as a floating point bit pattern being followed by a number of zeroes. So, e.g., 001101 translates to +// 1.01 (the "1." being implied) x (2 ^ 3) or 1010 -> 10 in base 10 (i.e., 1.01 with the decimal place +// being shifted to the right 3 places). +/*static uint32_t blitter_scanline_width[48] = +{ + 0, 0, 0, 0, // Note: This would really translate to 1, 1, 1, 1 + 2, 0, 0, 0, + 4, 0, 6, 0, + 8, 10, 12, 14, + 16, 20, 24, 28, + 32, 40, 48, 56, + 64, 80, 96, 112, + 128, 160, 192, 224, + 256, 320, 384, 448, + 512, 640, 768, 896, + 1024, 1280, 1536, 1792, + 2048, 2560, 3072, 3584 +};//*/ + +//static uint8_t * tom_ram_8; +//static uint8_t * paletteRam; +static uint8_t src; +static uint8_t dst; +static uint8_t misc; +static uint8_t a1ctl; +static uint8_t mode; +static uint8_t ity; +static uint8_t zop; +static uint8_t op; +static uint8_t ctrl; +static uint32_t a1_addr; +static uint32_t a2_addr; +static int32_t a1_zoffs; +static int32_t a2_zoffs; +static uint32_t xadd_a1_control; +static uint32_t xadd_a2_control; +static int32_t a1_pitch; +static int32_t a2_pitch; +static uint32_t n_pixels; +static uint32_t n_lines; +static int32_t a1_x; +static int32_t a1_y; +static int32_t a1_width; +static int32_t a2_x; +static int32_t a2_y; +static int32_t a2_width; +static int32_t a2_mask_x; +static int32_t a2_mask_y; +static int32_t a1_xadd; +static int32_t a1_yadd; +static int32_t a2_xadd; +static int32_t a2_yadd; +static uint8_t a1_phrase_mode; +static uint8_t a2_phrase_mode; +static int32_t a1_step_x = 0; +static int32_t a1_step_y = 0; +static int32_t a2_step_x = 0; +static int32_t a2_step_y = 0; +static uint32_t outer_loop; +static uint32_t inner_loop; +static uint32_t a2_psize; +static uint32_t a1_psize; +static uint32_t gouraud_add; +//static uint32_t gouraud_data; +//static uint16_t gint[4]; +//static uint16_t gfrac[4]; +//static uint8_t gcolour[4]; +static int gd_i[4]; +static int gd_c[4]; +static int gd_ia, gd_ca; +static int colour_index = 0; +static int32_t zadd; +static uint32_t z_i[4]; + +static int32_t a1_clip_x, a1_clip_y; + +// In the spirit of "get it right first, *then* optimize" I've taken the liberty +// of removing all the unnecessary code caching. If it turns out to be a good way +// to optimize the blitter, then we may revisit it in the future... + +// +// Generic blit handler +// +void blitter_generic(uint32_t cmd) +{ +/* +Blit! (0018FA70 <- 008DDC40) count: 2 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -2 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 100/12, A2 x/y: 106/0 Pattern: 000000F300000000 +*/ +//if (effect_start) +// specialLog = true; +/*if (cmd == 0x1401060C && blit_start_log) + specialLog = true;//*/ +//Testing only! +//uint32_t logGo = ((cmd == 0x01800E01 && REG(A1_BASE) == 0x898000) ? 1 : 0); + uint32_t srcdata, srczdata, dstdata, dstzdata, writedata, inhibit; + uint32_t bppSrc = (DSTA2 ? 1 << ((REG(A1_FLAGS) >> 3) & 0x07) : 1 << ((REG(A2_FLAGS) >> 3) & 0x07)); + +if (specialLog) +{ + WriteLog("About to do n x m blit (BM width is ? pixels)...\n"); + WriteLog("A1_STEP_X/Y = %08X/%08X, A2_STEP_X/Y = %08X/%08X\n", a1_step_x, a1_step_y, a2_step_x, a2_step_y); +} +/* if (BCOMPEN) + { + if (DSTA2) + a1_xadd = 0; + else + a2_xadd = 0; + }//*/ + + while (outer_loop--) + { +if (specialLog) +{ + WriteLog(" A1_X/Y = %08X/%08X, A2_X/Y = %08X/%08X\n", a1_x, a1_y, a2_x, a2_y); +} + uint32_t a1_start = a1_x, a2_start = a2_x, bitPos = 0; + + //Kludge for Hover Strike... + //I wonder if this kludge is in conjunction with the SRCENX down below... + // This isn't so much a kludge but the way things work in BCOMPEN mode...! + if (BCOMPEN && SRCENX) + { + if (n_pixels < bppSrc) + bitPos = bppSrc - n_pixels; + } + + inner_loop = n_pixels; + while (inner_loop--) + { +if (specialLog) +{ + WriteLog(" A1_X/Y = %08X/%08X, A2_X/Y = %08X/%08X\n", a1_x, a1_y, a2_x, a2_y); +} + srcdata = srczdata = dstdata = dstzdata = writedata = inhibit = 0; + + if (!DSTA2) // Data movement: A1 <- A2 + { + // load src data and Z +// if (SRCEN) + if (SRCEN || SRCENX) // Not sure if this is correct... (seems to be...!) + { + srcdata = READ_PIXEL(a2, REG(A2_FLAGS)); + + if (SRCENZ) + srczdata = READ_ZDATA(a2, REG(A2_FLAGS)); + else if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ + srczdata = READ_RDATA(SRCZINT, a2, REG(A2_FLAGS), a2_phrase_mode); + } + else // Use SRCDATA register... + { + srcdata = READ_RDATA(SRCDATA, a2, REG(A2_FLAGS), a2_phrase_mode); + + if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ + srczdata = READ_RDATA(SRCZINT, a2, REG(A2_FLAGS), a2_phrase_mode); + } + + // load dst data and Z + if (DSTEN) + { + dstdata = READ_PIXEL(a1, REG(A1_FLAGS)); + + if (DSTENZ) + dstzdata = READ_ZDATA(a1, REG(A1_FLAGS)); + else + dstzdata = READ_RDATA(DSTZ, a1, REG(A1_FLAGS), a1_phrase_mode); + } + else + { + dstdata = READ_RDATA(DSTDATA, a1, REG(A1_FLAGS), a1_phrase_mode); + + if (DSTENZ) + dstzdata = READ_RDATA(DSTZ, a1, REG(A1_FLAGS), a1_phrase_mode); + } + +/*This wasn't working... // a1 clipping + if (cmd & 0x00000040) + { + if (a1_x < 0 || a1_y < 0 || (a1_x >> 16) >= (REG(A1_CLIP) & 0x7FFF) + || (a1_y >> 16) >= ((REG(A1_CLIP) >> 16) & 0x7FFF)) + inhibit = 1; + }//*/ + + if (GOURZ) + srczdata = z_i[colour_index] >> 16; + + // apply z comparator + if (Z_OP_INF && srczdata < dstzdata) inhibit = 1; + if (Z_OP_EQU && srczdata == dstzdata) inhibit = 1; + if (Z_OP_SUP && srczdata > dstzdata) inhibit = 1; + + // apply data comparator +// Note: DCOMPEN only works in 8/16 bpp modes! !!! FIX !!! +// Does BCOMPEN only work in 1 bpp mode??? +// No, but it always does a 1 bit expansion no matter what the BPP of the channel is set to. !!! FIX !!! +// This is bit tricky... We need to fix the XADD value so that it acts like a 1BPP value while inside +// an 8BPP space. + if (DCOMPEN | BCOMPEN) + { +//Temp, for testing Hover Strike +//Doesn't seem to do it... Why? +//What needs to happen here is twofold. First, the address generator in the outer loop has +//to honor the BPP when calculating the start address (which it kinda does already). Second, +//it has to step bit by bit when using BCOMPEN. How to do this??? + if (BCOMPEN) +//small problem with this approach: it's not accurate... We need a proper address to begin with +//and *then* we can do the bit stepping from there the way it's *supposed* to be done... !!! FIX !!! +//[DONE] + { + uint32_t pixShift = (~bitPos) & (bppSrc - 1); + srcdata = (srcdata >> pixShift) & 0x01; + + bitPos++; +// if (bitPos % bppSrc == 0) +// a2_x += 0x00010000; + } +/* +Interesting (Hover Strike--large letter): + +Blit! (0018FA70 <- 008DDC40) count: 2 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -2 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 100/12, A2 x/y: 106/0 Pattern: 000000F300000000 + +Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -8 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 102/12, A2 x/y: 107/0 Pattern: 000000F300000000 + +Blit! (0018FA70 <- 008DDC40) count: 1 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -1 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 118/12, A2 x/y: 70/0 Pattern: 000000F300000000 + +Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -8 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 119/12, A2 x/y: 71/0 Pattern: 000000F300000000 + +Blit! (0018FA70 <- 008DDC40) count: 1 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -1 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 127/12, A2 x/y: 66/0 Pattern: 000000F300000000 + +Blit! (0018FA70 <- 008DDC40) count: 8 x 13, A1/2_FLAGS: 00014218/00013C18 [cmd: 1401060C] + CMD -> src: SRCENX dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: BCOMPEN BKGWREN + A1 step values: -8 (X), 1 (Y) + A2 step values: -1 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 8bpp, z-off: 0, width: 192 (1E), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 128/12, A2 x/y: 67/0 Pattern: 000000F300000000 +*/ + + + if (!CMPDST) + { +//WriteLog("Blitter: BCOMPEN set on command %08X inhibit prev:%u, now:", cmd, inhibit); + // compare source pixel with pattern pixel +/* +Blit! (000B8250 <- 0012C3A0) count: 16 x 1, A1/2_FLAGS: 00014420/00012000 [cmd: 05810001] + CMD -> src: SRCEN dst: misc: a1ctl: mode: ity: PATDSEL z-op: op: LFU_REPLACE ctrl: BCOMPEN + A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 1bpp, z-off: 0, width: 16 (10), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + x/y: 0/20 +... +*/ +// AvP is still wrong, could be cuz it's doing A1 -> A2... + +// Src is the 1bpp bitmap... DST is the PATTERN!!! +// This seems to solve at least ONE of the problems with MC3D... +// Why should this be inverted??? +// Bcuz it is. This is supposed to be used only for a bit -> pixel expansion... +/* if (srcdata == READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode)) +// if (srcdata != READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode)) + inhibit = 1;//*/ +/* uint32_t A2bpp = 1 << ((REG(A2_FLAGS) >> 3) & 0x07); + if (A2bpp == 1 || A2bpp == 16 || A2bpp == 8) + inhibit = (srcdata == 0 ? 1: 0); +// inhibit = !srcdata; + else + WriteLog("Blitter: Bad BPP (%u) selected for BCOMPEN mode!\n", A2bpp);//*/ +// What it boils down to is this: + + if (srcdata == 0) + inhibit = 1;//*/ + } + else + { + // compare destination pixel with pattern pixel + if (dstdata == READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode)) +// if (dstdata != READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode)) + inhibit = 1; + } + +// This is DEFINITELY WRONG +// if (a1_phrase_mode || a2_phrase_mode) +// inhibit = !inhibit; + } + + if (CLIPA1) + { + inhibit |= (((a1_x >> 16) < a1_clip_x && (a1_x >> 16) >= 0 + && (a1_y >> 16) < a1_clip_y && (a1_y >> 16) >= 0) ? 0 : 1); + } + + // compute the write data and store + if (!inhibit) + { +// Houston, we have a problem... +// Look here, at PATDSEL and GOURD. If both are active (as they are on the BIOS intro), then there's +// a conflict! E.g.: +//Blit! (00100000 <- 000095D0) count: 3 x 1, A1/2_FLAGS: 00014220/00004020 [cmd: 00011008] +// CMD -> src: dst: DSTEN misc: a1ctl: mode: GOURD ity: PATDSEL z-op: op: LFU_CLEAR ctrl: +// A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD +// A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 256 (20), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD +// A1 x/y: 90/171, A2 x/y: 808/0 Pattern: 776D770077007700 + + if (PATDSEL) + { + // use pattern data for write data + writedata = READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode); + } + else if (ADDDSEL) + { +/*if (blit_start_log) + WriteLog("BLIT: ADDDSEL srcdata: %08X\, dstdata: %08X, ", srcdata, dstdata);//*/ + + // intensity addition +//Ok, this is wrong... Or is it? Yes, it's wrong! !!! FIX !!! +/* writedata = (srcdata & 0xFF) + (dstdata & 0xFF); + if (!(TOPBEN) && writedata > 0xFF) +// writedata = 0xFF; + writedata &= 0xFF; + writedata |= (srcdata & 0xF00) + (dstdata & 0xF00); + if (!(TOPNEN) && writedata > 0xFFF) +// writedata = 0xFFF; + writedata &= 0xFFF; + writedata |= (srcdata & 0xF000) + (dstdata & 0xF000);//*/ +//notneeded--writedata &= 0xFFFF; +/*if (blit_start_log) + WriteLog("writedata: %08X\n", writedata);//*/ +/* +Hover Strike ADDDSEL blit: + +Blit! (00098D90 <- 0081DDC0) count: 320 x 287, A1/2_FLAGS: 00004220/00004020 [cmd: 00020208] + CMD -> src: dst: DSTEN misc: a1ctl: UPDA1 mode: ity: ADDDSEL z-op: op: LFU_CLEAR ctrl: + A1 step values: -320 (X), 1 (Y) + A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 256 (20), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 0/0, A2 x/y: 3288/0 Pattern: 0000000000000000 SRCDATA: 00FD00FD00FD00FD +*/ + writedata = (srcdata & 0xFF) + (dstdata & 0xFF); + + if (!TOPBEN) + { +//This is correct now, but slow... + int16_t s = (srcdata & 0xFF) | (srcdata & 0x80 ? 0xFF00 : 0x0000), + d = dstdata & 0xFF; + int16_t sum = s + d; + + if (sum < 0) + writedata = 0x00; + else if (sum > 0xFF) + writedata = 0xFF; + else + writedata = (uint32_t)sum; + } + +//This doesn't seem right... Looks like it would muck up the low byte... !!! FIX !!! + writedata |= (srcdata & 0xF00) + (dstdata & 0xF00); + + if (!TOPNEN && writedata > 0xFFF) + { + writedata &= 0xFFF; + } + + writedata |= (srcdata & 0xF000) + (dstdata & 0xF000); + } + else + { + if (LFU_NAN) writedata |= ~srcdata & ~dstdata; + if (LFU_NA) writedata |= ~srcdata & dstdata; + if (LFU_AN) writedata |= srcdata & ~dstdata; + if (LFU_A) writedata |= srcdata & dstdata; + } + +//Although, this looks like it's OK... (even if it is shitty!) +//According to JTRM, this is part of the four things the blitter does with the write data (the other +//three being PATDSEL, ADDDSEL, and LFU (default). I'm not sure which gets precedence, this or PATDSEL +//(see above blit example)... + if (GOURD) + writedata = ((gd_c[colour_index]) << 8) | (gd_i[colour_index] >> 16); + + if (SRCSHADE) + { + int intensity = srcdata & 0xFF; + int ia = gd_ia >> 16; + if (ia & 0x80) + ia = 0xFFFFFF00 | ia; + intensity += ia; + if (intensity < 0) + intensity = 0; + if (intensity > 0xFF) + intensity = 0xFF; + writedata = (srcdata & 0xFF00) | intensity; + } + } + else + { + writedata = dstdata; + srczdata = dstzdata; + } + +//Tried 2nd below for Hover Strike: No dice. + if (/*a1_phrase_mode || */BKGWREN || !inhibit) +// if (/*a1_phrase_mode || BKGWREN ||*/ !inhibit) + { +/*if (((REG(A1_FLAGS) >> 3) & 0x07) == 5) +{ + uint32_t offset = a1_addr+(PIXEL_OFFSET_32(a1)<<2); +// (((((uint32_t)a##_y >> 16) * a##_width) + (((uint32_t)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 16) & 1)) + if ((offset >= 0x1FF020 && offset <= 0x1FF03F) || (offset >= 0x1FF820 && offset <= 0x1FF83F)) + WriteLog("32bpp pixel write: A1 Phrase mode --> "); +}//*/ + // write to the destination + WRITE_PIXEL(a1, REG(A1_FLAGS), writedata); + if (DSTWRZ) + WRITE_ZDATA(a1, REG(A1_FLAGS), srczdata); + } + } + else // if (DSTA2) // Data movement: A1 -> A2 + { + // load src data and Z + if (SRCEN) + { + srcdata = READ_PIXEL(a1, REG(A1_FLAGS)); + if (SRCENZ) + srczdata = READ_ZDATA(a1, REG(A1_FLAGS)); + else if (cmd & 0x0001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ + srczdata = READ_RDATA(SRCZINT, a1, REG(A1_FLAGS), a1_phrase_mode); + } + else + { + srcdata = READ_RDATA(SRCDATA, a1, REG(A1_FLAGS), a1_phrase_mode); + if (cmd & 0x001C020) // PATDSEL | TOPBEN | TOPNEN | DSTWRZ + srczdata = READ_RDATA(SRCZINT, a1, REG(A1_FLAGS), a1_phrase_mode); + } + + // load dst data and Z + if (DSTEN) + { + dstdata = READ_PIXEL(a2, REG(A2_FLAGS)); + if (DSTENZ) + dstzdata = READ_ZDATA(a2, REG(A2_FLAGS)); + else + dstzdata = READ_RDATA(DSTZ, a2, REG(A2_FLAGS), a2_phrase_mode); + } + else + { + dstdata = READ_RDATA(DSTDATA, a2, REG(A2_FLAGS), a2_phrase_mode); + if (DSTENZ) + dstzdata = READ_RDATA(DSTZ, a2, REG(A2_FLAGS), a2_phrase_mode); + } + + if (GOURZ) + srczdata = z_i[colour_index] >> 16; + + // apply z comparator + if (Z_OP_INF && srczdata < dstzdata) inhibit = 1; + if (Z_OP_EQU && srczdata == dstzdata) inhibit = 1; + if (Z_OP_SUP && srczdata > dstzdata) inhibit = 1; + + // apply data comparator +//NOTE: The bit comparator (BCOMPEN) is NOT the same at the data comparator! + if (DCOMPEN | BCOMPEN) + { + if (!CMPDST) + { + // compare source pixel with pattern pixel +// AvP: Numbers are correct, but sprites are not! +//This doesn't seem to be a problem... But could still be wrong... +/* if (srcdata == READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode)) +// if (srcdata != READ_RDATA(PATTERNDATA, a1, REG(A1_FLAGS), a1_phrase_mode)) + inhibit = 1;//*/ +// This is probably not 100% correct... It works in the 1bpp case +// (in A1 <- A2 mode, that is...) +// AvP: This is causing blocks to be written instead of bit patterns... +// Works now... +// NOTE: We really should separate out the BCOMPEN & DCOMPEN stuff! +/* uint32_t A1bpp = 1 << ((REG(A1_FLAGS) >> 3) & 0x07); + if (A1bpp == 1 || A1bpp == 16 || A1bpp == 8) + inhibit = (srcdata == 0 ? 1: 0); + else + WriteLog("Blitter: Bad BPP (%u) selected for BCOMPEN mode!\n", A1bpp);//*/ +// What it boils down to is this: + if (srcdata == 0) + inhibit = 1;//*/ + } + else + { + // compare destination pixel with pattern pixel + if (dstdata == READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode)) +// if (dstdata != READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode)) + inhibit = 1; + } + +// This is DEFINITELY WRONG +// if (a1_phrase_mode || a2_phrase_mode) +// inhibit = !inhibit; + } + + if (CLIPA1) + { + inhibit |= (((a1_x >> 16) < a1_clip_x && (a1_x >> 16) >= 0 + && (a1_y >> 16) < a1_clip_y && (a1_y >> 16) >= 0) ? 0 : 1); + } + + // compute the write data and store + if (!inhibit) + { + if (PATDSEL) + { + // use pattern data for write data + writedata = READ_RDATA(PATTERNDATA, a2, REG(A2_FLAGS), a2_phrase_mode); + } + else if (ADDDSEL) + { + // intensity addition + writedata = (srcdata & 0xFF) + (dstdata & 0xFF); + if (!(TOPBEN) && writedata > 0xFF) + writedata = 0xFF; + writedata |= (srcdata & 0xF00) + (dstdata & 0xF00); + if (!(TOPNEN) && writedata > 0xFFF) + writedata = 0xFFF; + writedata |= (srcdata & 0xF000) + (dstdata & 0xF000); + } + else + { + if (LFU_NAN) + writedata |= ~srcdata & ~dstdata; + if (LFU_NA) + writedata |= ~srcdata & dstdata; + if (LFU_AN) + writedata |= srcdata & ~dstdata; + if (LFU_A) + writedata |= srcdata & dstdata; + } + + if (GOURD) + writedata = ((gd_c[colour_index]) << 8) | (gd_i[colour_index] >> 16); + + if (SRCSHADE) + { + int intensity = srcdata & 0xFF; + int ia = gd_ia >> 16; + if (ia & 0x80) + ia = 0xFFFFFF00 | ia; + intensity += ia; + if (intensity < 0) + intensity = 0; + if (intensity > 0xFF) + intensity = 0xFF; + writedata = (srcdata & 0xFF00) | intensity; + } + } + else + { + writedata = dstdata; + srczdata = dstzdata; + } + + if (/*a2_phrase_mode || */BKGWREN || !inhibit) + { +/*if (logGo) +{ + uint32_t offset = a2_addr+(PIXEL_OFFSET_16(a2)<<1); +// (((((uint32_t)a##_y >> 16) * a##_width) + (((uint32_t)a##_x >> 16) & ~1)) * (1 + a##_pitch) + (((uint32_t)a##_x >> 16) & 1)) + WriteLog("[%08X:%04X] ", offset, writedata); +}//*/ + // write to the destination + WRITE_PIXEL(a2, REG(A2_FLAGS), writedata); + + if (DSTWRZ) + WRITE_ZDATA(a2, REG(A2_FLAGS), srczdata); + } + } + + // Update x and y (inner loop) +//Now it does! But crappy, crappy, crappy! !!! FIX !!! [DONE] +//This is less than ideal, but it works... + if (!BCOMPEN) + {//*/ + a1_x += a1_xadd, a1_y += a1_yadd; + a2_x = (a2_x + a2_xadd) & a2_mask_x, a2_y = (a2_y + a2_yadd) & a2_mask_y; + } + else + { + a1_y += a1_yadd, a2_y = (a2_y + a2_yadd) & a2_mask_y; + if (!DSTA2) + { + a1_x += a1_xadd; + if (bitPos % bppSrc == 0) + a2_x = (a2_x + a2_xadd) & a2_mask_x; + } + else + { + a2_x = (a2_x + a2_xadd) & a2_mask_x; + if (bitPos % bppSrc == 0) + a1_x += a1_xadd; + } + }//*/ + + if (GOURZ) + z_i[colour_index] += zadd; + + if (GOURD || SRCSHADE) + { + gd_i[colour_index] += gd_ia; +//Hmm, this doesn't seem to do anything... +//But it is correct according to the JTRM...! +if ((int32_t)gd_i[colour_index] < 0) + gd_i[colour_index] = 0; +if (gd_i[colour_index] > 0x00FFFFFF) + gd_i[colour_index] = 0x00FFFFFF;//*/ + + gd_c[colour_index] += gd_ca; +if ((int32_t)gd_c[colour_index] < 0) + gd_c[colour_index] = 0; +if (gd_c[colour_index] > 0x000000FF) + gd_c[colour_index] = 0x000000FF;//*/ + } + + if (GOURD || SRCSHADE || GOURZ) + { + if (a1_phrase_mode) +//This screws things up WORSE (for the BIOS opening screen) +// if (a1_phrase_mode || a2_phrase_mode) + colour_index = (colour_index + 1) & 0x03; + } + } + +/* +Here's the problem... The phrase mode code! +Blit! (00100000 -> 00148000) count: 327 x 267, A1/2_FLAGS: 00004420/00004420 [cmd: 41802E01] + CMD -> src: SRCEN dst: misc: a1ctl: UPDA1 UPDA2 mode: DSTA2 GOURZ ity: z-op: op: LFU_REPLACE ctrl: SRCSHADE + A1 step values: -327 (X), 1 (Y) + A2 step values: -327 (X), 1 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 384 (22), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 28/58, A2 x/y: 28/58 Pattern: 00EA7BEA77EA77EA SRCDATA: 7BFF7BFF7BFF7BFF + +Below fixes it, but then borks: +; O + +Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -15 (X), 1 (Y) + A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 173/144, A2 x/y: 4052/0 + +Lesse, with pre-add we'd have: + + oooooooooooo +00001111222233334444555566667777 + ^ ^starts here... + | ^ends here. + |rolls back to here. Hmm. + +*/ +//NOTE: The way to fix the CD BIOS is to uncomment below and comment the stuff after +// the phrase mode mucking around. But it fucks up everything else... +//#define SCREWY_CD_DEPENDENT +#ifdef SCREWY_CD_DEPENDENT + a1_x += a1_step_x; + a1_y += a1_step_y; + a2_x += a2_step_x; + a2_y += a2_step_y;//*/ +#endif + + //New: Phrase mode taken into account! :-p +/* if (a1_phrase_mode) // v1 + { + // Bump the pointer to the next phrase boundary + // Even though it works, this is crappy... Clean it up! + uint32_t size = 64 / a1_psize; + + // Crappy kludge... ('aligning' source to destination) + if (a2_phrase_mode && DSTA2) + { + uint32_t extra = (a2_start >> 16) % size; + a1_x += extra << 16; + } + + uint32_t newx = (a1_x >> 16) / size; + uint32_t newxrem = (a1_x >> 16) % size; + a1_x &= 0x0000FFFF; + a1_x |= (((newx + (newxrem == 0 ? 0 : 1)) * size) & 0xFFFF) << 16; + }//*/ + if (a1_phrase_mode) // v2 + { + // Bump the pointer to the next phrase boundary + // Even though it works, this is crappy... Clean it up! + uint32_t size = 64 / a1_psize; + + // Crappy kludge... ('aligning' source to destination) + if (a2_phrase_mode && DSTA2) + { + uint32_t extra = (a2_start >> 16) % size; + a1_x += extra << 16; + } + + uint32_t pixelSize = (size - 1) << 16; + a1_x = (a1_x + pixelSize) & ~pixelSize; + } + +/* if (a2_phrase_mode) // v1 + { + // Bump the pointer to the next phrase boundary + // Even though it works, this is crappy... Clean it up! + uint32_t size = 64 / a2_psize; + + // Crappy kludge... ('aligning' source to destination) + // Prolly should do this for A1 channel as well... [DONE] + if (a1_phrase_mode && !DSTA2) + { + uint32_t extra = (a1_start >> 16) % size; + a2_x += extra << 16; + } + + uint32_t newx = (a2_x >> 16) / size; + uint32_t newxrem = (a2_x >> 16) % size; + a2_x &= 0x0000FFFF; + a2_x |= (((newx + (newxrem == 0 ? 0 : 1)) * size) & 0xFFFF) << 16; + }//*/ + if (a2_phrase_mode) // v1 + { + // Bump the pointer to the next phrase boundary + // Even though it works, this is crappy... Clean it up! + uint32_t size = 64 / a2_psize; + + // Crappy kludge... ('aligning' source to destination) + // Prolly should do this for A1 channel as well... [DONE] + if (a1_phrase_mode && !DSTA2) + { + uint32_t extra = (a1_start >> 16) % size; + a2_x += extra << 16; + } + + uint32_t pixelSize = (size - 1) << 16; + a2_x = (a2_x + pixelSize) & ~pixelSize; + } + + //Not entirely: This still mucks things up... !!! FIX !!! + //Should this go before or after the phrase mode mucking around? +#ifndef SCREWY_CD_DEPENDENT + a1_x += a1_step_x; + a1_y += a1_step_y; + a2_x += a2_step_x; + a2_y += a2_step_y;//*/ +#endif + } + + // write values back to registers + WREG(A1_PIXEL, (a1_y & 0xFFFF0000) | ((a1_x >> 16) & 0xFFFF)); + WREG(A1_FPIXEL, (a1_y << 16) | (a1_x & 0xFFFF)); + WREG(A2_PIXEL, (a2_y & 0xFFFF0000) | ((a2_x >> 16) & 0xFFFF)); +specialLog = false; +} + +void blitter_blit(uint32_t cmd) +{ +//Apparently this is doing *something*, just not sure exactly what... +/*if (cmd == 0x41802E01) +{ + WriteLog("BLIT: Found our blit. Was: %08X ", cmd); + cmd = 0x01800E01; + WriteLog("Is: %08X\n", cmd); +}//*/ + + uint32_t pitchValue[4] = { 0, 1, 3, 2 }; + colour_index = 0; + src = cmd & 0x07; + dst = (cmd >> 3) & 0x07; + misc = (cmd >> 6) & 0x03; + a1ctl = (cmd >> 8) & 0x7; + mode = (cmd >> 11) & 0x07; + ity = (cmd >> 14) & 0x0F; + zop = (cmd >> 18) & 0x07; + op = (cmd >> 21) & 0x0F; + ctrl = (cmd >> 25) & 0x3F; + + // Addresses in A1/2_BASE are *phrase* aligned, i.e., bottom three bits are ignored! + // NOTE: This fixes Rayman's bad collision detection AND keeps T2K working! + a1_addr = REG(A1_BASE) & 0xFFFFFFF8; + a2_addr = REG(A2_BASE) & 0xFFFFFFF8; + + a1_zoffs = (REG(A1_FLAGS) >> 6) & 7; + a2_zoffs = (REG(A2_FLAGS) >> 6) & 7; + + xadd_a1_control = (REG(A1_FLAGS) >> 16) & 0x03; + xadd_a2_control = (REG(A2_FLAGS) >> 16) & 0x03; + + a1_pitch = pitchValue[(REG(A1_FLAGS) & 0x03)]; + a2_pitch = pitchValue[(REG(A2_FLAGS) & 0x03)]; + + n_pixels = REG(PIXLINECOUNTER) & 0xFFFF; + n_lines = (REG(PIXLINECOUNTER) >> 16) & 0xFFFF; + + a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF); + a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16); +//According to the JTRM, X is restricted to 15 bits and Y is restricted to 12. +//But it seems to fuck up T2K! !!! FIX !!! +//Could it be sign extended??? Doesn't seem to be so according to JTRM +// a1_x &= 0x7FFFFFFF, a1_y &= 0x0FFFFFFF; +//Actually, it says that the X is 16 bits. But it still seems to mess with the Y when restricted to 12... +// a1_y &= 0x0FFFFFFF; + +// a1_width = blitter_scanline_width[((REG(A1_FLAGS) & 0x00007E00) >> 9)]; +// According to JTRM, this must give a *whole number* of phrases in the current +// pixel size (this means the lookup above is WRONG)... !!! FIX !!! + uint32_t m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F; + a1_width = ((0x04 | m) << e) >> 2;//*/ + + a2_x = (REG(A2_PIXEL) & 0x0000FFFF) << 16; + a2_y = (REG(A2_PIXEL) & 0xFFFF0000); +//According to the JTRM, X is restricted to 15 bits and Y is restricted to 12. +//But it seems to fuck up T2K! !!! FIX !!! +// a2_x &= 0x7FFFFFFF, a2_y &= 0x0FFFFFFF; +//Actually, it says that the X is 16 bits. But it still seems to mess with the Y when restricted to 12... +// a2_y &= 0x0FFFFFFF; + +// a2_width = blitter_scanline_width[((REG(A2_FLAGS) & 0x00007E00) >> 9)]; +// According to JTRM, this must give a *whole number* of phrases in the current +// pixel size (this means the lookup above is WRONG)... !!! FIX !!! + m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F; + a2_width = ((0x04 | m) << e) >> 2;//*/ + a2_mask_x = ((REG(A2_MASK) & 0x0000FFFF) << 16) | 0xFFFF; + a2_mask_y = (REG(A2_MASK) & 0xFFFF0000) | 0xFFFF; + + // Check for "use mask" flag + if (!(REG(A2_FLAGS) & 0x8000)) + { + a2_mask_x = 0xFFFFFFFF; // must be 16.16 + a2_mask_y = 0xFFFFFFFF; // must be 16.16 + } + + a1_phrase_mode = 0; + + // According to the official documentation, a hardware bug ties A2's yadd bit to A1's... + a2_yadd = a1_yadd = (YADD1_A1 ? 1 << 16 : 0); + + if (YSIGNSUB_A1) + a1_yadd = -a1_yadd; + + // determine a1_xadd + switch (xadd_a1_control) + { + case XADDPHR: +// This is a documented Jaguar bug relating to phrase mode and truncation... Look into it! + // add phrase offset to X and truncate + a1_xadd = 1 << 16; + a1_phrase_mode = 1; + break; + case XADDPIX: + // add pixelsize (1) to X + a1_xadd = 1 << 16; + break; + case XADD0: + // add zero (for those nice vertical lines) + a1_xadd = 0; + break; + case XADDINC: + // add the contents of the increment register + a1_xadd = (REG(A1_INC) << 16) | (REG(A1_FINC) & 0x0000FFFF); + a1_yadd = (REG(A1_INC) & 0xFFFF0000) | (REG(A1_FINC) >> 16); + break; + } + + +//Blit! (0011D000 -> 000B9600) count: 228 x 1, A1/2_FLAGS: 00073820/00064220 [cmd: 41802801] +// A1 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 128 (1C), addctl: XADDINC YADD1 XSIGNADD YSIGNADD +// A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 320 (21), addctl: XADD0 YADD1 XSIGNADD YSIGNADD +//if (YADD1_A1 && YADD1_A2 && xadd_a2_control == XADD0 && xadd_a1_control == XADDINC)// && +// uint32_t a1f = REG(A1_FLAGS), a2f = REG(A2_FLAGS); +//Ok, so this ISN'T it... Prolly the XADDPHR code above that's doing it... +//if (REG(A1_FLAGS) == 0x00073820 && REG(A2_FLAGS) == 0x00064220 && cmd == 0x41802801) +// A1 x/y: 14368/7, A2 x/y: 150/36 +//This is it... The problem... +//if ((a1_x >> 16) == 14368) // 14368 = $3820 +// return; //Lesse what we got... + + if (XSIGNSUB_A1) + a1_xadd = -a1_xadd; + + if (YSIGNSUB_A2) + a2_yadd = -a2_yadd; + + a2_phrase_mode = 0; + + // determine a2_xadd + switch (xadd_a2_control) + { + case XADDPHR: + // add phrase offset to X and truncate + a2_xadd = 1 << 16; + a2_phrase_mode = 1; + break; + case XADDPIX: + // add pixelsize (1) to X + a2_xadd = 1 << 16; + break; + case XADD0: + // add zero (for those nice vertical lines) + a2_xadd = 0; + break; +//This really isn't a valid bit combo for A2... Shouldn't this cause the blitter to just say no? + case XADDINC: +WriteLog("BLIT: Asked to use invalid bit combo (XADDINC) for A2...\n"); + // add the contents of the increment register + // since there is no register for a2 we just add 1 +//Let's do nothing, since it's not listed as a valid bit combo... +// a2_xadd = 1 << 16; + break; + } + + if (XSIGNSUB_A2) + a2_xadd = -a2_xadd; + + // Modify outer loop steps based on blitter command + + a1_step_x = 0; + a1_step_y = 0; + a2_step_x = 0; + a2_step_y = 0; + + if (UPDA1F) + a1_step_x = (REG(A1_FSTEP) & 0xFFFF), + a1_step_y = (REG(A1_FSTEP) >> 16); + + if (UPDA1) + a1_step_x |= ((REG(A1_STEP) & 0x0000FFFF) << 16), + a1_step_y |= ((REG(A1_STEP) & 0xFFFF0000)); + + if (UPDA2) + a2_step_x = (REG(A2_STEP) & 0x0000FFFF) << 16, + a2_step_y = (REG(A2_STEP) & 0xFFFF0000); + + outer_loop = n_lines; + + // Clipping... + + if (CLIPA1) + a1_clip_x = REG(A1_CLIP) & 0x7FFF, + a1_clip_y = (REG(A1_CLIP) >> 16) & 0x7FFF; + +// This phrase sizing is incorrect as well... !!! FIX !!! [NOTHING TO FIX] +// Err, this is pixel size... (and it's OK) + a2_psize = 1 << ((REG(A2_FLAGS) >> 3) & 0x07); + a1_psize = 1 << ((REG(A1_FLAGS) >> 3) & 0x07); + + // Z-buffering + if (GOURZ) + { + zadd = REG(ZINC); + + for(int v=0; v<4; v++) + z_i[v] = REG(PHRASEZ0 + v*4); + } + + // Gouraud shading + if (GOURD || GOURZ || SRCSHADE) + { + gd_c[0] = blitter_ram[PATTERNDATA + 6]; + gd_i[0] = ((uint32_t)blitter_ram[PATTERNDATA + 7] << 16) + | ((uint32_t)blitter_ram[SRCDATA + 6] << 8) | blitter_ram[SRCDATA + 7]; + + gd_c[1] = blitter_ram[PATTERNDATA + 4]; + gd_i[1] = ((uint32_t)blitter_ram[PATTERNDATA + 5] << 16) + | ((uint32_t)blitter_ram[SRCDATA + 4] << 8) | blitter_ram[SRCDATA + 5]; + + gd_c[2] = blitter_ram[PATTERNDATA + 2]; + gd_i[2] = ((uint32_t)blitter_ram[PATTERNDATA + 3] << 16) + | ((uint32_t)blitter_ram[SRCDATA + 2] << 8) | blitter_ram[SRCDATA + 3]; + + gd_c[3] = blitter_ram[PATTERNDATA + 0]; + gd_i[3] = ((uint32_t)blitter_ram[PATTERNDATA + 1] << 16) + | ((uint32_t)blitter_ram[SRCDATA + 0] << 8) | blitter_ram[SRCDATA + 1]; + + gouraud_add = REG(INTENSITYINC); + + gd_ia = gouraud_add & 0x00FFFFFF; + if (gd_ia & 0x00800000) + gd_ia = 0xFF000000 | gd_ia; + + gd_ca = (gouraud_add >> 24) & 0xFF; + if (gd_ca & 0x00000080) + gd_ca = 0xFFFFFF00 | gd_ca; + } + + // Bit comparitor fixing... +/* if (BCOMPEN) + { + // Determine the data flow direction... + if (!DSTA2) + a2_step_x /= (1 << ((REG(A2_FLAGS) >> 3) & 0x07)); + else + ;//add this later + }//*/ +/* if (BCOMPEN)//Kludge for Hover Strike... !!! FIX !!! + { + // Determine the data flow direction... + if (!DSTA2) + a2_x <<= 3; + }//*/ + +#ifdef LOG_BLITS + if (start_logging) + { + WriteLog("Blit!\n"); + WriteLog(" cmd = 0x%.8x\n",cmd); + WriteLog(" a1_base = %08X\n", a1_addr); + WriteLog(" a1_pitch = %d\n", a1_pitch); + WriteLog(" a1_psize = %d\n", a1_psize); + WriteLog(" a1_width = %d\n", a1_width); + WriteLog(" a1_xadd = %f (phrase=%d)\n", (float)a1_xadd / 65536.0, a1_phrase_mode); + WriteLog(" a1_yadd = %f\n", (float)a1_yadd / 65536.0); + WriteLog(" a1_xstep = %f\n", (float)a1_step_x / 65536.0); + WriteLog(" a1_ystep = %f\n", (float)a1_step_y / 65536.0); + WriteLog(" a1_x = %f\n", (float)a1_x / 65536.0); + WriteLog(" a1_y = %f\n", (float)a1_y / 65536.0); + WriteLog(" a1_zoffs = %i\n",a1_zoffs); + + WriteLog(" a2_base = %08X\n", a2_addr); + WriteLog(" a2_pitch = %d\n", a2_pitch); + WriteLog(" a2_psize = %d\n", a2_psize); + WriteLog(" a2_width = %d\n", a2_width); + WriteLog(" a2_xadd = %f (phrase=%d)\n", (float)a2_xadd / 65536.0, a2_phrase_mode); + WriteLog(" a2_yadd = %f\n", (float)a2_yadd / 65536.0); + WriteLog(" a2_xstep = %f\n", (float)a2_step_x / 65536.0); + WriteLog(" a2_ystep = %f\n", (float)a2_step_y / 65536.0); + WriteLog(" a2_x = %f\n", (float)a2_x / 65536.0); + WriteLog(" a2_y = %f\n", (float)a2_y / 65536.0); + WriteLog(" a2_mask_x= 0x%.4x\n",a2_mask_x); + WriteLog(" a2_mask_y= 0x%.4x\n",a2_mask_y); + WriteLog(" a2_zoffs = %i\n",a2_zoffs); + + WriteLog(" count = %d x %d\n", n_pixels, n_lines); + + WriteLog(" command = %08X\n", cmd); + WriteLog(" dsten = %i\n",DSTEN); + WriteLog(" srcen = %i\n",SRCEN); + WriteLog(" patdsel = %i\n",PATDSEL); + WriteLog(" color = 0x%.8x\n",REG(PATTERNDATA)); + WriteLog(" dcompen = %i\n",DCOMPEN); + WriteLog(" bcompen = %i\n",BCOMPEN); + WriteLog(" cmpdst = %i\n",CMPDST); + WriteLog(" GOURZ = %i\n",GOURZ); + WriteLog(" GOURD = %i\n",GOURD); + WriteLog(" SRCSHADE= %i\n",SRCSHADE); + } +#endif + +//NOTE: Pitch is ignored! + +//This *might* be the altimeter blits (they are)... +//On captured screen, x-pos for black (inner) is 259, for pink is 257 +//Black is short by 3, pink is short by 1... +/* +Blit! (00110000 <- 000BF010) count: 9 x 31, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 262/124, A2 x/y: 128/0 +Blit! (00110000 <- 000BF010) count: 5 x 38, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 264/117, A2 x/y: 407/0 + +Blit! (00110000 <- 000BF010) count: 9 x 23, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 step values: -10 (X), 1 (Y) + A1 -> pitch: 4(2) phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1(0) phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 262/132, A2 x/y: 129/0 +Blit! (00110000 <- 000BF010) count: 5 x 27, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 step values: -8 (X), 1 (Y) + A1 -> pitch: 4(2) phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1(0) phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 264/128, A2 x/y: 336/0 + + 264v vCursor ends up here... + xxxxx...` + 111122223333 + +262v vCursor ends up here... + xxxxxxxxx.' + 1111222233334444 + +Fixed! Now for more: + +; This looks like the ship icon in the upper left corner... + +Blit! (00110000 <- 0010B2A8) count: 11 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -12 (X), 1 (Y) + A2 step values: 0 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 20/24, A2 x/y: 5780/0 + +Also fixed! + +More (not sure this is a blitter problem as much as it's a GPU problem): +All but the "M" are trashed... +This does *NOT* look like a blitter problem, as it's rendering properly... +Actually, if you look at the A1 step values, there IS a discrepancy! + +; D + +Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -14 (X), 1 (Y) + A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 134/144, A2 x/y: 2516/0 +;129,146: +5,-2 + +; E + +Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -13 (X), 1 (Y) + A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 147/144, A2 x/y: 2660/0 + +; M + +Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -12 (X), 1 (Y) + A2 step values: 0 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 160/144, A2 x/y: 3764/0 + +; O + +Blit! (00110000 <- 0010B2A8) count: 12 x 12, A1/2_FLAGS: 000042E2/00000020 [cmd: 09800609] + CMD -> src: SRCEN dst: DSTEN misc: a1ctl: UPDA1 UPDA2 mode: ity: z-op: op: LFU_REPLACE ctrl: DCOMPEN + A1 step values: -15 (X), 1 (Y) + A2 step values: -4 (X), 0 (Y) [mask (unused): 00000000 - FFFFFFFF/FFFFFFFF] + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A1 x/y: 173/144, A2 x/y: 4052/0 + +*/ +//extern int op_start_log; +if (blit_start_log) +{ + const char * ctrlStr[4] = { "XADDPHR\0", "XADDPIX\0", "XADD0\0", "XADDINC\0" }; + const char * bppStr[8] = { "1bpp\0", "2bpp\0", "4bpp\0", "8bpp\0", "16bpp\0", "32bpp\0", "???\0", "!!!\0" }; + const char * opStr[16] = { "LFU_CLEAR", "LFU_NSAND", "LFU_NSAD", "LFU_NOTS", "LFU_SAND", "LFU_NOTD", "LFU_N_SXORD", "LFU_NSORND", + "LFU_SAD", "LFU_XOR", "LFU_D", "LFU_NSORD", "LFU_REPLACE", "LFU_SORND", "LFU_SORD", "LFU_ONE" }; + uint32_t /*src = cmd & 0x07, dst = (cmd >> 3) & 0x07, misc = (cmd >> 6) & 0x03, + a1ctl = (cmd >> 8) & 0x07,*/ mode = (cmd >> 11) & 0x07/*, ity = (cmd >> 14) & 0x0F, + zop = (cmd >> 18) & 0x07, op = (cmd >> 21) & 0x0F, ctrl = (cmd >> 25) & 0x3F*/; + uint32_t a1f = REG(A1_FLAGS), a2f = REG(A2_FLAGS); + uint32_t p1 = a1f & 0x07, p2 = a2f & 0x07, + d1 = (a1f >> 3) & 0x07, d2 = (a2f >> 3) & 0x07, + zo1 = (a1f >> 6) & 0x07, zo2 = (a2f >> 6) & 0x07, + w1 = (a1f >> 9) & 0x3F, w2 = (a2f >> 9) & 0x3F, + ac1 = (a1f >> 16) & 0x1F, ac2 = (a2f >> 16) & 0x1F; + uint32_t iw1 = ((0x04 | (w1 & 0x03)) << ((w1 & 0x3C) >> 2)) >> 2; + uint32_t iw2 = ((0x04 | (w2 & 0x03)) << ((w2 & 0x3C) >> 2)) >> 2; + WriteLog("Blit! (%08X %s %08X) count: %d x %d, A1/2_FLAGS: %08X/%08X [cmd: %08X]\n", a1_addr, (mode&0x01 ? "->" : "<-"), a2_addr, n_pixels, n_lines, a1f, a2f, cmd); +// WriteLog(" CMD -> src: %d, dst: %d, misc: %d, a1ctl: %d, mode: %d, ity: %1X, z-op: %d, op: %1X, ctrl: %02X\n", src, dst, misc, a1ctl, mode, ity, zop, op, ctrl); + + WriteLog(" CMD -> src: %s%s%s ", (cmd & 0x0001 ? "SRCEN " : ""), (cmd & 0x0002 ? "SRCENZ " : ""), (cmd & 0x0004 ? "SRCENX" : "")); + WriteLog("dst: %s%s%s ", (cmd & 0x0008 ? "DSTEN " : ""), (cmd & 0x0010 ? "DSTENZ " : ""), (cmd & 0x0020 ? "DSTWRZ" : "")); + WriteLog("misc: %s%s ", (cmd & 0x0040 ? "CLIP_A1 " : ""), (cmd & 0x0080 ? "???" : "")); + WriteLog("a1ctl: %s%s%s ", (cmd & 0x0100 ? "UPDA1F " : ""), (cmd & 0x0200 ? "UPDA1 " : ""), (cmd & 0x0400 ? "UPDA2" : "")); + WriteLog("mode: %s%s%s ", (cmd & 0x0800 ? "DSTA2 " : ""), (cmd & 0x1000 ? "GOURD " : ""), (cmd & 0x2000 ? "GOURZ" : "")); + WriteLog("ity: %s%s%s%s ", (cmd & 0x4000 ? "TOPBEN " : ""), (cmd & 0x8000 ? "TOPNEN " : ""), (cmd & 0x00010000 ? "PATDSEL" : ""), (cmd & 0x00020000 ? "ADDDSEL" : "")); + WriteLog("z-op: %s%s%s ", (cmd & 0x00040000 ? "ZMODELT " : ""), (cmd & 0x00080000 ? "ZMODEEQ " : ""), (cmd & 0x00100000 ? "ZMODEGT" : "")); + WriteLog("op: %s ", opStr[(cmd >> 21) & 0x0F]); + WriteLog("ctrl: %s%s%s%s%s%s\n", (cmd & 0x02000000 ? "CMPDST " : ""), (cmd & 0x04000000 ? "BCOMPEN " : ""), (cmd & 0x08000000 ? "DCOMPEN " : ""), (cmd & 0x10000000 ? "BKGWREN " : ""), (cmd & 0x20000000 ? "BUSHI " : ""), (cmd & 0x40000000 ? "SRCSHADE" : "")); + + if (UPDA1) + WriteLog(" A1 step values: %d (X), %d (Y)\n", a1_step_x >> 16, a1_step_y >> 16); + + if (UPDA2) + WriteLog(" A2 step values: %d (X), %d (Y) [mask (%sused): %08X - %08X/%08X]\n", a2_step_x >> 16, a2_step_y >> 16, (a2f & 0x8000 ? "" : "un"), REG(A2_MASK), a2_mask_x, a2_mask_y); + + WriteLog(" A1 -> pitch: %d phrases, depth: %s, z-off: %d, width: %d (%02X), addctl: %s %s %s %s\n", 1 << p1, bppStr[d1], zo1, iw1, w1, ctrlStr[ac1&0x03], (ac1&0x04 ? "YADD1" : "YADD0"), (ac1&0x08 ? "XSIGNSUB" : "XSIGNADD"), (ac1&0x10 ? "YSIGNSUB" : "YSIGNADD")); + WriteLog(" A2 -> pitch: %d phrases, depth: %s, z-off: %d, width: %d (%02X), addctl: %s %s %s %s\n", 1 << p2, bppStr[d2], zo2, iw2, w2, ctrlStr[ac2&0x03], (ac2&0x04 ? "YADD1" : "YADD0"), (ac2&0x08 ? "XSIGNSUB" : "XSIGNADD"), (ac2&0x10 ? "YSIGNSUB" : "YSIGNADD")); + WriteLog(" A1 x/y: %d/%d, A2 x/y: %d/%d Pattern: %08X%08X SRCDATA: %08X%08X\n", a1_x >> 16, a1_y >> 16, a2_x >> 16, a2_y >> 16, REG(PATTERNDATA), REG(PATTERNDATA + 4), REG(SRCDATA), REG(SRCDATA + 4)); +// blit_start_log = 0; +// op_start_log = 1; +} + + blitter_working = 1; +//#ifndef USE_GENERIC_BLITTER +// if (!blitter_execute_cached_code(blitter_in_cache(cmd))) +//#endif + blitter_generic(cmd); + +/*if (blit_start_log) +{ + if (a1_addr == 0xF03000 && a2_addr == 0x004D58) + { + WriteLog("\nBytes at 004D58:\n"); + for(int i=0x004D58; i<0x004D58+(10*127*4); i++) + WriteLog("%02X ", JaguarReadByte(i)); + WriteLog("\nBytes at F03000:\n"); + for(int i=0xF03000; i<0xF03000+(6*127*4); i++) + WriteLog("%02X ", JaguarReadByte(i)); + WriteLog("\n\n"); + } +}//*/ + + blitter_working = 0; +} +#endif // of the #if 0 near the top... +/******************************************************************************* +********************** STUFF CUT ABOVE THIS LINE! ****************************** +*******************************************************************************/ + + +void BlitterInit(void) +{ + BlitterReset(); +} + + +void BlitterReset(void) +{ + memset(blitter_ram, 0x00, 0xA0); +} + + +void BlitterDone(void) +{ + WriteLog("BLIT: Done.\n"); +} + + +uint8_t BlitterReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0xFF; + + // status register +//This isn't cycle accurate--how to fix? !!! FIX !!! +//Probably have to do some multi-threaded implementation or at least a reentrant safe implementation... +//Real hardware returns $00000805, just like the JTRM says. + if (offset == (0x38 + 0)) + return 0x00; + if (offset == (0x38 + 1)) + return 0x00; + if (offset == (0x38 + 2)) + return 0x08; + if (offset == (0x38 + 3)) + return 0x05; // always idle/never stopped (collision detection ignored!) + +// CHECK HERE ONCE THIS FIX HAS BEEN TESTED: [X] +//Fix for AvP: + if (offset >= 0x04 && offset <= 0x07) +//This is it. I wonder if it just ignores the lower three bits? +//No, this is a documented Jaguar I bug. It also bites the read at $F02230 as well... + return blitter_ram[offset + 0x08]; // A1_PIXEL ($F0220C) read at $F02204 + + if (offset >= 0x2C && offset <= 0x2F) + return blitter_ram[offset + 0x04]; // A2_PIXEL ($F02230) read at $F0222C + + return blitter_ram[offset]; +} + + +//Crappy! +uint16_t BlitterReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + return ((uint16_t)BlitterReadByte(offset, who) << 8) | (uint16_t)BlitterReadByte(offset+1, who); +} + + +//Crappy! +uint32_t BlitterReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + return (BlitterReadWord(offset, who) << 16) | BlitterReadWord(offset+2, who); +} + + +void BlitterWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ +/*if (offset & 0xFF == 0x7B) + WriteLog("--> Wrote to B_STOP: value -> %02X\n", data);*/ + offset &= 0xFF; +/*if ((offset >= PATTERNDATA) && (offset < PATTERNDATA + 8)) +{ + printf("--> %s wrote %02X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - PATTERNDATA); + fflush(stdout); +}//*/ + + // This handles writes to INTENSITY0-3 by also writing them to their proper places in + // PATTERNDATA & SOURCEDATA (should do the same for the Z registers! !!! FIX !!! [DONE]) + if ((offset >= 0x7C) && (offset <= 0x9B)) + { + switch (offset) + { + // INTENSITY registers 0-3 + case 0x7C: break; + case 0x7D: blitter_ram[PATTERNDATA + 7] = data; break; + case 0x7E: blitter_ram[SRCDATA + 6] = data; break; + case 0x7F: blitter_ram[SRCDATA + 7] = data; break; + + case 0x80: break; + case 0x81: blitter_ram[PATTERNDATA + 5] = data; break; + case 0x82: blitter_ram[SRCDATA + 4] = data; break; + case 0x83: blitter_ram[SRCDATA + 5] = data; break; + + case 0x84: break; + case 0x85: blitter_ram[PATTERNDATA + 3] = data; break; + case 0x86: blitter_ram[SRCDATA + 2] = data; break; + case 0x87: blitter_ram[SRCDATA + 3] = data; break; + + case 0x88: break; + case 0x89: blitter_ram[PATTERNDATA + 1] = data; break; + case 0x8A: blitter_ram[SRCDATA + 0] = data; break; + case 0x8B: blitter_ram[SRCDATA + 1] = data; break; + + + // Z registers 0-3 + case 0x8C: blitter_ram[SRCZINT + 6] = data; break; + case 0x8D: blitter_ram[SRCZINT + 7] = data; break; + case 0x8E: blitter_ram[SRCZFRAC + 6] = data; break; + case 0x8F: blitter_ram[SRCZFRAC + 7] = data; break; + + case 0x90: blitter_ram[SRCZINT + 4] = data; break; + case 0x91: blitter_ram[SRCZINT + 5] = data; break; + case 0x92: blitter_ram[SRCZFRAC + 4] = data; break; + case 0x93: blitter_ram[SRCZFRAC + 5] = data; break; + + case 0x94: blitter_ram[SRCZINT + 2] = data; break; + case 0x95: blitter_ram[SRCZINT + 3] = data; break; + case 0x96: blitter_ram[SRCZFRAC + 2] = data; break; + case 0x97: blitter_ram[SRCZFRAC + 3] = data; break; + + case 0x98: blitter_ram[SRCZINT + 0] = data; break; + case 0x99: blitter_ram[SRCZINT + 1] = data; break; + case 0x9A: blitter_ram[SRCZFRAC + 0] = data; break; + case 0x9B: blitter_ram[SRCZFRAC + 1] = data; break; + } + } + + // It looks weird, but this is how the 64 bit registers are actually handled...! + + else if ((offset >= SRCDATA + 0) && (offset <= SRCDATA + 3) + || (offset >= DSTDATA + 0) && (offset <= DSTDATA + 3) + || (offset >= DSTZ + 0) && (offset <= DSTZ + 3) + || (offset >= SRCZINT + 0) && (offset <= SRCZINT + 3) + || (offset >= SRCZFRAC + 0) && (offset <= SRCZFRAC + 3) + || (offset >= PATTERNDATA + 0) && (offset <= PATTERNDATA + 3)) + { + blitter_ram[offset + 4] = data; + } + else if ((offset >= SRCDATA + 4) && (offset <= SRCDATA + 7) + || (offset >= DSTDATA + 4) && (offset <= DSTDATA + 7) + || (offset >= DSTZ + 4) && (offset <= DSTZ + 7) + || (offset >= SRCZINT + 4) && (offset <= SRCZINT + 7) + || (offset >= SRCZFRAC + 4) && (offset <= SRCZFRAC + 7) + || (offset >= PATTERNDATA + 4) && (offset <= PATTERNDATA + 7)) + { + blitter_ram[offset - 4] = data; + } + else + blitter_ram[offset] = data; +} + + +void BlitterWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ +/*if (((offset & 0xFF) >= PATTERNDATA) && ((offset & 0xFF) < PATTERNDATA + 8)) +{ + printf("----> %s wrote %04X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - (0xF02200 + PATTERNDATA)); + fflush(stdout); +}*/ +//#if 1 +/* if (offset & 0xFF == A1_PIXEL && data == 14368) + { + WriteLog("\n1\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data); +extern bool doGPUDis; +doGPUDis = true; + } + if ((offset & 0xFF) == (A1_PIXEL + 2) && data == 14368) + { + WriteLog("\n2\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data); +extern bool doGPUDis; +doGPUDis = true; + }//*/ +//#endif + + BlitterWriteByte(offset + 0, data >> 8, who); + BlitterWriteByte(offset + 1, data & 0xFF, who); + + if ((offset & 0xFF) == 0x3A) + // I.e., the second write of 32-bit value--not convinced this is the best way to do this! + // But then again, according to the Jaguar docs, this is correct...! +/*extern int blit_start_log; +extern bool doGPUDis; +if (blit_start_log) +{ + WriteLog("BLIT: Blitter started by %s...\n", whoName[who]); + doGPUDis = true; +}//*/ +#ifndef USE_BOTH_BLITTERS +#ifdef USE_ORIGINAL_BLITTER + blitter_blit(GET32(blitter_ram, 0x38)); +#endif +#ifdef USE_MIDSUMMER_BLITTER + BlitterMidsummer(GET32(blitter_ram, 0x38)); +#endif +#ifdef USE_MIDSUMMER_BLITTER_MKII + BlitterMidsummer2(); +#endif +#else + { + if (vjs.useFastBlitter) + blitter_blit(GET32(blitter_ram, 0x38)); + else + BlitterMidsummer2(); + } +#endif +} +//F02278,9,A,B + + +void BlitterWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) +{ +/*if (((offset & 0xFF) >= PATTERNDATA) && ((offset & 0xFF) < PATTERNDATA + 8)) +{ + printf("------> %s wrote %08X to byte %u of PATTERNDATA...\n", whoName[who], data, offset - (0xF02200 + PATTERNDATA)); + fflush(stdout); +}//*/ +//#if 1 +/* if ((offset & 0xFF) == A1_PIXEL && (data & 0xFFFF) == 14368) + { + WriteLog("\n3\nA1_PIXEL written by %s (%u)...\n\n\n", whoName[who], data); +extern bool doGPUDis; +doGPUDis = true; + }//*/ +//#endif + + BlitterWriteWord(offset + 0, data >> 16, who); + BlitterWriteWord(offset + 2, data & 0xFFFF, who); +} + + +void LogBlit(void) +{ + const char * opStr[16] = { "LFU_CLEAR", "LFU_NSAND", "LFU_NSAD", "LFU_NOTS", "LFU_SAND", "LFU_NOTD", "LFU_N_SXORD", "LFU_NSORND", + "LFU_SAD", "LFU_XOR", "LFU_D", "LFU_NSORD", "LFU_REPLACE", "LFU_SORND", "LFU_SORD", "LFU_ONE" }; + uint32_t cmd = GET32(blitter_ram, 0x38); + uint32_t m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F; + uint32_t a1_width = ((0x04 | m) << e) >> 2; + m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F; + uint32_t a2_width = ((0x04 | m) << e) >> 2; + + WriteLog("Blit!\n"); + WriteLog(" COMMAND = %08X\n", cmd); + WriteLog(" a1_base = %08X\n", REG(A1_BASE)); + WriteLog(" a1_flags = %08X (%c %c %c %c%c . %c%c%c%c%c%c %c%c%c %c%c%c . %c%c)\n", REG(A1_FLAGS), + (REG(A1_FLAGS) & 0x100000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x080000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x040000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x020000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x010000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x004000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x002000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x001000 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000800 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000400 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000200 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000100 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000080 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000040 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000020 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000010 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000008 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000002 ? '1' : '0'), + (REG(A1_FLAGS) & 0x000001 ? '1' : '0')); + WriteLog(" pitch=%u, pixSz=%u, zOff=%u, width=%u, xCtrl=%u\n", + REG(A1_FLAGS) & 0x00003, (REG(A1_FLAGS) & 0x00038) >> 3, + (REG(A1_FLAGS) & 0x001C0) >> 6, a1_width, (REG(A1_FLAGS) & 0x30000) >> 16); + WriteLog(" a1_clip = %u, %u (%08X)\n", GET16(blitter_ram, A1_CLIP + 2), GET16(blitter_ram, A1_CLIP + 0), GET32(blitter_ram, A1_CLIP)); + WriteLog(" a1_pixel = %d, %d (%08X)\n", (int16_t)GET16(blitter_ram, A1_PIXEL + 2), (int16_t)GET16(blitter_ram, A1_PIXEL + 0), GET32(blitter_ram, A1_PIXEL)); + WriteLog(" a1_step = %d, %d (%08X)\n", (int16_t)GET16(blitter_ram, A1_STEP + 2), (int16_t)GET16(blitter_ram, A1_STEP + 0), GET32(blitter_ram, A1_STEP)); + WriteLog(" a1_fstep = %u, %u (%08X)\n", GET16(blitter_ram, A1_FSTEP + 2), GET16(blitter_ram, A1_FSTEP + 0), GET32(blitter_ram, A1_FSTEP)); + WriteLog(" a1_fpixel= %u, %u (%08X)\n", GET16(blitter_ram, A1_FPIXEL + 2), GET16(blitter_ram, A1_FPIXEL + 0), GET32(blitter_ram, A1_FPIXEL)); + WriteLog(" a1_inc = %d, %d (%08X)\n", (int16_t)GET16(blitter_ram, A1_INC + 2), (int16_t)GET16(blitter_ram, A1_INC + 0), GET32(blitter_ram, A1_INC)); + WriteLog(" a1_finc = %u, %u (%08X)\n", GET16(blitter_ram, A1_FINC + 2), GET16(blitter_ram, A1_FINC + 0), GET32(blitter_ram, A1_FINC)); + + WriteLog(" a2_base = %08X\n", REG(A2_BASE)); + WriteLog(" a2_flags = %08X (%c %c %c %c%c %c %c%c%c%c%c%c %c%c%c %c%c%c . %c%c)\n", REG(A2_FLAGS), + (REG(A2_FLAGS) & 0x100000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x080000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x040000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x020000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x010000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x008000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x004000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x002000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x001000 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000800 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000400 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000200 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000100 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000080 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000040 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000020 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000010 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000008 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000002 ? '1' : '0'), + (REG(A2_FLAGS) & 0x000001 ? '1' : '0')); + WriteLog(" pitch=%u, pixSz=%u, zOff=%u, width=%u, xCtrl=%u\n", + REG(A2_FLAGS) & 0x00003, (REG(A2_FLAGS) & 0x00038) >> 3, + (REG(A2_FLAGS) & 0x001C0) >> 6, a2_width, (REG(A2_FLAGS) & 0x30000) >> 16); + WriteLog(" a2_mask = %u, %u (%08X)\n", GET16(blitter_ram, A2_MASK + 2), GET16(blitter_ram, A2_MASK + 0), GET32(blitter_ram, A2_MASK)); + WriteLog(" a2_pixel = %d, %d (%08X)\n", (int16_t)GET16(blitter_ram, A2_PIXEL + 2), (int16_t)GET16(blitter_ram, A2_PIXEL + 0), GET32(blitter_ram, A2_PIXEL)); + WriteLog(" a2_step = %d, %d (%08X)\n", (int16_t)GET16(blitter_ram, A2_STEP + 2), (int16_t)GET16(blitter_ram, A2_STEP + 0), GET32(blitter_ram, A2_STEP)); + + WriteLog(" count = %d x %d\n", GET16(blitter_ram, PIXLINECOUNTER + 2), GET16(blitter_ram, PIXLINECOUNTER)); + + WriteLog(" SRCEN = %s\n", (SRCEN ? "1" : "0")); + WriteLog(" SRCENZ = %s\n", (SRCENZ ? "1" : "0")); + WriteLog(" SRCENX = %s\n", (SRCENX ? "1" : "0")); + WriteLog(" DSTEN = %s\n", (DSTEN ? "1" : "0")); + WriteLog(" DSTENZ = %s\n", (DSTENZ ? "1" : "0")); + WriteLog(" DSTWRZ = %s\n", (DSTWRZ ? "1" : "0")); + WriteLog(" CLIPA1 = %s\n", (CLIPA1 ? "1" : "0")); + WriteLog(" UPDA1F = %s\n", (UPDA1F ? "1" : "0")); + WriteLog(" UPDA1 = %s\n", (UPDA1 ? "1" : "0")); + WriteLog(" UPDA2 = %s\n", (UPDA2 ? "1" : "0")); + WriteLog(" DSTA2 = %s\n", (DSTA2 ? "1" : "0")); + WriteLog(" ZOP = %s %s %s\n", (Z_OP_INF ? "<" : ""), (Z_OP_EQU ? "=" : ""), (Z_OP_SUP ? ">" : "")); + WriteLog("+-LFUFUNC = %s\n", opStr[(cmd >> 21) & 0x0F]); + WriteLog("| PATDSEL = %s (PD=%08X%08X)\n", (PATDSEL ? "1" : "0"), REG(PATTERNDATA), REG(PATTERNDATA + 4)); + WriteLog("+-ADDDSEL = %s\n", (ADDDSEL ? "1" : "0")); + WriteLog(" CMPDST = %s\n", (CMPDST ? "1" : "0")); + WriteLog(" BCOMPEN = %s\n", (BCOMPEN ? "1" : "0")); + WriteLog(" DCOMPEN = %s\n", (DCOMPEN ? "1" : "0")); + WriteLog(" TOPBEN = %s\n", (TOPBEN ? "1" : "0")); + WriteLog(" TOPNEN = %s\n", (TOPNEN ? "1" : "0")); + WriteLog(" BKGWREN = %s\n", (BKGWREN ? "1" : "0")); + WriteLog(" GOURD = %s (II=%08X, SD=%08X%08X)\n", (GOURD ? "1" : "0"), REG(INTENSITYINC), REG(SRCDATA), REG(SRCDATA + 4)); + WriteLog(" GOURZ = %s (ZI=%08X, ZD=%08X%08X, SZ1=%08X%08X, SZ2=%08X%08X)\n", (GOURZ ? "1" : "0"), REG(ZINC), REG(DSTZ), REG(DSTZ + 4), + REG(SRCZINT), REG(SRCZINT + 4), REG(SRCZFRAC), REG(SRCZFRAC + 4)); + WriteLog(" SRCSHADE = %s\n", (SRCSHADE ? "1" : "0")); +} + + +#ifdef USE_MIDSUMMER_BLITTER +// +// Here's an attempt to write a blitter that conforms to the Midsummer specs--since +// it's supposedly backwards compatible, it should work well... +// +//#define LOG_BLITTER_MEMORY_ACCESSES + +#define DATINIT (false) +#define TXTEXT (false) +#define POLYGON (false) + +void BlitterMidsummer(uint32_t cmd) +{ +#ifdef LOG_BLITS + LogBlit(); +#endif +uint32_t outer_loop, inner_loop, a1_addr, a2_addr; +int32_t a1_x, a1_y, a2_x, a2_y, a1_width, a2_width; +uint8_t a1_phrase_mode, a2_phrase_mode; + + a1_addr = REG(A1_BASE) & 0xFFFFFFF8; + a2_addr = REG(A2_BASE) & 0xFFFFFFF8; + a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF); + a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16); + uint32_t m = (REG(A1_FLAGS) >> 9) & 0x03, e = (REG(A1_FLAGS) >> 11) & 0x0F; + a1_width = ((0x04 | m) << e) >> 2;//*/ + a2_x = (REG(A2_PIXEL) & 0x0000FFFF) << 16; + a2_y = (REG(A2_PIXEL) & 0xFFFF0000); + m = (REG(A2_FLAGS) >> 9) & 0x03, e = (REG(A2_FLAGS) >> 11) & 0x0F; + a2_width = ((0x04 | m) << e) >> 2;//*/ + + a1_phrase_mode = a2_phrase_mode = 0; + + if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 0) + a1_phrase_mode = 1; + + if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 0) + a2_phrase_mode = 1; + +#define INNER0 (inner_loop == 0) +#define OUTER0 (outer_loop == 0) + +// $01800005 has SRCENX, may have to investigate further... +// $00011008 has GOURD & DSTEN. +// $41802F41 has SRCSHADE, CLIPA1 +/*bool logBlit = false; +if (cmd != 0x00010200 && cmd != 0x01800001 && cmd != 0x01800005 + && cmd != 0x00011008 && cmd !=0x41802F41) +{ + logBlit = true; + LogBlit(); +}//*/ + + uint64_t srcData = GET64(blitter_ram, SRCDATA), srcXtraData, + dstData = GET64(blitter_ram, DSTDATA), writeData; + uint32_t srcAddr, dstAddr; + uint8_t bitCount, a1PixelSize, a2PixelSize; + + // JTRM says phrase mode only works for 8BPP or higher, so let's try this... + uint32_t phraseOffset[8] = { 8, 8, 8, 8, 4, 2, 0, 0 }; + uint8_t pixelShift[8] = { 3, 2, 1, 0, 1, 2, 0, 0 }; + + a1PixelSize = (blitter_ram[A1_FLAGS + 3] >> 3) & 0x07; + a2PixelSize = (blitter_ram[A2_FLAGS + 3] >> 3) & 0x07; + + outer_loop = GET16(blitter_ram, PIXLINECOUNTER + 0); + + if (outer_loop == 0) + outer_loop = 0x10000; + + // We just list the states here and jump from state to state in order to + // keep things somewhat clear. Optimization/cleanups later. + +//idle: // Blitter is idle, and will not perform any bus activity +/* +idle Blitter is off the bus, and no activity takes place. +if GO if DATINIT goto init_if + else goto inner +*/ + if (DATINIT) + goto init_if; + else + goto inner; + +/* +inner Inner loop is active, read and write cycles are performed +*/ +inner: // Run inner loop state machine (asserts step from its idle state) + inner_loop = GET16(blitter_ram, PIXLINECOUNTER + 2); + + if (inner_loop == 0) + inner_loop = 0x10000; + +/* +------------------------------ +idle: Inactive, blitter is idle or passing round outer loop +idle Another state in the outer loop is active. No bus transfers are performed. +if STEP + if SRCENX goto sreadx + else if TXTEXT goto txtread + else if SRCEN goto sread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ + if (SRCENX) + goto sreadx; + else if (TXTEXT) + goto txtread; + else if (SRCEN) + goto sread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +/* +sreadx Extra source data read at the start of an inner loop pass. +if STEP + if SRCENZ goto szreadx + else if TXTEXT goto txtread + else if SRCEN goto sread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ +sreadx: // Extra source data read + if (SRCENZ) + goto szreadx; + else if (TXTEXT) + goto txtread; + else if (SRCEN) + goto sread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +/* +szreadx Extra source Z read as the start of an inner loop pass. +if STEP + if TXTEXT goto txtread + else goto sread +*/ +szreadx: // Extra source Z read + if (TXTEXT) + goto txtread; + else + goto sread; + +/* +txtread Read texture data from external memory. This state is only used for external texture. + TEXTEXT is the condition TEXTMODE=1. +if STEP + if SRCEN goto sread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ +txtread: // Read external texture data + if (SRCEN) + goto sread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +/* +sread Source data read. +if STEP + if SRCENZ goto szread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ +sread: // Source data read +//The JTRM doesn't really specify the internal structure of the source data read, but I would +//imagine that if it's in phrase mode that it starts by reading the phrase that the window is +//pointing at. Likewise, the pixel (if in BPP 1, 2 & 4, chopped) otherwise. It probably still +//transfers an entire phrase even in pixel mode. +//Odd thought: Does it expand, e.g., 1 BPP pixels into 32 BPP internally? Hmm... +//No. +/* + a1_addr = REG(A1_BASE) & 0xFFFFFFF8; + a2_addr = REG(A2_BASE) & 0xFFFFFFF8; + a1_zoffs = (REG(A1_FLAGS) >> 6) & 7; + a2_zoffs = (REG(A2_FLAGS) >> 6) & 7; + xadd_a1_control = (REG(A1_FLAGS) >> 16) & 0x03; + xadd_a2_control = (REG(A2_FLAGS) >> 16) & 0x03; + a1_pitch = pitchValue[(REG(A1_FLAGS) & 0x03)]; + a2_pitch = pitchValue[(REG(A2_FLAGS) & 0x03)]; + n_pixels = REG(PIXLINECOUNTER) & 0xFFFF; + n_lines = (REG(PIXLINECOUNTER) >> 16) & 0xFFFF; + a1_x = (REG(A1_PIXEL) << 16) | (REG(A1_FPIXEL) & 0xFFFF); + a1_y = (REG(A1_PIXEL) & 0xFFFF0000) | (REG(A1_FPIXEL) >> 16); + a2_psize = 1 << ((REG(A2_FLAGS) >> 3) & 0x07); + a1_psize = 1 << ((REG(A1_FLAGS) >> 3) & 0x07); + a1_phrase_mode = 0; + a2_phrase_mode = 0; + a1_width = ((0x04 | m) << e) >> 2; + a2_width = ((0x04 | m) << e) >> 2; + + // write values back to registers + WREG(A1_PIXEL, (a1_y & 0xFFFF0000) | ((a1_x >> 16) & 0xFFFF)); + WREG(A1_FPIXEL, (a1_y << 16) | (a1_x & 0xFFFF)); + WREG(A2_PIXEL, (a2_y & 0xFFFF0000) | ((a2_x >> 16) & 0xFFFF)); +*/ + // Calculate the address to be read... + +//Need to fix phrase mode calcs here, since they should *step* by eight, not mulitply. +//Also, need to fix various differing BPP modes here, since offset won't be correct except +//for 8BPP. !!! FIX !!! + srcAddr = (DSTA2 ? a1_addr : a2_addr); + +/* if ((DSTA2 ? a1_phrase_mode : a2_phrase_mode) == 1) + { + srcAddr += (((DSTA2 ? a1_x : a2_x) >> 16) + + (((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width))); + } + else*/ + { +// uint32_t pixAddr = ((DSTA2 ? a1_x : a2_x) >> 16) +// + (((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width)); + int32_t pixAddr = (int16_t)((DSTA2 ? a1_x : a2_x) >> 16) + + ((int16_t)((DSTA2 ? a1_y : a2_y) >> 16) * (DSTA2 ? a1_width : a2_width)); + + if ((DSTA2 ? a1PixelSize : a2PixelSize) < 3) + pixAddr >>= pixelShift[(DSTA2 ? a1PixelSize : a2PixelSize)]; + else if ((DSTA2 ? a1PixelSize : a2PixelSize) > 3) + pixAddr <<= pixelShift[(DSTA2 ? a1PixelSize : a2PixelSize)]; + + srcAddr += pixAddr; + } + + // And read it! + + if ((DSTA2 ? a1_phrase_mode : a2_phrase_mode) == 1) + { + srcData = ((uint64_t)JaguarReadLong(srcAddr, BLITTER) << 32) + | (uint64_t)JaguarReadLong(srcAddr + 4, BLITTER); + } + else + { +//1,2,&4BPP are wrong here... !!! FIX !!! + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 0) // 1 BPP + srcData = JaguarReadByte(srcAddr, BLITTER); + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 1) // 2 BPP + srcData = JaguarReadByte(srcAddr, BLITTER); + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 2) // 4 BPP + srcData = JaguarReadByte(srcAddr, BLITTER); + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 3) // 8 BPP + srcData = JaguarReadByte(srcAddr, BLITTER); + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 4) // 16 BPP + srcData = JaguarReadWord(srcAddr, BLITTER); + if ((DSTA2 ? a1PixelSize : a2PixelSize) == 5) // 32 BPP + srcData = JaguarReadLong(srcAddr, BLITTER); + } + +#ifdef LOG_BLITTER_MEMORY_ACCESSES +if (logBlit) + WriteLog("BLITTER: srcAddr=%08X, srcData=%08X %08X\n", srcAddr, (uint32_t)(srcData >> 32), (uint32_t)(srcData & 0xFFFFFFFF)); +#endif + + if (SRCENZ) + goto szread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +szread: // Source Z read +/* +szread Source Z read. +if STEP + if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ + if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +dread: // Destination data read +/* +dread Destination data read. +if STEP + if DSTENZ goto dzread + else goto dwrite +*/ + // Calculate the destination address to be read... + +//Need to fix phrase mode calcs here, since they should *step* by eight, not mulitply. +//Also, need to fix various differing BPP modes here, since offset won't be correct except +//for 8BPP. !!! FIX !!! + dstAddr = (DSTA2 ? a2_addr : a1_addr); + + { +// uint32_t pixAddr = ((DSTA2 ? a2_x : a1_x) >> 16) +// + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width)); + int32_t pixAddr = (int16_t)((DSTA2 ? a2_x : a1_x) >> 16) + + ((int16_t)((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width)); + + if ((DSTA2 ? a2PixelSize : a1PixelSize) < 3) + pixAddr >>= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)]; + else if ((DSTA2 ? a2PixelSize : a1PixelSize) > 3) + pixAddr <<= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)]; + + dstAddr += pixAddr; + } + + // And read it! + + if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1) + { + dstData = ((uint64_t)JaguarReadLong(srcAddr, BLITTER) << 32) + | (uint64_t)JaguarReadLong(srcAddr + 4, BLITTER); + } + else + { +//1,2,&4BPP are wrong here... !!! FIX !!! + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 0) // 1 BPP + dstData = JaguarReadByte(dstAddr, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 1) // 2 BPP + dstData = JaguarReadByte(dstAddr, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 2) // 4 BPP + dstData = JaguarReadByte(dstAddr, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 3) // 8 BPP + dstData = JaguarReadByte(dstAddr, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 4) // 16 BPP + dstData = JaguarReadWord(dstAddr, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 5) // 32 BPP + dstData = JaguarReadLong(dstAddr, BLITTER); + } + +#ifdef LOG_BLITTER_MEMORY_ACCESSES +if (logBlit) + WriteLog("BLITTER (dread): dstAddr=%08X, dstData=%08X %08X\n", dstAddr, (uint32_t)(dstData >> 32), (uint32_t)(dstData & 0xFFFFFFFF)); +#endif + + if (DSTENZ) + goto dzread; + else + goto dwrite; + +dzread: // Destination Z read +/* +dzread Destination Z read. +if STEP goto dwrite +*/ + goto dwrite; + +dwrite: // Destination data write +/* +dwrite Destination write. Every pass round the inner loop must go through this state.. +if STEP + if DSTWRZ goto dzwrite + else if INNER0 goto idle + else if TXTEXT goto txtread + else if SRCEN goto sread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ +/* +Blit! + a1_base = 00100000 + a1_pitch = 0 + a1_psize = 16 + a1_width = 320 + a1_xadd = 1.000000 (phrase=0) + a1_yadd = 0.000000 + a1_x = 159.000000 + a1_y = 1.000000 + a1_zoffs = 0 + a2_base = 000095D0 + a2_pitch = 0 + a2_psize = 16 + a2_width = 256 + a2_xadd = 1.000000 (phrase=1) + a2_yadd = 0.000000 + a2_x = 2.000000 + a2_y = 0.000000 + a2_mask_x= 0xFFFFFFFF + a2_mask_y= 0xFFFFFFFF + a2_zoffs = 0 + count = 2 x 1 + COMMAND = 00011008 + SRCEN = 0 + DSTEN = 1 + UPDA1F = 0 + UPDA1 = 0 + UPDA2 = 0 + DSTA2 = 0 +--LFUFUNC = LFU_CLEAR +| PATDSEL = 1 (PD=77C7 7700 7700 7700) +--ADDDSEL = 0 + GOURD = 1 (II=00FC 1A00, SD=FF00 0000 0000 0000) +*/ + +//Still need to do CLIPA1 and SRCSHADE and GOURD and GOURZ... + + // Check clipping... + + if (CLIPA1) + { + uint16_t x = a1_x >> 16, y = a1_y >> 16; + + if (x >= GET16(blitter_ram, A1_CLIP + 2) || y >= GET16(blitter_ram, A1_CLIP)) + goto inhibitWrite; + } + + // Figure out what gets written... + + if (PATDSEL) + { + writeData = GET64(blitter_ram, PATTERNDATA); +//GOURD works properly only in 16BPP mode... +//SRCDATA holds the intensity fractions... +//Does GOURD get calc'ed here or somewhere else??? +//Temporary testing kludge... +//if (GOURD) +// writeData >>= 48; +// writeData = 0xFF88; +//OK, it's not writing an entire strip of pixels... Why? +//bad incrementing, that's why! + } + else if (ADDDSEL) + { + // Apparently this only works with 16-bit pixels. Not sure if it works in phrase mode either. +//Also, take TOPBEN & TOPNEN into account here as well... + writeData = srcData + dstData; + } + else // LFUFUNC is the default... + { + writeData = 0; + + if (LFU_NAN) + writeData |= ~srcData & ~dstData; + if (LFU_NA) + writeData |= ~srcData & dstData; + if (LFU_AN) + writeData |= srcData & ~dstData; + if (LFU_A) + writeData |= srcData & dstData; + } + + // Calculate the address to be written... + + dstAddr = (DSTA2 ? a2_addr : a1_addr); + +/* if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1) + { +//both of these calculate the wrong address because they don't take into account +//pixel sizes... + dstAddr += ((DSTA2 ? a2_x : a1_x) >> 16) + + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width)); + } + else*/ + { +/* dstAddr += ((DSTA2 ? a2_x : a1_x) >> 16) + + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width));*/ +// uint32_t pixAddr = ((DSTA2 ? a2_x : a1_x) >> 16) +// + (((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width)); + int32_t pixAddr = (int16_t)((DSTA2 ? a2_x : a1_x) >> 16) + + ((int16_t)((DSTA2 ? a2_y : a1_y) >> 16) * (DSTA2 ? a2_width : a1_width)); + + if ((DSTA2 ? a2PixelSize : a1PixelSize) < 3) + pixAddr >>= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)]; + else if ((DSTA2 ? a2PixelSize : a1PixelSize) > 3) + pixAddr <<= pixelShift[(DSTA2 ? a2PixelSize : a1PixelSize)]; + + dstAddr += pixAddr; + } + + // And write it! + + if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1) + { + JaguarWriteLong(dstAddr, writeData >> 32, BLITTER); + JaguarWriteLong(dstAddr + 4, writeData & 0xFFFFFFFF, BLITTER); + } + else + { +//1,2,&4BPP are wrong here... !!! FIX !!! + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 0) // 1 BPP + JaguarWriteByte(dstAddr, writeData, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 1) // 2 BPP + JaguarWriteByte(dstAddr, writeData, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 2) // 4 BPP + JaguarWriteByte(dstAddr, writeData, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 3) // 8 BPP + JaguarWriteByte(dstAddr, writeData, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 4) // 16 BPP + JaguarWriteWord(dstAddr, writeData, BLITTER); + if ((DSTA2 ? a2PixelSize : a1PixelSize) == 5) // 32 BPP + JaguarWriteLong(dstAddr, writeData, BLITTER); + } + +#ifdef LOG_BLITTER_MEMORY_ACCESSES +if (logBlit) + WriteLog("BLITTER: dstAddr=%08X, writeData=%08X %08X\n", dstAddr, (uint32_t)(writeData >> 32), (uint32_t)(writeData & 0xFFFFFFFF)); +#endif + +inhibitWrite://Should this go here? or on the other side of the X/Y incrementing? +//Seems OK here... for now. + +// Do funky X/Y incrementation here as well... !!! FIX !!! + + // Handle A1 channel stepping + + if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 0) + a1_x += phraseOffset[a1PixelSize] << 16; + else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 1) + a1_x += (blitter_ram[A1_FLAGS + 1] & 0x08 ? -1 << 16 : 1 << 16); +/* else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 2) + a1_x += 0 << 16; */ + else if ((blitter_ram[A1_FLAGS + 1] & 0x03) == 3) + { +//Always add the FINC here??? That was the problem with the BIOS screen... So perhaps. + a1_x += GET16(blitter_ram, A1_FINC + 2); + a1_y += GET16(blitter_ram, A1_FINC + 0); + + a1_x += GET16(blitter_ram, A1_INC + 2) << 16; + a1_y += GET16(blitter_ram, A1_INC + 0) << 16; + } + + if ((blitter_ram[A1_FLAGS + 1] & 0x04) && (blitter_ram[A1_FLAGS + 1] & 0x03 != 3)) + a1_y += (blitter_ram[A1_FLAGS + 1] & 0x10 ? -1 << 16 : 1 << 16); + + // Handle A2 channel stepping + + if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 0) + a2_x += phraseOffset[a2PixelSize] << 16; + else if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 1) + a2_x += (blitter_ram[A2_FLAGS + 1] & 0x08 ? -1 << 16 : 1 << 16); +/* else if ((blitter_ram[A2_FLAGS + 1] & 0x03) == 2) + a2_x += 0 << 16; */ + + if (blitter_ram[A2_FLAGS + 1] & 0x04) + a2_y += (blitter_ram[A2_FLAGS + 1] & 0x10 ? -1 << 16 : 1 << 16); + +//Need to fix this so that it subtracts (saturating, of course) the correct number of pixels +//in phrase mode... !!! FIX !!! [DONE] +//Need to fix this so that it counts down the correct item. Does it count the +//source or the destination phrase mode??? +//It shouldn't matter, because we *should* end up processing the same amount +//the same number of pixels... Not sure though. + if ((DSTA2 ? a2_phrase_mode : a1_phrase_mode) == 1) + { + if (inner_loop < phraseOffset[DSTA2 ? a2PixelSize : a1PixelSize]) + inner_loop = 0; + else + inner_loop -= phraseOffset[DSTA2 ? a2PixelSize : a1PixelSize]; + } + else + inner_loop--; + + + if (DSTWRZ) + goto dzwrite; + else if (INNER0) + goto indone; + else if (TXTEXT) + goto txtread; + else if (SRCEN) + goto sread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +dzwrite: // Destination Z write +/* +dzwrite Destination Z write. +if STEP + if INNER0 goto idle + else if TXTEXT goto txtread + else if SRCEN goto sread + else if DSTEN goto dread + else if DSTENZ goto dzread + else goto dwrite +*/ + if (INNER0) + goto indone; + else if (TXTEXT) + goto txtread; + else if (SRCEN) + goto sread; + else if (DSTEN) + goto dread; + else if (DSTENZ) + goto dzread; + else + goto dwrite; + +/* +------------------------------ +if INDONE if OUTER0 goto idle +else if UPDA1F goto a1fupdate +else if UPDA1 goto a1update +else if GOURZ.POLYGON goto zfupdate +else if UPDA2 goto a2update +else if DATINIT goto init_if +else restart inner +*/ +indone: + outer_loop--; + + + if (OUTER0) + goto blitter_done; + else if (UPDA1F) + goto a1fupdate; + else if (UPDA1) + goto a1update; +//kill this, for now... +// else if (GOURZ.POLYGON) +// goto zfupdate; + else if (UPDA2) + goto a2update; + else if (DATINIT) + goto init_if; + else + goto inner; + +a1fupdate: // Update A1 pointer fractions and more (see below) +/* +a1fupdate A1 step fraction is added to A1 pointer fraction + POLYGON true: A1 step delta X and Y fraction parts are added to the A1 + step X and Y fraction parts (the value prior to this add is used for + the step to pointer add). + POLYGON true: inner count step fraction is added to the inner count + fraction part + POLYGON.GOURD true: the I fraction step is added to the computed + intensity fraction parts + + POLYGON.GOURD true: the I fraction step delta is added to the I + fraction step +goto a1update +*/ +/* +#define A1_PIXEL ((uint32_t)0x0C) // Integer part of the pixel (Y.i and X.i) +#define A1_STEP ((uint32_t)0x10) // Integer part of the step +#define A1_FSTEP ((uint32_t)0x14) // Fractional part of the step +#define A1_FPIXEL ((uint32_t)0x18) // Fractional part of the pixel (Y.f and X.f) +*/ + +// This is all kinda murky. All we have are the Midsummer docs to give us any guidance, +// and it's incomplete or filled with errors (like above). Aarrrgggghhhhh! + +//This isn't right. Is it? I don't think the fractional parts are signed... +// a1_x += (int32_t)((int16_t)GET16(blitter_ram, A1_FSTEP + 2)); +// a1_y += (int32_t)((int16_t)GET16(blitter_ram, A1_FSTEP + 0)); + a1_x += GET16(blitter_ram, A1_FSTEP + 2); + a1_y += GET16(blitter_ram, A1_FSTEP + 0); + + goto a1update; + +a1update: // Update A1 pointer integers +/* +a1update A1 step is added to A1 pointer, with carry from the fractional add + POLYGON true: A1 step delta X and Y integer parts are added to the A1 + step X and Y integer parts, with carry from the corresponding + fractional part add (again, the value prior to this add is used for + the step to pointer add). + POLYGON true: inner count step is added to the inner count, with carry + POLYGON.GOURD true: the I step is added to the computed intensities, + with carry + + POLYGON.GOURD true: the I step delta is added to the I step, with + carry the texture X and Y step delta values are added to the X and Y + step values. +if GOURZ.POLYGON goto zfupdate +else if UPDA2 goto a2update +else if DATINIT goto init_if +else restart inner +*/ + a1_x += (int32_t)(GET16(blitter_ram, A1_STEP + 2) << 16); + a1_y += (int32_t)(GET16(blitter_ram, A1_STEP + 0) << 16); + + +//kill this, for now... +// if (GOURZ.POLYGON) + if (false) + goto zfupdate; + else if (UPDA2) + goto a2update; + else if (DATINIT) + goto init_if; + else + goto inner; + +zfupdate: // Update computed Z step fractions +/* +zfupdate the Z fraction step is added to the computed Z fraction parts + + the Z fraction step delta is added to the Z fraction step +goto zupdate +*/ + goto zupdate; + +zupdate: // Update computed Z step integers +/* +zupdate the Z step is added to the computed Zs, with carry + + the Z step delta is added to the Z step, with carry +if UPDA2 goto a2update +else if DATINIT goto init_if +else restart inner +*/ + if (UPDA2) + goto a2update; + else if (DATINIT) + goto init_if; + else + goto inner; + +a2update: // Update A2 pointer +/* +a2update A2 step is added to the A2 pointer +if DATINIT goto init_if +else restart inner +*/ + a2_x += (int32_t)(GET16(blitter_ram, A2_STEP + 2) << 16); + a2_y += (int32_t)(GET16(blitter_ram, A2_STEP + 0) << 16); + + + if (DATINIT) + goto init_if; + else + goto inner; + +init_if: // Initialise intensity fractions and texture X +/* +init_if Initialise the fractional part of the computed intensity fields, from + the increment and step registers. The texture X integer and fractional + parts can also be initialised. +goto init_ii +*/ + goto init_ii; + +init_ii: // Initialise intensity integers and texture Y +/* +init_ii Initialise the integer part of the computed intensity, and texture Y + integer and fractional parts +if GOURZ goto init_zf +else goto inner +*/ + if (GOURZ) + goto init_zf; + else + goto inner; + +init_zf: // Initialise Z fractions +/* +init_zf Initialise the fractional part of the computed Z fields. +goto init_zi +*/ + goto init_zi; + +init_zi: // Initialise Z integers +/* +init_zi Initialise the integer part of the computed Z fields. +goto inner +*/ + goto inner; + + +/* +The outer loop state machine fires off the inner loop, and controls the updating +process between passes through the inner loop. + ++ -- these functions are irrelevant if the DATINIT function is enabled, which it + will normally be. + +All these states will complete in one clock cycle, with the exception of the idle +state, which means the blitter is quiescent; and the inner state, which takes as +long as is required to complete one strip of pixels. It is therefore possible for +the blitter to spend a maximum of nine clock cycles of inactivity between passes +through the inner loop. +*/ + +blitter_done: + {} +} +#endif + + +// +// Here's attempt #2--taken from the Oberon chip specs! +// + +#ifdef USE_MIDSUMMER_BLITTER_MKII + +void ADDRGEN(uint32_t &, uint32_t &, bool, bool, + uint16_t, uint16_t, uint32_t, uint8_t, uint8_t, uint8_t, uint8_t, + uint16_t, uint16_t, uint32_t, uint8_t, uint8_t, uint8_t, uint8_t); +void ADDARRAY(uint16_t * addq, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, + uint64_t dstd, uint32_t iinc, uint8_t initcin[], uint64_t initinc, uint16_t initpix, + uint32_t istep, uint64_t patd, uint64_t srcd, uint64_t srcz1, uint64_t srcz2, + uint32_t zinc, uint32_t zstep); +void ADD16SAT(uint16_t &r, uint8_t &co, uint16_t a, uint16_t b, uint8_t cin, bool sat, bool eightbit, bool hicinh); +void ADDAMUX(int16_t &adda_x, int16_t &adda_y, uint8_t addasel, int16_t a1_step_x, int16_t a1_step_y, + int16_t a1_stepf_x, int16_t a1_stepf_y, int16_t a2_step_x, int16_t a2_step_y, + int16_t a1_inc_x, int16_t a1_inc_y, int16_t a1_incf_x, int16_t a1_incf_y, uint8_t adda_xconst, + bool adda_yconst, bool addareg, bool suba_x, bool suba_y); +void ADDBMUX(int16_t &addb_x, int16_t &addb_y, uint8_t addbsel, int16_t a1_x, int16_t a1_y, + int16_t a2_x, int16_t a2_y, int16_t a1_frac_x, int16_t a1_frac_y); +void DATAMUX(int16_t &data_x, int16_t &data_y, uint32_t gpu_din, int16_t addq_x, int16_t addq_y, bool addqsel); +void ADDRADD(int16_t &addq_x, int16_t &addq_y, bool a1fracldi, + uint16_t adda_x, uint16_t adda_y, uint16_t addb_x, uint16_t addb_y, uint8_t modx, bool suba_x, bool suba_y); +void DATA(uint64_t &wdata, uint8_t &dcomp, uint8_t &zcomp, bool &nowrite, + bool big_pix, bool cmpdst, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, bool daddq_sel, uint8_t data_sel, + uint8_t dbinh, uint8_t dend, uint8_t dstart, uint64_t dstd, uint32_t iinc, uint8_t lfu_func, uint64_t &patd, bool patdadd, + bool phrase_mode, uint64_t srcd, bool srcdread, bool srczread, bool srcz2add, uint8_t zmode, + bool bcompen, bool bkgwren, bool dcompen, uint8_t icount, uint8_t pixsize, + uint64_t &srcz, uint64_t dstz, uint32_t zinc); +void COMP_CTRL(uint8_t &dbinh, bool &nowrite, + bool bcompen, bool big_pix, bool bkgwren, uint8_t dcomp, bool dcompen, uint8_t icount, + uint8_t pixsize, bool phrase_mode, uint8_t srcd, uint8_t zcomp); +#define VERBOSE_BLITTER_LOGGING + +void BlitterMidsummer2(void) +{ +#ifdef LOG_BLITS + LogBlit(); +#endif + if (startConciseBlitLogging) + LogBlit(); + + // Here's what the specs say the state machine does. Note that this can probably be + // greatly simplified (also, it's different from what John has in his Oberon docs): +//Will remove stuff that isn't in Jaguar I once fully described (stuff like texture won't +//be described here at all)... + + uint32_t cmd = GET32(blitter_ram, COMMAND); + +#if 0 +logBlit = false; +if ( + cmd != 0x00010200 && // PATDSEL + cmd != 0x01800001 // SRCEN LFUFUNC=C + && cmd != 0x01800005 +//Boot ROM ATARI letters: + && cmd != 0x00011008 // DSTEN GOURD PATDSEL +//Boot ROM spinning cube: + && cmd != 0x41802F41 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 GOURZ ZMODE=0 LFUFUNC=C SRCSHADE +//T2K intro screen: + && cmd != 0x01800E01 // SRCEN UPDA1 UPDA2 DSTA2 LFUFUNC=C +//T2K TEMPEST letters: + && cmd != 0x09800741 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 LFUFUNC=C DCOMPEN +//Static letters on Cybermorph intro screen: + && cmd != 0x09800609 // SRCEN DSTEN UPDA1 UPDA2 LFUFUNC=C DCOMPEN +//Static pic on title screen: + && cmd != 0x01800601 // SRCEN UPDA1 UPDA2 LFUFUNC=C +//Turning letters on Cybermorph intro screen: +// && cmd != 0x09800F41 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 LFUFUNC=C DCOMPEN + && cmd != 0x00113078 // DSTEN DSTENZ DSTWRZ CLIP_A1 GOURD GOURZ PATDSEL ZMODE=4 + && cmd != 0x09900F39 // SRCEN DSTEN DSTENZ DSTWRZ UPDA1 UPDA1F UPDA2 DSTA2 ZMODE=4 LFUFUNC=C DCOMPEN + && cmd != 0x09800209 // SRCEN DSTEN UPDA1 LFUFUNC=C DCOMPEN + && cmd != 0x00011200 // UPDA1 GOURD PATDSEL +//Start of Hover Strike (clearing screen): + && cmd != 0x00010000 // PATDSEL +//Hover Strike text: + && cmd != 0x1401060C // SRCENX DSTEN UPDA1 UPDA2 PATDSEL BCOMPEN BKGWREN +//Hover Strike 3D stuff + && cmd != 0x01902839 // SRCEN DSTEN DSTENZ DSTWRZ DSTA2 GOURZ ZMODE=4 LFUFUNC=C +//Hover Strike darkening on intro to play (briefing) screen + && cmd != 0x00020208 // DSTEN UPDA1 ADDDSEL +//Trevor McFur stuff: + && cmd != 0x05810601 // SRCEN UPDA1 UPDA2 PATDSEL BCOMPEN + && cmd != 0x01800201 // SRCEN UPDA1 LFUFUNC=C +//T2K: + && cmd != 0x00011000 // GOURD PATDSEL + && cmd != 0x00011040 // CLIP_A1 GOURD PATDSEL +//Checkered flag: + && cmd != 0x01800000 // LFUFUNC=C + && cmd != 0x01800401 // + && cmd != 0x01800040 // + && cmd != 0x00020008 // +// && cmd != 0x09800F41 // SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 LFUFUNC=C DCOMPEN + ) + logBlit = true;//*/ +#else +logBlit = true; +#endif +if (blit_start_log == 0) // Wait for the signal... + logBlit = false;//*/ +//temp, for testing... +/*if (cmd != 0x49820609) + logBlit = false;//*/ + +/* +Some T2K unique blits: +logBlit = F, cmd = 00010200 * +logBlit = F, cmd = 00011000 +logBlit = F, cmd = 00011040 +logBlit = F, cmd = 01800005 * +logBlit = F, cmd = 09800741 * + +Hover Strike mission selection screen: +Blit! (CMD = 01902839) // SRCEN DSTEN DSTENZ DSTWRZ DSTA2 GOURZ ZMODE=4 LFUFUNC=C + +Checkered Flag blits in the screw up zone: +Blit! (CMD = 01800001) // SRCEN LFUFUNC=C +Blit! (CMD = 01800000) // LFUFUNC=C +Blit! (CMD = 00010000) // PATDSEL + +Wolfenstein 3D in the fuckup zone: +Blit! (CMD = 01800000) // LFUFUNC=C +*/ + +//printf("logBlit = %s, cmd = %08X\n", (logBlit ? "T" : "F"), cmd); +//fflush(stdout); +//logBlit = true; + +/* +Blit! (CMD = 00011040) +Flags: CLIP_A1 GOURD PATDSEL + count = 18 x 1 + a1_base = 00100000, a2_base = 0081F6A8 + a1_x = 00A7, a1_y = 0014, a1_frac_x = 0000, a1_frac_y = 0000, a2_x = 0001, a2_y = 0000 + a1_step_x = FE80, a1_step_y = 0001, a1_stepf_x = 0000, a1_stepf_y = 0000, a2_step_x = FFF8, a2_step_y = 0001 + a1_inc_x = 0001, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0180, a1_win_y = 0118, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+phr/+0 + a1_pixsize = 4, a2_pixsize = 4 +*/ +//Testing T2K... +/*logBlit = false; +if (cmd == 0x00011040 + && (GET16(blitter_ram, A1_PIXEL + 2) == 0x00A7) && (GET16(blitter_ram, A1_PIXEL + 0) == 0x0014) + && (GET16(blitter_ram, A2_PIXEL + 2) == 0x0001) && (GET16(blitter_ram, A2_PIXEL + 0) == 0x0000) + && (GET16(blitter_ram, PIXLINECOUNTER + 2) == 18)) + logBlit = true;*/ + + // Line states passed in via the command register + + bool srcen = (SRCEN), srcenx = (SRCENX), srcenz = (SRCENZ), + dsten = (DSTEN), dstenz = (DSTENZ), dstwrz = (DSTWRZ), clip_a1 = (CLIPA1), + upda1 = (UPDA1), upda1f = (UPDA1F), upda2 = (UPDA2), dsta2 = (DSTA2), + gourd = (GOURD), gourz = (GOURZ), topben = (TOPBEN), topnen = (TOPNEN), + patdsel = (PATDSEL), adddsel = (ADDDSEL), cmpdst = (CMPDST), bcompen = (BCOMPEN), + dcompen = (DCOMPEN), bkgwren = (BKGWREN), srcshade = (SRCSHADE); + + uint8_t zmode = (cmd & 0x01C0000) >> 18, lfufunc = (cmd & 0x1E00000) >> 21; +//Missing: BUSHI +//Where to find various lines: +// clip_a1 -> inner +// gourd -> dcontrol, inner, outer, state +// gourz -> dcontrol, inner, outer, state +// cmpdst -> blit, data, datacomp, state +// bcompen -> acontrol, inner, mcontrol, state +// dcompen -> inner, state +// bkgwren -> inner, state +// srcshade -> dcontrol, inner, state +// adddsel -> dcontrol +//NOTE: ADDDSEL takes precedence over PATDSEL, PATDSEL over LFU_FUNC +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + char zfs[512], lfus[512]; + zfs[0] = lfus[0] = 0; + if (dstwrz || dstenz || gourz) + sprintf(zfs, " ZMODE=%X", zmode); + if (!(patdsel || adddsel)) + sprintf(lfus, " LFUFUNC=%X", lfufunc); + WriteLog("\nBlit! (CMD = %08X)\nFlags:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", cmd, + (srcen ? " SRCEN" : ""), (srcenx ? " SRCENX" : ""), (srcenz ? " SRCENZ" : ""), + (dsten ? " DSTEN" : ""), (dstenz ? " DSTENZ" : ""), (dstwrz ? " DSTWRZ" : ""), + (clip_a1 ? " CLIP_A1" : ""), (upda1 ? " UPDA1" : ""), (upda1f ? " UPDA1F" : ""), + (upda2 ? " UPDA2" : ""), (dsta2 ? " DSTA2" : ""), (gourd ? " GOURD" : ""), + (gourz ? " GOURZ" : ""), (topben ? " TOPBEN" : ""), (topnen ? " TOPNEN" : ""), + (patdsel ? " PATDSEL" : ""), (adddsel ? " ADDDSEL" : ""), zfs, lfus, (cmpdst ? " CMPDST" : ""), + (bcompen ? " BCOMPEN" : ""), (dcompen ? " DCOMPEN" : ""), (bkgwren ? " BKGWREN" : ""), + (srcshade ? " SRCSHADE" : "")); + WriteLog(" count = %d x %d\n", GET16(blitter_ram, PIXLINECOUNTER + 2), GET16(blitter_ram, PIXLINECOUNTER)); +} +#endif + + // Lines that don't exist in Jaguar I (and will never be asserted) + + bool polygon = false, datinit = false, a1_stepld = false, a2_stepld = false, ext_int = false; + bool istepadd = false, istepfadd = false, finneradd = false, inneradd = false; + bool zstepfadd = false, zstepadd = false; + + // Various state lines (initial state--basically the reset state of the FDSYNCs) + + bool go = true, idle = true, inner = false, a1fupdate = false, a1update = false, + zfupdate = false, zupdate = false, a2update = false, init_if = false, init_ii = false, + init_zf = false, init_zi = false; + + bool outer0 = false, indone = false; + + bool idlei, inneri, a1fupdatei, a1updatei, zfupdatei, zupdatei, a2updatei, init_ifi, init_iii, + init_zfi, init_zii; + + bool notgzandp = !(gourz && polygon); + + // Various registers set up by user + + uint16_t ocount = GET16(blitter_ram, PIXLINECOUNTER); + uint8_t a1_pitch = blitter_ram[A1_FLAGS + 3] & 0x03; + uint8_t a2_pitch = blitter_ram[A2_FLAGS + 3] & 0x03; + uint8_t a1_pixsize = (blitter_ram[A1_FLAGS + 3] & 0x38) >> 3; + uint8_t a2_pixsize = (blitter_ram[A2_FLAGS + 3] & 0x38) >> 3; + uint8_t a1_zoffset = (GET16(blitter_ram, A1_FLAGS + 2) >> 6) & 0x07; + uint8_t a2_zoffset = (GET16(blitter_ram, A2_FLAGS + 2) >> 6) & 0x07; + uint8_t a1_width = (blitter_ram[A1_FLAGS + 2] >> 1) & 0x3F; + uint8_t a2_width = (blitter_ram[A2_FLAGS + 2] >> 1) & 0x3F; + bool a2_mask = blitter_ram[A2_FLAGS + 2] & 0x80; + uint8_t a1addx = blitter_ram[A1_FLAGS + 1] & 0x03, a2addx = blitter_ram[A2_FLAGS + 1] & 0x03; + bool a1addy = blitter_ram[A1_FLAGS + 1] & 0x04, a2addy = blitter_ram[A2_FLAGS + 1] & 0x04; + bool a1xsign = blitter_ram[A1_FLAGS + 1] & 0x08, a2xsign = blitter_ram[A2_FLAGS + 1] & 0x08; + bool a1ysign = blitter_ram[A1_FLAGS + 1] & 0x10, a2ysign = blitter_ram[A2_FLAGS + 1] & 0x10; + uint32_t a1_base = GET32(blitter_ram, A1_BASE) & 0xFFFFFFF8; // Phrase aligned by ignoring bottom 3 bits + uint32_t a2_base = GET32(blitter_ram, A2_BASE) & 0xFFFFFFF8; + + uint16_t a1_win_x = GET16(blitter_ram, A1_CLIP + 2) & 0x7FFF; + uint16_t a1_win_y = GET16(blitter_ram, A1_CLIP + 0) & 0x7FFF; + int16_t a1_x = (int16_t)GET16(blitter_ram, A1_PIXEL + 2); + int16_t a1_y = (int16_t)GET16(blitter_ram, A1_PIXEL + 0); + int16_t a1_step_x = (int16_t)GET16(blitter_ram, A1_STEP + 2); + int16_t a1_step_y = (int16_t)GET16(blitter_ram, A1_STEP + 0); + uint16_t a1_stepf_x = GET16(blitter_ram, A1_FSTEP + 2); + uint16_t a1_stepf_y = GET16(blitter_ram, A1_FSTEP + 0); + uint16_t a1_frac_x = GET16(blitter_ram, A1_FPIXEL + 2); + uint16_t a1_frac_y = GET16(blitter_ram, A1_FPIXEL + 0); + int16_t a1_inc_x = (int16_t)GET16(blitter_ram, A1_INC + 2); + int16_t a1_inc_y = (int16_t)GET16(blitter_ram, A1_INC + 0); + uint16_t a1_incf_x = GET16(blitter_ram, A1_FINC + 2); + uint16_t a1_incf_y = GET16(blitter_ram, A1_FINC + 0); + + int16_t a2_x = (int16_t)GET16(blitter_ram, A2_PIXEL + 2); + int16_t a2_y = (int16_t)GET16(blitter_ram, A2_PIXEL + 0); + uint16_t a2_mask_x = GET16(blitter_ram, A2_MASK + 2); + uint16_t a2_mask_y = GET16(blitter_ram, A2_MASK + 0); + int16_t a2_step_x = (int16_t)GET16(blitter_ram, A2_STEP + 2); + int16_t a2_step_y = (int16_t)GET16(blitter_ram, A2_STEP + 0); + + uint64_t srcd1 = GET64(blitter_ram, SRCDATA); + uint64_t srcd2 = 0; + uint64_t dstd = GET64(blitter_ram, DSTDATA); + uint64_t patd = GET64(blitter_ram, PATTERNDATA); + uint32_t iinc = GET32(blitter_ram, INTENSITYINC); + uint64_t srcz1 = GET64(blitter_ram, SRCZINT); + uint64_t srcz2 = GET64(blitter_ram, SRCZFRAC); + uint64_t dstz = GET64(blitter_ram, DSTZ); + uint32_t zinc = GET32(blitter_ram, ZINC); + uint32_t collision = GET32(blitter_ram, COLLISIONCTRL);// 0=RESUME, 1=ABORT, 2=STOPEN + + uint8_t pixsize = (dsta2 ? a2_pixsize : a1_pixsize); // From ACONTROL + +//Testing Trevor McFur--I *think* it's the circle on the lower RHS of the screen... +/*logBlit = false; +if (cmd == 0x05810601 && (GET16(blitter_ram, PIXLINECOUNTER + 2) == 96) + && (GET16(blitter_ram, PIXLINECOUNTER + 0) == 72)) + logBlit = true;//*/ +//Testing... +//if (cmd == 0x1401060C) patd = 0xFFFFFFFFFFFFFFFFLL; +//if (cmd == 0x1401060C) patd = 0x00000000000000FFLL; +//If it's still not working (bcompen-patd) then see who's writing what to patd and where... +//Still not OK. Check to see who's writing what to where in patd! +//It looks like M68K is writing to the top half of patd... Hmm... +/* +----> M68K wrote 0000 to byte 15737344 of PATTERNDATA... +--> M68K wrote 00 to byte 0 of PATTERNDATA... +--> M68K wrote 00 to byte 1 of PATTERNDATA... +----> M68K wrote 00FF to byte 15737346 of PATTERNDATA... +--> M68K wrote 00 to byte 2 of PATTERNDATA... +--> M68K wrote FF to byte 3 of PATTERNDATA... +logBlit = F, cmd = 1401060C + +Wren0 := ND6 (wren\[0], gpua\[5], gpua\[6..8], bliten, gpu_memw); +Wren1 := ND6 (wren\[1], gpua[5], gpua\[6..8], bliten, gpu_memw); +Wren2 := ND6 (wren\[2], gpua\[5], gpua[6], gpua\[7..8], bliten, gpu_memw); +Wren3 := ND6 (wren\[3], gpua[5], gpua[6], gpua\[7..8], bliten, gpu_memw); + +--> 0 000x xx00 +Dec0 := D38GH (a1baseld, a1flagld, a1winld, a1ptrld, a1stepld, a1stepfld, a1fracld, a1incld, gpua[2..4], wren\[0]); +--> 0 001x xx00 +Dec1 := D38GH (a1incfld, a2baseld, a2flagld, a2maskld, a2ptrldg, a2stepld, cmdldt, countldt, gpua[2..4], wren\[1]); +--> 0 010x xx00 +Dec2 := D38GH (srcd1ldg[0..1], dstdldg[0..1], dstzldg[0..1], srcz1ldg[0..1], gpua[2..4], wren\[2]); +--> 0 011x xx00 +Dec3 := D38GH (srcz2ld[0..1], patdld[0..1], iincld, zincld, stopld, intld[0], gpua[2..4], wren\[3]); + +wren[3] is asserted when gpu address bus = 0 011x xx00 +patdld[0] -> 0 0110 1000 -> $F02268 (lo 32 bits) +patdld[1] -> 0 0110 1100 -> $F0226C (hi 32 bits) + +So... It's reversed! The data organization of the patd register is [low 32][high 32]! !!! FIX !!! [DONE] +And fix all the other 64 bit registers [DONE] +*/ +/*if (cmd == 0x1401060C) +{ + printf("logBlit = %s, cmd = %08X\n", (logBlit ? "T" : "F"), cmd); + fflush(stdout); +}*/ +/*logBlit = false; +if ((cmd == 0x00010200) && (GET16(blitter_ram, PIXLINECOUNTER + 2) == 9)) + logBlit = true; + +; Pink altimeter bar + +Blit! (00110000 <- 000BF010) count: 9 x 23, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 step values: -10 (X), 1 (Y) + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 262/132, A2 x/y: 129/0 +;x-coord is 257 in pic, so add 5 +;20 for ship, 33 for #... Let's see if we can find 'em! + +; Black altimeter bar + +Blit! (00110000 <- 000BF010) count: 5 x 29, A1/2_FLAGS: 000042E2/00010020 [cmd: 00010200] + CMD -> src: dst: misc: a1ctl: UPDA1 mode: ity: PATDSEL z-op: op: LFU_CLEAR ctrl: + A1 step values: -8 (X), 1 (Y) + A1 -> pitch: 4 phrases, depth: 16bpp, z-off: 3, width: 320 (21), addctl: XADDPHR YADD0 XSIGNADD YSIGNADD + A2 -> pitch: 1 phrases, depth: 16bpp, z-off: 0, width: 1 (00), addctl: XADDPIX YADD0 XSIGNADD YSIGNADD + A1 x/y: 264/126, A2 x/y: 336/0 + +Here's the pink bar--note that it's phrase mode without dread, so how does this work??? +Not sure, but I *think* that somehow it MUXes the data at the write site in on the left or right side +of the write data when masked in phrase mode. I'll have to do some tracing to see if this is the mechanism +it uses or not... + +Blit! (CMD = 00010200) +Flags: UPDA1 PATDSEL + count = 9 x 11 + a1_base = 00110010, a2_base = 000BD7E0 + a1_x = 0106, a1_y = 0090, a1_frac_x = 0000, a1_frac_y = 8000, a2_x = 025A, a2_y = 0000 + a1_step_x = FFF6, a1_step_y = 0001, a1_stepf_x = 5E00, a1_stepf_y = D100, a2_step_x = FFF7, a2_step_y = 0001 + a1_inc_x = 0001, a1_inc_y = FFFF, a1_incf_x = 0000, a1_incf_y = E000 + a1_win_x = 0000, a1_win_y = 0000, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+1/+0 + a1_pixsize = 4, a2_pixsize = 4 + srcd=BAC673AC2C92E578 dstd=0000000000000000 patd=74C074C074C074C0 iinc=0002E398 + srcz1=7E127E12000088DA srcz2=DBE06DF000000000 dstz=0000000000000000 zinc=FFFE4840, coll=0 + Phrase mode is ON + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... + Entering DWRITE state... + Dest write address/pix address: 0016A830/0 [dstart=20 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] [7400000074C074C0] (icount=0007, inc=2) + Entering A1_ADD state [a1_x=0106, a1_y=0090, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0016A850/0 [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] [74C074C074C074C0] (icount=0003, inc=4) + Entering A1_ADD state [a1_x=0108, a1_y=0090, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0016A870/0 [dstart=0 dend=30 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] [74C074C074C00000] (icount=FFFF, inc=4) + Entering A1_ADD state [a1_x=010C, a1_y=0090, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering IDLE_INNER state... + Leaving INNER state... (ocount=000A) + [in=F a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering A1UPDATE state... (272/144 -> 262/145) + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... +*/ + + // Bugs in Jaguar I + + a2addy = a1addy; // A2 channel Y add bit is tied to A1's + +//if (logBlit && (ocount > 20)) logBlit = false; +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog(" a1_base = %08X, a2_base = %08X\n", a1_base, a2_base); + WriteLog(" a1_x = %04X, a1_y = %04X, a1_frac_x = %04X, a1_frac_y = %04X, a2_x = %04X, a2_y = %04X\n", (uint16_t)a1_x, (uint16_t)a1_y, a1_frac_x, a1_frac_y, (uint16_t)a2_x, (uint16_t)a2_y); + WriteLog(" a1_step_x = %04X, a1_step_y = %04X, a1_stepf_x = %04X, a1_stepf_y = %04X, a2_step_x = %04X, a2_step_y = %04X\n", (uint16_t)a1_step_x, (uint16_t)a1_step_y, a1_stepf_x, a1_stepf_y, (uint16_t)a2_step_x, (uint16_t)a2_step_y); + WriteLog(" a1_inc_x = %04X, a1_inc_y = %04X, a1_incf_x = %04X, a1_incf_y = %04X\n", (uint16_t)a1_inc_x, (uint16_t)a1_inc_y, a1_incf_x, a1_incf_y); + WriteLog(" a1_win_x = %04X, a1_win_y = %04X, a2_mask_x = %04X, a2_mask_y = %04X\n", a1_win_x, a1_win_y, a2_mask_x, a2_mask_y); + char x_add_str[4][4] = { "phr", "1", "0", "inc" }; + WriteLog(" a2_mask=%s a1add=%s%s/%s%s a2add=%s%s/%s%s\n", (a2_mask ? "T" : "F"), (a1xsign ? "-" : "+"), x_add_str[a1addx], + (a1ysign ? "-" : "+"), (a1addy ? "1" : "0"), (a2xsign ? "-" : "+"), x_add_str[a2addx], + (a2ysign ? "-" : "+"), (a2addy ? "1" : "0")); + WriteLog(" a1_pixsize = %u, a2_pixsize = %u\n", a1_pixsize, a2_pixsize); + WriteLog(" srcd=%08X%08X dstd=%08X%08X patd=%08X%08X iinc=%08X\n", + (uint32_t)(srcd1 >> 32), (uint32_t)(srcd1 & 0xFFFFFFFF), + (uint32_t)(dstd >> 32), (uint32_t)(dstd & 0xFFFFFFFF), + (uint32_t)(patd >> 32), (uint32_t)(patd & 0xFFFFFFFF), iinc); + WriteLog(" srcz1=%08X%08X srcz2=%08X%08X dstz=%08X%08X zinc=%08X, coll=%X\n", + (uint32_t)(srcz1 >> 32), (uint32_t)(srcz1 & 0xFFFFFFFF), + (uint32_t)(srcz2 >> 32), (uint32_t)(srcz2 & 0xFFFFFFFF), + (uint32_t)(dstz >> 32), (uint32_t)(dstz & 0xFFFFFFFF), zinc, collision); +} +#endif + + // Various state lines set up by user + + bool phrase_mode = ((!dsta2 && a1addx == 0) || (dsta2 && a2addx == 0) ? true : false); // From ACONTROL +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Phrase mode is %s\n", (phrase_mode ? "ON" : "off")); +#endif +//logBlit = false; + + // Stopgap vars to simulate various lines + + uint16_t a1FracCInX = 0, a1FracCInY = 0; + + while (true) + { + // IDLE + + if ((idle && !go) || (inner && outer0 && indone)) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering IDLE state...\n"); +#endif + idlei = true; + +//Instead of a return, let's try breaking out of the loop... +break; +// return; + } + else + idlei = false; + + // INNER LOOP ACTIVE +/* + Entering DWRITE state... (icount=0000, inc=4) + Entering IDLE_INNER state... + Leaving INNER state... (ocount=00EF) + [in=T a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... +Now: + [in=F a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] +*/ + + if ((idle && go && !datinit) + || (inner && !indone) + || (inner && indone && !outer0 && !upda1f && !upda1 && notgzandp && !upda2 && !datinit) + || (a1update && !upda2 && notgzandp && !datinit) + || (zupdate && !upda2 && !datinit) + || (a2update && !datinit) + || (init_ii && !gourz) + || (init_zi)) + { + inneri = true; + } + else + inneri = false; + + // A1 FRACTION UPDATE + + if (inner && indone && !outer0 && upda1f) + { + a1fupdatei = true; + } + else + a1fupdatei = false; + + // A1 POINTER UPDATE + + if ((a1fupdate) + || (inner && indone && !outer0 && !upda1f && upda1)) + { + a1updatei = true; + } + else + a1updatei = false; + + // Z FRACTION UPDATE + + if ((a1update && gourz && polygon) + || (inner && indone && !outer0 && !upda1f && !upda1 && gourz && polygon)) + { + zfupdatei = true; + } + else + zfupdatei = false; + + // Z INTEGER UPDATE + + if (zfupdate) + { + zupdatei = true; + } + else + zupdatei = false; + + // A2 POINTER UPDATE + + if ((a1update && upda2 && notgzandp) + || (zupdate && upda2) + || (inner && indone && !outer0 && !upda1f && notgzandp && !upda1 && upda2)) + { + a2updatei = true; + } + else + a2updatei = false; + + // INITIALIZE INTENSITY FRACTION + + if ((zupdate && !upda2 && datinit) + || (a1update && !upda2 && datinit && notgzandp) + || (inner && indone && !outer0 && !upda1f && !upda1 && notgzandp && !upda2 && datinit) + || (a2update && datinit) + || (idle && go && datinit)) + { + init_ifi = true; + } + else + init_ifi = false; + + // INITIALIZE INTENSITY INTEGER + + if (init_if) + { + init_iii = true; + } + else + init_iii = false; + + // INITIALIZE Z FRACTION + + if (init_ii && gourz) + { + init_zfi = true; + } + else + init_zfi = false; + + // INITIALIZE Z INTEGER + + if (init_zf) + { + init_zii = true; + } + else + init_zii = false; + +// Here we move the fooi into their foo counterparts in order to simulate the moving +// of data into the various FDSYNCs... Each time we loop we simulate one clock cycle... + + idle = idlei; + inner = inneri; + a1fupdate = a1fupdatei; + a1update = a1updatei; + zfupdate = zfupdatei; // * + zupdate = zupdatei; // * + a2update = a2updatei; + init_if = init_ifi; // * + init_ii = init_iii; // * + init_zf = init_zfi; // * + init_zi = init_zii; // * +// * denotes states that will never assert for Jaguar I +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" [in=%c a1f=%c a1=%c zf=%c z=%c a2=%c iif=%c iii=%c izf=%c izi=%c]\n", + (inner ? 'T' : 'F'), (a1fupdate ? 'T' : 'F'), (a1update ? 'T' : 'F'), + (zfupdate ? 'T' : 'F'), (zupdate ? 'T' : 'F'), (a2update ? 'T' : 'F'), + (init_if ? 'T' : 'F'), (init_ii ? 'T' : 'F'), (init_zf ? 'T' : 'F'), + (init_zi ? 'T' : 'F')); +#endif + +// Now, depending on how we want to handle things, we could either put the implementation +// of the various pieces up above, or handle them down below here. + +// Let's try postprocessing for now... + + if (inner) + { + indone = false; +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering INNER state...\n"); +#endif + uint16_t icount = GET16(blitter_ram, PIXLINECOUNTER + 2); + bool idle_inner = true, step = true, sreadx = false, szreadx = false, sread = false, + szread = false, dread = false, dzread = false, dwrite = false, dzwrite = false; + bool inner0 = false; + bool idle_inneri, sreadxi, szreadxi, sreadi, szreadi, dreadi, dzreadi, dwritei, dzwritei; + + // State lines that will never assert in Jaguar I + + bool textext = false, txtread = false; + +//other stuff +uint8_t srcshift = 0; +bool sshftld = true; // D flipflop (D -> Q): instart -> sshftld +//NOTE: sshftld probably is only asserted at the beginning of the inner loop. !!! FIX !!! +/* +Blit! (CMD = 01800005) +Flags: SRCEN SRCENX LFUFUNC=C + count = 626 x 1 + a1_base = 00037290, a2_base = 000095D0 + a1_x = 0000, a1_y = 0000, a2_x = 0002, a2_y = 0000 + a1_pixsize = 4, a2_pixsize = 4 + srcd=0000000000000000, dstd=0000000000000000, patd=0000000000000000 + Phrase mode is ON + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... + Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20] + Source extra read address/pix address: 000095D4/0 [0000001C00540038] + Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0] + Source read address/pix address: 000095D8/0 [0054003800009814] + Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026E, inc=4) + Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0] + Source read address/pix address: 000095E0/0 [00009968000377C7] + Entering A2_ADD state [a2_x=0008, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 00037298/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026A, inc=4) + Entering A1_ADD state [a1_x=0004, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... +*/ + +// while (!idle_inner) + while (true) + { + // IDLE + + if ((idle_inner && !step) + || (dzwrite && step && inner0) + || (dwrite && step && !dstwrz && inner0)) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering IDLE_INNER state...\n"); +#endif + idle_inneri = true; +break; + } + else + idle_inneri = false; + + // EXTRA SOURCE DATA READ + + if ((idle_inner && step && srcenx) + || (sreadx && !step)) + { + sreadxi = true; + } + else + sreadxi = false; + + // EXTRA SOURCE ZED READ + + if ((sreadx && step && srcenz) + || (szreadx && !step)) + { + szreadxi = true; + } + else + szreadxi = false; + + // TEXTURE DATA READ (not implemented because not in Jaguar I) + + // SOURCE DATA READ + + if ((szreadx && step && !textext) + || (sreadx && step && !srcenz && srcen) + || (idle_inner && step && !srcenx && !textext && srcen) + || (dzwrite && step && !inner0 && !textext && srcen) + || (dwrite && step && !dstwrz && !inner0 && !textext && srcen) + || (txtread && step && srcen) + || (sread && !step)) + { + sreadi = true; + } + else + sreadi = false; + + // SOURCE ZED READ + + if ((sread && step && srcenz) + || (szread && !step)) + { + szreadi = true; + } + else + szreadi = false; + + // DESTINATION DATA READ + + if ((szread && step && dsten) + || (sread && step && !srcenz && dsten) + || (sreadx && step && !srcenz && !textext && !srcen && dsten) + || (idle_inner && step && !srcenx && !textext && !srcen && dsten) + || (dzwrite && step && !inner0 && !textext && !srcen && dsten) + || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && dsten) + || (txtread && step && !srcen && dsten) + || (dread && !step)) + { + dreadi = true; + } + else + dreadi = false; + + // DESTINATION ZED READ + + if ((dread && step && dstenz) + || (szread && step && !dsten && dstenz) + || (sread && step && !srcenz && !dsten && dstenz) + || (sreadx && step && !srcenz && !textext && !srcen && !dsten && dstenz) + || (idle_inner && step && !srcenx && !textext && !srcen && !dsten && dstenz) + || (dzwrite && step && !inner0 && !textext && !srcen && !dsten && dstenz) + || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && !dsten && dstenz) + || (txtread && step && !srcen && !dsten && dstenz) + || (dzread && !step)) + { + dzreadi = true; + } + else + dzreadi = false; + + // DESTINATION DATA WRITE + + if ((dzread && step) + || (dread && step && !dstenz) + || (szread && step && !dsten && !dstenz) + || (sread && step && !srcenz && !dsten && !dstenz) + || (txtread && step && !srcen && !dsten && !dstenz) + || (sreadx && step && !srcenz && !textext && !srcen && !dsten && !dstenz) + || (idle_inner && step && !srcenx && !textext && !srcen && !dsten && !dstenz) + || (dzwrite && step && !inner0 && !textext && !srcen && !dsten && !dstenz) + || (dwrite && step && !dstwrz && !inner0 && !textext && !srcen && !dsten && !dstenz) + || (dwrite && !step)) + { + dwritei = true; + } + else + dwritei = false; + + // DESTINATION ZED WRITE + + if ((dzwrite && !step) + || (dwrite && step && dstwrz)) + { + dzwritei = true; + } + else + dzwritei = false; + +//Kludge: A QnD way to make sure that sshftld is asserted only for the first +// cycle of the inner loop... +sshftld = idle_inner; + +// Here we move the fooi into their foo counterparts in order to simulate the moving +// of data into the various FDSYNCs... Each time we loop we simulate one clock cycle... + + idle_inner = idle_inneri; + sreadx = sreadxi; + szreadx = szreadxi; + sread = sreadi; + szread = szreadi; + dread = dreadi; + dzread = dzreadi; + dwrite = dwritei; + dzwrite = dzwritei; + +// Here's a few more decodes--not sure if they're supposed to go here or not... + + bool srca_addi = (sreadxi && !srcenz) || (sreadi && !srcenz) || szreadxi || szreadi; + + bool dsta_addi = (dwritei && !dstwrz) || dzwritei; + + bool gensrc = sreadxi || szreadxi || sreadi || szreadi; + bool gendst = dreadi || dzreadi || dwritei || dzwritei; + bool gena2i = (gensrc && !dsta2) || (gendst && dsta2); + + bool zaddr = szreadx || szread || dzread || dzwrite; + +// Some stuff from MCONTROL.NET--not sure if this is the correct use of this decode or not... +/*Fontread\ := OND1 (fontread\, sread[1], sreadx[1], bcompen); +Fontread := INV1 (fontread, fontread\); +Justt := NAN3 (justt, fontread\, phrase_mode, tactive\); +Justify := TS (justify, justt, busen);*/ +bool fontread = (sread || sreadx) && bcompen; +bool justify = !(!fontread && phrase_mode /*&& tactive*/); + +/* Generate inner loop update enables */ +/* +A1_addi := MX2 (a1_addi, dsta_addi, srca_addi, dsta2); +A2_addi := MX2 (a2_addi, srca_addi, dsta_addi, dsta2); +A1_add := FD1 (a1_add, a1_add\, a1_addi, clk); +A2_add := FD1 (a2_add, a2_add\, a2_addi, clk); +A2_addb := BUF1 (a2_addb, a2_add); +*/ + bool a1_add = (dsta2 ? srca_addi : dsta_addi); + bool a2_add = (dsta2 ? dsta_addi : srca_addi); + +/* Address adder input A register selection +000 A1 step integer part +001 A1 step fraction part +010 A1 increment integer part +011 A1 increment fraction part +100 A2 step + +bit 2 = a2update +bit 1 = /a2update . (a1_add . a1addx[0..1]) +bit 0 = /a2update . ( a1fupdate + + a1_add . atick[0] . a1addx[0..1]) +The /a2update term on bits 0 and 1 is redundant. +Now look-ahead based +*/ + uint8_t addasel = (a1fupdate || (a1_add && a1addx == 3) ? 0x01 : 0x00); + addasel |= (a1_add && a1addx == 3 ? 0x02 : 0x00); + addasel |= (a2update ? 0x04 : 0x00); +/* Address adder input A X constant selection +adda_xconst[0..2] generate a power of 2 in the range 1-64 or all +zeroes when they are all 1 +Remember - these are pixels, so to add one phrase the pixel size +has to be taken into account to get the appropriate value. +for A1 + if a1addx[0..1] are 00 set 6 - pixel size + if a1addx[0..1] are 01 set the value 000 + if a1addx[0..1] are 10 set the value 111 +similarly for A2 +JLH: Also, 11 will likewise set the value to 111 +*/ + uint8_t a1_xconst = 6 - a1_pixsize, a2_xconst = 6 - a2_pixsize; + + if (a1addx == 1) + a1_xconst = 0; + else if (a1addx & 0x02) + a1_xconst = 7; + + if (a2addx == 1) + a2_xconst = 0; + else if (a2addx & 0x02) + a2_xconst = 7; + + uint8_t adda_xconst = (a2_add ? a2_xconst : a1_xconst); +/* Address adder input A Y constant selection +22 June 94 - This was erroneous, because only the a1addy bit was reflected here. +Therefore, the selection has to be controlled by a bug fix bit. +JLH: Bug fix bit in Jaguar II--not in Jaguar I! +*/ + bool adda_yconst = a1addy; +/* Address adder input A register versus constant selection +given by a1_add . a1addx[0..1] + + a1update + + a1fupdate + + a2_add . a2addx[0..1] + + a2update +*/ + bool addareg = ((a1_add && a1addx == 3) || a1update || a1fupdate + || (a2_add && a2addx == 3) || a2update ? true : false); +/* The adders can be put into subtract mode in add pixel size +mode when the corresponding flags are set */ + bool suba_x = ((a1_add && a1xsign && a1addx == 1) || (a2_add && a2xsign && a2addx == 1) ? true : false); + bool suba_y = ((a1_add && a1addy && a1ysign) || (a2_add && a2addy && a2ysign) ? true : false); +/* Address adder input B selection +00 A1 pointer +01 A2 pointer +10 A1 fraction +11 Zero + +Bit 1 = a1fupdate + + (a1_add . atick[0] . a1addx[0..1]) + + a1fupdate . a1_stepld + + a1update . a1_stepld + + a2update . a2_stepld +Bit 0 = a2update + a2_add + + a1fupdate . a1_stepld + + a1update . a1_stepld + + a2update . a2_stepld +*/ + uint8_t addbsel = (a2update || a2_add || (a1fupdate && a1_stepld) + || (a1update && a1_stepld) || (a2update && a2_stepld) ? 0x01 : 0x00); + addbsel |= (a1fupdate || (a1_add && a1addx == 3) || (a1fupdate && a1_stepld) + || (a1update && a1_stepld) || (a2update && a2_stepld) ? 0x02 : 0x00); + +/* The modulo bits are used to align X onto a phrase boundary when +it is being updated by one phrase +000 no mask +001 mask bit 0 +010 mask bits 1-0 +.. +110 mask bits 5-0 + +Masking is enabled for a1 when a1addx[0..1] is 00, and the value +is 6 - the pixel size (again!) +*/ + uint8_t maska1 = (a1_add && a1addx == 0 ? 6 - a1_pixsize : 0); + uint8_t maska2 = (a2_add && a2addx == 0 ? 6 - a2_pixsize : 0); + uint8_t modx = (a2_add ? maska2 : maska1); +/* Generate load strobes for the increment updates */ + +/*A1pldt := NAN2 (a1pldt, atick[1], a1_add); +A1ptrldi := NAN2 (a1ptrldi, a1update\, a1pldt); + +A1fldt := NAN4 (a1fldt, atick[0], a1_add, a1addx[0..1]); +A1fracldi := NAN2 (a1fracldi, a1fupdate\, a1fldt); + +A2pldt := NAN2 (a2pldt, atick[1], a2_add); +A2ptrldi := NAN2 (a2ptrldi, a2update\, a2pldt);*/ + bool a1fracldi = a1fupdate || (a1_add && a1addx == 3); + +// Some more from DCONTROL... +// atick[] just MAY be important here! We're assuming it's true and dropping the term... +// That will probably screw up some of the lower terms that seem to rely on the timing of it... +#warning srcdreadd is not properly initialized! +bool srcdreadd = false; // Set in INNER.NET +//Shadeadd\ := NAN2H (shadeadd\, dwrite, srcshade); +//Shadeadd := INV2 (shadeadd, shadeadd\); +bool shadeadd = dwrite && srcshade; +/* Data adder control, input A selection +000 Destination data +001 Initialiser pixel value +100 Source data - computed intensity fraction +101 Pattern data - computed intensity +110 Source zed 1 - computed zed +111 Source zed 2 - computed zed fraction + +Bit 0 = dwrite . gourd . atick[1] + + dzwrite . gourz . atick[0] + + istepadd + + zstepfadd + + init_if + init_ii + init_zf + init_zi +Bit 1 = dzwrite . gourz . (atick[0] + atick[1]) + + zstepadd + + zstepfadd +Bit 2 = (gourd + gourz) . /(init_if + init_ii + init_zf + init_zi) + + dwrite . srcshade +*/ +uint8_t daddasel = ((dwrite && gourd) || (dzwrite && gourz) || istepadd || zstepfadd + || init_if || init_ii || init_zf || init_zi ? 0x01 : 0x00); +daddasel |= ((dzwrite && gourz) || zstepadd || zstepfadd ? 0x02 : 0x00); +daddasel |= (((gourd || gourz) && !(init_if || init_ii || init_zf || init_zi)) + || (dwrite && srcshade) ? 0x04 : 0x00); +/* Data adder control, input B selection +0000 Source data +0001 Data initialiser increment +0100 Bottom 16 bits of I increment repeated four times +0101 Top 16 bits of I increment repeated four times +0110 Bottom 16 bits of Z increment repeated four times +0111 Top 16 bits of Z increment repeated four times +1100 Bottom 16 bits of I step repeated four times +1101 Top 16 bits of I step repeated four times +1110 Bottom 16 bits of Z step repeated four times +1111 Top 16 bits of Z step repeated four times + +Bit 0 = dwrite . gourd . atick[1] + + dzwrite . gourz . atick[1] + + dwrite . srcshade + + istepadd + + zstepadd + + init_if + init_ii + init_zf + init_zi +Bit 1 = dzwrite . gourz . (atick[0] + atick[1]) + + zstepadd + + zstepfadd +Bit 2 = dwrite . gourd . (atick[0] + atick[1]) + + dzwrite . gourz . (atick[0] + atick[1]) + + dwrite . srcshade + + istepadd + istepfadd + zstepadd + zstepfadd +Bit 3 = istepadd + istepfadd + zstepadd + zstepfadd +*/ +uint8_t daddbsel = ((dwrite && gourd) || (dzwrite && gourz) || (dwrite && srcshade) + || istepadd || zstepadd || init_if || init_ii || init_zf || init_zi ? 0x01 : 0x00); +daddbsel |= ((dzwrite && gourz) || zstepadd || zstepfadd ? 0x02 : 0x00); +daddbsel |= ((dwrite && gourd) || (dzwrite && gourz) || (dwrite && srcshade) + || istepadd || istepfadd || zstepadd || zstepfadd ? 0x04 : 0x00); +daddbsel |= (istepadd && istepfadd && zstepadd && zstepfadd ? 0x08 : 0x00); +/* Data adder mode control +000 16-bit normal add +001 16-bit saturating add with carry +010 8-bit saturating add with carry, carry into top byte is + inhibited (YCrCb) +011 8-bit saturating add with carry, carry into top byte and + between top nybbles is inhibited (CRY) +100 16-bit normal add with carry +101 16-bit saturating add +110 8-bit saturating add, carry into top byte is inhibited +111 8-bit saturating add, carry into top byte and between top + nybbles is inhibited + +The first five are used for Gouraud calculations, the latter three +for adding source and destination data + +Bit 0 = dzwrite . gourz . atick[1] + + dwrite . gourd . atick[1] . /topnen . /topben . /ext_int + + dwrite . gourd . atick[1] . topnen . topben . /ext_int + + zstepadd + + istepadd . /topnen . /topben . /ext_int + + istepadd . topnen . topben . /ext_int + + /gourd . /gourz . /topnen . /topben + + /gourd . /gourz . topnen . topben + + shadeadd . /topnen . /topben + + shadeadd . topnen . topben + + init_ii . /topnen . /topben . /ext_int + + init_ii . topnen . topben . /ext_int + + init_zi + +Bit 1 = dwrite . gourd . atick[1] . /topben . /ext_int + + istepadd . /topben . /ext_int + + /gourd . /gourz . /topben + + shadeadd . /topben + + init_ii . /topben . /ext_int + +Bit 2 = /gourd . /gourz + + shadeadd + + dwrite . gourd . atick[1] . ext_int + + istepadd . ext_int + + init_ii . ext_int +*/ +uint8_t daddmode = ((dzwrite && gourz) || (dwrite && gourd && !topnen && !topben && !ext_int) + || (dwrite && gourd && topnen && topben && !ext_int) || zstepadd + || (istepadd && !topnen && !topben && !ext_int) + || (istepadd && topnen && topben && !ext_int) || (!gourd && !gourz && !topnen && !topben) + || (!gourd && !gourz && topnen && topben) || (shadeadd && !topnen && !topben) + || (shadeadd && topnen && topben) || (init_ii && !topnen && !topben && !ext_int) + || (init_ii && topnen && topben && !ext_int) || init_zi ? 0x01 : 0x00); +daddmode |= ((dwrite && gourd && !topben && !ext_int) || (istepadd && !topben && !ext_int) + || (!gourd && !gourz && !topben) || (shadeadd && !topben) + || (init_ii && !topben && !ext_int) ? 0x02 : 0x00); +daddmode |= ((!gourd && !gourz) || shadeadd || (dwrite && gourd && ext_int) + || (istepadd && ext_int) || (init_ii && ext_int) ? 0x04 : 0x00); +/* Data add load controls +Pattern fraction (dest data) is loaded on + dwrite . gourd . atick[0] + + istepfadd . /datinit + + init_if +Pattern data is loaded on + dwrite . gourd . atick[1] + + istepadd . /datinit . /datinit + + init_ii +Source z1 is loaded on + dzwrite . gourz . atick[1] + + zstepadd . /datinit . /datinit + + init_zi +Source z2 is loaded on + dzwrite . gourz . atick[0] + + zstepfadd + + init_zf +Texture map shaded data is loaded on + srcdreadd . srcshade +*/ +bool patfadd = (dwrite && gourd) || (istepfadd && !datinit) || init_if; +bool patdadd = (dwrite && gourd) || (istepadd && !datinit) || init_ii; +bool srcz1add = (dzwrite && gourz) || (zstepadd && !datinit) || init_zi; +bool srcz2add = (dzwrite && gourz) || zstepfadd || init_zf; +bool srcshadd = srcdreadd && srcshade; +bool daddq_sel = patfadd || patdadd || srcz1add || srcz2add || srcshadd; +/* Select write data +This has to be controlled from stage 1 of the pipe-line, delayed +by one tick, as the write occurs in the cycle after the ack. + +00 pattern data +01 lfu data +10 adder output +11 source zed + +Bit 0 = /patdsel . /adddsel + + dzwrite1d +Bit 1 = adddsel + + dzwrite1d +*/ +uint8_t data_sel = ((!patdsel && !adddsel) || dzwrite ? 0x01 : 0x00) + | (adddsel || dzwrite ? 0x02 : 0x00); + +uint32_t address, pixAddr; +ADDRGEN(address, pixAddr, gena2i, zaddr, + a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset, + a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset); + +//Here's my guess as to how the addresses get truncated to phrase boundaries in phrase mode... +if (!justify) + address &= 0xFFFFF8; + +/* Generate source alignment shift + ------------------------------- +The source alignment shift for data move is the difference between +the source and destination X pointers, multiplied by the pixel +size. Only the low six bits of the pointers are of interest, as +pixel sizes are always a power of 2 and window rows are always +phrase aligned. + +When not in phrase mode, the top 3 bits of the shift value are +set to zero (2/26). + +Source shifting is also used to extract bits for bit-to-byte +expansion in phrase mode. This involves only the bottom three +bits of the shift value, and is based on the offset within the +phrase of the destination X pointer, in pixels. + +Source shifting is disabled when srcen is not set. +*/ +uint8_t dstxp = (dsta2 ? a2_x : a1_x) & 0x3F; +uint8_t srcxp = (dsta2 ? a1_x : a2_x) & 0x3F; +uint8_t shftv = ((dstxp - srcxp) << pixsize) & 0x3F; +/* The phrase mode alignment count is given by the phrase offset +of the first pixel, for bit to byte expansion */ +uint8_t pobb = 0; + +if (pixsize == 3) + pobb = dstxp & 0x07; +if (pixsize == 4) + pobb = dstxp & 0x03; +if (pixsize == 5) + pobb = dstxp & 0x01; + +bool pobbsel = phrase_mode && bcompen; +uint8_t loshd = (pobbsel ? pobb : shftv) & 0x07; +uint8_t shfti = (srcen || pobbsel ? (sshftld ? loshd : srcshift & 0x07) : 0); +/* Enable for high bits is srcen . phrase_mode */ +shfti |= (srcen && phrase_mode ? (sshftld ? shftv & 0x38 : srcshift & 0x38) : 0); +srcshift = shfti; + + if (sreadx) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering SREADX state..."); +#endif +//uint32_t srcAddr, pixAddr; +//ADDRGEN(srcAddr, pixAddr, gena2i, zaddr, +// a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset, +// a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset); + srcd2 = srcd1; + srcd1 = ((uint64_t)JaguarReadLong(address + 0, BLITTER) << 32) + | (uint64_t)JaguarReadLong(address + 4, BLITTER); +//Kludge to take pixel size into account... +//Hmm. If we're not in phrase mode, this is most likely NOT going to be used... +//Actually, it would be--because of BCOMPEN expansion, for example... +if (!phrase_mode) +{ + if (bcompen) + srcd1 >>= 56; + else + { + if (pixsize == 5) + srcd1 >>= 32; + else if (pixsize == 4) + srcd1 >>= 48; + else + srcd1 >>= 56; + } +}//*/ +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Source extra read address/pix address: %08X/%1X [%08X%08X]\n", + address, pixAddr, (uint32_t)(srcd1 >> 32), (uint32_t)(srcd1 & 0xFFFFFFFF)); +#endif + } + + if (szreadx) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering SZREADX state..."); +#endif + srcz2 = srcz1; + srcz1 = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Src Z extra read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr, + (uint32_t)(dstz >> 32), (uint32_t)(dstz & 0xFFFFFFFF)); +#endif + } + + if (sread) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering SREAD state..."); +#endif +//uint32_t srcAddr, pixAddr; +//ADDRGEN(srcAddr, pixAddr, gena2i, zaddr, +// a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset, +// a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset); +srcd2 = srcd1; +srcd1 = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); +//Kludge to take pixel size into account... +if (!phrase_mode) +{ + if (bcompen) + srcd1 >>= 56; + else + { + if (pixsize == 5) + srcd1 >>= 32; + else if (pixsize == 4) + srcd1 >>= 48; + else + srcd1 >>= 56; + } +} +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Source read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr, + (uint32_t)(srcd1 >> 32), (uint32_t)(srcd1 & 0xFFFFFFFF)); +//fflush(stdout); +} +#endif + } + + if (szread) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Entering SZREAD state..."); +//fflush(stdout); +} +#endif + srcz2 = srcz1; + srcz1 = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); +//Kludge to take pixel size into account... I believe that it only has to take 16BPP mode into account. Not sure tho. +if (!phrase_mode && pixsize == 4) + srcz1 >>= 48; + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog(" Src Z read address/pix address: %08X/%1X [%08X%08X]\n", address, pixAddr, + (uint32_t)(dstz >> 32), (uint32_t)(dstz & 0xFFFFFFFF)); +} +#endif + } + + if (dread) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering DREAD state..."); +#endif +//uint32_t dstAddr, pixAddr; +//ADDRGEN(dstAddr, pixAddr, gena2i, zaddr, +// a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset, +// a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset); +dstd = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); +//Kludge to take pixel size into account... +if (!phrase_mode) +{ + if (pixsize == 5) + dstd >>= 32; + else if (pixsize == 4) + dstd >>= 48; + else + dstd >>= 56; +} +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Dest read address/pix address: %08X/%1X [%08X%08X]\n", address, + pixAddr, (uint32_t)(dstd >> 32), (uint32_t)(dstd & 0xFFFFFFFF)); +#endif + } + + if (dzread) + { +// Is Z always 64 bit read? Or sometimes 16 bit (dependent on phrase_mode)? +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering DZREAD state..."); +#endif + dstz = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); +//Kludge to take pixel size into account... I believe that it only has to take 16BPP mode into account. Not sure tho. +if (!phrase_mode && pixsize == 4) + dstz >>= 48; + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Dest Z read address/pix address: %08X/%1X [%08X%08X]\n", address, + pixAddr, (uint32_t)(dstz >> 32), (uint32_t)(dstz & 0xFFFFFFFF)); +#endif + } + +// These vars should probably go further up in the code... !!! FIX !!! +// We can't preassign these unless they're static... +//uint64_t srcz = 0; // These are assigned to shut up stupid compiler warnings--dwrite is ALWAYS asserted +//bool winhibit = false; +uint64_t srcz; +bool winhibit; +//NOTE: SRCSHADE requires GOURZ to be set to work properly--another Jaguar I bug + if (dwrite) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Entering DWRITE state..."); +#endif +//Counter is done on the dwrite state...! (We'll do it first, since it affects dstart/dend calculations.) +//Here's the voodoo for figuring the correct amount of pixels in phrase mode (or not): + int8_t inct = -((dsta2 ? a2_x : a1_x) & 0x07); // From INNER_CNT + uint8_t inc = 0; + inc = (!phrase_mode || (phrase_mode && (inct & 0x01)) ? 0x01 : 0x00); + inc |= (phrase_mode && (((pixsize == 3 || pixsize == 4) && (inct & 0x02)) || pixsize == 5 && !(inct & 0x01)) ? 0x02 : 0x00); + inc |= (phrase_mode && ((pixsize == 3 && (inct & 0x04)) || (pixsize == 4 && !(inct & 0x03))) ? 0x04 : 0x00); + inc |= (phrase_mode && pixsize == 3 && !(inct & 0x07) ? 0x08 : 0x00); + + uint16_t oldicount = icount; // Save icount to detect underflow... + icount -= inc; + + if (icount == 0 || ((icount & 0x8000) && !(oldicount & 0x8000))) + inner0 = true; +// X/Y stepping is also done here, I think...No. It's done when a1_add or a2_add is asserted... + +//********************************************************************************* +//Start & end write mask computations... +//********************************************************************************* + +uint8_t dstart = 0; + +if (pixsize == 3) + dstart = (dstxp & 0x07) << 3; +if (pixsize == 4) + dstart = (dstxp & 0x03) << 4; +if (pixsize == 5) + dstart = (dstxp & 0x01) << 5; + +dstart = (phrase_mode ? dstart : pixAddr & 0x07); + +//This is the other Jaguar I bug... Normally, should ALWAYS select a1_x here. +uint16_t dstxwr = (dsta2 ? a2_x : a1_x) & 0x7FFE; +uint16_t pseq = dstxwr ^ (a1_win_x & 0x7FFE); +pseq = (pixsize == 5 ? pseq : pseq & 0x7FFC); +pseq = ((pixsize & 0x06) == 4 ? pseq : pseq & 0x7FF8); +bool penden = clip_a1 && (pseq == 0); +uint8_t window_mask = 0; + +if (pixsize == 3) + window_mask = (a1_win_x & 0x07) << 3; +if (pixsize == 4) + window_mask = (a1_win_x & 0x03) << 4; +if (pixsize == 5) + window_mask = (a1_win_x & 0x01) << 5; + +window_mask = (penden ? window_mask : 0); + +/* + Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20] + Source extra read address/pix address: 000095D0/0 [000004E40000001C] + Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=20] + Source read address/pix address: 000095D8/0 [0054003800009814] + Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=20][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000001C00000000] (icount=026E, inc=4) + Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + +(icount=026E, inc=4) +icount & 0x03 = 0x02 + << 4 = 0x20 + +window_mask = 0x1000 + +Therefore, it chooses the inner_mask over the window_mask every time! Argh! +This is because we did this wrong: +Innerm[3-5] := AN2 (inner_mask[3-5], imb[3-5], inner0); +NOTE! This doesn't fix the problem because inner0 is asserted too late to help here. !!! FIX !!! [Should be DONE] +*/ + +/* The mask to be used if within one phrase of the end of the inner +loop, similarly */ +uint8_t inner_mask = 0; + +if (pixsize == 3) + inner_mask = (icount & 0x07) << 3; +if (pixsize == 4) + inner_mask = (icount & 0x03) << 4; +if (pixsize == 5) + inner_mask = (icount & 0x01) << 5; +if (!inner0) + inner_mask = 0; +/* The actual mask used should be the lesser of the window masks and +the inner mask, where is all cases 000 means 1000. */ +window_mask = (window_mask == 0 ? 0x40 : window_mask); +inner_mask = (inner_mask == 0 ? 0x40 : inner_mask); +uint8_t emask = (window_mask > inner_mask ? inner_mask : window_mask); +/* The mask to be used for the pixel size, to which must be added +the bit offset */ +uint8_t pma = pixAddr + (1 << pixsize); +/* Select the mask */ +uint8_t dend = (phrase_mode ? emask : pma); + +/* The cycle width in phrase mode is normally one phrase. However, +at the start and end it may be narrower. The start and end masks +are used to generate this. The width is given by: + + 8 - start mask - (8 - end mask) += end mask - start mask + +This is only used for writes in phrase mode. +Start and end from the address level of the pipeline are used. +*/ +uint8_t pwidth = (((dend | dstart) & 0x07) == 0 ? 0x08 : (dend - dstart) & 0x07); + +//uint32_t dstAddr, pixAddr; +//ADDRGEN(dstAddr, pixAddr, gena2i, zaddr, +// a1_x, a1_y, a1_base, a1_pitch, a1_pixsize, a1_width, a1_zoffset, +// a2_x, a2_y, a2_base, a2_pitch, a2_pixsize, a2_width, a2_zoffset); +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" Dest write address/pix address: %08X/%1X", address, pixAddr); +#endif + +//More testing... This is almost certainly wrong, but how else does this work??? +//Seems to kinda work... But still, this doesn't seem to make any sense! +if (phrase_mode && !dsten) + dstd = ((uint64_t)JaguarReadLong(address, BLITTER) << 32) | (uint64_t)JaguarReadLong(address + 4, BLITTER); + +//Testing only... for now... +//This is wrong because the write data is a combination of srcd and dstd--either run +//thru the LFU or in PATDSEL or ADDDSEL mode. [DONE now, thru DATA module] +// Precedence is ADDDSEL > PATDSEL > LFU. +//Also, doesn't take into account the start & end masks, or the phrase width... +//Now it does! + +// srcd2 = xxxx xxxx 0123 4567, srcd = 8901 2345 xxxx xxxx, srcshift = $20 (32) +uint64_t srcd = (srcd2 << (64 - srcshift)) | (srcd1 >> srcshift); +//bleh, ugly ugly ugly +if (srcshift == 0) + srcd = srcd1; + +//NOTE: This only works with pixel sizes less than 8BPP... +//DOUBLE NOTE: Still need to do regression testing to ensure that this doesn't break other stuff... !!! CHECK !!! +if (!phrase_mode && srcshift != 0) + srcd = ((srcd2 & 0xFF) << (8 - srcshift)) | ((srcd1 & 0xFF) >> srcshift); + +//Z DATA() stuff done here... And it has to be done before any Z shifting... +//Note that we need to have phrase mode start/end support here... (Not since we moved it from dzwrite...!) +/* +Here are a couple of Cybermorph blits with Z: +$00113078 // DSTEN DSTENZ DSTWRZ CLIP_A1 GOURD GOURZ PATDSEL ZMODE=4 +$09900F39 // SRCEN DSTEN DSTENZ DSTWRZ UPDA1 UPDA1F UPDA2 DSTA2 ZMODE=4 LFUFUNC=C DCOMPEN + +We're having the same phrase mode overwrite problem we had with the pixels... !!! FIX !!! +Odd. It's equating 0 with 0... Even though ZMODE is $04 (less than)! +*/ +if (gourz) +{ +/* +void ADDARRAY(uint16_t * addq, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, + uint64_t dstd, uint32_t iinc, uint8_t initcin[], uint64_t initinc, uint16_t initpix, + uint32_t istep, uint64_t patd, uint64_t srcd, uint64_t srcz1, uint64_t srcz2, + uint32_t zinc, uint32_t zstep) +*/ + uint16_t addq[4]; + uint8_t initcin[4] = { 0, 0, 0, 0 }; + ADDARRAY(addq, 7/*daddasel*/, 6/*daddbsel*/, 0/*daddmode*/, 0, 0, initcin, 0, 0, 0, 0, 0, srcz1, srcz2, zinc, 0); + srcz2 = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; + ADDARRAY(addq, 6/*daddasel*/, 7/*daddbsel*/, 1/*daddmode*/, 0, 0, initcin, 0, 0, 0, 0, 0, srcz1, srcz2, zinc, 0); + srcz1 = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; + +#if 0//def VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog("\n[srcz1=%08X%08X, srcz2=%08X%08X, zinc=%08X", + (uint32_t)(srcz1 >> 32), (uint32_t)(srcz1 & 0xFFFFFFFF), + (uint32_t)(srcz2 >> 32), (uint32_t)(srcz2 & 0xFFFFFFFF), zinc); +#endif +} + +uint8_t zSrcShift = srcshift & 0x30; +srcz = (srcz2 << (64 - zSrcShift)) | (srcz1 >> zSrcShift); +//bleh, ugly ugly ugly +if (zSrcShift == 0) + srcz = srcz1; + +#if 0//def VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog(" srcz=%08X%08X]\n", (uint32_t)(srcz >> 32), (uint32_t)(srcz & 0xFFFFFFFF)); +#endif + +//When in SRCSHADE mode, it adds the IINC to the read source (from LFU???) +//According to following line, it gets LFU mode. But does it feed the source into the LFU +//after the add? +//Dest write address/pix address: 0014E83E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003F, inc=1) +//Let's try this: +if (srcshade) +{ +//NOTE: This is basically doubling the work done by DATA--since this is what +// ADDARRAY is loaded with when srschshade is enabled... !!! FIX !!! +// Also note that it doesn't work properly unless GOURZ is set--there's the clue! + uint16_t addq[4]; + uint8_t initcin[4] = { 0, 0, 0, 0 }; + ADDARRAY(addq, 4/*daddasel*/, 5/*daddbsel*/, 7/*daddmode*/, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0); + srcd = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; +} +//Seems to work... Not 100% sure tho. +//end try this + +//Temporary kludge, to see if the fractional pattern does anything... +//This works, BTW +//But it seems to mess up in Cybermorph... the shading should be smooth but it isn't... +//Seems the carry out is lost again... !!! FIX !!! [DONE--see below] +if (patfadd) +{ + uint16_t addq[4]; + uint8_t initcin[4] = { 0, 0, 0, 0 }; + ADDARRAY(addq, 4/*daddasel*/, 4/*daddbsel*/, 0/*daddmode*/, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0); + srcd1 = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; +} + +//Note that we still don't take atick[0] & [1] into account here, so this will skip half of the data needed... !!! FIX !!! +//Not yet enumerated: dbinh, srcdread, srczread +//Also, should do srcshift on the z value in phrase mode... !!! FIX !!! [DONE] +//As well as add a srcz variable we can set external to this state... !!! FIX !!! [DONE] + +uint64_t wdata; +uint8_t dcomp, zcomp; +DATA(wdata, dcomp, zcomp, winhibit, + true, cmpdst, daddasel, daddbsel, daddmode, daddq_sel, data_sel, 0/*dbinh*/, + dend, dstart, dstd, iinc, lfufunc, patd, patdadd, + phrase_mode, srcd, false/*srcdread*/, false/*srczread*/, srcz2add, zmode, + bcompen, bkgwren, dcompen, icount & 0x07, pixsize, + srcz, dstz, zinc); +/* +Seems that the phrase mode writes with DCOMPEN and DSTEN are corrupting inside of DATA: !!! FIX !!! +It's fairly random as well. 7CFE -> 7DFE, 7FCA -> 78CA, 7FA4 -> 78A4, 7F88 -> 8F88 +It could be related to an uninitialized variable, like the zmode bug... +[DONE] +It was a bug in the dech38el data--it returned $FF for ungated instead of $00... + +Blit! (CMD = 09800609) +Flags: SRCEN DSTEN UPDA1 UPDA2 LFUFUNC=C DCOMPEN + count = 10 x 12 + a1_base = 00110000, a2_base = 0010B2A8 + a1_x = 004B, a1_y = 00D8, a1_frac_x = 0000, a1_frac_y = 0000, a2_x = 0704, a2_y = 0000 + a1_step_x = FFF3, a1_step_y = 0001, a1_stepf_x = 0000, a1_stepf_y = 0000, a2_step_x = FFFC, a2_step_y = 0000 + a1_inc_x = 0000, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0000, a1_win_y = 0000, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+phr/+0 + a1_pixsize = 4, a2_pixsize = 4 + srcd=0000000000000000 dstd=0000000000000000 patd=0000000000000000 iinc=00000000 + srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, coll=0 + Phrase mode is ON + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... + Entering SREAD state... Source read address/pix address: 0010C0B0/0 [0000000078047804] + Entering A2_ADD state [a2_x=0704, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DREAD state... + Dest read address/pix address: 00197240/0 [0000000000000028] + Entering DWRITE state... + Dest write address/pix address: 00197240/0 [dstart=30 dend=40 pwidth=8 srcshift=30][daas=0 dabs=0 dam=7 ds=1 daq=F] [0000000000000028] (icount=0009, inc=1) + Entering A1_ADD state [a1_x=004B, a1_y=00D8, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0010C0B8/0 [7804780478047804] + Entering A2_ADD state [a2_x=0708, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DREAD state... + Dest read address/pix address: 00197260/0 [0028000000200008] + Entering DWRITE state... + Dest write address/pix address: 00197260/0 [dstart=0 dend=40 pwidth=8 srcshift=30][daas=0 dabs=0 dam=7 ds=1 daq=F] [0028780478047804] (icount=0005, inc=4) + Entering A1_ADD state [a1_x=004C, a1_y=00D8, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0010C0C0/0 [0000000000000000] + Entering A2_ADD state [a2_x=070C, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DREAD state... + Dest read address/pix address: 00197280/0 [0008001800180018] + Entering DWRITE state... + Dest write address/pix address: 00197280/0 [dstart=0 dend=40 pwidth=8 srcshift=30][daas=0 dabs=0 dam=7 ds=1 daq=F] [7804780478040018] (icount=0001, inc=4) + Entering A1_ADD state [a1_x=0050, a1_y=00D8, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0010C0C8/0 [000078047BFE7BFE] + Entering A2_ADD state [a2_x=0710, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering DREAD state... + Dest read address/pix address: 001972A0/0 [0008002000000000] + Entering DWRITE state... + Dest write address/pix address: 001972A0/0 [dstart=0 dend=10 pwidth=8 srcshift=30][daas=0 dabs=0 dam=7 ds=1 daq=F] [0008002000000000] (icount=FFFD, inc=4) + Entering A1_ADD state [a1_x=0054, a1_y=00D8, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering IDLE_INNER state... +*/ + +//Why isn't this taken care of in DATA? Because, DATA is modifying its local copy instead of the one used here. +//!!! FIX !!! [DONE] +//if (patdadd) +// patd = wdata; + +//if (patfadd) +// srcd1 = wdata; + +/* +DEF ADDRCOMP ( + a1_outside // A1 pointer is outside window bounds + :OUT; +INT16/ a1_x +INT16/ a1_y +INT15/ a1_win_x +INT15/ a1_win_y + :IN); +BEGIN + +// The address is outside if negative, or if greater than or equal +// to the window size + +A1_xcomp := MAG_15 (a1xgr, a1xeq, a1xlt, a1_x{0..14}, a1_win_x{0..14}); +A1_ycomp := MAG_15 (a1ygr, a1yeq, a1ylt, a1_y{0..14}, a1_win_y{0..14}); +A1_outside := OR6 (a1_outside, a1_x{15}, a1xgr, a1xeq, a1_y{15}, a1ygr, a1yeq); +*/ +//NOTE: There seems to be an off-by-one bug here in the clip_a1 section... !!! FIX !!! +// Actually, seems to be related to phrase mode writes... +// Or is it? Could be related to non-15-bit compares as above? +if (clip_a1 && ((a1_x & 0x8000) || (a1_y & 0x8000) || (a1_x >= a1_win_x) || (a1_y >= a1_win_y))) + winhibit = true; + +if (!winhibit) +{ + if (phrase_mode) + { + JaguarWriteLong(address + 0, wdata >> 32, BLITTER); + JaguarWriteLong(address + 4, wdata & 0xFFFFFFFF, BLITTER); + } + else + { + if (pixsize == 5) + JaguarWriteLong(address, wdata & 0xFFFFFFFF, BLITTER); + else if (pixsize == 4) + JaguarWriteWord(address, wdata & 0x0000FFFF, BLITTER); + else + JaguarWriteByte(address, wdata & 0x000000FF, BLITTER); + } +} + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog(" [%08X%08X]%s", (uint32_t)(wdata >> 32), (uint32_t)(wdata & 0xFFFFFFFF), (winhibit ? "[X]" : "")); + WriteLog(" (icount=%04X, inc=%u)\n", icount, (uint16_t)inc); + WriteLog(" [dstart=%X dend=%X pwidth=%X srcshift=%X]", dstart, dend, pwidth, srcshift); + WriteLog("[daas=%X dabs=%X dam=%X ds=%X daq=%s]\n", daddasel, daddbsel, daddmode, data_sel, (daddq_sel ? "T" : "F")); +} +#endif + } + + if (dzwrite) + { +// OK, here's the big insight: When NOT in GOURZ mode, srcz1 & 2 function EXACTLY the same way that +// srcd1 & 2 work--there's an implicit shift from srcz1 to srcz2 whenever srcz1 is read. +// OTHERWISE, srcz1 is the integer for the computed Z and srcz2 is the fractional part. +// Writes to srcz1 & 2 follow the same pattern as the other 64-bit registers--low 32 at the low address, +// high 32 at the high address (little endian!). +// NOTE: GOURZ is still not properly supported. Check patd/patf handling... +// Phrase mode start/end masks are not properly supported either... +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog(" Entering DZWRITE state..."); + WriteLog(" Dest Z write address/pix address: %08X/%1X [%08X%08X]\n", address, + pixAddr, (uint32_t)(srcz >> 32), (uint32_t)(srcz & 0xFFFFFFFF)); +} +#endif +//This is not correct... !!! FIX !!! +//Should be OK now... We'll see... +//Nope. Having the same starstep write problems in phrase mode as we had with pixels... !!! FIX !!! +//This is not causing the problem in Hover Strike... :-/ +//The problem was with the SREADX not shifting. Still problems with Z comparisons & other text in pregame screen... +if (!winhibit) +{ + if (phrase_mode) + { + JaguarWriteLong(address + 0, srcz >> 32, BLITTER); + JaguarWriteLong(address + 4, srcz & 0xFFFFFFFF, BLITTER); + } + else + { + if (pixsize == 4) + JaguarWriteWord(address, srcz & 0x0000FFFF, BLITTER); + } +}//*/ +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +// printf(" [%08X%08X]\n", (uint32_t)(srcz >> 32), (uint32_t)(srcz & 0xFFFFFFFF)); +// fflush(stdout); +//printf(" [dstart=%X dend=%X pwidth=%X srcshift=%X]", dstart, dend, pwidth, srcshift); + WriteLog(" [dstart=? dend=? pwidth=? srcshift=%X]", srcshift); + WriteLog("[daas=%X dabs=%X dam=%X ds=%X daq=%s]\n", daddasel, daddbsel, daddmode, data_sel, (daddq_sel ? "T" : "F")); +// fflush(stdout); +} +#endif + } + +/* +This is because the address generator was using only 15 bits of the X when it should have +used 16! + +There's a slight problem here: The X pointer isn't wrapping like it should when it hits +the edge of the window... Notice how the X isn't reset at the edge of the window: + +Blit! (CMD = 00010000) +Flags: PATDSEL + count = 160 x 261 + a1_base = 000E8008, a2_base = 0001FA68 + a1_x = 0000, a1_y = 0000, a1_frac_x = 0000, a1_frac_y = 0000, a2_x = 0000, a2_y = 0000 + a1_step_x = 0000, a1_step_y = 0000, a1_stepf_x = 0000, a1_stepf_y = 0000, a2_step_x = 0000, a2_step_y = 0000 + a1_inc_x = 0000, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0000, a1_win_y = 0000, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+phr/+0 + a1_pixsize = 5, a2_pixsize = 5 + srcd=7717771777177717 dstd=0000000000000000 patd=7730773077307730 iinc=00000000 + srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, coll=0 + Phrase mode is ON + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... + Entering DWRITE state... Dest write address/pix address: 000E8008/0 [7730773077307730] (icount=009E, inc=2) + srcz=0000000000000000][dcomp=AA zcomp=00 dbinh=00] +[srcz=0000000000000000 dstz=0000000000000000 zwdata=0000000000000000 mask=7FFF] + [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] + Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + Entering DWRITE state... Dest write address/pix address: 000E8018/0 [7730773077307730] (icount=009C, inc=2) + srcz=0000000000000000][dcomp=AA zcomp=00 dbinh=00] +[srcz=0000000000000000 dstz=0000000000000000 zwdata=0000000000000000 mask=7FFF] + [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] + Entering A1_ADD state [a1_x=0002, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + +... + + Entering A1_ADD state [a1_x=009C, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + Entering DWRITE state... Dest write address/pix address: 000E84F8/0 [7730773077307730] (icount=0000, inc=2) + srcz=0000000000000000][dcomp=AA zcomp=00 dbinh=00] +[srcz=0000000000000000 dstz=0000000000000000 zwdata=0000000000000000 mask=7FFF] + [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] + Entering A1_ADD state [a1_x=009E, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + Entering IDLE_INNER state... + + Leaving INNER state... (ocount=0104) + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + + Entering INNER state... + Entering DWRITE state... Dest write address/pix address: 000E8508/0 [7730773077307730] (icount=009E, inc=2) + srcz=0000000000000000][dcomp=AA zcomp=00 dbinh=00] +[srcz=0000000000000000 dstz=0000000000000000 zwdata=0000000000000000 mask=7FFF] + [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] + Entering A1_ADD state [a1_x=00A0, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + Entering DWRITE state... Dest write address/pix address: 000E8518/0 [7730773077307730] (icount=009C, inc=2) + srcz=0000000000000000][dcomp=AA zcomp=00 dbinh=00] +[srcz=0000000000000000 dstz=0000000000000000 zwdata=0000000000000000 mask=7FFF] + [dstart=0 dend=40 pwidth=8 srcshift=0][daas=0 dabs=0 dam=7 ds=0 daq=F] + Entering A1_ADD state [a1_x=00A2, a1_y=0000, addasel=0, addbsel=0, modx=1, addareg=F, adda_xconst=1, adda_yconst=0]... + +*/ + + if (a1_add) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +//printf(" Entering A1_ADD state [addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0")); +WriteLog(" Entering A1_ADD state [a1_x=%04X, a1_y=%04X, addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", a1_x, a1_y, addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0")); +//fflush(stdout); +} +#endif +int16_t adda_x, adda_y, addb_x, addb_y, data_x, data_y, addq_x, addq_y; +ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y, + a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y); +ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y); +ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y); + +#if 0//def VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" [adda_x=%d, adda_y=%d, addb_x=%d, addb_y=%d, addq_x=%d, addq_y=%d]\n", adda_x, adda_y, addb_x, addb_y, addq_x, addq_y); +//fflush(stdout); +} +#endif +//Now, write to what??? +//a2ptrld comes from a2ptrldi... +//I believe it's addbsel that determines the writeback... +// This is where atick[0] & [1] come in, in determining which part (fractional, integer) +// gets written to... +//a1_x = addq_x; +//a1_y = addq_y; +//Kludge, to get A1 channel increment working... +if (a1addx == 3) +{ + a1_frac_x = addq_x, a1_frac_y = addq_y; + +addasel = 2, addbsel = 0, a1fracldi = false; +ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y, + a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y); +ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y); +ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y); + + a1_x = addq_x, a1_y = addq_y; +} +else + a1_x = addq_x, a1_y = addq_y; + } + + if (a2_add) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +//printf(" Entering A2_ADD state [addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0")); +WriteLog(" Entering A2_ADD state [a2_x=%04X, a2_y=%04X, addasel=%X, addbsel=%X, modx=%X, addareg=%s, adda_xconst=%u, adda_yconst=%s]...\n", a2_x, a2_y, addasel, addbsel, modx, (addareg ? "T" : "F"), adda_xconst, (adda_yconst ? "1" : "0")); +//fflush(stdout); +} +#endif +//void ADDAMUX(int16_t &adda_x, int16_t &adda_y, uint8_t addasel, int16_t a1_step_x, int16_t a1_step_y, +// int16_t a1_stepf_x, int16_t a1_stepf_y, int16_t a2_step_x, int16_t a2_step_y, +// int16_t a1_inc_x, int16_t a1_inc_y, int16_t a1_incf_x, int16_t a1_incf_y, uint8_t adda_xconst, +// bool adda_yconst, bool addareg, bool suba_x, bool suba_y) +//void ADDBMUX(int16_t &addb_x, int16_t &addb_y, uint8_t addbsel, int16_t a1_x, int16_t a1_y, +// int16_t a2_x, int16_t a2_y, int16_t a1_frac_x, int16_t a1_frac_y) +//void ADDRADD(int16_t &addq_x, int16_t &addq_y, bool a1fracldi, +// int16_t adda_x, int16_t adda_y, int16_t addb_x, int16_t addb_y, uint8_t modx, bool suba_x, bool suba_y) +//void DATAMUX(int16_t &data_x, int16_t &data_y, uint32_t gpu_din, int16_t addq_x, int16_t addq_y, bool addqsel) +int16_t adda_x, adda_y, addb_x, addb_y, data_x, data_y, addq_x, addq_y; +ADDAMUX(adda_x, adda_y, addasel, a1_step_x, a1_step_y, a1_stepf_x, a1_stepf_y, a2_step_x, a2_step_y, + a1_inc_x, a1_inc_y, a1_incf_x, a1_incf_y, adda_xconst, adda_yconst, addareg, suba_x, suba_y); +ADDBMUX(addb_x, addb_y, addbsel, a1_x, a1_y, a2_x, a2_y, a1_frac_x, a1_frac_y); +ADDRADD(addq_x, addq_y, a1fracldi, adda_x, adda_y, addb_x, addb_y, modx, suba_x, suba_y); + +#if 0//def VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" [adda_x=%d, adda_y=%d, addb_x=%d, addb_y=%d, addq_x=%d, addq_y=%d]\n", adda_x, adda_y, addb_x, addb_y, addq_x, addq_y); +//fflush(stdout); +} +#endif +//Now, write to what??? +//a2ptrld comes from a2ptrldi... +//I believe it's addbsel that determines the writeback... +a2_x = addq_x; +a2_y = addq_y; + } + } +/* +Flags: SRCEN CLIP_A1 UPDA1 UPDA1F UPDA2 DSTA2 GOURZ ZMODE=0 LFUFUNC=C SRCSHADE + count = 64 x 55 + a1_base = 0015B000, a2_base = 0014B000 + a1_x = 0000, a1_y = 0000, a1_frac_x = 8000, a1_frac_y = 8000, a2_x = 001F, a2_y = 0038 + a1_step_x = FFFFFFC0, a1_step_y = 0001, a1_stepf_x = 0000, a1_stepf_y = 2AAA, a2_step_x = FFFFFFC0, a2_step_y = 0001 + a1_inc_x = 0001, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0040, a1_win_y = 0040, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+inc/+0 a2add=+1/+0 + a1_pixsize = 4, a2_pixsize = 4 + srcd=FF00FF00FF00FF00 dstd=0000000000000000 patd=0000000000000000 iinc=00000000 + srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, col=0 + Phrase mode is off + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... + Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505] + Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0014E83E/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003F, inc=1) + Entering A2_ADD state [a2_x=001F, a2_y=0038, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505] + Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0014E942/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003E, inc=1) + Entering A2_ADD state [a2_x=0021, a2_y=0039, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505] + Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0014EA46/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003D, inc=1) + Entering A2_ADD state [a2_x=0023, a2_y=003A, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]... + Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505] + Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0014EB4A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=003C, inc=1) + Entering A2_ADD state [a2_x=0025, a2_y=003B, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]... + ... + Entering SREAD state... Source read address/pix address: 0015B000/0 [6505650565056505] + Entering A1_ADD state [a1_x=FFFF8000, a1_y=FFFF8000, addasel=3, addbsel=2, modx=0, addareg=T, adda_xconst=7, adda_yconst=0]... + Entering DWRITE state... + Dest write address/pix address: 0015283A/0 [dstart=0 dend=10 pwidth=8 srcshift=0][daas=4 dabs=5 dam=7 ds=1 daq=F] [0000000000006505] (icount=0000, inc=1) + Entering A2_ADD state [a2_x=009D, a2_y=0077, addasel=0, addbsel=1, modx=0, addareg=F, adda_xconst=0, adda_yconst=0]... + Entering IDLE_INNER state... + Leaving INNER state... (ocount=0036) + [in=F a1f=T a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering A1FUPDATE state... + [in=F a1f=F a1=T zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering A1UPDATE state... (-32768/-32768 -> 32704/-32767) + [in=F a1f=F a1=F zf=F z=F a2=T iif=F iii=F izf=F izi=F] + Entering A2UPDATE state... (159/120 -> 95/121) + [in=T a1f=F a1=F zf=F z=F a2=F iif=F iii=F izf=F izi=F] + Entering INNER state... +*/ + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Leaving INNER state..."); +//fflush(stdout); +} +#endif + indone = true; +// The outer counter is updated here as well on the clock cycle... + +/* the inner loop is started whenever another state is about to +cause the inner state to go active */ +//Instart := ND7 (instart, innert[0], innert[2..7]); + +//Actually, it's done only when inner gets asserted without the 2nd line of conditions +//(inner AND !indone) +//fixed now... +//Since we don't get here until the inner loop is finished (indone = true) we can get +//away with doing it here...! + ocount--; + + if (ocount == 0) + outer0 = true; +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" (ocount=%04X)\n", ocount); +//fflush(stdout); +} +#endif + } + + if (a1fupdate) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Entering A1FUPDATE state...\n"); +//fflush(stdout); +} +#endif + uint32_t a1_frac_xt = (uint32_t)a1_frac_x + (uint32_t)a1_stepf_x; + uint32_t a1_frac_yt = (uint32_t)a1_frac_y + (uint32_t)a1_stepf_y; + a1FracCInX = a1_frac_xt >> 16; + a1FracCInY = a1_frac_yt >> 16; + a1_frac_x = (uint16_t)(a1_frac_xt & 0xFFFF); + a1_frac_y = (uint16_t)(a1_frac_yt & 0xFFFF); + } + + if (a1update) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Entering A1UPDATE state... (%d/%d -> ", a1_x, a1_y); +//fflush(stdout); +} +#endif + a1_x += a1_step_x + a1FracCInX; + a1_y += a1_step_y + a1FracCInY; +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog("%d/%d)\n", a1_x, a1_y); +//fflush(stdout); +} +#endif + } + + if (a2update) + { +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" Entering A2UPDATE state... (%d/%d -> ", a2_x, a2_y); +//fflush(stdout); +} +#endif + a2_x += a2_step_x; + a2_y += a2_step_y; +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog("%d/%d)\n", a2_x, a2_y); +//fflush(stdout); +} +#endif + } + } + +// We never get here! !!! FIX !!! + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog("Done!\na1_x=%04X a1_y=%04X a1_frac_x=%04X a1_frac_y=%04X a2_x=%04X a2_y%04X\n", + GET16(blitter_ram, A1_PIXEL + 2), + GET16(blitter_ram, A1_PIXEL + 0), + GET16(blitter_ram, A1_FPIXEL + 2), + GET16(blitter_ram, A1_FPIXEL + 0), + GET16(blitter_ram, A2_PIXEL + 2), + GET16(blitter_ram, A2_PIXEL + 0)); +// fflush(stdout); +} +#endif + + // Write values back to registers (in real blitter, these are continuously updated) + SET16(blitter_ram, A1_PIXEL + 2, a1_x); + SET16(blitter_ram, A1_PIXEL + 0, a1_y); + SET16(blitter_ram, A1_FPIXEL + 2, a1_frac_x); + SET16(blitter_ram, A1_FPIXEL + 0, a1_frac_y); + SET16(blitter_ram, A2_PIXEL + 2, a2_x); + SET16(blitter_ram, A2_PIXEL + 0, a2_y); + +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) +{ + WriteLog("Writeback!\na1_x=%04X a1_y=%04X a1_frac_x=%04X a1_frac_y=%04X a2_x=%04X a2_y%04X\n", + GET16(blitter_ram, A1_PIXEL + 2), + GET16(blitter_ram, A1_PIXEL + 0), + GET16(blitter_ram, A1_FPIXEL + 2), + GET16(blitter_ram, A1_FPIXEL + 0), + GET16(blitter_ram, A2_PIXEL + 2), + GET16(blitter_ram, A2_PIXEL + 0)); +// fflush(stdout); +} +#endif +} + + +/* + int16_t a1_x = (int16_t)GET16(blitter_ram, A1_PIXEL + 2); + int16_t a1_y = (int16_t)GET16(blitter_ram, A1_PIXEL + 0); + uint16_t a1_frac_x = GET16(blitter_ram, A1_FPIXEL + 2); + uint16_t a1_frac_y = GET16(blitter_ram, A1_FPIXEL + 0); + int16_t a2_x = (int16_t)GET16(blitter_ram, A2_PIXEL + 2); + int16_t a2_y = (int16_t)GET16(blitter_ram, A2_PIXEL + 0); + +Seems that the ending a1_x should be written between blits, but it doesn't seem to be... + +Blit! (CMD = 01800000) +Flags: LFUFUNC=C + count = 28672 x 1 + a1_base = 00050000, a2_base = 00070000 + a1_x = 0000, a1_y = 0000, a1_frac_x = 49CD, a1_frac_y = 0000, a2_x = 0033, a2_y = 0001 + a1_step_x = 0000, a1_step_y = 0000, a1_stepf_x = 939A, a1_stepf_y = 0000, a2_step_x = 0000, a2_step_y = 0000 + a1_inc_x = 0000, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0100, a1_win_y = 0020, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+phr/+0 + a1_pixsize = 4, a2_pixsize = 3 + srcd=DEDEDEDEDEDEDEDE dstd=0000000000000000 patd=0000000000000000 iinc=00000000 + srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, coll=0 + Phrase mode is ON + +Blit! (CMD = 01800000) +Flags: LFUFUNC=C + count = 28672 x 1 + a1_base = 00050000, a2_base = 00070000 + a1_x = 0000, a1_y = 0000, a1_frac_x = 49CD, a1_frac_y = 0000, a2_x = 0033, a2_y = 0001 + a1_step_x = 0000, a1_step_y = 0000, a1_stepf_x = 939A, a1_stepf_y = 0000, a2_step_x = 0000, a2_step_y = 0000 + a1_inc_x = 0000, a1_inc_y = 0000, a1_incf_x = 0000, a1_incf_y = 0000 + a1_win_x = 0100, a1_win_y = 0020, a2_mask_x = 0000, a2_mask_y = 0000 + a2_mask=F a1add=+phr/+0 a2add=+phr/+0 + a1_pixsize = 4, a2_pixsize = 3 + srcd=D6D6D6D6D6D6D6D6 dstd=0000000000000000 patd=0000000000000000 iinc=00000000 + srcz1=0000000000000000 srcz2=0000000000000000 dstz=0000000000000000 zinc=00000000, coll=0 + Phrase mode is ON +*/ + + + +// Various pieces of the blitter puzzle are teased out here... + + + +/* +DEF ADDRGEN ( +INT24/ address // byte address + pixa[0..2] // bit part of address, un-pipe-lined + :OUT; +INT16/ a1_x +INT16/ a1_y +INT21/ a1_base + a1_pitch[0..1] + a1_pixsize[0..2] + a1_width[0..5] + a1_zoffset[0..1] +INT16/ a2_x +INT16/ a2_y +INT21/ a2_base + a2_pitch[0..1] + a2_pixsize[0..2] + a2_width[0..5] + a2_zoffset[0..1] + apipe // load address pipe-line latch + clk // co-processor clock + gena2 // generate A2 as opposed to A1 + zaddr // generate Z address + :IN); +*/ + +void ADDRGEN(uint32_t &address, uint32_t &pixa, bool gena2, bool zaddr, + uint16_t a1_x, uint16_t a1_y, uint32_t a1_base, uint8_t a1_pitch, uint8_t a1_pixsize, uint8_t a1_width, uint8_t a1_zoffset, + uint16_t a2_x, uint16_t a2_y, uint32_t a2_base, uint8_t a2_pitch, uint8_t a2_pixsize, uint8_t a2_width, uint8_t a2_zoffset) +{ +// uint16_t x = (gena2 ? a2_x : a1_x) & 0x7FFF; + uint16_t x = (gena2 ? a2_x : a1_x) & 0xFFFF; // Actually uses all 16 bits to generate address...! + uint16_t y = (gena2 ? a2_y : a1_y) & 0x0FFF; + uint8_t width = (gena2 ? a2_width : a1_width); + uint8_t pixsize = (gena2 ? a2_pixsize : a1_pixsize); + uint8_t pitch = (gena2 ? a2_pitch : a1_pitch); + uint32_t base = (gena2 ? a2_base : a1_base) >> 3;//Only upper 21 bits are passed around the bus? Seems like it... + uint8_t zoffset = (gena2 ? a2_zoffset : a1_zoffset); + + uint32_t ytm = ((uint32_t)y << 2) + (width & 0x02 ? (uint32_t)y << 1 : 0) + (width & 0x01 ? (uint32_t)y : 0); + + uint32_t ya = (ytm << (width >> 2)) >> 2; + + uint32_t pa = ya + x; + + /*uint32*/ pixa = pa << pixsize; + + uint8_t pt = ((pitch & 0x01) && !(pitch & 0x02) ? 0x01 : 0x00) + | (!(pitch & 0x01) && (pitch & 0x02) ? 0x02 : 0x00); +// uint32_t phradr = pixa << pt; + uint32_t phradr = (pixa >> 6) << pt; + uint32_t shup = (pitch == 0x03 ? (pixa >> 6) : 0); + + uint8_t za = (zaddr ? zoffset : 0) & 0x03; +// uint32_t addr = za + (phradr & 0x07) + (shup << 1) + base; + uint32_t addr = za + phradr + (shup << 1) + base; + /*uint32*/ address = ((pixa & 0x38) >> 3) | ((addr & 0x1FFFFF) << 3); +#if 0//def VERBOSE_BLITTER_LOGGING +if (logBlit) +{ +WriteLog(" [gena2=%s, x=%04X, y=%04X, w=%1X, pxsz=%1X, ptch=%1X, b=%08X, zoff=%1X]\n", (gena2 ? "T" : "F"), x, y, width, pixsize, pitch, base, zoffset); +WriteLog(" [ytm=%X, ya=%X, pa=%X, pixa=%X, pt=%X, phradr=%X, shup=%X, za=%X, addr=%X, address=%X]\n", ytm, ya, pa, pixa, pt, phradr, shup, za, addr, address); +//fflush(stdout); +} +#endif + pixa &= 0x07; +/* + Entering INNER state... + [gena2=T, x=0002, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0] + [ytm=0, ya=0, pa=2, pixa=20, pt=0, phradr=0, shup=0, za=0, addr=12BA, address=95D4] + Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20] + Source extra read address/pix address: 000095D4/0 [0000001C00540038] + Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0] + [ytm=0, ya=0, pa=4, pixa=40, pt=0, phradr=1, shup=0, za=0, addr=12BB, address=95D8] + Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0] + Source read address/pix address: 000095D8/0 [0054003800009814] + Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + [gena2=F, x=0000, y=0000, w=20, pxsz=4, ptch=0, b=00006E52, zoff=0] + [ytm=0, ya=0, pa=0, pixa=0, pt=0, phradr=0, shup=0, za=0, addr=6E52, address=37290] + Entering DWRITE state... + Dest write address/pix address: 00037290/0 [dstart=0 dend=20 pwidth=8 srcshift=0] (icount=026E, inc=4) + Entering A1_ADD state [a1_x=0000, a1_y=0000, addasel=0, addbsel=0, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + [gena2=T, x=0008, y=0000, w=20, pxsz=4, ptch=0, b=000012BA, zoff=0] + [ytm=0, ya=0, pa=8, pixa=80, pt=0, phradr=2, shup=0, za=0, addr=12BC, address=95E0] +*/ +/* +Obviously wrong: + Entering SREAD state... + [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0] + [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=40, shup=0, za=0, addr=10AC, address=8560] + Source read address/pix address: 00008560/0 [8C27981B327E00F0] + +2nd pass (still wrong): + Entering SREAD state... + [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0] + [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=40, shup=0, za=0, addr=10EC, address=8760] + Source read address/pix address: 00008760/0 [00E06DC04581880C] + +Correct!: + Entering SREAD state... + [gena2=T, x=0004, y=0000, w=20, pxsz=4, ptch=0, b=000010AC, zoff=0] + [ytm=0, ya=0, pa=4, pixa=0, pt=0, phradr=1, shup=0, za=0, addr=10AD, address=8568] + Source read address/pix address: 00008568/0 [6267981A327C00F0] + +OK, now we're back into incorrect (or is it?): + Entering SREADX state... [dstart=0 dend=20 pwidth=8 srcshift=20] + Source extra read address/pix address: 000095D4/0 [0000 001C 0054 0038] + Entering A2_ADD state [a2_x=0002, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... + Entering SREAD state... [dstart=0 dend=20 pwidth=8 srcshift=0] + Source read address/pix address: 000095D8/0 [0054 0038 0000 9814] + Entering A2_ADD state [a2_x=0004, a2_y=0000, addasel=0, addbsel=1, modx=2, addareg=F, adda_xconst=2, adda_yconst=0]... +I think this may be correct...! +*/ +} + +/* +// source and destination address update conditions + +Sraat0 := AN2 (sraat[0], sreadxi, srcenz\); +Sraat1 := AN2 (sraat[1], sreadi, srcenz\); +Srca_addi := OR4 (srca_addi, szreadxi, szreadi, sraat[0..1]); +Srca_add := FD1Q (srca_add, srca_addi, clk); + +Dstaat := AN2 (dstaat, dwritei, dstwrz\); +Dsta_addi := OR2 (dsta_addi, dzwritei, dstaat); +// Dsta_add := FD1Q (dsta_add, dsta_addi, clk); + +// source and destination address generate conditions + +Gensrc := OR4 (gensrc, sreadxi, szreadxi, sreadi, szreadi); +Gendst := OR4 (gendst, dreadi, dzreadi, dwritei, dzwritei); +Dsta2\ := INV1 (dsta2\, dsta2); +Gena2t0 := NAN2 (gena2t[0], gensrc, dsta2\); +Gena2t1 := NAN2 (gena2t[1], gendst, dsta2); +Gena2i := NAN2 (gena2i, gena2t[0..1]); +Gena2 := FD1QU (gena2, gena2i, clk); + +Zaddr := OR4 (zaddr, szreadx, szread, dzread, dzwrite); +*/ + +/*void foo(void) +{ + // Basically, the above translates to: + bool srca_addi = (sreadxi && !srcenz) || (sreadi && !srcenz) || szreadxi || szreadi; + + bool dsta_addi = (dwritei && !dstwrz) || dzwritei; + + bool gensrc = sreadxi || szreadxi || sreadi || szreadi; + bool gendst = dreadi || szreadi || dwritei || dzwritei; + bool gena2i = (gensrc && !dsta2) || (gendst && dsta2); + + bool zaddr = szreadx || szread || dzread || dzwrite; +}*/ + +/* +// source data reads + +Srcdpset\ := NAN2 (srcdpset\, readreq, sread); +Srcdpt1 := NAN2 (srcdpt[1], srcdpend, srcdack\); +Srcdpt2 := NAN2 (srcdpt[2], srcdpset\, srcdpt[1]); +Srcdpend := FD2Q (srcdpend, srcdpt[2], clk, reset\); + +Srcdxpset\ := NAN2 (srcdxpset\, readreq, sreadx); +Srcdxpt1 := NAN2 (srcdxpt[1], srcdxpend, srcdxack\); +Srcdxpt2 := NAN2 (srcdxpt[2], srcdxpset\, srcdxpt[1]); +Srcdxpend := FD2Q (srcdxpend, srcdxpt[2], clk, reset\); + +Sdpend := OR2 (sdpend, srcdxpend, srcdpend); +Srcdreadt := AN2 (srcdreadt, sdpend, read_ack); + +//2/9/92 - enhancement? +//Load srcdread on the next tick as well to modify it in srcshade + +Srcdreadd := FD1Q (srcdreadd, srcdreadt, clk); +Srcdread := AOR1 (srcdread, srcshade, srcdreadd, srcdreadt); + +// source zed reads + +Srczpset\ := NAN2 (srczpset\, readreq, szread); +Srczpt1 := NAN2 (srczpt[1], srczpend, srczack\); +Srczpt2 := NAN2 (srczpt[2], srczpset\, srczpt[1]); +Srczpend := FD2Q (srczpend, srczpt[2], clk, reset\); + +Srczxpset\ := NAN2 (srczxpset\, readreq, szreadx); +Srczxpt1 := NAN2 (srczxpt[1], srczxpend, srczxack\); +Srczxpt2 := NAN2 (srczxpt[2], srczxpset\, srczxpt[1]); +Srczxpend := FD2Q (srczxpend, srczxpt[2], clk, reset\); + +Szpend := OR2 (szpend, srczpend, srczxpend); +Srczread := AN2 (srczread, szpend, read_ack); + +// destination data reads + +Dstdpset\ := NAN2 (dstdpset\, readreq, dread); +Dstdpt0 := NAN2 (dstdpt[0], dstdpend, dstdack\); +Dstdpt1 := NAN2 (dstdpt[1], dstdpset\, dstdpt[0]); +Dstdpend := FD2Q (dstdpend, dstdpt[1], clk, reset\); +Dstdread := AN2 (dstdread, dstdpend, read_ack); + +// destination zed reads + +Dstzpset\ := NAN2 (dstzpset\, readreq, dzread); +Dstzpt0 := NAN2 (dstzpt[0], dstzpend, dstzack\); +Dstzpt1 := NAN2 (dstzpt[1], dstzpset\, dstzpt[0]); +Dstzpend := FD2Q (dstzpend, dstzpt[1], clk, reset\); +Dstzread := AN2 (dstzread, dstzpend, read_ack); +*/ + +/*void foo2(void) +{ + // Basically, the above translates to: + bool srcdpend = (readreq && sread) || (srcdpend && !srcdack); + bool srcdxpend = (readreq && sreadx) || (srcdxpend && !srcdxack); + bool sdpend = srcxpend || srcdpend; + bool srcdread = ((sdpend && read_ack) && srcshade) || (sdpend && read_ack);//the latter term is lookahead + +}*/ + + +//////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////// +// Here's an important bit: The source data adder logic. Need to track down the inputs!!! // +//////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////// + +/* +DEF ADDARRAY ( +INT16/ addq[0..3] + :OUT; + clk + daddasel[0..2] // data adder input A selection + daddbsel[0..3] + daddmode[0..2] +INT32/ dstd[0..1] +INT32/ iinc + initcin[0..3] // carry into the adders from the initializers + initinc[0..63] // the initialisation increment + initpix[0..15] // Data initialiser pixel value +INT32/ istep +INT32/ patd[0..1] +INT32/ srcdlo +INT32/ srcdhi +INT32/ srcz1[0..1] +INT32/ srcz2[0..1] + reset\ +INT32/ zinc +INT32/ zstep + :IN); +*/ +void ADDARRAY(uint16_t * addq, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, + uint64_t dstd, uint32_t iinc, uint8_t initcin[], uint64_t initinc, uint16_t initpix, + uint32_t istep, uint64_t patd, uint64_t srcd, uint64_t srcz1, uint64_t srcz2, + uint32_t zinc, uint32_t zstep) +{ + uint32_t initpix2 = ((uint32_t)initpix << 16) | initpix; + uint32_t addalo[8], addahi[8]; + addalo[0] = dstd & 0xFFFFFFFF; + addalo[1] = initpix2; + addalo[2] = 0; + addalo[3] = 0; + addalo[4] = srcd & 0xFFFFFFFF; + addalo[5] = patd & 0xFFFFFFFF; + addalo[6] = srcz1 & 0xFFFFFFFF; + addalo[7] = srcz2 & 0xFFFFFFFF; + addahi[0] = dstd >> 32; + addahi[1] = initpix2; + addahi[2] = 0; + addahi[3] = 0; + addahi[4] = srcd >> 32; + addahi[5] = patd >> 32; + addahi[6] = srcz1 >> 32; + addahi[7] = srcz2 >> 32; + uint16_t adda[4]; + adda[0] = addalo[daddasel] & 0xFFFF; + adda[1] = addalo[daddasel] >> 16; + adda[2] = addahi[daddasel] & 0xFFFF; + adda[3] = addahi[daddasel] >> 16; + + uint16_t wordmux[8]; + wordmux[0] = iinc & 0xFFFF; + wordmux[1] = iinc >> 16; + wordmux[2] = zinc & 0xFFFF; + wordmux[3] = zinc >> 16;; + wordmux[4] = istep & 0xFFFF; + wordmux[5] = istep >> 16;; + wordmux[6] = zstep & 0xFFFF; + wordmux[7] = zstep >> 16;; + uint16_t word = wordmux[((daddbsel & 0x08) >> 1) | (daddbsel & 0x03)]; + uint16_t addb[4]; + bool dbsel2 = daddbsel & 0x04; + bool iincsel = (daddbsel & 0x01) && !(daddbsel & 0x04); + + if (!dbsel2 && !iincsel) + addb[0] = srcd & 0xFFFF, + addb[1] = (srcd >> 16) & 0xFFFF, + addb[2] = (srcd >> 32) & 0xFFFF, + addb[3] = (srcd >> 48) & 0xFFFF; + else if (dbsel2 && !iincsel) + addb[0] = addb[1] = addb[2] = addb[3] = word; + else if (!dbsel2 && iincsel) + addb[0] = initinc & 0xFFFF, + addb[1] = (initinc >> 16) & 0xFFFF, + addb[2] = (initinc >> 32) & 0xFFFF, + addb[3] = (initinc >> 48) & 0xFFFF; + else + addb[0] = addb[1] = addb[2] = addb[3] = 0; + + uint8_t cinsel = (daddmode >= 1 && daddmode <= 4 ? 1 : 0); + +static uint8_t co[4];//These are preserved between calls... + uint8_t cin[4]; + + for(int i=0; i<4; i++) + cin[i] = initcin[i] | (co[i] & cinsel); + + bool eightbit = daddmode & 0x02; + bool sat = daddmode & 0x03; + bool hicinh = ((daddmode & 0x03) == 0x03); + +//Note that the carry out is saved between calls to this function... + for(int i=0; i<4; i++) + ADD16SAT(addq[i], co[i], adda[i], addb[i], cin[i], sat, eightbit, hicinh); +} + + +/* +DEF ADD16SAT ( +INT16/ r // result + co // carry out + :IO; +INT16/ a +INT16/ b + cin + sat + eightbit + hicinh + :IN); +*/ +void ADD16SAT(uint16_t &r, uint8_t &co, uint16_t a, uint16_t b, uint8_t cin, bool sat, bool eightbit, bool hicinh) +{ +/*if (logBlit) +{ + printf("--> [sat=%s 8b=%s hicinh=%s] %04X + %04X (+ %u) = ", (sat ? "T" : "F"), (eightbit ? "T" : "F"), (hicinh ? "T" : "F"), a, b, cin); + fflush(stdout); +}*/ + uint8_t carry[4]; + uint32_t qt = (a & 0xFF) + (b & 0xFF) + cin; + carry[0] = (qt & 0x0100 ? 1 : 0); + uint16_t q = qt & 0x00FF; + carry[1] = (carry[0] && !eightbit ? carry[0] : 0); + qt = (a & 0x0F00) + (b & 0x0F00) + (carry[1] << 8); + carry[2] = (qt & 0x1000 ? 1 : 0); + q |= qt & 0x0F00; + carry[3] = (carry[2] && !hicinh ? carry[2] : 0); + qt = (a & 0xF000) + (b & 0xF000) + (carry[3] << 12); + co = (qt & 0x10000 ? 1 : 0); + q |= qt & 0xF000; + + uint8_t btop = (eightbit ? (b & 0x0080) >> 7 : (b & 0x8000) >> 15); + uint8_t ctop = (eightbit ? carry[0] : co); + + bool saturate = sat && (btop ^ ctop); + bool hisaturate = saturate && !eightbit; +/*if (logBlit) +{ + printf("bt=%u ct=%u s=%u hs=%u] ", btop, ctop, saturate, hisaturate); + fflush(stdout); +}*/ + + r = (saturate ? (ctop ? 0x00FF : 0x0000) : q & 0x00FF); + r |= (hisaturate ? (ctop ? 0xFF00 : 0x0000) : q & 0xFF00); +/*if (logBlit) +{ + printf("%04X (co=%u)\n", r, co); + fflush(stdout); +}*/ +} + + +/** ADDAMUX - Address adder input A selection ******************* + +This module generates the data loaded into the address adder input A. This is +the update value, and can be one of four registers : A1 step, A2 step, A1 +increment and A1 fraction. It can complement these values to perform +subtraction, and it can generate constants to increment / decrement the window +pointers. + +addasel[0..2] select the register to add + +000 A1 step integer part +001 A1 step fraction part +010 A1 increment integer part +011 A1 increment fraction part +100 A2 step + +adda_xconst[0..2] generate a power of 2 in the range 1-64 or all zeroes when +they are all 1. + +addareg selects register value to be added as opposed to constant +value. + +suba_x, suba_y complement the X and Y values + +*/ + +/* +DEF ADDAMUX ( +INT16/ adda_x +INT16/ adda_y + :OUT; + addasel[0..2] +INT16/ a1_step_x +INT16/ a1_step_y +INT16/ a1_stepf_x +INT16/ a1_stepf_y +INT16/ a2_step_x +INT16/ a2_step_y +INT16/ a1_inc_x +INT16/ a1_inc_y +INT16/ a1_incf_x +INT16/ a1_incf_y + adda_xconst[0..2] + adda_yconst + addareg + suba_x + suba_y :IN); +*/ +void ADDAMUX(int16_t &adda_x, int16_t &adda_y, uint8_t addasel, int16_t a1_step_x, int16_t a1_step_y, + int16_t a1_stepf_x, int16_t a1_stepf_y, int16_t a2_step_x, int16_t a2_step_y, + int16_t a1_inc_x, int16_t a1_inc_y, int16_t a1_incf_x, int16_t a1_incf_y, uint8_t adda_xconst, + bool adda_yconst, bool addareg, bool suba_x, bool suba_y) +{ + +/*INT16/ addac_x, addac_y, addar_x, addar_y, addart_x, addart_y, +INT16/ addas_x, addas_y, suba_x16, suba_y16 +:LOCAL; +BEGIN + +Zero := TIE0 (zero);*/ + +/* Multiplex the register terms */ + +/*Addaselb[0-2] := BUF8 (addaselb[0-2], addasel[0-2]); +Addart_x := MX4 (addart_x, a1_step_x, a1_stepf_x, a1_inc_x, a1_incf_x, addaselb[0..1]); +Addar_x := MX2 (addar_x, addart_x, a2_step_x, addaselb[2]); +Addart_y := MX4 (addart_y, a1_step_y, a1_stepf_y, a1_inc_y, a1_incf_y, addaselb[0..1]); +Addar_y := MX2 (addar_y, addart_y, a2_step_y, addaselb[2]);*/ + +////////////////////////////////////// C++ CODE ////////////////////////////////////// + int16_t xterm[4], yterm[4]; + xterm[0] = a1_step_x, xterm[1] = a1_stepf_x, xterm[2] = a1_inc_x, xterm[3] = a1_incf_x; + yterm[0] = a1_step_y, yterm[1] = a1_stepf_y, yterm[2] = a1_inc_y, yterm[3] = a1_incf_y; + int16_t addar_x = (addasel & 0x04 ? a2_step_x : xterm[addasel & 0x03]); + int16_t addar_y = (addasel & 0x04 ? a2_step_y : yterm[addasel & 0x03]); +////////////////////////////////////////////////////////////////////////////////////// + +/* Generate a constant value - this is a power of 2 in the range +0-64, or zero. The control bits are adda_xconst[0..2], when they +are all 1 the result is 0. +Constants for Y can only be 0 or 1 */ + +/*Addac_xlo := D38H (addac_x[0..6], unused[0], adda_xconst[0..2]); +Unused[0] := DUMMY (unused[0]); + +Addac_x := JOIN (addac_x, addac_x[0..6], zero, zero, zero, zero, zero, zero, zero, zero, zero); +Addac_y := JOIN (addac_y, adda_yconst, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, + zero, zero, zero, zero, zero);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + int16_t addac_x = (adda_xconst == 0x07 ? 0 : 1 << adda_xconst); + int16_t addac_y = (adda_yconst ? 0x01 : 0); +////////////////////////////////////////////////////////////////////////////////////// + +/* Select between constant value and register value */ + +/*Addas_x := MX2 (addas_x, addac_x, addar_x, addareg); +Addas_y := MX2 (addas_y, addac_y, addar_y, addareg);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + int16_t addas_x = (addareg ? addar_x : addac_x); + int16_t addas_y = (addareg ? addar_y : addac_y); +////////////////////////////////////////////////////////////////////////////////////// + +/* Complement these values (complement flag gives adder carry in)*/ + +/*Suba_x16 := JOIN (suba_x16, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, + suba_x, suba_x, suba_x, suba_x, suba_x, suba_x, suba_x); +Suba_y16 := JOIN (suba_y16, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, + suba_y, suba_y, suba_y, suba_y, suba_y, suba_y, suba_y); +Adda_x := EO (adda_x, suba_x16, addas_x); +Adda_y := EO (adda_y, suba_y16, addas_y);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + adda_x = addas_x ^ (suba_x ? 0xFFFF : 0x0000); + adda_y = addas_y ^ (suba_y ? 0xFFFF : 0x0000); +////////////////////////////////////////////////////////////////////////////////////// + +//END; +} + + +/** ADDBMUX - Address adder input B selection ******************* + +This module selects the register to be updated by the address +adder. This can be one of three registers, the A1 and A2 +pointers, or the A1 fractional part. It can also be zero, so that the step +registers load directly into the pointers. +*/ + +/*DEF ADDBMUX ( +INT16/ addb_x +INT16/ addb_y + :OUT; + addbsel[0..1] +INT16/ a1_x +INT16/ a1_y +INT16/ a2_x +INT16/ a2_y +INT16/ a1_frac_x +INT16/ a1_frac_y + :IN); +INT16/ zero16 :LOCAL; +BEGIN*/ +void ADDBMUX(int16_t &addb_x, int16_t &addb_y, uint8_t addbsel, int16_t a1_x, int16_t a1_y, + int16_t a2_x, int16_t a2_y, int16_t a1_frac_x, int16_t a1_frac_y) +{ + +/*Zero := TIE0 (zero); +Zero16 := JOIN (zero16, zero, zero, zero, zero, zero, zero, zero, + zero, zero, zero, zero, zero, zero, zero, zero, zero); +Addbselb[0-1] := BUF8 (addbselb[0-1], addbsel[0-1]); +Addb_x := MX4 (addb_x, a1_x, a2_x, a1_frac_x, zero16, addbselb[0..1]); +Addb_y := MX4 (addb_y, a1_y, a2_y, a1_frac_y, zero16, addbselb[0..1]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + int16_t xterm[4], yterm[4]; + xterm[0] = a1_x, xterm[1] = a2_x, xterm[2] = a1_frac_x, xterm[3] = 0; + yterm[0] = a1_y, yterm[1] = a2_y, yterm[2] = a1_frac_y, yterm[3] = 0; + addb_x = xterm[addbsel & 0x03]; + addb_y = yterm[addbsel & 0x03]; +////////////////////////////////////////////////////////////////////////////////////// + +//END; +} + + +/** DATAMUX - Address local data bus selection ****************** + +Select between the adder output and the input data bus +*/ + +/*DEF DATAMUX ( +INT16/ data_x +INT16/ data_y + :OUT; +INT32/ gpu_din +INT16/ addq_x +INT16/ addq_y + addqsel + :IN); + +INT16/ gpu_lo, gpu_hi +:LOCAL; +BEGIN*/ +void DATAMUX(int16_t &data_x, int16_t &data_y, uint32_t gpu_din, int16_t addq_x, int16_t addq_y, bool addqsel) +{ +/*Gpu_lo := JOIN (gpu_lo, gpu_din{0..15}); +Gpu_hi := JOIN (gpu_hi, gpu_din{16..31}); + +Addqselb := BUF8 (addqselb, addqsel); +Data_x := MX2 (data_x, gpu_lo, addq_x, addqselb); +Data_y := MX2 (data_y, gpu_hi, addq_y, addqselb);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + data_x = (addqsel ? addq_x : (int16_t)(gpu_din & 0xFFFF)); + data_y = (addqsel ? addq_y : (int16_t)(gpu_din >> 16)); +////////////////////////////////////////////////////////////////////////////////////// + +//END; +} + + +/****************************************************************** +addradd +29/11/90 + +Blitter Address Adder +--------------------- +The blitter address adder is a pair of sixteen bit adders, one +each for X and Y. The multiplexing of the input terms is +performed elsewhere, but this adder can also perform modulo +arithmetic to align X-addresses onto phrase boundaries. + +modx[0..2] take values +000 no mask +001 mask bit 0 +010 mask bits 1-0 +.. +110 mask bits 5-0 + +******************************************************************/ + +/*IMPORT duplo, tosh; + +DEF ADDRADD ( +INT16/ addq_x +INT16/ addq_y + :OUT; + a1fracldi // propagate address adder carry +INT16/ adda_x +INT16/ adda_y +INT16/ addb_x +INT16/ addb_y + clk[0] // co-processor clock + modx[0..2] + suba_x + suba_y + :IN); + +BEGIN + +Zero := TIE0 (zero);*/ +void ADDRADD(int16_t &addq_x, int16_t &addq_y, bool a1fracldi, + uint16_t adda_x, uint16_t adda_y, uint16_t addb_x, uint16_t addb_y, uint8_t modx, bool suba_x, bool suba_y) +{ + +/* Perform the addition */ + +/*Adder_x := ADD16 (addqt_x[0..15], co_x, adda_x{0..15}, addb_x{0..15}, ci_x); +Adder_y := ADD16 (addq_y[0..15], co_y, adda_y{0..15}, addb_y{0..15}, ci_y);*/ + +/* latch carry and propagate if required */ + +/*Cxt0 := AN2 (cxt[0], co_x, a1fracldi); +Cxt1 := FD1Q (cxt[1], cxt[0], clk[0]); +Ci_x := EO (ci_x, cxt[1], suba_x); + +yt0 := AN2 (cyt[0], co_y, a1fracldi); +Cyt1 := FD1Q (cyt[1], cyt[0], clk[0]); +Ci_y := EO (ci_y, cyt[1], suba_y);*/ + +////////////////////////////////////// C++ CODE ////////////////////////////////////// +//I'm sure the following will generate a bunch of warnings, but will have to do for now. + static uint16_t co_x = 0, co_y = 0; // Carry out has to propogate between function calls... + uint16_t ci_x = co_x ^ (suba_x ? 1 : 0); + uint16_t ci_y = co_y ^ (suba_y ? 1 : 0); + uint32_t addqt_x = adda_x + addb_x + ci_x; + uint32_t addqt_y = adda_y + addb_y + ci_y; + co_x = ((addqt_x & 0x10000) && a1fracldi ? 1 : 0); + co_y = ((addqt_y & 0x10000) && a1fracldi ? 1 : 0); +////////////////////////////////////////////////////////////////////////////////////// + +/* Mask low bits of X to 0 if required */ + +/*Masksel := D38H (unused[0], masksel[0..4], maskbit[5], unused[1], modx[0..2]); + +Maskbit[0-4] := OR2 (maskbit[0-4], masksel[0-4], maskbit[1-5]); + +Mask[0-5] := MX2 (addq_x[0-5], addqt_x[0-5], zero, maskbit[0-5]); + +Addq_x := JOIN (addq_x, addq_x[0..5], addqt_x[6..15]); +Addq_y := JOIN (addq_y, addq_y[0..15]);*/ + +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint16_t mask[8] = { 0xFFFF, 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, 0xFFE0, 0xFFC0, 0x0000 }; + addq_x = addqt_x & mask[modx]; + addq_y = addqt_y & 0xFFFF; +////////////////////////////////////////////////////////////////////////////////////// + +//Unused[0-1] := DUMMY (unused[0-1]); + +//END; +} + + +/* +DEF DATA ( + wdata[0..63] // co-processor write data bus + :BUS; + dcomp[0..7] // data byte equal flags + srcd[0..7] // bits to use for bit to byte expansion + zcomp[0..3] // output from Z comparators + :OUT; + a1_x[0..1] // low two bits of A1 X pointer + big_pix // pixel organisation is big-endian + blitter_active // blitter is active + clk // co-processor clock + cmpdst // compare dest rather than source + colorld // load the pattern color fields + daddasel[0..2] // data adder input A selection + daddbsel[0..3] // data adder input B selection + daddmode[0..2] // data adder mode + daddq_sel // select adder output vs. GPU data + data[0..63] // co-processor read data bus + data_ena // enable write data + data_sel[0..1] // select data to write + dbinh\[0..7] // byte oriented changed data inhibits + dend[0..5] // end of changed write data zone + dpipe[0..1] // load computed data pipe-line latch + dstart[0..5] // start of changed write data zone + dstdld[0..1] // dest data load (two halves) + dstzld[0..1] // dest zed load (two halves) + ext_int // enable extended precision intensity calculations +INT32/ gpu_din // GPU data bus + iincld // I increment load + iincldx // alternate I increment load + init_if // initialise I fraction phase + init_ii // initialise I integer phase + init_zf // initialise Z fraction phase + intld[0..3] // computed intensities load + istepadd // intensity step integer add + istepfadd // intensity step fraction add + istepld // I step load + istepdld // I step delta load + lfu_func[0..3] // LFU function code + patdadd // pattern data gouraud add + patdld[0..1] // pattern data load (two halves) + pdsel[0..1] // select pattern data type + phrase_mode // phrase write mode + reload // transfer contents of double buffers + reset\ // system reset + srcd1ld[0..1] // source register 1 load (two halves) + srcdread // source data read load enable + srczread // source zed read load enable + srcshift[0..5] // source alignment shift + srcz1ld[0..1] // source zed 1 load (two halves) + srcz2add // zed fraction gouraud add + srcz2ld[0..1] // source zed 2 load (two halves) + textrgb // texture mapping in RGB mode + txtd[0..63] // data from the texture unit + zedld[0..3] // computed zeds load + zincld // Z increment load + zmode[0..2] // Z comparator mode + zpipe[0..1] // load computed zed pipe-line latch + zstepadd // zed step integer add + zstepfadd // zed step fraction add + zstepld // Z step load + zstepdld // Z step delta load + :IN); +*/ + +void DATA(uint64_t &wdata, uint8_t &dcomp, uint8_t &zcomp, bool &nowrite, + bool big_pix, bool cmpdst, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, bool daddq_sel, uint8_t data_sel, + uint8_t dbinh, uint8_t dend, uint8_t dstart, uint64_t dstd, uint32_t iinc, uint8_t lfu_func, uint64_t &patd, bool patdadd, + bool phrase_mode, uint64_t srcd, bool srcdread, bool srczread, bool srcz2add, uint8_t zmode, + bool bcompen, bool bkgwren, bool dcompen, uint8_t icount, uint8_t pixsize, + uint64_t &srcz, uint64_t dstz, uint32_t zinc) +{ +/* + Stuff we absolutely *need* to have passed in/out: +IN: + patdadd, dstd, srcd, patd, daddasel, daddbsel, daddmode, iinc, srcz1, srcz2, big_pix, phrase_mode, cmpdst +OUT: + changed patd (wdata I guess...) (Nope. We pass it back directly now...) +*/ + +// Source data registers + +/*Data_src := DATA_SRC (srcdlo, srcdhi, srcz[0..1], srczo[0..1], srczp[0..1], srcz1[0..1], srcz2[0..1], big_pix, + clk, gpu_din, intld[0..3], local_data0, local_data1, srcd1ld[0..1], srcdread, srczread, srcshift[0..5], + srcz1ld[0..1], srcz2add, srcz2ld[0..1], zedld[0..3], zpipe[0..1]); +Srcd[0-7] := JOIN (srcd[0-7], srcdlo{0-7}); +Srcd[8-31] := JOIN (srcd[8-31], srcdlo{8-31}); +Srcd[32-63] := JOIN (srcd[32-63], srcdhi{0-31});*/ + +// Destination data registers + +/*Data_dst := DATA_DST (dstd[0..63], dstz[0..1], clk, dstdld[0..1], dstzld[0..1], load_data[0..1]); +Dstdlo := JOIN (dstdlo, dstd[0..31]); +Dstdhi := JOIN (dstdhi, dstd[32..63]);*/ + +// Pattern and Color data registers + +// Looks like this is simply another register file for the pattern data registers. No adding or anything funky +// going on. Note that patd & patdv will output the same info. +// Patdldl/h (patdld[0..1]) can select the local_data bus to overwrite the current pattern data... +// Actually, it can be either patdld OR patdadd...! +/*Data_pat := DATA_PAT (colord[0..15], int0dp[8..10], int1dp[8..10], int2dp[8..10], int3dp[8..10], mixsel[0..2], + patd[0..63], patdv[0..1], clk, colorld, dpipe[0], ext_int, gpu_din, intld[0..3], local_data0, local_data1, + patdadd, patdld[0..1], reload, reset\); +Patdlo := JOIN (patdlo, patd[0..31]); +Patdhi := JOIN (patdhi, patd[32..63]);*/ + +// Multiplying data Mixer (NOT IN JAGUAR I) + +/*Datamix := DATAMIX (patdo[0..1], clk, colord[0..15], dpipe[1], dstd[0..63], int0dp[8..10], int1dp[8..10], + int2dp[8..10], int3dp[8..10], mixsel[0..2], patd[0..63], pdsel[0..1], srcd[0..63], textrgb, txtd[0..63]);*/ + +// Logic function unit + +/*Lfu := LFU (lfu[0..1], srcdlo, srcdhi, dstdlo, dstdhi, lfu_func[0..3]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint64_t funcmask[2] = { 0, 0xFFFFFFFFFFFFFFFFLL }; + uint64_t func0 = funcmask[lfu_func & 0x01]; + uint64_t func1 = funcmask[(lfu_func >> 1) & 0x01]; + uint64_t func2 = funcmask[(lfu_func >> 2) & 0x01]; + uint64_t func3 = funcmask[(lfu_func >> 3) & 0x01]; + uint64_t lfu = (~srcd & ~dstd & func0) | (~srcd & dstd & func1) | (srcd & ~dstd & func2) | (srcd & dstd & func3); +////////////////////////////////////////////////////////////////////////////////////// + +// Increment and Step Registers + +// Does it do anything without the step add lines? Check it! +// No. This is pretty much just a register file without the Jaguar II lines... +/*Inc_step := INC_STEP (iinc, istep[0..31], zinc, zstep[0..31], clk, ext_int, gpu_din, iincld, iincldx, istepadd, + istepfadd, istepld, istepdld, reload, reset\, zincld, zstepadd, zstepfadd, zstepld, zstepdld); +Istep := JOIN (istep, istep[0..31]); +Zstep := JOIN (zstep, zstep[0..31]);*/ + +// Pixel data comparator + +/*Datacomp := DATACOMP (dcomp[0..7], cmpdst, dstdlo, dstdhi, patdlo, patdhi, srcdlo, srcdhi);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + dcomp = 0; + uint64_t cmpd = patd ^ (cmpdst ? dstd : srcd); + + if ((cmpd & 0x00000000000000FFLL) == 0) + dcomp |= 0x01; + if ((cmpd & 0x000000000000FF00LL) == 0) + dcomp |= 0x02; + if ((cmpd & 0x0000000000FF0000LL) == 0) + dcomp |= 0x04; + if ((cmpd & 0x00000000FF000000LL) == 0) + dcomp |= 0x08; + if ((cmpd & 0x000000FF00000000LL) == 0) + dcomp |= 0x10; + if ((cmpd & 0x0000FF0000000000LL) == 0) + dcomp |= 0x20; + if ((cmpd & 0x00FF000000000000LL) == 0) + dcomp |= 0x40; + if ((cmpd & 0xFF00000000000000LL) == 0) + dcomp |= 0x80; +////////////////////////////////////////////////////////////////////////////////////// + +// Zed comparator for Z-buffer operations + +/*Zedcomp := ZEDCOMP (zcomp[0..3], srczp[0..1], dstz[0..1], zmode[0..2]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +//srczp is srcz pipelined, also it goes through a source shift as well... +/*The shift is basically like so (each piece is 16 bits long): + + 0 1 2 3 4 5 6 + srcz1lolo srcz1lohi srcz1hilo srcz1hihi srcrz2lolo srcz2lohi srcz2hilo + +with srcshift bits 4 & 5 selecting the start position +*/ +//So... basically what we have here is: + zcomp = 0; + + if ((((srcz & 0x000000000000FFFFLL) < (dstz & 0x000000000000FFFFLL)) && (zmode & 0x01)) + || (((srcz & 0x000000000000FFFFLL) == (dstz & 0x000000000000FFFFLL)) && (zmode & 0x02)) + || (((srcz & 0x000000000000FFFFLL) > (dstz & 0x000000000000FFFFLL)) && (zmode & 0x04))) + zcomp |= 0x01; + + if ((((srcz & 0x00000000FFFF0000LL) < (dstz & 0x00000000FFFF0000LL)) && (zmode & 0x01)) + || (((srcz & 0x00000000FFFF0000LL) == (dstz & 0x00000000FFFF0000LL)) && (zmode & 0x02)) + || (((srcz & 0x00000000FFFF0000LL) > (dstz & 0x00000000FFFF0000LL)) && (zmode & 0x04))) + zcomp |= 0x02; + + if ((((srcz & 0x0000FFFF00000000LL) < (dstz & 0x0000FFFF00000000LL)) && (zmode & 0x01)) + || (((srcz & 0x0000FFFF00000000LL) == (dstz & 0x0000FFFF00000000LL)) && (zmode & 0x02)) + || (((srcz & 0x0000FFFF00000000LL) > (dstz & 0x0000FFFF00000000LL)) && (zmode & 0x04))) + zcomp |= 0x04; + + if ((((srcz & 0xFFFF000000000000LL) < (dstz & 0xFFFF000000000000LL)) && (zmode & 0x01)) + || (((srcz & 0xFFFF000000000000LL) == (dstz & 0xFFFF000000000000LL)) && (zmode & 0x02)) + || (((srcz & 0xFFFF000000000000LL) > (dstz & 0xFFFF000000000000LL)) && (zmode & 0x04))) + zcomp |= 0x08; + +//TEMP, TO TEST IF ZCOMP IS THE CULPRIT... +//Nope, this is NOT the problem... +//zcomp=0; +// We'll do the comparison/bit/byte inhibits here, since that's they way it happens +// in the real thing (dcomp goes out to COMP_CTRL and back into DATA through dbinh)... +#if 1 + uint8_t dbinht; +// bool nowrite; + COMP_CTRL(dbinht, nowrite, + bcompen, true/*big_pix*/, bkgwren, dcomp, dcompen, icount, pixsize, phrase_mode, srcd & 0xFF, zcomp); + dbinh = dbinht; +// dbinh = 0x00; +#endif + +#if 1 +#ifdef VERBOSE_BLITTER_LOGGING +if (logBlit) + WriteLog("\n[dcomp=%02X zcomp=%02X dbinh=%02X]\n", dcomp, zcomp, dbinh); +#endif +#endif +////////////////////////////////////////////////////////////////////////////////////// + +// 22 Mar 94 +// The data initializer - allows all four initial values to be computed from one (NOT IN JAGUAR I) + +/*Datinit := DATINIT (initcin[0..3], initinc[0..63], initpix[0..15], a1_x[0..1], big_pix, clk, iinc, init_if, init_ii, + init_zf, istep[0..31], zinc, zstep[0..31]);*/ + +// Adder array for Z and intensity increments + +/*Addarray := ADDARRAY (addq[0..3], clk, daddasel[0..2], daddbsel[0..3], daddmode[0..2], dstdlo, dstdhi, iinc, + initcin[0..3], initinc[0..63], initpix[0..15], istep, patdv[0..1], srcdlo, srcdhi, srcz1[0..1], + srcz2[0..1], reset\, zinc, zstep);*/ +/*void ADDARRAY(uint16_t * addq, uint8_t daddasel, uint8_t daddbsel, uint8_t daddmode, + uint64_t dstd, uint32_t iinc, uint8_t initcin[], uint64_t initinc, uint16_t initpix, + uint32_t istep, uint64_t patd, uint64_t srcd, uint64_t srcz1, uint64_t srcz2, + uint32_t zinc, uint32_t zstep)*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint16_t addq[4]; + uint8_t initcin[4] = { 0, 0, 0, 0 }; + ADDARRAY(addq, daddasel, daddbsel, daddmode, dstd, iinc, initcin, 0, 0, 0, patd, srcd, 0, 0, 0, 0); + + //This is normally done asynchronously above (thru local_data) when in patdadd mode... +//And now it's passed back to the caller to be persistent between calls...! +//But it's causing some serious fuck-ups in T2K now... !!! FIX !!! [DONE--???] +//Weird! It doesn't anymore...! + if (patdadd) + patd = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; +////////////////////////////////////////////////////////////////////////////////////// + +// Local data bus multiplexer + +/*Local_mux := LOCAL_MUX (local_data[0..1], load_data[0..1], + addq[0..3], gpu_din, data[0..63], blitter_active, daddq_sel); +Local_data0 := JOIN (local_data0, local_data[0]); +Local_data1 := JOIN (local_data1, local_data[1]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// + +// Data output multiplexer and tri-state drive + +/*Data_mux := DATA_MUX (wdata[0..63], addq[0..3], big_pix, dstdlo, dstdhi, dstz[0..1], data_sel[0..1], data_ena, + dstart[0..5], dend[0..5], dbinh\[0..7], lfu[0..1], patdo[0..1], phrase_mode, srczo[0..1]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +// NOTE: patdo comes from DATAMIX and can be considered the same as patd for Jaguar I + +////////////////////////////////////////////////////////////////////////////////////// +//} + +/*DEF DATA_MUX ( + wdata[0..63] // co-processor rwrite data bus + :BUS; +INT16/ addq[0..3] + big_pix // Pixel organisation is big-endian +INT32/ dstdlo +INT32/ dstdhi +INT32/ dstzlo +INT32/ dstzhi + data_sel[0..1] // source of write data + data_ena // enable write data onto read/write bus + dstart[0..5] // start of changed write data + dend[0..5] // end of changed write data + dbinh\[0..7] // byte oriented changed data inhibits +INT32/ lfu[0..1] +INT32/ patd[0..1] + phrase_mode // phrase write mode +INT32/ srczlo +INT32/ srczhi + :IN);*/ + +/*INT32/ addql[0..1], ddatlo, ddathi zero32 +:LOCAL; +BEGIN + +Phrase_mode\ := INV1 (phrase_mode\, phrase_mode); +Zero := TIE0 (zero); +Zero32 := JOIN (zero32, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero, zero);*/ + +/* Generate a changed data mask */ + +/*Edis := OR6 (edis\, dend[0..5]); +Ecoarse := DECL38E (e_coarse\[0..7], dend[3..5], edis\); +E_coarse[0] := INV1 (e_coarse[0], e_coarse\[0]); +Efine := DECL38E (unused[0], e_fine\[1..7], dend[0..2], e_coarse[0]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint8_t decl38e[2][8] = { { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } }; + uint8_t dech38[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; + uint8_t dech38el[2][8] = { { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }; + + int en = (dend & 0x3F ? 1 : 0); + uint8_t e_coarse = decl38e[en][(dend & 0x38) >> 3]; // Actually, this is e_coarse inverted... + uint8_t e_fine = decl38e[(e_coarse & 0x01) ^ 0x01][dend & 0x07]; + e_fine &= 0xFE; +////////////////////////////////////////////////////////////////////////////////////// + +/*Scoarse := DECH38 (s_coarse[0..7], dstart[3..5]); +Sfen\ := INV1 (sfen\, s_coarse[0]); +Sfine := DECH38EL (s_fine[0..7], dstart[0..2], sfen\);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint8_t s_coarse = dech38[(dstart & 0x38) >> 3]; + uint8_t s_fine = dech38el[(s_coarse & 0x01) ^ 0x01][dstart & 0x07]; +////////////////////////////////////////////////////////////////////////////////////// + +/*Maskt[0] := BUF1 (maskt[0], s_fine[0]); +Maskt[1-7] := OAN1P (maskt[1-7], maskt[0-6], s_fine[1-7], e_fine\[1-7]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint16_t maskt = s_fine & 0x0001; + maskt |= (((maskt & 0x0001) || (s_fine & 0x02)) && (e_fine & 0x02) ? 0x0002 : 0x0000); + maskt |= (((maskt & 0x0002) || (s_fine & 0x04)) && (e_fine & 0x04) ? 0x0004 : 0x0000); + maskt |= (((maskt & 0x0004) || (s_fine & 0x08)) && (e_fine & 0x08) ? 0x0008 : 0x0000); + maskt |= (((maskt & 0x0008) || (s_fine & 0x10)) && (e_fine & 0x10) ? 0x0010 : 0x0000); + maskt |= (((maskt & 0x0010) || (s_fine & 0x20)) && (e_fine & 0x20) ? 0x0020 : 0x0000); + maskt |= (((maskt & 0x0020) || (s_fine & 0x40)) && (e_fine & 0x40) ? 0x0040 : 0x0000); + maskt |= (((maskt & 0x0040) || (s_fine & 0x80)) && (e_fine & 0x80) ? 0x0080 : 0x0000); +////////////////////////////////////////////////////////////////////////////////////// + +/* Produce a look-ahead on the ripple carry: +masktla = s_coarse[0] . /e_coarse[0] */ +/*Masktla := AN2 (masktla, s_coarse[0], e_coarse\[0]); +Maskt[8] := OAN1P (maskt[8], masktla, s_coarse[1], e_coarse\[1]); +Maskt[9-14] := OAN1P (maskt[9-14], maskt[8-13], s_coarse[2-7], e_coarse\[2-7]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + maskt |= (((s_coarse & e_coarse & 0x01) || (s_coarse & 0x02)) && (e_coarse & 0x02) ? 0x0100 : 0x0000); + maskt |= (((maskt & 0x0100) || (s_coarse & 0x04)) && (e_coarse & 0x04) ? 0x0200 : 0x0000); + maskt |= (((maskt & 0x0200) || (s_coarse & 0x08)) && (e_coarse & 0x08) ? 0x0400 : 0x0000); + maskt |= (((maskt & 0x0400) || (s_coarse & 0x10)) && (e_coarse & 0x10) ? 0x0800 : 0x0000); + maskt |= (((maskt & 0x0800) || (s_coarse & 0x20)) && (e_coarse & 0x20) ? 0x1000 : 0x0000); + maskt |= (((maskt & 0x1000) || (s_coarse & 0x40)) && (e_coarse & 0x40) ? 0x2000 : 0x0000); + maskt |= (((maskt & 0x2000) || (s_coarse & 0x80)) && (e_coarse & 0x80) ? 0x4000 : 0x0000); +////////////////////////////////////////////////////////////////////////////////////// + +/* The bit terms are mirrored for big-endian pixels outside phrase +mode. The byte terms are mirrored for big-endian pixels in phrase +mode. */ + +/*Mirror_bit := AN2M (mir_bit, phrase_mode\, big_pix); +Mirror_byte := AN2H (mir_byte, phrase_mode, big_pix); + +Masktb[14] := BUF1 (masktb[14], maskt[14]); +Masku[0] := MX4 (masku[0], maskt[0], maskt[7], maskt[14], zero, mir_bit, mir_byte); +Masku[1] := MX4 (masku[1], maskt[1], maskt[6], maskt[14], zero, mir_bit, mir_byte); +Masku[2] := MX4 (masku[2], maskt[2], maskt[5], maskt[14], zero, mir_bit, mir_byte); +Masku[3] := MX4 (masku[3], maskt[3], maskt[4], masktb[14], zero, mir_bit, mir_byte); +Masku[4] := MX4 (masku[4], maskt[4], maskt[3], masktb[14], zero, mir_bit, mir_byte); +Masku[5] := MX4 (masku[5], maskt[5], maskt[2], masktb[14], zero, mir_bit, mir_byte); +Masku[6] := MX4 (masku[6], maskt[6], maskt[1], masktb[14], zero, mir_bit, mir_byte); +Masku[7] := MX4 (masku[7], maskt[7], maskt[0], masktb[14], zero, mir_bit, mir_byte); +Masku[8] := MX2 (masku[8], maskt[8], maskt[13], mir_byte); +Masku[9] := MX2 (masku[9], maskt[9], maskt[12], mir_byte); +Masku[10] := MX2 (masku[10], maskt[10], maskt[11], mir_byte); +Masku[11] := MX2 (masku[11], maskt[11], maskt[10], mir_byte); +Masku[12] := MX2 (masku[12], maskt[12], maskt[9], mir_byte); +Masku[13] := MX2 (masku[13], maskt[13], maskt[8], mir_byte); +Masku[14] := MX2 (masku[14], maskt[14], maskt[0], mir_byte);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool mir_bit = true/*big_pix*/ && !phrase_mode; + bool mir_byte = true/*big_pix*/ && phrase_mode; + uint16_t masku = maskt; + + if (mir_bit) + { + masku &= 0xFF00; + masku |= (maskt >> 7) & 0x0001; + masku |= (maskt >> 5) & 0x0002; + masku |= (maskt >> 3) & 0x0004; + masku |= (maskt >> 1) & 0x0008; + masku |= (maskt << 1) & 0x0010; + masku |= (maskt << 3) & 0x0020; + masku |= (maskt << 5) & 0x0040; + masku |= (maskt << 7) & 0x0080; + } + + if (mir_byte) + { + masku = 0; + masku |= (maskt >> 14) & 0x0001; + masku |= (maskt >> 13) & 0x0002; + masku |= (maskt >> 12) & 0x0004; + masku |= (maskt >> 11) & 0x0008; + masku |= (maskt >> 10) & 0x0010; + masku |= (maskt >> 9) & 0x0020; + masku |= (maskt >> 8) & 0x0040; + masku |= (maskt >> 7) & 0x0080; + + masku |= (maskt >> 5) & 0x0100; + masku |= (maskt >> 3) & 0x0200; + masku |= (maskt >> 1) & 0x0400; + masku |= (maskt << 1) & 0x0800; + masku |= (maskt << 3) & 0x1000; + masku |= (maskt << 5) & 0x2000; + masku |= (maskt << 7) & 0x4000; + } +////////////////////////////////////////////////////////////////////////////////////// + +/* The maskt terms define the area for changed data, but the byte +inhibit terms can override these */ + +/*Mask[0-7] := AN2 (mask[0-7], masku[0-7], dbinh\[0]); +Mask[8-14] := AN2H (mask[8-14], masku[8-14], dbinh\[1-7]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint16_t mask = masku & (!(dbinh & 0x01) ? 0xFFFF : 0xFF00); + mask &= ~(((uint16_t)dbinh & 0x00FE) << 7); +////////////////////////////////////////////////////////////////////////////////////// + +/*Addql[0] := JOIN (addql[0], addq[0..1]); +Addql[1] := JOIN (addql[1], addq[2..3]); + +Dsel0b[0-1] := BUF8 (dsel0b[0-1], data_sel[0]); +Dsel1b[0-1] := BUF8 (dsel1b[0-1], data_sel[1]); +Ddatlo := MX4 (ddatlo, patd[0], lfu[0], addql[0], zero32, dsel0b[0], dsel1b[0]); +Ddathi := MX4 (ddathi, patd[1], lfu[1], addql[1], zero32, dsel0b[1], dsel1b[1]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + uint64_t dmux[4]; + dmux[0] = patd; + dmux[1] = lfu; + dmux[2] = ((uint64_t)addq[3] << 48) | ((uint64_t)addq[2] << 32) | ((uint64_t)addq[1] << 16) | (uint64_t)addq[0]; + dmux[3] = 0; + uint64_t ddat = dmux[data_sel]; +////////////////////////////////////////////////////////////////////////////////////// + +/*Zed_sel := AN2 (zed_sel, data_sel[0..1]); +Zed_selb[0-1] := BUF8 (zed_selb[0-1], zed_sel); + +Dat[0-7] := MX4 (dat[0-7], dstdlo{0-7}, ddatlo{0-7}, dstzlo{0-7}, srczlo{0-7}, mask[0-7], zed_selb[0]); +Dat[8-15] := MX4 (dat[8-15], dstdlo{8-15}, ddatlo{8-15}, dstzlo{8-15}, srczlo{8-15}, mask[8], zed_selb[0]); +Dat[16-23] := MX4 (dat[16-23], dstdlo{16-23}, ddatlo{16-23}, dstzlo{16-23}, srczlo{16-23}, mask[9], zed_selb[0]); +Dat[24-31] := MX4 (dat[24-31], dstdlo{24-31}, ddatlo{24-31}, dstzlo{24-31}, srczlo{24-31}, mask[10], zed_selb[0]); +Dat[32-39] := MX4 (dat[32-39], dstdhi{0-7}, ddathi{0-7}, dstzhi{0-7}, srczhi{0-7}, mask[11], zed_selb[1]); +Dat[40-47] := MX4 (dat[40-47], dstdhi{8-15}, ddathi{8-15}, dstzhi{8-15}, srczhi{8-15}, mask[12], zed_selb[1]); +Dat[48-55] := MX4 (dat[48-55], dstdhi{16-23}, ddathi{16-23}, dstzhi{16-23}, srczhi{16-23}, mask[13], zed_selb[1]); +Dat[56-63] := MX4 (dat[56-63], dstdhi{24-31}, ddathi{24-31}, dstzhi{24-31}, srczhi{24-31}, mask[14], zed_selb[1]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + wdata = ((ddat & mask) | (dstd & ~mask)) & 0x00000000000000FFLL; + wdata |= (mask & 0x0100 ? ddat : dstd) & 0x000000000000FF00LL; + wdata |= (mask & 0x0200 ? ddat : dstd) & 0x0000000000FF0000LL; + wdata |= (mask & 0x0400 ? ddat : dstd) & 0x00000000FF000000LL; + wdata |= (mask & 0x0800 ? ddat : dstd) & 0x000000FF00000000LL; + wdata |= (mask & 0x1000 ? ddat : dstd) & 0x0000FF0000000000LL; + wdata |= (mask & 0x2000 ? ddat : dstd) & 0x00FF000000000000LL; + wdata |= (mask & 0x4000 ? ddat : dstd) & 0xFF00000000000000LL; +/*if (logBlit) +{ + printf("\n[ddat=%08X%08X dstd=%08X%08X wdata=%08X%08X mask=%04X]\n", + (uint32_t)(ddat >> 32), (uint32_t)(ddat & 0xFFFFFFFF), + (uint32_t)(dstd >> 32), (uint32_t)(dstd & 0xFFFFFFFF), + (uint32_t)(wdata >> 32), (uint32_t)(wdata & 0xFFFFFFFF), mask); + fflush(stdout); +}//*/ +//This is a crappy way of handling this, but it should work for now... + uint64_t zwdata; + zwdata = ((srcz & mask) | (dstz & ~mask)) & 0x00000000000000FFLL; + zwdata |= (mask & 0x0100 ? srcz : dstz) & 0x000000000000FF00LL; + zwdata |= (mask & 0x0200 ? srcz : dstz) & 0x0000000000FF0000LL; + zwdata |= (mask & 0x0400 ? srcz : dstz) & 0x00000000FF000000LL; + zwdata |= (mask & 0x0800 ? srcz : dstz) & 0x000000FF00000000LL; + zwdata |= (mask & 0x1000 ? srcz : dstz) & 0x0000FF0000000000LL; + zwdata |= (mask & 0x2000 ? srcz : dstz) & 0x00FF000000000000LL; + zwdata |= (mask & 0x4000 ? srcz : dstz) & 0xFF00000000000000LL; +if (logBlit) +{ + WriteLog("\n[srcz=%08X%08X dstz=%08X%08X zwdata=%08X%08X mask=%04X]\n", + (uint32_t)(srcz >> 32), (uint32_t)(srcz & 0xFFFFFFFF), + (uint32_t)(dstz >> 32), (uint32_t)(dstz & 0xFFFFFFFF), + (uint32_t)(zwdata >> 32), (uint32_t)(zwdata & 0xFFFFFFFF), mask); +// fflush(stdout); +}//*/ + srcz = zwdata; +////////////////////////////////////////////////////////////////////////////////////// + +/*Data_enab[0-1] := BUF8 (data_enab[0-1], data_ena); +Datadrv[0-31] := TS (wdata[0-31], dat[0-31], data_enab[0]); +Datadrv[32-63] := TS (wdata[32-63], dat[32-63], data_enab[1]); + +Unused[0] := DUMMY (unused[0]); + +END;*/ +} + + +/** COMP_CTRL - Comparator output control logic ***************** + +This block is responsible for taking the comparator outputs and +using them as appropriate to inhibit writes. Two methods are +supported for inhibiting write data: + +- suppression of the inner loop controlled write operation +- a set of eight byte inhibit lines to write back dest data + +The first technique is used in pixel oriented modes, the second in +phrase mode, but the phrase mode form is only applicable to eight +and sixteen bit pixel modes. + +Writes can be suppressed by data being equal, by the Z comparator +conditions being met, or by the bit to pixel expansion scheme. + +Pipe-lining issues: the data derived comparator outputs are stable +until the next data read, well after the affected write from this +operation. However, the inner counter bits can count immediately +before the ack for the last write. Therefore, it is necessary to +delay bcompbit select terms by one inner loop pipe-line stage, +when generating the select for the data control - the output is +delayed one further tick to give it write data timing (2/34). + +There is also a problem with computed data - the new values are +calculated before the write associated with the old value has been +performed. The is taken care of within the zed comparator by +pipe-lining the comparator inputs where appropriate. +*/ + +//#define LOG_COMP_CTRL +/*DEF COMP_CTRL ( + dbinh\[0..7] // destination byte inhibit lines + nowrite // suppress inner loop write operation + :OUT; + bcompen // bit selector inhibit enable + big_pix // pixels are big-endian + bkgwren // enable dest data write in pix inhibit + clk // co-processor clock + dcomp[0..7] // output of data byte comparators + dcompen // data comparator inhibit enable + icount[0..2] // low bits of inner count + pixsize[0..2] // destination pixel size + phrase_mode // phrase write mode + srcd[0..7] // bits to use for bit to byte expansion + step_inner // inner loop advance + zcomp[0..3] // output of word zed comparators + :IN);*/ +void COMP_CTRL(uint8_t &dbinh, bool &nowrite, + bool bcompen, bool big_pix, bool bkgwren, uint8_t dcomp, bool dcompen, uint8_t icount, + uint8_t pixsize, bool phrase_mode, uint8_t srcd, uint8_t zcomp) +{ +//BEGIN + +/*Bkgwren\ := INV1 (bkgwren\, bkgwren); +Phrase_mode\ := INV1 (phrase_mode\, phrase_mode); +Pixsize\[0-2] := INV2 (pixsize\[0-2], pixsize[0-2]);*/ + +/* The bit comparator bits are derived from the source data, which +will have been suitably aligned for phrase mode. The contents of +the inner counter are used to select which bit to use. + +When not in phrase mode the inner count value is used to select +one bit. It is assumed that the count has already occurred, so, +7 selects bit 0, etc. In big-endian pixel mode, this turns round, +so that a count of 7 selects bit 7. + +In phrase mode, the eight bits are used directly, and this mode is +only applicable to 8-bit pixel mode (2/34) */ + +/*Bcompselt[0-2] := EO (bcompselt[0-2], icount[0-2], big_pix); +Bcompbit := MX8 (bcompbit, srcd[7], srcd[6], srcd[5], + srcd[4], srcd[3], srcd[2], srcd[1], srcd[0], bcompselt[0..2]); +Bcompbit\ := INV1 (bcompbit\, bcompbit);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("\n [bcompen=%s dcompen=%s phrase_mode=%s bkgwren=%s dcomp=%02X zcomp=%02X]", (bcompen ? "T" : "F"), (dcompen ? "T" : "F"), (phrase_mode ? "T" : "F"), (bkgwren ? "T" : "F"), dcomp, zcomp); + WriteLog("\n "); +// fflush(stdout); +} +#endif + uint8_t bcompselt = (big_pix ? ~icount : icount) & 0x07; + uint8_t bitmask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + bool bcompbit = srcd & bitmask[bcompselt]; +////////////////////////////////////////////////////////////////////////////////////// + +/* pipe-line the count */ +/*Bcompsel[0-2] := FDSYNC (bcompsel[0-2], bcompselt[0-2], step_inner, clk); +Bcompbt := MX8 (bcompbitpt, srcd[7], srcd[6], srcd[5], + srcd[4], srcd[3], srcd[2], srcd[1], srcd[0], bcompsel[0..2]); +Bcompbitp := FD1Q (bcompbitp, bcompbitpt, clk); +Bcompbitp\ := INV1 (bcompbitp\, bcompbitp);*/ + +/* For pixel mode, generate the write inhibit signal for all modes +on bit inhibit, for 8 and 16 bit modes on comparator inhibit, and +for 16 bit mode on Z inhibit + +Nowrite = bcompen . /bcompbit . /phrase_mode + + dcompen . dcomp[0] . /phrase_mode . pixsize = 011 + + dcompen . dcomp[0..1] . /phrase_mode . pixsize = 100 + + zcomp[0] . /phrase_mode . pixsize = 100 +*/ + +/*Nowt0 := NAN3 (nowt[0], bcompen, bcompbit\, phrase_mode\); +Nowt1 := ND6 (nowt[1], dcompen, dcomp[0], phrase_mode\, pixsize\[2], pixsize[0..1]); +Nowt2 := ND7 (nowt[2], dcompen, dcomp[0..1], phrase_mode\, pixsize[2], pixsize\[0..1]); +Nowt3 := NAN5 (nowt[3], zcomp[0], phrase_mode\, pixsize[2], pixsize\[0..1]); +Nowt4 := NAN4 (nowt[4], nowt[0..3]); +Nowrite := AN2 (nowrite, nowt[4], bkgwren\);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + nowrite = ((bcompen && !bcompbit && !phrase_mode) + || (dcompen && (dcomp & 0x01) && !phrase_mode && (pixsize == 3)) + || (dcompen && ((dcomp & 0x03) == 0x03) && !phrase_mode && (pixsize == 4)) + || ((zcomp & 0x01) && !phrase_mode && (pixsize == 4))) + && !bkgwren; +////////////////////////////////////////////////////////////////////////////////////// + +/*Winht := NAN3 (winht, bcompen, bcompbitp\, phrase_mode\); +Winhibit := NAN4 (winhibit, winht, nowt[1..3]);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +//This is the same as above, but with bcompbit delayed one tick and called 'winhibit' +//Small difference: Besides the pipeline effect, it's also not using !bkgwren... +// bool winhibit = (bcompen && ! + bool winhibit = (bcompen && !bcompbit && !phrase_mode) + || (dcompen && (dcomp & 0x01) && !phrase_mode && (pixsize == 3)) + || (dcompen && ((dcomp & 0x03) == 0x03) && !phrase_mode && (pixsize == 4)) + || ((zcomp & 0x01) && !phrase_mode && (pixsize == 4)); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[nw=%s wi=%s]", (nowrite ? "T" : "F"), (winhibit ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/* For phrase mode, generate the byte inhibit signals for eight bit +mode 011, or sixteen bit mode 100 +dbinh\[0] = pixsize[2] . zcomp[0] + + pixsize[2] . dcomp[0] . dcomp[1] . dcompen + + /pixsize[2] . dcomp[0] . dcompen + + /srcd[0] . bcompen + +Inhibits 0-3 are also used when not in phrase mode to write back +destination data. +*/ + +/*Srcd\[0-7] := INV1 (srcd\[0-7], srcd[0-7]); + +Di0t0 := NAN2H (di0t[0], pixsize[2], zcomp[0]); +Di0t1 := NAN4H (di0t[1], pixsize[2], dcomp[0..1], dcompen); +Di0t2 := NAN2 (di0t[2], srcd\[0], bcompen); +Di0t3 := NAN3 (di0t[3], pixsize\[2], dcomp[0], dcompen); +Di0t4 := NAN4 (di0t[4], di0t[0..3]); +Dbinh[0] := ANR1P (dbinh\[0], di0t[4], phrase_mode, winhibit);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + dbinh = 0; + bool di0t0_1 = ((pixsize & 0x04) && (zcomp & 0x01)) + || ((pixsize & 0x04) && (dcomp & 0x01) && (dcomp & 0x02) && dcompen); + bool di0t4 = di0t0_1 + || (!(srcd & 0x01) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x01) && dcompen); + dbinh |= (!((di0t4 && phrase_mode) || winhibit) ? 0x01 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di0t0_1=%s di0t4=%s]", (di0t0_1 ? "T" : "F"), (di0t4 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di1t0 := NAN3 (di1t[0], pixsize\[2], dcomp[1], dcompen); +Di1t1 := NAN2 (di1t[1], srcd\[1], bcompen); +Di1t2 := NAN4 (di1t[2], di0t[0..1], di1t[0..1]); +Dbinh[1] := ANR1 (dbinh\[1], di1t[2], phrase_mode, winhibit);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di1t2 = di0t0_1 + || (!(srcd & 0x02) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x02) && dcompen); + dbinh |= (!((di1t2 && phrase_mode) || winhibit) ? 0x02 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di1t2=%s]", (di1t2 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di2t0 := NAN2H (di2t[0], pixsize[2], zcomp[1]); +Di2t1 := NAN4H (di2t[1], pixsize[2], dcomp[2..3], dcompen); +Di2t2 := NAN2 (di2t[2], srcd\[2], bcompen); +Di2t3 := NAN3 (di2t[3], pixsize\[2], dcomp[2], dcompen); +Di2t4 := NAN4 (di2t[4], di2t[0..3]); +Dbinh[2] := ANR1 (dbinh\[2], di2t[4], phrase_mode, winhibit);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// +//[bcompen=F dcompen=T phrase_mode=T bkgwren=F][nw=F wi=F] +//[di0t0_1=F di0t4=F][di1t2=F][di2t0_1=T di2t4=T][di3t2=T][di4t0_1=F di2t4=F][di5t2=F][di6t0_1=F di6t4=F][di7t2=F] +//[dcomp=$00 dbinh=$0C][7804780400007804] (icount=0005, inc=4) + bool di2t0_1 = ((pixsize & 0x04) && (zcomp & 0x02)) + || ((pixsize & 0x04) && (dcomp & 0x04) && (dcomp & 0x08) && dcompen); + bool di2t4 = di2t0_1 + || (!(srcd & 0x04) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x04) && dcompen); + dbinh |= (!((di2t4 && phrase_mode) || winhibit) ? 0x04 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di2t0_1=%s di2t4=%s]", (di2t0_1 ? "T" : "F"), (di2t4 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di3t0 := NAN3 (di3t[0], pixsize\[2], dcomp[3], dcompen); +Di3t1 := NAN2 (di3t[1], srcd\[3], bcompen); +Di3t2 := NAN4 (di3t[2], di2t[0..1], di3t[0..1]); +Dbinh[3] := ANR1 (dbinh\[3], di3t[2], phrase_mode, winhibit);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di3t2 = di2t0_1 + || (!(srcd & 0x08) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x08) && dcompen); + dbinh |= (!((di3t2 && phrase_mode) || winhibit) ? 0x08 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di3t2=%s]", (di3t2 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di4t0 := NAN2H (di4t[0], pixsize[2], zcomp[2]); +Di4t1 := NAN4H (di4t[1], pixsize[2], dcomp[4..5], dcompen); +Di4t2 := NAN2 (di4t[2], srcd\[4], bcompen); +Di4t3 := NAN3 (di4t[3], pixsize\[2], dcomp[4], dcompen); +Di4t4 := NAN4 (di4t[4], di4t[0..3]); +Dbinh[4] := NAN2 (dbinh\[4], di4t[4], phrase_mode);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di4t0_1 = ((pixsize & 0x04) && (zcomp & 0x04)) + || ((pixsize & 0x04) && (dcomp & 0x10) && (dcomp & 0x20) && dcompen); + bool di4t4 = di4t0_1 + || (!(srcd & 0x10) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x10) && dcompen); + dbinh |= (!(di4t4 && phrase_mode) ? 0x10 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di4t0_1=%s di2t4=%s]", (di4t0_1 ? "T" : "F"), (di4t4 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di5t0 := NAN3 (di5t[0], pixsize\[2], dcomp[5], dcompen); +Di5t1 := NAN2 (di5t[1], srcd\[5], bcompen); +Di5t2 := NAN4 (di5t[2], di4t[0..1], di5t[0..1]); +Dbinh[5] := NAN2 (dbinh\[5], di5t[2], phrase_mode);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di5t2 = di4t0_1 + || (!(srcd & 0x20) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x20) && dcompen); + dbinh |= (!(di5t2 && phrase_mode) ? 0x20 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di5t2=%s]", (di5t2 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di6t0 := NAN2H (di6t[0], pixsize[2], zcomp[3]); +Di6t1 := NAN4H (di6t[1], pixsize[2], dcomp[6..7], dcompen); +Di6t2 := NAN2 (di6t[2], srcd\[6], bcompen); +Di6t3 := NAN3 (di6t[3], pixsize\[2], dcomp[6], dcompen); +Di6t4 := NAN4 (di6t[4], di6t[0..3]); +Dbinh[6] := NAN2 (dbinh\[6], di6t[4], phrase_mode);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di6t0_1 = ((pixsize & 0x04) && (zcomp & 0x08)) + || ((pixsize & 0x04) && (dcomp & 0x40) && (dcomp & 0x80) && dcompen); + bool di6t4 = di6t0_1 + || (!(srcd & 0x40) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x40) && dcompen); + dbinh |= (!(di6t4 && phrase_mode) ? 0x40 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di6t0_1=%s di6t4=%s]", (di6t0_1 ? "T" : "F"), (di6t4 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +/*Di7t0 := NAN3 (di7t[0], pixsize\[2], dcomp[7], dcompen); +Di7t1 := NAN2 (di7t[1], srcd\[7], bcompen); +Di7t2 := NAN4 (di7t[2], di6t[0..1], di7t[0..1]); +Dbinh[7] := NAN2 (dbinh\[7], di7t[2], phrase_mode);*/ +////////////////////////////////////// C++ CODE ////////////////////////////////////// + bool di7t2 = di6t0_1 + || (!(srcd & 0x80) && bcompen) + || (!(pixsize & 0x04) && (dcomp & 0x80) && dcompen); + dbinh |= (!(di7t2 && phrase_mode) ? 0x80 : 0x00); +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[di7t2=%s]", (di7t2 ? "T" : "F")); +// fflush(stdout); +} +#endif +////////////////////////////////////////////////////////////////////////////////////// + +//END; +//kludge +dbinh = ~dbinh; +#ifdef LOG_COMP_CTRL +if (logBlit) +{ + WriteLog("[dcomp=$%02X dbinh=$%02X]\n ", dcomp, dbinh); +// fflush(stdout); +} +#endif +} + + +////////////////////////////////////// C++ CODE ////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// + +// !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! +// !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! +// !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! TESTING !!! + +#endif + diff --git a/waterbox/virtualjaguar/src/blitter.h b/waterbox/virtualjaguar/src/blitter.h new file mode 100644 index 0000000000..d57e866f98 --- /dev/null +++ b/waterbox/virtualjaguar/src/blitter.h @@ -0,0 +1,30 @@ +// +// Jaguar blitter implementation +// + +#ifndef __BLITTER_H__ +#define __BLITTER_H__ + +//#include "types.h" +#include "memory.h" + +void BlitterInit(void); +void BlitterReset(void); +void BlitterDone(void); + +uint8_t BlitterReadByte(uint32_t, uint32_t who = UNKNOWN); +uint16_t BlitterReadWord(uint32_t, uint32_t who = UNKNOWN); +uint32_t BlitterReadLong(uint32_t, uint32_t who = UNKNOWN); +void BlitterWriteByte(uint32_t, uint8_t, uint32_t who = UNKNOWN); +void BlitterWriteWord(uint32_t, uint16_t, uint32_t who = UNKNOWN); +void BlitterWriteLong(uint32_t, uint32_t, uint32_t who = UNKNOWN); + +uint32_t blitter_reg_read(uint32_t offset); +void blitter_reg_write(uint32_t offset, uint32_t data); + +extern uint8_t blitter_working; + +//For testing only... +void LogBlit(void); + +#endif // __BLITTER_H__ diff --git a/waterbox/virtualjaguar/src/cdintf.cpp b/waterbox/virtualjaguar/src/cdintf.cpp new file mode 100644 index 0000000000..1cf2ee2e2d --- /dev/null +++ b/waterbox/virtualjaguar/src/cdintf.cpp @@ -0,0 +1,161 @@ +// +// OS agnostic CDROM interface functions +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 01/16/2010 Created this log ;-) +// + +// +// This now uses the supposedly cross-platform libcdio to do the necessary +// low-level CD twiddling we need that libsdl can't do currently. Jury is +// still out on whether or not to make this a conditional compilation or not. +// + +// Comment this out if you don't have libcdio installed +// (Actually, this is defined in the Makefile to prevent having to edit +// things too damn much. Jury is still out whether or not to make this +// change permanent.) +//#define HAVE_LIB_CDIO + +#include "cdintf.h" // Every OS has to implement these + +#ifdef HAVE_LIB_CDIO +#include // Now using OS agnostic CD access routines! +#endif +#include "log.h" + + +/* +static void TestCDIO(void) +{ + // See what (if anything) is installed. + CdIo_t * p_cdio = cdio_open(0, DRIVER_DEVICE); + driver_id_t driver_id; + + if (p_cdio != NULL) + { + WriteLog("CDIO: The driver selected is %s.\n", cdio_get_driver_name(p_cdio)); + WriteLog("CDIO: The default device for this driver is %s.\n\n", cdio_get_default_device(p_cdio)); + cdio_destroy(p_cdio); + } + else + { + WriteLog("CDIO: A suitable CD-ROM driver was not found.\n\n"); + } +} +*/ + +// +// *** OK, here's where we're going to attempt to put the platform agnostic CD interface *** +// + +#ifdef HAVE_LIB_CDIO +static CdIo_t * cdioPtr = NULL; +#endif + + +bool CDIntfInit(void) +{ +#ifdef HAVE_LIB_CDIO + cdioPtr = cdio_open(NULL, DRIVER_DEVICE); + + if (cdioPtr == NULL) + { +#endif + WriteLog("CDINTF: No suitable CD-ROM driver found.\n"); + return false; +#ifdef HAVE_LIB_CDIO + } + + WriteLog("CDINTF: Successfully opened CD-ROM interface.\n"); + + return true; +#endif +} + + +void CDIntfDone(void) +{ + WriteLog("CDINTF: Shutting down CD-ROM subsystem.\n"); + +#ifdef HAVE_LIB_CDIO + if (cdioPtr) + cdio_destroy(cdioPtr); +#endif +} + + +bool CDIntfReadBlock(uint32_t sector, uint8_t * buffer) +{ +#warning "!!! FIX !!! CDIntfReadBlock not implemented!" + // !!! FIX !!! + WriteLog("CDINTF: ReadBlock unimplemented!\n"); + return false; +} + + +uint32_t CDIntfGetNumSessions(void) +{ +#warning "!!! FIX !!! CDIntfGetNumSessions not implemented!" + // !!! FIX !!! + // Still need relevant code here... !!! FIX !!! + return 2; +} + + +void CDIntfSelectDrive(uint32_t driveNum) +{ +#warning "!!! FIX !!! CDIntfSelectDrive not implemented!" + // !!! FIX !!! + WriteLog("CDINTF: SelectDrive unimplemented!\n"); +} + + +uint32_t CDIntfGetCurrentDrive(void) +{ +#warning "!!! FIX !!! CDIntfGetCurrentDrive not implemented!" + // !!! FIX !!! + WriteLog("CDINTF: GetCurrentDrive unimplemented!\n"); + return 0; +} + + +const uint8_t * CDIntfGetDriveName(uint32_t driveNum) +{ +#warning "!!! FIX !!! CDIntfGetDriveName driveNum is currently ignored!" + // driveNum is currently ignored... !!! FIX !!! + +#ifdef HAVE_LIB_CDIO + uint8_t * driveName = (uint8_t *)cdio_get_default_device(cdioPtr); + WriteLog("CDINTF: The drive name for the current driver is %s.\n", driveName); + + return driveName; +#else + return (uint8_t *)"NONE"; +#endif +} + + +uint8_t CDIntfGetSessionInfo(uint32_t session, uint32_t offset) +{ +#warning "!!! FIX !!! CDIntfGetSessionInfo not implemented!" + // !!! FIX !!! + WriteLog("CDINTF: GetSessionInfo unimplemented!\n"); + return 0xFF; +} + + +uint8_t CDIntfGetTrackInfo(uint32_t track, uint32_t offset) +{ +#warning "!!! FIX !!! CDIntfTrackInfo not implemented!" + // !!! FIX !!! + WriteLog("CDINTF: GetTrackInfo unimplemented!\n"); + return 0xFF; +} + diff --git a/waterbox/virtualjaguar/src/cdintf.h b/waterbox/virtualjaguar/src/cdintf.h new file mode 100644 index 0000000000..83c021b1e5 --- /dev/null +++ b/waterbox/virtualjaguar/src/cdintf.h @@ -0,0 +1,22 @@ +// +// CDINTF.H: OS agnostic CDROM access funcions +// +// by James Hammons +// + +#ifndef __CDINTF_H__ +#define __CDINTF_H__ + +#include + +bool CDIntfInit(void); +void CDIntfDone(void); +bool CDIntfReadBlock(uint32_t, uint8_t *); +uint32_t CDIntfGetNumSessions(void); +void CDIntfSelectDrive(uint32_t); +uint32_t CDIntfGetCurrentDrive(void); +const uint8_t * CDIntfGetDriveName(uint32_t); +uint8_t CDIntfGetSessionInfo(uint32_t, uint32_t); +uint8_t CDIntfGetTrackInfo(uint32_t, uint32_t); + +#endif // __CDINTF_H__ diff --git a/waterbox/virtualjaguar/src/cdrom.cpp b/waterbox/virtualjaguar/src/cdrom.cpp new file mode 100644 index 0000000000..8823d43c8e --- /dev/null +++ b/waterbox/virtualjaguar/src/cdrom.cpp @@ -0,0 +1,1365 @@ +// +// CD handler +// +// Originally by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Extensive rewrites/cleanups/fixes by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 01/16/2010 Created this log ;-) +// + +#include "cdrom.h" + +#include // For memset, etc. +//#include "jaguar.h" // For GET32/SET32 macros +//#include "m68k.h" //??? +//#include "memory.h" +#include "cdintf.h" // System agnostic CD interface functions +#include "log.h" +#include "dac.h" + +//#define CDROM_LOG // For CDROM logging, obviously + +/* +BUTCH equ $DFFF00 ; base of Butch=interrupt control register, R/W +DSCNTRL equ BUTCH+4 ; DSA control register, R/W +DS_DATA equ BUTCH+$A ; DSA TX/RX data, R/W +I2CNTRL equ BUTCH+$10 ; i2s bus control register, R/W +SBCNTRL equ BUTCH+$14 ; CD subcode control register, R/W +SUBDATA equ BUTCH+$18 ; Subcode data register A +SUBDATB equ BUTCH+$1C ; Subcode data register B +SB_TIME equ BUTCH+$20 ; Subcode time and compare enable (D24) +FIFO_DATA equ BUTCH+$24 ; i2s FIFO data +I2SDAT1 equ BUTCH+$24 ; i2s FIFO data +I2SDAT2 equ BUTCH+$28 ; i2s FIFO data + equ BUTCH+$2C ; CD EEPROM interface + +; +; Butch's hardware registers +; +;BUTCH equ $DFFF00 ;base of Butch=interrupt control register, R/W +; +; When written (Long): +; +; bit0 - set to enable interrupts +; bit1 - enable CD data FIFO half full interrupt +; bit2 - enable CD subcode frame-time interrupt (@ 2x spped = 7ms.) +; bit3 - enable pre-set subcode time-match found interrupt +; bit4 - CD module command transmit buffer empty interrupt +; bit5 - CD module command receive buffer full +; bit6 - CIRC failure interrupt +; +; bit7-31 reserved, set to 0 +; +; When read (Long): +; +; bit0-8 reserved +; +; bit9 - CD data FIFO half-full flag pending +; bit10 - Frame pending +; bit11 - Subcode data pending +; bit12 - Command to CD drive pending (trans buffer empty if 1) +; bit13 - Response from CD drive pending (rec buffer full if 1) +; bit14 - CD uncorrectable data error pending +; +; Offsets from BUTCH +; +O_DSCNTRL equ 4 ; DSA control register, R/W +O_DS_DATA equ $A ; DSA TX/RX data, R/W +; +O_I2CNTRL equ $10 ; i2s bus control register, R/W +; +; When read: +; +; b0 - I2S data from drive is ON if 1 +; b1 - I2S path to Jerry is ON if 1 +; b2 - reserved +; b3 - host bus width is 16 if 1, else 32 +; b4 - FIFO state is not empty if 1 +; +O_SBCNTRL equ $14 ; CD subcode control register, R/W +O_SUBDATA equ $18 ; Subcode data register A +O_SUBDATB equ $1C ; Subcode data register B +O_SB_TIME equ $20 ; Subcode time and compare enable (D24) +O_FIFODAT equ $24 ; i2s FIFO data +O_I2SDAT2 equ $28 ; i2s FIFO data (old) +*/ + +/* +Commands sent through DS_DATA: + +$01nn - ? Play track nn ? Seek to track nn ? +$0200 - Stop CD +$03nn - Read session nn TOC (short) +$0400 - Pause CD +$0500 - Unpause CD +$10nn - Goto (min?) +$11nn - Goto (sec?) +$12nn - Goto (frm?) +$14nn - Read session nn TOC (full) +$15nn - Set CD mode +$18nn - Spin up CD to session nn +$5000 - ? +$5100 - Mute CD (audio mode only) +$51FF - Unmute CD (audio mode only) +$5400 - Read # of sessions on CD +$70nn - Set oversampling mode + +Commands send through serial bus: + +$100 - ? Acknowledge ? (Erase/Write disable) +$130 - ? (Seems to always prefix the $14n commands) (Erase/Write enable) +$140 - Returns ACK (1) (Write to NVRAM?) (Write selected register) +$141 - Returns ACK (1) +$142 - Returns ACK (1) +$143 - Returns ACK (1) +$144 - Returns ACK (1) +$145 - Returns ACK (1) +$180 - Returns 16-bit value (NVRAM?) (read from EEPROM) +$181 - Returns 16-bit value +$182 - Returns 16-bit value +$183 - Returns 16-bit value +$184 - Returns 16-bit value +$185 - Returns 16-bit value + +; The BUTCH interface for the CD-ROM module is a long-word register, +; where only the least signifigant 4 bits are used +; +eeprom equ $DFFF2c ;interface to CD-eeprom +; +; bit3 - busy if 0 after write cmd, or Data In after read cmd +; bit2 - Data Out +; bit1 - clock +; bit0 - Chip Select (CS) +; +; +; Commands specific to the National Semiconductor NM93C14 +; +; +; 9-bit commands.. +; 876543210 +eREAD equ %110000000 ;read from EEPROM +eEWEN equ %100110000 ;Erase/write Enable +eERASE equ %111000000 ;Erase selected register +eWRITE equ %101000000 ;Write selected register +eERAL equ %100100000 ;Erase all registers +eWRAL equ %100010000 ;Writes all registers +eEWDS equ %100000000 ;Erase/Write disable (default) + +So... are there $40 words of memory? 128 bytes? + +*/ + +// Private function prototypes + +static void CDROMBusWrite(uint16_t); +static uint16_t CDROMBusRead(void); + +#define BUTCH 0x00 // base of Butch == interrupt control register, R/W +#define DSCNTRL BUTCH + 0x04 // DSA control register, R/W +#define DS_DATA BUTCH + 0x0A // DSA TX/RX data, R/W +#define I2CNTRL BUTCH + 0x10 // i2s bus control register, R/W +#define SBCNTRL BUTCH + 0x14 // CD subcode control register, R/W +#define SUBDATA BUTCH + 0x18 // Subcode data register A +#define SUBDATB BUTCH + 0x1C // Subcode data register B +#define SB_TIME BUTCH + 0x20 // Subcode time and compare enable (D24) +#define FIFO_DATA BUTCH + 0x24 // i2s FIFO data +#define I2SDAT2 BUTCH + 0x28 // i2s FIFO data (old) +#define UNKNOWN BUTCH + 0x2C // Seems to be some sort of I2S interface + +const char * BReg[12] = { "BUTCH", "DSCNTRL", "DS_DATA", "???", "I2CNTRL", + "SBCNTRL", "SUBDATA", "SUBDATB", "SB_TIME", "FIFO_DATA", "I2SDAT2", + "UNKNOWN" }; +//extern const char * whoName[9]; + + +static uint8_t cdRam[0x100]; +static uint16_t cdCmd = 0, cdPtr = 0; +static bool haveCDGoodness; +static uint32_t min, sec, frm, block; +static uint8_t cdBuf[2352 + 96]; +static uint32_t cdBufPtr = 2352; +//Also need to set up (save/restore) the CD's NVRAM + + +//extern bool GetRawTOC(void); +void CDROMInit(void) +{ + haveCDGoodness = CDIntfInit(); + +//GetRawTOC(); +/*uint8_t buf[2448]; +uint32_t sec = 18667 - 150; +memset(buf, 0, 2448); +if (!CDIntfReadBlock(sec, buf)) +{ + WriteLog("CDROM: Attempt to read with subchannel data failed!\n"); + return; +} + +//24x98+96 +//96=4x24=4x4x6 +WriteLog("\nCDROM: Read sector %u...\n\n", sec); +for(int i=0; i<98; i++) +{ + WriteLog("%04X: ", i*24); + for(int j=0; j<24; j++) + { + WriteLog("%02X ", buf[j + (i*24)]); + } + WriteLog("\n"); +} +WriteLog("\nRaw P-W subchannel data:\n\n"); +for(int i=0; i<6; i++) +{ + WriteLog("%02X: ", i*16); + for(int j=0; j<16; j++) + { + WriteLog("%02X ", buf[2352 + j + (i*16)]); + } + WriteLog("\n"); +} +WriteLog("\nP subchannel data: "); +for(int i=0; i<96; i+=8) +{ + uint8_t b = 0; + for(int j=0; j<8; j++) + b |= ((buf[2352 + i + j] & 0x80) >> 7) << (7 - j); + + WriteLog("%02X ", b); +} +WriteLog("\nQ subchannel data: "); +for(int i=0; i<96; i+=8) +{ + uint8_t b = 0; + for(int j=0; j<8; j++) + b |= ((buf[2352 + i + j] & 0x40) >> 6) << (7 - j); + + WriteLog("%02X ", b); +} +WriteLog("\n\n");//*/ +} + +void CDROMReset(void) +{ + memset(cdRam, 0x00, 0x100); + cdCmd = 0; +} + +void CDROMDone(void) +{ + CDIntfDone(); +} + + +// +// This approach is probably wrong, but let's do it for now. +// What's needed is a complete overhaul of the interrupt system so that +// interrupts are handled as they're generated--instead of the current +// scheme where they're handled on scanline boundaries. +// +void BUTCHExec(uint32_t cycles) +{ +#if 1 +// We're chickening out for now... +return; +#else +// extern uint8_t * jerry_ram_8; // Hmm. + + // For now, we just do the FIFO interrupt. Timing is also likely to be WRONG as well. + uint32_t cdState = GET32(cdRam, BUTCH); + + if (!(cdState & 0x01)) // No BUTCH interrupts enabled + return; + + if (!(cdState & 0x22)) + return; // For now, we only handle FIFO/buffer full interrupts... + + // From what I can make out, it seems that each FIFO is 32 bytes long + +// DSPSetIRQLine(DSPIRQ_EXT, ASSERT_LINE); +//I'm *sure* this is wrong--prolly need to generate DSP IRQs as well! + if (jerry_ram_8[0x23] & 0x3F) // Only generate an IRQ if enabled! + GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE); +#endif +} + + +// +// CD-ROM memory access functions +// + +uint8_t CDROMReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ +#ifdef CDROM_LOG + if ((offset & 0xFF) < 12 * 4) + WriteLog("[%s] ", BReg[(offset & 0xFF) / 4]); + WriteLog("CDROM: %s reading byte $%02X from $%08X [68K PC=$%08X]\n", whoName[who], offset, cdRam[offset & 0xFF], m68k_get_reg(NULL, M68K_REG_PC)); +#endif + return cdRam[offset & 0xFF]; +} + +static uint8_t trackNum = 1, minTrack, maxTrack; +//static uint8_t minutes[16] = { 0, 0, 2, 5, 7, 10, 12, 15, 17, 20, 22, 25, 27, 30, 32, 35 }; +//static uint8_t seconds[16] = { 0, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0 }; +//static uint8_t frames[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +//static uint16_t sd = 0; +uint16_t CDROMReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0xFF; + + uint16_t data = 0x0000; + + if (offset == BUTCH) + data = 0x0000; + else if (offset == BUTCH + 2) +// We need to fix this so it's not as brain-dead as it is now--i.e., make it so that when +// a command is sent to the CDROM, we control here whether or not it succeeded or whether +// the command is still being carried out, etc. + +// bit12 - Command to CD drive pending (trans buffer empty if 1) +// bit13 - Response from CD drive pending (rec buffer full if 1) +// data = (haveCDGoodness ? 0x3000 : 0x0000); // DSA RX Interrupt pending bit (0 = pending) +//This only returns ACKs for interrupts that are set: +//This doesn't work for the initial code that writes $180000 to BUTCH. !!! FIX !!! + data = (haveCDGoodness ? cdRam[BUTCH + 3] << 8 : 0x0000); +// else if (offset == SUBDATA + 2) +// data = sd++ | 0x0010; // Have no idea what this is... + else if (offset == DS_DATA && haveCDGoodness) + { + if ((cdCmd & 0xFF00) == 0x0100) // ??? + { +//Not sure how to acknowledge the ???... +// data = 0x0400;//?? 0x0200; + cdPtr++; + switch (cdPtr) + { + case 1: + data = 0x0000; + break; + case 2: + data = 0x0100; + break; + case 3: + data = 0x0200; + break; + case 4: + data = 0x0300; + break; + case 5: + data = 0x0400; + }//*/ + //WriteLog("CDROM: Reading DS_DATA (???), cdCmd=$%04X\n", cdCmd); + } + else if ((cdCmd & 0xFF00) == 0x0200) // Stop CD + { +//Not sure how to acknowledge the stop... + data = 0x0400;//?? 0x0200; +/* cdPtr++; + switch (cdPtr) + { + case 1: + data = 0x00FF; + break; + case 2: + data = 0x01FF; + break; + case 3: + data = 0x02FF; + break; + case 4: + data = 0x03FF; + break; + case 5: + data = 0x0400; + }//*/ + WriteLog("CDROM: Reading DS_DATA (stop), cdCmd=$%04X\n", cdCmd); + } + else if ((cdCmd & 0xFF00) == 0x0300) // Read session TOC (overview?) + { + +/* +TOC: [Sess] [adrCtl] [?] [point] [?] [?] [?] [?] [pmin] [psec] [pframe] +TOC: 1 10 00 a0 00:00:00 00 01:00:00 +TOC: 1 10 00 a1 00:00:00 00 01:00:00 +TOC: 1 10 00 a2 00:00:00 00 03:42:42 +TOC: 1 10 00 1 00:00:00 00 00:02:00 <-- Track #1 +TOC: 1 50 00 b0 06:12:42 02 79:59:74 +TOC: 1 50 00 c0 128:00:32 00 97:18:06 +TOC: 2 10 00 a0 00:00:00 00 02:00:00 +TOC: 2 10 00 a1 00:00:00 00 11:00:00 +TOC: 2 10 00 a2 00:00:00 00 54:32:18 +TOC: 2 10 00 2 00:00:00 00 06:14:42 <-- Track #2 +TOC: 2 10 00 3 00:00:00 00 06:24:42 <-- Track #3 +TOC: 2 10 00 4 00:00:00 00 17:42:00 <-- Track #4 +TOC: 2 10 00 5 00:00:00 00 22:26:15 <-- Track #5 +TOC: 2 10 00 6 00:00:00 00 29:50:16 <-- Track #6 +TOC: 2 10 00 7 00:00:00 00 36:01:49 <-- Track #7 +TOC: 2 10 00 8 00:00:00 00 40:37:59 <-- Track #8 +TOC: 2 10 00 9 00:00:00 00 45:13:70 <-- Track #9 +TOC: 2 10 00 a 00:00:00 00 49:50:06 <-- Track #10 +TOC: 2 10 00 b 00:00:00 00 54:26:17 <-- Track #11 +*/ + +//Should do something like so: +// data = GetSessionInfo(cdCmd & 0xFF, cdPtr); + data = CDIntfGetSessionInfo(cdCmd & 0xFF, cdPtr); + if (data == 0xFF) // Failed... + { + data = 0x0400; + WriteLog("CDROM: Requested invalid session #%u (or failed to load TOC, or bad cdPtr value)\n", cdCmd & 0xFF); + } + else + { + data |= (0x20 | cdPtr++) << 8; + WriteLog("CDROM: Reading DS_DATA (session #%u TOC byte #%u): $%04X\n", cdCmd & 0xFF, cdPtr, data); + } + +/* bool isValidSession = ((cdCmd & 0xFF) == 0 ? true : false);//Hardcoded... !!! FIX !!! +//NOTE: This should return error condition if the requested session doesn't exist! ($0400?) + if (isValidSession) + { + cdPtr++; + switch (cdPtr) + { + case 1: + data = 0x2001; // Min track for this session? + break; + case 2: + data = 0x210A; // Max track for this session? + break; + case 3: + data = 0x2219; // Max lead-out time, absolute minutes + break; + case 4: + data = 0x2319; // Max lead-out time, absolute seconds + break; + case 5: + data = 0x2419; // Max lead-out time, absolute frames + break; + default: + data = 0xFFFF; + +//; +0 - unused, reserved (0) +//; +1 - unused, reserved (0) +//; +2 - minimum track number +//; +3 - maximum track number +//; +4 - total number of sessions +//; +5 - start of last lead-out time, absolute minutes +//; +6 - start of last lead-out time, absolute seconds +//; +7 - start of last lead-out time, absolute frames + + } + WriteLog("CDROM: Reading DS_DATA (session #%u TOC byte #%u): $%04X\n", cdCmd & 0xFF, cdPtr, data); + } + else + { + data = 0x0400; + WriteLog("CDROM: Requested invalid session #%u\n", cdCmd & 0xFF); + }*/ + } + // Seek to m, s, or f position + else if ((cdCmd & 0xFF00) == 0x1000 || (cdCmd & 0xFF00) == 0x1100 || (cdCmd & 0xFF00) == 0x1200) + data = 0x0100; // Success, though this doesn't take error handling into account. + // Ideally, we would also set the bits in BUTCH to let the processor know that + // this is ready to be read... !!! FIX !!! + else if ((cdCmd & 0xFF00) == 0x1400) // Read "full" session TOC + { +//Need to be a bit more tricky here, since it's reading the "session" TOC instead of the +//full TOC--so we need to check for the min/max tracks for each session here... [DONE] + + if (trackNum > maxTrack) + { + data = 0x400; +WriteLog("CDROM: Requested invalid track #%u for session #%u\n", trackNum, cdCmd & 0xFF); + } + else + { + if (cdPtr < 0x62) + data = (cdPtr << 8) | trackNum; + else if (cdPtr < 0x65) + data = (cdPtr << 8) | CDIntfGetTrackInfo(trackNum, (cdPtr - 2) & 0x0F); + +WriteLog("CDROM: Reading DS_DATA (session #%u, full TOC byte #%u): $%04X\n", cdCmd & 0xFF, (cdPtr+1) & 0x0F, data); + + cdPtr++; + if (cdPtr == 0x65) + cdPtr = 0x60, trackNum++; + } + + // Note that it seems to return track info in sets of 4 (or is it 5?) +/* +; +0 - track # (must be non-zero) +; +1 - absolute minutes (0..99), start of track +; +2 - absolute seconds (0..59), start of track +; +3 - absolute frames, (0..74), start of track +; +4 - session # (0..99) +; +5 - track duration minutes +; +6 - track duration seconds +; +7 - track duration frames +*/ + // Seems to be the following format: $60xx -> Track #xx + // $61xx -> min? (trk?) + // $62xx -> sec? (min?) + // $63xx -> frame? (sec?) + // $64xx -> ? (frame?) +/* cdPtr++; + switch (cdPtr) + { + case 1: + data = 0x6000 | trackNum; // Track # + break; + case 2: + data = 0x6100 | trackNum; // Track # (again?) + break; + case 3: + data = 0x6200 | minutes[trackNum]; // Minutes + break; + case 4: + data = 0x6300 | seconds[trackNum]; // Seconds + break; + case 5: + data = 0x6400 | frames[trackNum]; // Frames + trackNum++; + cdPtr = 0; + }//*/ + } + else if ((cdCmd & 0xFF00) == 0x1500) // Read CD mode + { + data = cdCmd | 0x0200; // ?? not sure ?? [Seems OK] + WriteLog("CDROM: Reading DS_DATA (mode), cdCmd=$%04X\n", cdCmd); + } + else if ((cdCmd & 0xFF00) == 0x1800) // Spin up session # + { + data = cdCmd; + WriteLog("CDROM: Reading DS_DATA (spin up session), cdCmd=$%04X\n", cdCmd); + } + else if ((cdCmd & 0xFF00) == 0x5400) // Read # of sessions + { + data = cdCmd | 0x00; // !!! Hardcoded !!! FIX !!! + WriteLog("CDROM: Reading DS_DATA (# of sessions), cdCmd=$%04X\n", cdCmd); + } + else if ((cdCmd & 0xFF00) == 0x7000) // Read oversampling + { +//NOTE: This setting will probably affect the # of DSP interrupts that need to happen. !!! FIX !!! + data = cdCmd; + WriteLog("CDROM: Reading DS_DATA (oversampling), cdCmd=$%04X\n", cdCmd); + } + else + { + data = 0x0400; + WriteLog("CDROM: Reading DS_DATA, unhandled cdCmd=$%04X\n", cdCmd); + } + } + else if (offset == DS_DATA && !haveCDGoodness) + data = 0x0400; // No CD interface present, so return error + else if (offset >= FIFO_DATA && offset <= FIFO_DATA + 3) + { + } + else if (offset >= FIFO_DATA + 4 && offset <= FIFO_DATA + 7) + { + } + else + data = GET16(cdRam, offset); + +//Returning $00000008 seems to cause it to use the starfield. Dunno why. +// It looks like it's getting the CD_mode this way... +//Temp, for testing... +//Very interesting...! Seems to control sumthin' or other... +/*if (offset == 0x2C || offset == 0x2E) + data = 0xFFFF;//*/ +/*if (offset == 0x2C) + data = 0x0000; +if (offset == 0x2E) + data = 0;//0x0008;//*/ + if (offset == UNKNOWN + 2) + data = CDROMBusRead(); + +#ifdef CDROM_LOG + if ((offset & 0xFF) < 11 * 4) + WriteLog("[%s] ", BReg[(offset & 0xFF) / 4]); + if (offset != UNKNOWN && offset != UNKNOWN + 2) + WriteLog("CDROM: %s reading word $%04X from $%08X [68K PC=$%08X]\n", whoName[who], data, offset, m68k_get_reg(NULL, M68K_REG_PC)); +#endif + return data; +} + +void CDROMWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0xFF; + cdRam[offset] = data; + +#ifdef CDROM_LOG + if ((offset & 0xFF) < 12 * 4) + WriteLog("[%s] ", BReg[(offset & 0xFF) / 4]); + WriteLog("CDROM: %s writing byte $%02X at $%08X [68K PC=$%08X]\n", whoName[who], data, offset, m68k_get_reg(NULL, M68K_REG_PC)); +#endif +} + +void CDROMWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0xFF; + SET16(cdRam, offset, data); + + // Command register +//Lesse what this does... Seems to work OK...! + if (offset == DS_DATA) + { + cdCmd = data; + if ((data & 0xFF00) == 0x0200) // Stop CD + { + cdPtr = 0; + WriteLog("CDROM: Stopping CD\n", data & 0xFF); + } + else if ((data & 0xFF00) == 0x0300) // Read session TOC (short? overview?) + { + cdPtr = 0; + WriteLog("CDROM: Reading TOC for session #%u\n", data & 0xFF); + } +//Not sure how these three acknowledge... + else if ((data & 0xFF00) == 0x1000) // Seek to minute position + { + min = data & 0x00FF; + } + else if ((data & 0xFF00) == 0x1100) // Seek to second position + { + sec = data & 0x00FF; + } + else if ((data & 0xFF00) == 0x1200) // Seek to frame position + { + frm = data & 0x00FF; + block = (((min * 60) + sec) * 75) + frm; + cdBufPtr = 2352; // Ensure that SSI read will do so immediately + WriteLog("CDROM: Seeking to %u:%02u:%02u [block #%u]\n", min, sec, frm, block); + } + else if ((data & 0xFF00) == 0x1400) // Read "full" TOC for session + { + cdPtr = 0x60, + minTrack = CDIntfGetSessionInfo(data & 0xFF, 0), + maxTrack = CDIntfGetSessionInfo(data & 0xFF, 1); + trackNum = minTrack; + WriteLog("CDROM: Reading \"full\" TOC for session #%u (min=%u, max=%u)\n", data & 0xFF, minTrack, maxTrack); + } + else if ((data & 0xFF00) == 0x1500) // Set CDROM mode + { + // Mode setting is as follows: bit 0 set -> single speed, bit 1 set -> double, + // bit 3 set -> multisession CD, bit 3 unset -> audio CD + WriteLog("CDROM: Setting mode $%02X\n", data & 0xFF); + } + else if ((data & 0xFF00) == 0x1800) // Spin up session # + { + WriteLog("CDROM: Spinning up session #%u\n", data & 0xFF); + } + else if ((data & 0xFF00) == 0x5400) // Read # of sessions + { + WriteLog("CDROM: Reading # of sessions\n", data & 0xFF); + } + else if ((data & 0xFF00) == 0x7000) // Set oversampling rate + { + // 1 = none, 2 = 2x, 3 = 4x, 4 = 8x + uint32_t rates[5] = { 0, 1, 2, 4, 8 }; + WriteLog("CDROM: Setting oversample rate to %uX\n", rates[(data & 0xFF)]); + } + else + WriteLog("CDROM: Unknown command $%04X\n", data); + }//*/ + + if (offset == UNKNOWN + 2) + CDROMBusWrite(data); + +#ifdef CDROM_LOG + if ((offset & 0xFF) < 11 * 4) + WriteLog("[%s] ", BReg[(offset & 0xFF) / 4]); + if (offset != UNKNOWN && offset != UNKNOWN + 2) + WriteLog("CDROM: %s writing word $%04X at $%08X [68K PC=$%08X]\n", whoName[who], data, offset, m68k_get_reg(NULL, M68K_REG_PC)); +#endif +} + +// +// State machine for sending/receiving data along a serial bus +// + +enum ButchState { ST_INIT, ST_RISING, ST_FALLING }; +static ButchState currentState = ST_INIT; +static uint16_t counter = 0; +static bool cmdTx = false; +static uint16_t busCmd; +static uint16_t rxData, txData; +static uint16_t rxDataBit; +static bool firstTime = false; + +static void CDROMBusWrite(uint16_t data) +{ +//This is kinda lame. What we should do is check for a 0->1 transition on either bits 0 or 1... +//!!! FIX !!! + +#ifdef CDROM_LOG + if (data & 0xFFF0) + WriteLog("CDROM: BusWrite write on unknown line: $%04X\n", data); +#endif + + switch (currentState) + { + case ST_INIT: + currentState = ST_RISING; + break; + case ST_RISING: + if (data & 0x0001) // Command coming + { + cmdTx = true; + counter = 0; + busCmd = 0; + } + else + { + if (cmdTx) + { + busCmd <<= 1; // Make room for next bit + busCmd |= (data & 0x04); // & put it in + counter++; + + if (counter == 9) + { + busCmd >>= 2; // Because we ORed bit 2, we need to shift right by 2 + cmdTx = false; + +//What it looks like: +//It seems that the $18x series reads from NVRAM while the +//$130, $14x, $100 series writes values to NVRAM... + if (busCmd == 0x180) + rxData = 0x0024;//1234; + else if (busCmd == 0x181) + rxData = 0x0004;//5678; + else if (busCmd == 0x182) + rxData = 0x0071;//9ABC; + else if (busCmd == 0x183) + rxData = 0xFF67;//DEF0; + else if (busCmd == 0x184) + rxData = 0xFFFF;//892F; + else if (busCmd == 0x185) + rxData = 0xFFFF;//8000; + else + rxData = 0x0001; +// rxData = 0x8349;//8000;//0F67; + + counter = 0; + firstTime = true; + txData = 0; +#ifdef CDROM_LOG + WriteLog("CDROM: *** BusWrite got command $%04X\n", busCmd); +#endif + } + } + else + { + txData = (txData << 1) | ((data & 0x04) >> 2); +//WriteLog("[%s]", data & 0x04 ? "1" : "0"); + + rxDataBit = (rxData & 0x8000) >> 12; + rxData <<= 1; + counter++; +#ifdef CDROM_LOG + if (counter == 16) + WriteLog("CDROM: *** BusWrite got extra command $%04X\n", txData); +#endif + } + } + + currentState = ST_FALLING; + break; + case ST_FALLING: + currentState = ST_INIT; + break; + } +} + +static uint16_t CDROMBusRead(void) +{ +// It seems the counter == 0 simply waits for a single bit acknowledge-- !!! FIX !!! +// Or does it? Hmm. It still "pumps" 16 bits through above, so how is this special? +// Seems to be because it sits and looks at it as if it will change. Dunno! +#ifdef CDROM_LOG + if ((counter & 0x0F) == 0) + { + if (counter == 0 && rxDataBit == 0) + { + if (firstTime) + { + firstTime = false; + WriteLog("0...\n"); + } + } + else + WriteLog("%s\n", rxDataBit ? "1" : "0"); + } + else + WriteLog("%s", rxDataBit ? "1" : "0"); +#endif + + return rxDataBit; +} + +// +// This simulates a read from BUTCH over the SSI to JERRY. Uses real reading! +// +//temp, until I can fix my CD image... Argh! +static uint8_t cdBuf2[2532 + 96], cdBuf3[2532 + 96]; +uint16_t GetWordFromButchSSI(uint32_t offset, uint32_t who/*= UNKNOWN*/) +{ + bool go = ((offset & 0x0F) == 0x0A || (offset & 0x0F) == 0x0E ? true : false); + + if (!go) + return 0x000; + +// The problem comes in here. Really, we should generate the IRQ once we've stuffed +// our values into the DAC L/RRXD ports... +// But then again, the whole IRQ system needs an overhaul in order to make it more +// cycle accurate WRT to the various CPUs. Right now, it's catch-as-catch-can, which +// means that IRQs get serviced on scanline boundaries instead of when they occur. + cdBufPtr += 2; + + if (cdBufPtr >= 2352) + { +WriteLog("CDROM: %s reading block #%u...\n", whoName[who], block); + //No error checking. !!! FIX !!! +//NOTE: We have to subtract out the 1st track start as well (in cdintf_foo.cpp)! +// CDIntfReadBlock(block - 150, cdBuf); + +//Crappy kludge for shitty shit. Lesse if it works! + CDIntfReadBlock(block - 150, cdBuf2); + CDIntfReadBlock(block - 149, cdBuf3); + for(int i=0; i<2352-4; i+=4) + { + cdBuf[i+0] = cdBuf2[i+4]; + cdBuf[i+1] = cdBuf2[i+5]; + cdBuf[i+2] = cdBuf2[i+2]; + cdBuf[i+3] = cdBuf2[i+3]; + } + cdBuf[2348] = cdBuf3[0]; + cdBuf[2349] = cdBuf3[1]; + cdBuf[2350] = cdBuf2[2350]; + cdBuf[2351] = cdBuf2[2351];//*/ + + block++, cdBufPtr = 0; + } + +/*extern bool doDSPDis; +if (block == 244968) + doDSPDis = true;//*/ + +WriteLog("[%04X:%01X]", GET16(cdBuf, cdBufPtr), offset & 0x0F); +if (cdBufPtr % 32 == 30) + WriteLog("\n"); + +// return GET16(cdBuf, cdBufPtr); +//This probably isn't endian safe... +// But then again... It seems that even though the data on the CD is organized as +// LL LH RL RH the way it expects to see the data is RH RL LH LL. +// D'oh! It doesn't matter *how* the data comes in, since it puts each sample into +// its own left or right side queue, i.e. it reads them 32 bits at a time and puts +// them into their L/R channel queues. It does seem, though, that it expects the +// right channel to be the upper 16 bits and the left to be the lower 16. + return (cdBuf[cdBufPtr + 1] << 8) | cdBuf[cdBufPtr + 0]; +} + +bool ButchIsReadyToSend(void) +{ +#ifdef LOG_CDROM_VERBOSE +WriteLog("Butch is%s ready to send...\n", cdRam[I2CNTRL + 3] & 0x02 ? "" : " not"); +#endif + return (cdRam[I2CNTRL + 3] & 0x02 ? true : false); +} + +// +// This simulates a read from BUTCH over the SSI to JERRY. Uses real reading! +// +void SetSSIWordsXmittedFromButch(void) +{ + +// The problem comes in here. Really, we should generate the IRQ once we've stuffed +// our values into the DAC L/RRXD ports... +// But then again, the whole IRQ system needs an overhaul in order to make it more +// cycle accurate WRT to the various CPUs. Right now, it's catch-as-catch-can, which +// means that IRQs get serviced on scanline boundaries instead of when they occur. + +// NOTE: The CD BIOS uses the following SMODE: +// DAC: M68K writing to SMODE. Bits: WSEN FALLING [68K PC=00050D8C] + cdBufPtr += 4; + + if (cdBufPtr >= 2352) + { +WriteLog("CDROM: Reading block #%u...\n", block); + //No error checking. !!! FIX !!! +//NOTE: We have to subtract out the 1st track start as well (in cdintf_foo.cpp)! +// CDIntfReadBlock(block - 150, cdBuf); + +//Crappy kludge for shitty shit. Lesse if it works! +//It does! That means my CD is WRONG! FUCK! + +// But, then again, according to Belboz at AA the two zeroes in front *ARE* necessary... +// So that means my CD is OK, just this method is wrong! +// It all depends on whether or not the interrupt occurs on the RISING or FALLING edge +// of the word strobe... !!! FIX !!! + +// When WS rises, left channel was done transmitting. When WS falls, right channel is done. +// CDIntfReadBlock(block - 150, cdBuf2); +// CDIntfReadBlock(block - 149, cdBuf3); + CDIntfReadBlock(block, cdBuf2); + CDIntfReadBlock(block + 1, cdBuf3); + memcpy(cdBuf, cdBuf2 + 2, 2350); + cdBuf[2350] = cdBuf3[0]; + cdBuf[2351] = cdBuf3[1];//*/ + + block++, cdBufPtr = 0; + +/*extern bool doDSPDis; +static int foo = 0; +if (block == 244968) +{ + foo++; +WriteLog("\n***** foo = %u, block = %u *****\n\n", foo, block); + if (foo == 2) + doDSPDis = true; +}//*/ + } + + +WriteLog("[%02X%02X %02X%02X]", cdBuf[cdBufPtr+1], cdBuf[cdBufPtr+0], cdBuf[cdBufPtr+3], cdBuf[cdBufPtr+2]); +if (cdBufPtr % 32 == 28) + WriteLog("\n"); + +//This probably isn't endian safe... +// But then again... It seems that even though the data on the CD is organized as +// LL LH RL RH the way it expects to see the data is RH RL LH LL. +// D'oh! It doesn't matter *how* the data comes in, since it puts each sample into +// its own left or right side queue, i.e. it reads them 32 bits at a time and puts +// them into their L/R channel queues. It does seem, though, that it expects the +// right channel to be the upper 16 bits and the left to be the lower 16. + +// This behavior is strictly a function of *where* the WS creates an IRQ. If the data +// is shifted by two zeroes (00 00 in front of the data file) then this *is* the +// correct behavior, since the left channel will be xmitted followed by the right + +// Now we have definitive proof: The MYST CD shows a word offset. So that means we have +// to figure out how to make that work here *without* having to load 2 sectors, offset, etc. +// !!! FIX !!! + lrxd = (cdBuf[cdBufPtr + 3] << 8) | cdBuf[cdBufPtr + 2], + rrxd = (cdBuf[cdBufPtr + 1] << 8) | cdBuf[cdBufPtr + 0]; +} + +/* +[18667] +TOC for MYST + +CDINTF: Disc summary + # of sessions: 2, # of tracks: 10 + Session info: + 1: min track= 1, max track= 1, lead out= 1:36:67 + 2: min track= 2, max track=10, lead out=55:24:71 + Track info: + 1: start= 0:02:00 + 2: start= 4:08:67 + 3: start= 4:16:65 + 4: start= 4:29:19 + 5: start=29:31:03 + 6: start=33:38:50 + 7: start=41:38:60 + 8: start=44:52:18 + 9: start=51:51:22 + 10: start=55:18:73 + +CDROM: Read sector 18517 (18667 - 150)... + +0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0018: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0048: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0078: 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00 +0798: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +07B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +07C8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00[54 41 49 52]54 41 +07E0: 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 +07F8: 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 49 52 54 41 +0810: 49 52 54 41 49 52[54 41 49 52]54 41 52 41 20 49 50 41 52 50 56 4F 44 45 +0828: 44 20 54 41 20 41 45 48 44 41 52 45 41 20 52 54 20 49[00 00 00 50]01 00 +0840: 80 83 FC 23 07 00 07 00 F0 00 0C 21 FC 23 07 00 07 00 F1 00 0C A1 FC 33 +0858: FF FF F0 00 4E 00 7C 2E 1F 00 FC FF 00 61 08 00 F9 4E 00 00 00 51 E7 48 +0870: 00 FE 39 30 F1 00 02 40 40 02 10 00 00 67 1C 00 79 42 01 00 8C D3 3C 34 +0888: 37 03 3C 30 81 05 3C 3C 0A 01 3C 38 F1 00 00 60 1A 00 FC 33 01 00 01 00 +08A0: 8C D3 3C 34 4B 03 3C 30 65 05 3C 3C 42 01 3C 38 1F 01 C0 33 01 00 88 D3 +08B8: C4 33 01 00 8A D3 00 32 41 E2 41 94 7C D4 04 00 7C 92 01 00 41 00 00 04 +08D0: C1 33 01 00 82 D3 C1 33 F0 00 3C 00 C2 33 01 00 80 D3 C2 33 F0 00 38 00 +08E8: C2 33 F0 00 3A 00 06 3A 44 9A C5 33 01 00 84 D3 44 DC C6 33 01 00 86 D3 +0900: F9 33 01 00 84 D3 F0 00 46 00 FC 33 FF FF F0 00 48 00 FC 23 00 00 00 00 +0918: F0 00 2A 00 FC 33 00 00 F0 00 58 00 DF 4C 7F 00 75 4E 00 00 00 00 00 00 + +Raw P-W subchannel data: + +00: 80 80 C0 80 80 80 80 C0 80 80 80 80 80 80 C0 80 +10: 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 +20: 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 C0 +30: 80 80 80 80 80 80 80 80 80 80 80 80 80 C0 80 80 +40: 80 80 80 80 C0 80 80 80 80 C0 C0 80 80 C0 C0 80 +50: C0 80 80 C0 C0 C0 80 80 C0 80 80 80 C0 80 80 80 + +P subchannel data: FF FF FF FF FF FF FF FF FF FF FF FF +Q subchannel data: 21 02 00 00 00 01 00 04 08 66 9C 88 + +Run address: $5000, Length: $18380 +*/ + + +/* +CD_read function from the CD BIOS: Note that it seems to direct the EXT1 interrupt +to the GPU--so that would mean *any* interrupt that BUTCH generates would be routed +to the GPU... + +read: + btst.l #31,d0 + bne.w .play + subq.l #4,a0 ; Make up for ISR pre-increment + move.l d0,-(sp) + move.l BUTCH,d0 + and.l #$ffff0000,d0 + move.l d0,BUTCH ; NO INTERRUPTS!!!!!!!!!!! + move.l (sp)+,d0 +; move.l #0,BUTCH + + move.w #$101,J_INT + + move.l d1,-(sp) + move.l I2CNTRL,d1 ;Read I2S Control Register + bclr #2,d1 ; Stop data + move.l d1,I2CNTRL + move.l (sp)+,d1 + + move.l PTRLOC,a2 + move.l a0,(a2)+ + move.l a1,(a2)+ + move.l #0,(a2)+ + + btst.b #7,INITTYPE + beq .not_bad + move.l PTRLOC,a0 + asl.l #5,d2 + + move.l d2,-(sp) + + or.l #$089a3c1a,d2 ; These instructions include the bclr + move.l d2,188(a0) + + move.l (sp)+,d2 + + swap d2 + or.l #$3c1a1838,d2 ; These instructions include the bclr + move.l d2,196(a0) + + move.l #16,(a2)+ + move.l d1,(a2) + +.not_bad: + + move.w DS_DATA,d1 ; Clear any pending DSARX states + move.l I2CNTRL,d1 ; Clear any pending errors + +; Drain the FIFO so that we don't get overloaded + +.dump: + move.l FIFO_DATA,d1 + move.l I2CNTRL,d1 + btst #4,d1 + bne.b .dump + +.butch_go: + move.l BUTCH,d1 + and.l #$FFFF0000,d1 + or.l #%000100001,d1 ;Enable DSARX interrupt + move.l d1,BUTCH +; move.l #%000100001,BUTCH ;Enable DSARX interrupt + +; Do a play @ + +.play: move.l d0,d1 ; mess with copy in d1 + lsr.l #8,d1 ; shift the byte over + lsr.w #8,d1 + or.w #$1000,d1 ; format it for goto + move.w d1,DS_DATA ; DSA tx + bsr.b DSA_tx + + move.l d0,d1 ; mess with copy in d1 + lsr.w #8,d1 + or.w #$1100,d1 ; format it for goto + move.w d1,DS_DATA ; DSA tx + bsr.b DSA_tx + + move.l d0,d1 ; mess with copy in d1 + and.w #$00FF,d1 ; mask for minutes + or.w #$1200,d1 ; format it for goto + move.w d1,DS_DATA ; DSA tx + bsr.b DSA_tx + + rts + + +**************************** +* Here's the GPU interrupt * +**************************** + +JERRY_ISR: + movei #G_FLAGS,r30 + load (r30),r29 ;read the flags + + movei #BUTCH,r24 + +make_ptr: + move pc,Ptrloc + movei #(make_ptr-PTRPOS),TEMP + sub TEMP,Ptrloc + +HERE: + move pc,r25 + movei #(EXIT_ISR-HERE),r27 + add r27,r25 + +; Is this a DSARX interrupt? + + load (r24),r27 ;check for DSARX int pending + btst #13,r27 + jr z,fifo_read ; This should ALWAYS fall thru the first time + +; Set the match bit, to allow data +; moveq #3,r26 ; enable FIFO only +; Don't just jam a value +; Clear the DSARX and set FIFO + bclr #5,r27 + bset #1,r27 + store r27,(r24) + addq #$10,r24 + load (r24),r27 + bset #2,r27 + store r27,(r24) ; Disable SUBCODE match + +; Now we clear the DSARX interrupt in Butch + + subq #12,r24 ; does what the above says + load (r24),r26 ;Clears DSA pending interrupt + addq #6,r24 + loadw (r24),r27 ; Read DSA response + btst #10,r27 ; Check for error + jr nz,error + or r26,r26 + jump (r25) +; nop + +fifo_read: +; Check for ERROR!!!!!!!!!!!!!!!!!!!!! + btst #14,r27 + jr z,noerror + bset #31,r27 +error: + addq #$10,r24 + load (r24),TEMP + or TEMP,TEMP + subq #$10,r24 + load (Ptrloc),TEMP + addq #8,Ptrloc + store TEMP,(Ptrloc) + subq #8,Ptrloc +noerror: + load (Ptrloc),Dataptr ;get pointer + +; Check to see if we should stop + addq #4,Ptrloc + load (Ptrloc),TEMP + subq #4,Ptrloc + cmp Dataptr,TEMP + jr pl,notend +; nop + bclr #0,r27 + store r27,(r24) + +notend: + movei #FIFO_DATA,CDdata + move CDdata,r25 + addq #4,CDdata +loptop: + load (CDdata),TEMP + load (r25),r30 + load (CDdata),r21 + load (r25),r22 + load (CDdata),r24 + load (r25),r20 + load (CDdata),r19 + load (r25),r18 + addq #4,Dataptr + store TEMP,(Dataptr) + addqt #4,Dataptr + store r30,(Dataptr) + addqt #4,Dataptr + store r21,(Dataptr) + addqt #4,Dataptr + store r22,(Dataptr) + addqt #4,Dataptr + store r24,(Dataptr) + addqt #4,Dataptr + store r20,(Dataptr) + addqt #4,Dataptr + store r19,(Dataptr) + addqt #4,Dataptr + store r18,(Dataptr) + + store Dataptr,(Ptrloc) + +exit_isr: + movei #J_INT,r24 ; Acknowledge in Jerry + moveq #1,TEMP + bset #8,TEMP + storew TEMP,(r24) + +.if FLAG +; Stack r18 + load (r31),r18 + addq #4,r31 + +; Stack r19 + load (r31),r19 + addq #4,r31 + +; Stack r20 + load (r31),r20 + addq #4,r31 + +; Stack r21 + load (r31),r21 + addq #4,r31 + +; Stack r22 + load (r31),r22 + addq #4,r31 + +; Stack r23 + load (r31),r23 + addq #4,r31 + +; Stack r26 + load (r31),r26 + addq #4,r31 + +; Stack r27 + load (r31),r27 + addq #4,r31 + +; Stack r24 + load (r31),r24 + addq #4,r31 + +; Stack r25 + load (r31),r25 + addq #4,r31 +.endif + + movei #G_FLAGS,r30 + +;r29 already has flags + bclr #3,r29 ;IMASK + bset #10,r29 ;Clear DSP int bit in TOM + + load (r31),r28 ;Load return address + + + addq #2,r28 ;Fix it up + addq #4,r31 + jump (r28) ;Return + store r29,(r30) ;Restore broken flags + + + align long + +stackbot: + ds.l 20 +STACK: + + +*/ + diff --git a/waterbox/virtualjaguar/src/cdrom.h b/waterbox/virtualjaguar/src/cdrom.h new file mode 100644 index 0000000000..c7d32b2716 --- /dev/null +++ b/waterbox/virtualjaguar/src/cdrom.h @@ -0,0 +1,26 @@ +// +// CDROM.H +// + +#ifndef __CDROM_H__ +#define __CDROM_H__ + +//#include "types.h" +#include "memory.h" + +void CDROMInit(void); +void CDROMReset(void); +void CDROMDone(void); + +void BUTCHExec(uint32_t cycles); + +uint8_t CDROMReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t CDROMReadWord(uint32_t offset, uint32_t who = UNKNOWN); +void CDROMWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void CDROMWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); + +bool ButchIsReadyToSend(void); +uint16_t GetWordFromButchSSI(uint32_t offset, uint32_t who = UNKNOWN); +void SetSSIWordsXmittedFromButch(void); + +#endif // __CDROM_H__ diff --git a/waterbox/virtualjaguar/src/crc32.cpp b/waterbox/virtualjaguar/src/crc32.cpp new file mode 100644 index 0000000000..1886971ef7 --- /dev/null +++ b/waterbox/virtualjaguar/src/crc32.cpp @@ -0,0 +1,63 @@ +// +// CRC support +// +// by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Cleanups by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +#include "crc32.h" + +static unsigned long crctable[256] = +{ + 0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL, 0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L, + 0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L, 0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L, + 0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL, 0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L, + 0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL, 0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L, + 0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L, 0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL, + 0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L, 0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L, + 0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L, 0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL, + 0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L, 0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL, + 0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL, 0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L, + 0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L, 0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L, + 0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL, 0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L, + 0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL, 0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L, + 0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L, 0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL, + 0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L, 0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L, + 0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L, 0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL, + 0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L, 0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL, + 0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL, 0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L, + 0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L, 0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L, + 0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL, 0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L, + 0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL, 0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L, + 0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L, 0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL, + 0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L, 0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L, + 0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L, 0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL, + 0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L, 0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL, + 0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL, 0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L, + 0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L, 0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L, + 0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL, 0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L, + 0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL, 0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L, + 0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L, 0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL, + 0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L, 0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L, + 0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L, 0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL, + 0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L, 0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL +}; + + +int crc32_calcCheckSum(unsigned char * data, unsigned int length) +{ + unsigned long crc = 0xFFFFFFFF; + + for(unsigned int i=0; i> 8); + + return crc ^ 0xFFFFFFFF; +} diff --git a/waterbox/virtualjaguar/src/crc32.h b/waterbox/virtualjaguar/src/crc32.h new file mode 100644 index 0000000000..ceddd03f00 --- /dev/null +++ b/waterbox/virtualjaguar/src/crc32.h @@ -0,0 +1,10 @@ +// +// CRC32.H +// + +#ifndef __CRC32_H__ +#define __CRC32_H__ + +int crc32_calcCheckSum(unsigned char * data, unsigned int length); + +#endif // __CRC32_H__ diff --git a/waterbox/virtualjaguar/src/cry2rgb.h b/waterbox/virtualjaguar/src/cry2rgb.h new file mode 100644 index 0000000000..636b45d487 --- /dev/null +++ b/waterbox/virtualjaguar/src/cry2rgb.h @@ -0,0 +1,71 @@ +// +// Red Color Values for CrY<->RGB Color Conversion +// +uint8_t redcv[16][16] = { + // 0 1 2 3 4 5 6 7 8 9 A B C D E F + // ---------------------------------------------------------------------- + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // 0 + { 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 19, 0}, // 1 + { 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 64, 43, 21, 0}, // 2 + { 102,102,102,102,102,102,102,102,102,102,102,95, 71, 47, 23, 0}, // 3 + { 135,135,135,135,135,135,135,135,135,135,130,104,78, 52, 26, 0}, // 4 + { 169,169,169,169,169,169,169,169,169,170,141,113,85, 56, 28, 0}, // 5 + { 203,203,203,203,203,203,203,203,203,183,153,122,91, 61, 30, 0}, // 6 + { 237,237,237,237,237,237,237,237,230,197,164,131,98, 65, 32, 0}, // 7 + { 255,255,255,255,255,255,255,255,247,214,181,148,15, 82, 49, 7}, // 8 + { 255,255,255,255,255,255,255,255,255,235,204,173,143,112,81, 51}, // 9 + { 255,255,255,255,255,255,255,255,255,255,227,198,170,141,113,85}, // A + { 255,255,255,255,255,255,255,255,255,255,249,223,197,171,145,119}, // B + { 255,255,255,255,255,255,255,255,255,255,255,248,224,200,177,153}, // C + { 255,255,255,255,255,255,255,255,255,255,255,255,252,230,208,187}, // D + { 255,255,255,255,255,255,255,255,255,255,255,255,255,255,240,221}, // E + { 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255} // F +}; + +// +// Green Color Values for CrY<->RGB Color Conversion +// +uint8_t greencv[16][16] = { + // 0 1 2 3 4 5 6 7 8 9 A B C D E F + // ---------------------------------------------------------------------- + { 0, 17, 34, 51,68, 85, 102,119,136,153,170,187,204,221,238,255}, // 0 + { 0, 19, 38, 57,77, 96, 115,134,154,173,192,211,231,250,255,255}, // 1 + { 0, 21, 43, 64,86, 107,129,150,172,193,215,236,255,255,255,255}, // 2 + { 0, 23, 47, 71,95, 119,142,166,190,214,238,255,255,255,255,255}, // 3 + { 0, 26, 52, 78,104,130,156,182,208,234,255,255,255,255,255,255}, // 4 + { 0, 28, 56, 85,113,141,170,198,226,255,255,255,255,255,255,255}, // 5 + { 0, 30, 61, 91,122,153,183,214,244,255,255,255,255,255,255,255}, // 6 + { 0, 32, 65, 98,131,164,197,230,255,255,255,255,255,255,255,255}, // 7 + { 0, 32, 65, 98,131,164,197,230,255,255,255,255,255,255,255,255}, // 8 + { 0, 30, 61, 91,122,153,183,214,244,255,255,255,255,255,255,255}, // 9 + { 0, 28, 56, 85,113,141,170,198,226,255,255,255,255,255,255,255}, // A + { 0, 26, 52, 78,104,130,156,182,208,234,255,255,255,255,255,255}, // B + { 0, 23, 47, 71,95, 119,142,166,190,214,238,255,255,255,255,255}, // C + { 0, 21, 43, 64,86, 107,129,150,172,193,215,236,255,255,255,255}, // D + { 0, 19, 38, 57,77, 96, 115,134,154,173,192,211,231,250,255,255}, // E + { 0, 17, 34, 51,68, 85, 102,119,136,153,170,187,204,221,238,255} // F +}; + +// +// Blue Color Values for CrY<->RGB Color Conversion +// +uint8_t bluecv[16][16] = { + // 0 1 2 3 4 5 6 7 8 9 A B C D E F + // ---------------------------------------------------------------------- + { 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255}, // 0 + { 255,255,255,255,255,255,255,255,255,255,255,255,255,255,240,221}, // 1 + { 255,255,255,255,255,255,255,255,255,255,255,255,252,230,208,187}, // 2 + { 255,255,255,255,255,255,255,255,255,255,255,248,224,200,177,153}, // 3 + { 255,255,255,255,255,255,255,255,255,255,249,223,197,171,145,119}, // 4 + { 255,255,255,255,255,255,255,255,255,255,227,198,170,141,113,85}, // 5 + { 255,255,255,255,255,255,255,255,255,235,204,173,143,112,81, 51}, // 6 + { 255,255,255,255,255,255,255,255,247,214,181,148,115,82, 49, 17}, // 7 + { 237,237,237,237,237,237,237,237,230,197,164,131,98, 65, 32, 0}, // 8 + { 203,203,203,203,203,203,203,203,203,183,153,122,91, 61, 30, 0}, // 9 + { 169,169,169,169,169,169,169,169,169,170,141,113,85, 56, 28, 0}, // A + { 135,135,135,135,135,135,135,135,135,135,130,104,78, 52, 26, 0}, // B + { 102,102,102,102,102,102,102,102,102,102,102,95, 71, 47, 23, 0}, // C + { 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 64, 43, 21, 0}, // D + { 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 34, 19, 0}, // E + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} // F +}; diff --git a/waterbox/virtualjaguar/src/dac.cpp b/waterbox/virtualjaguar/src/dac.cpp new file mode 100644 index 0000000000..78bd4f8059 --- /dev/null +++ b/waterbox/virtualjaguar/src/dac.cpp @@ -0,0 +1,301 @@ +// +// DAC (really, Synchronous Serial Interface) Handler +// +// Originally by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Rewritten by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 04/30/2012 Changed SDL audio handler to run JERRY +// + +// Need to set up defaults that the BIOS sets for the SSI here in DACInit()... !!! FIX !!! +// or something like that... Seems like it already does, but it doesn't seem to +// work correctly...! Perhaps just need to set up SSI stuff so BUTCH doesn't get +// confused... + +// After testing on a real Jaguar, it seems clear that the I2S interrupt drives +// the audio subsystem. So while you can drive the audio at a *slower* rate than +// set by SCLK, you can't drive it any *faster*. Also note, that if the I2S +// interrupt is not enabled/running on the DSP, then there is no audio. Also, +// audio can be muted by clearing bit 8 of JOYSTICK (JOY1). +// +// Approach: We can run the DSP in the host system's audio IRQ, by running the +// DSP for the alloted time (depending on the host buffer size & sample rate) +// by simply reading the L/R_I2S (L/RTXD) registers at regular intervals. We +// would also have to time the I2S/TIMER0/TIMER1 interrupts in the DSP as well. +// This way, we can run the host audio IRQ at, say, 48 KHz and not have to care +// so much about SCLK and running a separate buffer and all the attendant +// garbage that comes with that awful approach. +// +// There would still be potential gotchas, as the SCLK can theoretically drive +// the I2S at 26590906 / 2 (for SCLK == 0) = 13.3 MHz which corresponds to an +// audio rate 416 KHz (dividing the I2S rate by 32, for 16-bit stereo). It +// seems doubtful that anything useful could come of such a high rate, and we +// can probably safely ignore any such ridiculously high audio rates. It won't +// sound the same as on a real Jaguar, but who cares? :-) + +#include "dac.h" + +#include "cdrom.h" +#include "dsp.h" +#include "event.h" +#include "jerry.h" +#include "jaguar.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" +#include "settings.h" + + +//#define DEBUG_DAC + +#define BUFFER_SIZE 0x10000 // Make the DAC buffers 64K x 16 bits +#define DAC_AUDIO_RATE 48000 // Set the audio rate to 48 KHz + +// Jaguar memory locations + +#define LTXD 0xF1A148 +#define RTXD 0xF1A14C +#define LRXD 0xF1A148 +#define RRXD 0xF1A14C +#define SCLK 0xF1A150 +#define SMODE 0xF1A154 + +// Global variables + +// These are defined in memory.h/cpp +//uint16_t lrxd, rrxd; // I2S ports (into Jaguar) + +// Local variables + +//static uint8_t SCLKFrequencyDivider = 19; // Default is roughly 22 KHz (20774 Hz in NTSC mode) +// /*static*/ uint16_t serialMode = 0; + +// Private function prototypes + +void DSPSampleCallback(void); + + +// +// Initialize the SDL sound system +// +void DACInit(void) +{ + ltxd = lrxd = 0; + sclk = 19; // Default is roughly 22 KHz + + uint32_t riscClockRate = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL); + uint32_t cyclesPerSample = riscClockRate / DAC_AUDIO_RATE; + WriteLog("DAC: RISC clock = %u, cyclesPerSample = %u\n", riscClockRate, cyclesPerSample); +} + + +// +// Reset the sound buffer FIFOs +// +void DACReset(void) +{ +// LeftFIFOHeadPtr = LeftFIFOTailPtr = 0, RightFIFOHeadPtr = RightFIFOTailPtr = 1; + ltxd = lrxd = 0; +} + + +// +// Pause/unpause the SDL audio thread +// +void DACPauseAudioThread(bool state/*= true*/) +{ +} + + +// +// Close down the SDL sound subsystem +// +void DACDone(void) +{ + WriteLog("DAC: Done.\n"); +} + + +// Approach: Run the DSP for however many cycles needed to correspond to whatever sample rate +// we've set the audio to run at. So, e.g., if we run it at 48 KHz, then we would run the DSP +// for however much time it takes to fill the buffer. So with a 2K buffer, this would correspond +// to running the DSP for 0.042666... seconds. At 26590906 Hz, this would correspond to +// running the DSP for 1134545 cycles. You would then sample the L/RTXD registers every +// 1134545 / 2048 = 554 cycles to fill the buffer. You would also have to manage interrupt +// timing as well (generating them at the proper times), but that shouldn't be too difficult... +// If the DSP isn't running, then fill the buffer with L/RTXD and exit. + +// +// SDL callback routine to fill audio buffer +// +// Note: The samples are packed in the buffer in 16 bit left/16 bit right pairs. +// Also, length is the length of the buffer in BYTES +// +static uint16_t * sampleBuffer; +static int bufferIndex = 0; +static int numberOfSamples = 0; +static bool bufferDone = false; +void SoundCallback(uint16_t * buffer, int length) +{ + // 1st, check to see if the DSP is running. If not, fill the buffer with L/RXTD and exit. + + if (!DSPIsRunning()) + { + for(int i=0; i<(length/2); i+=2) + { + buffer[i + 0] = ltxd; + buffer[i + 1] = rtxd; + } + + return; + } + + // The length of time we're dealing with here is 1/48000 s, so we multiply this + // by the number of cycles per second to get the number of cycles for one sample. +// uint32_t riscClockRate = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL); +// uint32_t cyclesPerSample = riscClockRate / DAC_AUDIO_RATE; + // This is the length of time +// timePerSample = (1000000.0 / (double)riscClockRate) * (); + + // Now, run the DSP for that length of time for each sample we need to make + + bufferIndex = 0; + sampleBuffer = buffer; +// If length is the length of the sample buffer in BYTES, then shouldn't the # of +// samples be / 4? No, because we bump the sample count by 2, so this is OK. + numberOfSamples = length / 2; + bufferDone = false; + + SetCallbackTime(DSPSampleCallback, 1000000.0 / (double)DAC_AUDIO_RATE, EVENT_JERRY); + + // These timings are tied to NTSC, need to fix that in event.cpp/h! [FIXED] + do + { + double timeToNextEvent = GetTimeToNextEvent(EVENT_JERRY); + + if (vjs.DSPEnabled) + { + if (vjs.usePipelinedDSP) + DSPExecP2(USEC_TO_RISC_CYCLES(timeToNextEvent)); + else + DSPExec(USEC_TO_RISC_CYCLES(timeToNextEvent)); + } + + HandleNextEvent(EVENT_JERRY); + } + while (!bufferDone); +} + + +void DSPSampleCallback(void) +{ + sampleBuffer[bufferIndex + 0] = ltxd; + sampleBuffer[bufferIndex + 1] = rtxd; + bufferIndex += 2; + + if (bufferIndex == numberOfSamples) + { + bufferDone = true; + return; + } + + SetCallbackTime(DSPSampleCallback, 1000000.0 / (double)DAC_AUDIO_RATE, EVENT_JERRY); +} + + +#if 0 +// +// Calculate the frequency of SCLK * 32 using the divider +// +int GetCalculatedFrequency(void) +{ + int systemClockFrequency = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL); + + // We divide by 32 here in order to find the frequency of 32 SCLKs in a row (transferring + // 16 bits of left data + 16 bits of right data = 32 bits, 1 SCLK = 1 bit transferred). + return systemClockFrequency / (32 * (2 * (SCLKFrequencyDivider + 1))); +} +#endif + + +// +// LTXD/RTXD/SCLK/SMODE ($F1A148/4C/50/54) +// +void DACWriteByte(uint32_t offset, uint8_t data, uint32_t who/*= UNKNOWN*/) +{ + WriteLog("DAC: %s writing BYTE %02X at %08X\n", whoName[who], data, offset); + if (offset == SCLK + 3) + DACWriteWord(offset - 3, (uint16_t)data); +} + + +void DACWriteWord(uint32_t offset, uint16_t data, uint32_t who/*= UNKNOWN*/) +{ + if (offset == LTXD + 2) + { + ltxd = data; + } + else if (offset == RTXD + 2) + { + rtxd = data; + } + else if (offset == SCLK + 2) // Sample rate + { + WriteLog("DAC: Writing %u to SCLK (by %s)...\n", data, whoName[who]); + + sclk = data & 0xFF; + JERRYI2SInterruptTimer = -1; + RemoveCallback(JERRYI2SCallback); + JERRYI2SCallback(); + } + else if (offset == SMODE + 2) + { +// serialMode = data; + smode = data; + WriteLog("DAC: %s writing to SMODE. Bits: %s%s%s%s%s%s [68K PC=%08X]\n", whoName[who], + (data & 0x01 ? "INTERNAL " : ""), (data & 0x02 ? "MODE " : ""), + (data & 0x04 ? "WSEN " : ""), (data & 0x08 ? "RISING " : ""), + (data & 0x10 ? "FALLING " : ""), (data & 0x20 ? "EVERYWORD" : ""), + m68k_get_reg(NULL, M68K_REG_PC)); + } +} + + +// +// LRXD/RRXD/SSTAT ($F1A148/4C/50) +// +uint8_t DACReadByte(uint32_t offset, uint32_t who/*= UNKNOWN*/) +{ +// WriteLog("DAC: %s reading byte from %08X\n", whoName[who], offset); + return 0xFF; +} + + +//static uint16_t fakeWord = 0; +uint16_t DACReadWord(uint32_t offset, uint32_t who/*= UNKNOWN*/) +{ +// WriteLog("DAC: %s reading word from %08X\n", whoName[who], offset); +// return 0xFFFF; +// WriteLog("DAC: %s reading WORD %04X from %08X\n", whoName[who], fakeWord, offset); +// return fakeWord++; +//NOTE: This only works if a bunch of things are set in BUTCH which we currently don't +// check for. !!! FIX !!! +// Partially fixed: We check for I2SCNTRL in the JERRY I2S routine... +// return GetWordFromButchSSI(offset, who); + if (offset == LRXD || offset == RRXD) + return 0x0000; + else if (offset == LRXD + 2) + return lrxd; + else if (offset == RRXD + 2) + return rrxd; + + return 0xFFFF; // May need SSTAT as well... (but may be a Jaguar II only feature) +} + diff --git a/waterbox/virtualjaguar/src/dac.h b/waterbox/virtualjaguar/src/dac.h new file mode 100644 index 0000000000..52a9324dab --- /dev/null +++ b/waterbox/virtualjaguar/src/dac.h @@ -0,0 +1,33 @@ +// +// DAC.H: Header file +// + +#ifndef __DAC_H__ +#define __DAC_H__ + +#include "memory.h" + +void DACInit(void); +void DACReset(void); +void DACPauseAudioThread(bool state = true); +void DACDone(void); +//int GetCalculatedFrequency(void); + +// DAC memory access + +void DACWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void DACWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); +uint8_t DACReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t DACReadWord(uint32_t offset, uint32_t who = UNKNOWN); + + +// DAC defines + +#define SMODE_INTERNAL 0x01 +#define SMODE_MODE 0x02 +#define SMODE_WSEN 0x04 +#define SMODE_RISING 0x08 +#define SMODE_FALLING 0x10 +#define SMODE_EVERYWORD 0x20 + +#endif // __DAC_H__ diff --git a/waterbox/virtualjaguar/src/dsp.cpp b/waterbox/virtualjaguar/src/dsp.cpp new file mode 100644 index 0000000000..7ce82eef79 --- /dev/null +++ b/waterbox/virtualjaguar/src/dsp.cpp @@ -0,0 +1,4799 @@ +// +// DSP core +// +// Originally by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Extensive cleanups/rewrites by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 11/26/2011 Added fixes for LOAD/STORE alignment issues +// + +#include "dsp.h" + +#include +#include "dac.h" +#include "gpu.h" +#include "jagdasm.h" +#include "jaguar.h" +#include "jerry.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" + + +// Seems alignment in loads & stores was off... +#define DSP_CORRECT_ALIGNMENT +//#define DSP_CORRECT_ALIGNMENT_STORE + +//#define DSP_DEBUG +//#define DSP_DEBUG_IRQ +//#define DSP_DEBUG_PL2 +//#define DSP_DEBUG_STALL +//#define DSP_DEBUG_CC +#define NEW_SCOREBOARD + +// Disassembly definitions + +#if 0 +#define DSP_DIS_ABS +#define DSP_DIS_ADD +#define DSP_DIS_ADDC +#define DSP_DIS_ADDQ +#define DSP_DIS_ADDQMOD +#define DSP_DIS_ADDQT +#define DSP_DIS_AND +#define DSP_DIS_BCLR +#define DSP_DIS_BSET +#define DSP_DIS_BTST +#define DSP_DIS_CMP +#define DSP_DIS_CMPQ +#define DSP_DIS_IMACN +#define DSP_DIS_IMULT +#define DSP_DIS_IMULTN +#define DSP_DIS_ILLEGAL +#define DSP_DIS_JR +#define DSP_DIS_JUMP +#define DSP_DIS_LOAD +#define DSP_DIS_LOAD14I +#define DSP_DIS_LOAD14R +#define DSP_DIS_LOAD15I +#define DSP_DIS_LOAD15R +#define DSP_DIS_LOADB +#define DSP_DIS_LOADW +#define DSP_DIS_MOVE +#define DSP_DIS_MOVEI +#define DSP_DIS_MOVEQ +#define DSP_DIS_MOVEFA +#define DSP_DIS_MOVEPC // Pipeline only! +#define DSP_DIS_MOVETA +#define DSP_DIS_MULT +#define DSP_DIS_NEG +#define DSP_DIS_NOP +#define DSP_DIS_NOT +#define DSP_DIS_OR +#define DSP_DIS_RESMAC +#define DSP_DIS_ROR +#define DSP_DIS_RORQ +#define DSP_DIS_SHARQ +#define DSP_DIS_SHLQ +#define DSP_DIS_SHRQ +#define DSP_DIS_STORE +#define DSP_DIS_STORE14I +#define DSP_DIS_STORE15I +#define DSP_DIS_STOREB +#define DSP_DIS_STOREW +#define DSP_DIS_SUB +#define DSP_DIS_SUBC +#define DSP_DIS_SUBQ +#define DSP_DIS_SUBQT +#define DSP_DIS_XOR +//*/ +bool doDSPDis = false; +//bool doDSPDis = true; +#endif +bool doDSPDis = false; +//#define DSP_DIS_JR +//#define DSP_DIS_JUMP + +/* +No dis yet: ++ subqt 4560 ++ mult 1472 ++ imultn 395024 ++ resmac 395024 ++ imacn 395024 ++ addqmod 93328 + +dsp opcodes use: ++ add 1672497 ++ addq 4366576 ++ addqt 44405640 ++ sub 94833 ++ subq 111769 ++ and 47416 ++ btst 94521 ++ bset 2277826 ++ bclr 3223372 ++ mult 47104 ++ imult 237080 ++ shlq 365464 ++ shrq 141624 ++ sharq 318368 ++ cmp 45175078 ++ move 2238994 ++ moveq 335305 ++ moveta 19 ++ movefa 47406440 ++ movei 1920664 ++ loadb 94832 ++ load 4031281 ++ load_r15_indexed 284500 ++ store 2161732 ++ store_r15_indexed 47416 ++ jump 3872424 ++ jr 46386967 ++ nop 3300029 ++ load_r14_ri 1229448 +*/ + +// Pipeline structures + +const bool affectsScoreboard[64] = +{ + true, true, true, true, + true, true, true, true, + true, true, true, true, + true, false, true, true, + + true, true, false, true, + false, true, true, true, + true, true, true, true, + true, true, false, false, + + true, true, true, true, + false, true, true, true, + true, true, true, true, + true, false, false, false, + + true, false, false, true, + false, false, true, true, + true, false, true, true, + false, false, false, true +}; + +struct PipelineStage +{ + uint16_t instruction; + uint8_t opcode, operand1, operand2; + uint32_t reg1, reg2, areg1, areg2; + uint32_t result; + uint8_t writebackRegister; + // General memory store... + uint32_t address; + uint32_t value; + uint8_t type; +}; + +#define TYPE_BYTE 0 +#define TYPE_WORD 1 +#define TYPE_DWORD 2 +#define PIPELINE_STALL 64 // Set to # of opcodes + 1 +#ifndef NEW_SCOREBOARD +bool scoreboard[32]; +#else +uint8_t scoreboard[32]; +#endif +uint8_t plPtrFetch, plPtrRead, plPtrExec, plPtrWrite; +PipelineStage pipeline[4]; +bool IMASKCleared = false; + +// DSP flags (old--have to get rid of this crap) + +#define CINT0FLAG 0x00200 +#define CINT1FLAG 0x00400 +#define CINT2FLAG 0x00800 +#define CINT3FLAG 0x01000 +#define CINT4FLAG 0x02000 +#define CINT04FLAGS (CINT0FLAG | CINT1FLAG | CINT2FLAG | CINT3FLAG | CINT4FLAG) +#define CINT5FLAG 0x20000 /* DSP only */ + +// DSP_FLAGS bits + +#define ZERO_FLAG 0x00001 +#define CARRY_FLAG 0x00002 +#define NEGA_FLAG 0x00004 +#define IMASK 0x00008 +#define INT_ENA0 0x00010 +#define INT_ENA1 0x00020 +#define INT_ENA2 0x00040 +#define INT_ENA3 0x00080 +#define INT_ENA4 0x00100 +#define INT_CLR0 0x00200 +#define INT_CLR1 0x00400 +#define INT_CLR2 0x00800 +#define INT_CLR3 0x01000 +#define INT_CLR4 0x02000 +#define REGPAGE 0x04000 +#define DMAEN 0x08000 +#define INT_ENA5 0x10000 +#define INT_CLR5 0x20000 + +// DSP_CTRL bits + +#define DSPGO 0x00001 +#define CPUINT 0x00002 +#define DSPINT0 0x00004 +#define SINGLE_STEP 0x00008 +#define SINGLE_GO 0x00010 +// Bit 5 is unused! +#define INT_LAT0 0x00040 +#define INT_LAT1 0x00080 +#define INT_LAT2 0x00100 +#define INT_LAT3 0x00200 +#define INT_LAT4 0x00400 +#define BUS_HOG 0x00800 +#define VERSION 0x0F000 +#define INT_LAT5 0x10000 + +extern uint32_t jaguar_mainRom_crc32; + +// Is opcode 62 *really* a NOP? Seems like it... +static void dsp_opcode_abs(void); +static void dsp_opcode_add(void); +static void dsp_opcode_addc(void); +static void dsp_opcode_addq(void); +static void dsp_opcode_addqmod(void); +static void dsp_opcode_addqt(void); +static void dsp_opcode_and(void); +static void dsp_opcode_bclr(void); +static void dsp_opcode_bset(void); +static void dsp_opcode_btst(void); +static void dsp_opcode_cmp(void); +static void dsp_opcode_cmpq(void); +static void dsp_opcode_div(void); +static void dsp_opcode_imacn(void); +static void dsp_opcode_imult(void); +static void dsp_opcode_imultn(void); +static void dsp_opcode_jr(void); +static void dsp_opcode_jump(void); +static void dsp_opcode_load(void); +static void dsp_opcode_loadb(void); +static void dsp_opcode_loadw(void); +static void dsp_opcode_load_r14_indexed(void); +static void dsp_opcode_load_r14_ri(void); +static void dsp_opcode_load_r15_indexed(void); +static void dsp_opcode_load_r15_ri(void); +static void dsp_opcode_mirror(void); +static void dsp_opcode_mmult(void); +static void dsp_opcode_move(void); +static void dsp_opcode_movei(void); +static void dsp_opcode_movefa(void); +static void dsp_opcode_move_pc(void); +static void dsp_opcode_moveq(void); +static void dsp_opcode_moveta(void); +static void dsp_opcode_mtoi(void); +static void dsp_opcode_mult(void); +static void dsp_opcode_neg(void); +static void dsp_opcode_nop(void); +static void dsp_opcode_normi(void); +static void dsp_opcode_not(void); +static void dsp_opcode_or(void); +static void dsp_opcode_resmac(void); +static void dsp_opcode_ror(void); +static void dsp_opcode_rorq(void); +static void dsp_opcode_xor(void); +static void dsp_opcode_sat16s(void); +static void dsp_opcode_sat32s(void); +static void dsp_opcode_sh(void); +static void dsp_opcode_sha(void); +static void dsp_opcode_sharq(void); +static void dsp_opcode_shlq(void); +static void dsp_opcode_shrq(void); +static void dsp_opcode_store(void); +static void dsp_opcode_storeb(void); +static void dsp_opcode_storew(void); +static void dsp_opcode_store_r14_indexed(void); +static void dsp_opcode_store_r14_ri(void); +static void dsp_opcode_store_r15_indexed(void); +static void dsp_opcode_store_r15_ri(void); +static void dsp_opcode_sub(void); +static void dsp_opcode_subc(void); +static void dsp_opcode_subq(void); +static void dsp_opcode_subqmod(void); +static void dsp_opcode_subqt(void); +static void dsp_opcode_illegal(void); + +/*uint8_t dsp_opcode_cycles[64] = +{ + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 1, 3, 1, 18, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 2, 2, 2, 2, 3, 4, + 5, 4, 5, 6, 6, 1, 1, 1, + 1, 2, 2, 2, 1, 1, 9, 3, + 3, 1, 6, 6, 2, 2, 3, 3 +};//*/ +//Here's a QnD kludge... +//This is wrong, wrong, WRONG, but it seems to work for the time being... +//(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!) +//What's needed here is a way to take pipeline effects into account (including pipeline stalls!)... +// Yup, without cheating like this, the sound in things like Rayman, FACTS, & +// Tripper Getem get starved for time and sounds like crap. So we have to figure +// out how to fix that. :-/ +uint8_t dsp_opcode_cycles[64] = +{ + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 9, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 2, + 2, 2, 2, 3, 3, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 4, 1, + 1, 1, 3, 3, 1, 1, 1, 1 +};//*/ + +void (* dsp_opcode[64])() = +{ + dsp_opcode_add, dsp_opcode_addc, dsp_opcode_addq, dsp_opcode_addqt, + dsp_opcode_sub, dsp_opcode_subc, dsp_opcode_subq, dsp_opcode_subqt, + dsp_opcode_neg, dsp_opcode_and, dsp_opcode_or, dsp_opcode_xor, + dsp_opcode_not, dsp_opcode_btst, dsp_opcode_bset, dsp_opcode_bclr, + dsp_opcode_mult, dsp_opcode_imult, dsp_opcode_imultn, dsp_opcode_resmac, + dsp_opcode_imacn, dsp_opcode_div, dsp_opcode_abs, dsp_opcode_sh, + dsp_opcode_shlq, dsp_opcode_shrq, dsp_opcode_sha, dsp_opcode_sharq, + dsp_opcode_ror, dsp_opcode_rorq, dsp_opcode_cmp, dsp_opcode_cmpq, + dsp_opcode_subqmod, dsp_opcode_sat16s, dsp_opcode_move, dsp_opcode_moveq, + dsp_opcode_moveta, dsp_opcode_movefa, dsp_opcode_movei, dsp_opcode_loadb, + dsp_opcode_loadw, dsp_opcode_load, dsp_opcode_sat32s, dsp_opcode_load_r14_indexed, + dsp_opcode_load_r15_indexed, dsp_opcode_storeb, dsp_opcode_storew, dsp_opcode_store, + dsp_opcode_mirror, dsp_opcode_store_r14_indexed, dsp_opcode_store_r15_indexed, dsp_opcode_move_pc, + dsp_opcode_jump, dsp_opcode_jr, dsp_opcode_mmult, dsp_opcode_mtoi, + dsp_opcode_normi, dsp_opcode_nop, dsp_opcode_load_r14_ri, dsp_opcode_load_r15_ri, + dsp_opcode_store_r14_ri, dsp_opcode_store_r15_ri, dsp_opcode_illegal, dsp_opcode_addqmod, +}; + +uint32_t dsp_opcode_use[65]; + +const char * dsp_opcode_str[65]= +{ + "add", "addc", "addq", "addqt", + "sub", "subc", "subq", "subqt", + "neg", "and", "or", "xor", + "not", "btst", "bset", "bclr", + "mult", "imult", "imultn", "resmac", + "imacn", "div", "abs", "sh", + "shlq", "shrq", "sha", "sharq", + "ror", "rorq", "cmp", "cmpq", + "subqmod", "sat16s", "move", "moveq", + "moveta", "movefa", "movei", "loadb", + "loadw", "load", "sat32s", "load_r14_indexed", + "load_r15_indexed", "storeb", "storew", "store", + "mirror", "store_r14_indexed","store_r15_indexed","move_pc", + "jump", "jr", "mmult", "mtoi", + "normi", "nop", "load_r14_ri", "load_r15_ri", + "store_r14_ri", "store_r15_ri", "illegal", "addqmod", + "STALL" +}; + +uint32_t dsp_pc; +static uint64_t dsp_acc; // 40 bit register, NOT 32! +static uint32_t dsp_remain; +static uint32_t dsp_modulo; +static uint32_t dsp_flags; +static uint32_t dsp_matrix_control; +static uint32_t dsp_pointer_to_matrix; +static uint32_t dsp_data_organization; +uint32_t dsp_control; +static uint32_t dsp_div_control; +static uint8_t dsp_flag_z, dsp_flag_n, dsp_flag_c; +static uint32_t * dsp_reg = NULL, * dsp_alternate_reg = NULL; +uint32_t dsp_reg_bank_0[32], dsp_reg_bank_1[32]; + +static uint32_t dsp_opcode_first_parameter; +static uint32_t dsp_opcode_second_parameter; + +#define DSP_RUNNING (dsp_control & 0x01) + +#define RM dsp_reg[dsp_opcode_first_parameter] +#define RN dsp_reg[dsp_opcode_second_parameter] +#define ALTERNATE_RM dsp_alternate_reg[dsp_opcode_first_parameter] +#define ALTERNATE_RN dsp_alternate_reg[dsp_opcode_second_parameter] +#define IMM_1 dsp_opcode_first_parameter +#define IMM_2 dsp_opcode_second_parameter + +#define CLR_Z (dsp_flag_z = 0) +#define CLR_ZN (dsp_flag_z = dsp_flag_n = 0) +#define CLR_ZNC (dsp_flag_z = dsp_flag_n = dsp_flag_c = 0) +#define SET_Z(r) (dsp_flag_z = ((r) == 0)) +#define SET_N(r) (dsp_flag_n = (((uint32_t)(r) >> 31) & 0x01)) +#define SET_C_ADD(a,b) (dsp_flag_c = ((uint32_t)(b) > (uint32_t)(~(a)))) +#define SET_C_SUB(a,b) (dsp_flag_c = ((uint32_t)(b) > (uint32_t)(a))) +#define SET_ZN(r) SET_N(r); SET_Z(r) +#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) +#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) + +uint32_t dsp_convert_zero[32] = { + 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; + +uint8_t dsp_branch_condition_table[32 * 8]; +static uint16_t mirror_table[65536]; +static uint8_t dsp_ram_8[0x2000]; + +#define BRANCH_CONDITION(x) dsp_branch_condition_table[(x) + ((jaguar_flags & 7) << 5)] + +static uint32_t dsp_in_exec = 0; +static uint32_t dsp_releaseTimeSlice_flag = 0; + +FILE * dsp_fp; + +#ifdef DSP_DEBUG_CC +// Comparison core vars (used only for core comparison! :-) +static uint64_t count = 0; +static uint8_t ram1[0x2000], ram2[0x2000]; +static uint32_t regs1[64], regs2[64]; +static uint32_t ctrl1[14], ctrl2[14]; +#endif + +// Private function prototypes + +void DSPDumpRegisters(void); +void DSPDumpDisassembly(void); +void FlushDSPPipeline(void); + + +void dsp_reset_stats(void) +{ + for(int i=0; i<65; i++) + dsp_opcode_use[i] = 0; +} + + +void DSPReleaseTimeslice(void) +{ +//This does absolutely nothing!!! !!! FIX !!! + dsp_releaseTimeSlice_flag = 1; +} + + +void dsp_build_branch_condition_table(void) +{ + // Fill in the mirror table + for(int i=0; i<65536; i++) + { + mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) + | ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) + | ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) + | ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) + | ((i << 1) & 0x0100) | ((i << 3) & 0x0200) + | ((i << 5) & 0x0400) | ((i << 7) & 0x0800) + | ((i << 9) & 0x1000) | ((i << 11) & 0x2000) + | ((i << 13) & 0x4000) | ((i << 15) & 0x8000); + } + + // Fill in the condition table + for(int i=0; i<8; i++) + { + for(int j=0; j<32; j++) + { + int result = 1; + + if ((j & 1) && (i & ZERO_FLAG)) + result = 0; + + if ((j & 2) && (!(i & ZERO_FLAG))) + result = 0; + + if ((j & 4) && (i & (CARRY_FLAG << (j >> 4)))) + result = 0; + + if ((j & 8) && (!(i & (CARRY_FLAG << (j >> 4))))) + result = 0; + + dsp_branch_condition_table[i * 32 + j] = result; + } + } +} + + +uint8_t DSPReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: ReadByte--Attempt to read from DSP register file by %s!\n", whoName[who]); +// battlemorph +// if ((offset==0xF1CFE0)||(offset==0xF1CFE2)) +// return(0xffff); + // mutant penguin +/* if ((jaguar_mainRom_crc32==0xbfd751a4)||(jaguar_mainRom_crc32==0x053efaf9)) + { + if (offset==0xF1CFE0) + return(0xff); + }*/ + if (offset >= DSP_WORK_RAM_BASE && offset <= (DSP_WORK_RAM_BASE + 0x1FFF)) + return dsp_ram_8[offset - DSP_WORK_RAM_BASE]; + + if (offset >= DSP_CONTROL_RAM_BASE && offset <= (DSP_CONTROL_RAM_BASE + 0x1F)) + { + uint32_t data = DSPReadLong(offset & 0xFFFFFFFC, who); + + if ((offset & 0x03) == 0) + return (data >> 24); + else if ((offset & 0x03) == 1) + return ((data >> 16) & 0xFF); + else if ((offset & 0x03) == 2) + return ((data >> 8) & 0xFF); + else if ((offset & 0x03) == 3) + return (data & 0xFF); + } + + return JaguarReadByte(offset, who); +} + + +uint16_t DSPReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: ReadWord--Attempt to read from DSP register file by %s!\n", whoName[who]); + //??? + offset &= 0xFFFFFFFE; + + if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE+0x1FFF) + { + offset -= DSP_WORK_RAM_BASE; +/* uint16_t data = (((uint16_t)dsp_ram_8[offset])<<8)|((uint16_t)dsp_ram_8[offset+1]); + return data;*/ + return GET16(dsp_ram_8, offset); + } + else if ((offset>=DSP_CONTROL_RAM_BASE)&&(offset> 16; + } + + return JaguarReadWord(offset, who); +} + + +uint32_t DSPReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: ReadLong--Attempt to read from DSP register file by %s!\n", whoName[who]); + + // ??? WHY ??? + offset &= 0xFFFFFFFC; +/*if (offset == 0xF1BCF4) +{ + WriteLog("DSPReadLong: Reading from 0xF1BCF4... -> %08X [%02X %02X %02X %02X][%04X %04X]\n", GET32(dsp_ram_8, 0x0CF4), dsp_ram_8[0x0CF4], dsp_ram_8[0x0CF5], dsp_ram_8[0x0CF6], dsp_ram_8[0x0CF7], JaguarReadWord(0xF1BCF4, DSP), JaguarReadWord(0xF1BCF6, DSP)); + DSPDumpDisassembly(); +}*/ + if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF) + { + offset -= DSP_WORK_RAM_BASE; + return GET32(dsp_ram_8, offset); + } +//NOTE: Didn't return DSP_ACCUM!!! +//Mebbe it's not 'spose to! Yes, it is! + if (offset >= DSP_CONTROL_RAM_BASE && offset <= DSP_CONTROL_RAM_BASE + 0x23) + { + offset &= 0x3F; + switch (offset) + { + case 0x00: + dsp_flags = (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + return dsp_flags & 0xFFFFC1FF; + case 0x04: return dsp_matrix_control; + case 0x08: return dsp_pointer_to_matrix; + case 0x0C: return dsp_data_organization; + case 0x10: return dsp_pc; + case 0x14: return dsp_control; + case 0x18: return dsp_modulo; + case 0x1C: return dsp_remain; + case 0x20: + return (int32_t)((int8_t)(dsp_acc >> 32)); // Top 8 bits of 40-bit accumulator, sign extended + } + // unaligned long read-- !!! FIX !!! + return 0xFFFFFFFF; + } + + return JaguarReadLong(offset, who); +} + + +void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: WriteByte--Attempt to write to DSP register file by %s!\n", whoName[who]); + + if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE + 0x2000)) + { + offset -= DSP_WORK_RAM_BASE; + dsp_ram_8[offset] = data; +//This is rather stupid! !!! FIX !!! +/* if (dsp_in_exec == 0) + { + m68k_end_timeslice(); + dsp_releaseTimeslice(); + }*/ + return; + } + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE + 0x20)) + { + uint32_t reg = offset & 0x1C; + int bytenum = offset & 0x03; + + if ((reg >= 0x1C) && (reg <= 0x1F)) + dsp_div_control = (dsp_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); + else + { +//This looks funky. !!! FIX !!! + uint32_t old_data = DSPReadLong(offset&0xFFFFFFC, who); + bytenum = 3 - bytenum; // convention motorola !!! + old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); + DSPWriteLong(offset & 0xFFFFFFC, old_data, who); + } + return; + } +// WriteLog("dsp: writing %.2x at 0x%.8x\n",data,offset); +//Should this *ever* happen??? Shouldn't we be saying "unknown" here??? +// Well, yes, it can. There are 3 MMU users after all: 68K, GPU & DSP...! + JaguarWriteByte(offset, data, who); +} + + +void DSPWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: WriteWord--Attempt to write to DSP register file by %s!\n", whoName[who]); + offset &= 0xFFFFFFFE; +/*if (offset == 0xF1BCF4) +{ + WriteLog("DSPWriteWord: Writing to 0xF1BCF4... %04X -> %04X\n", GET16(dsp_ram_8, 0x0CF4), data); +}*/ +// WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset); + if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000)) + { +/*if (offset == 0xF1B2F4) +{ + WriteLog("DSP: %s is writing %04X at location 0xF1B2F4 (DSP_PC: %08X)...\n", whoName[who], data, dsp_pc); +}//*/ + offset -= DSP_WORK_RAM_BASE; + dsp_ram_8[offset] = data >> 8; + dsp_ram_8[offset+1] = data & 0xFF; +//This is rather stupid! !!! FIX !!! +/* if (dsp_in_exec == 0) + { +// WriteLog("dsp: writing %.4x at 0x%.8x\n",data,offset+DSP_WORK_RAM_BASE); + m68k_end_timeslice(); + dsp_releaseTimeslice(); + }*/ +//CC only! +#ifdef DSP_DEBUG_CC +SET16(ram1, offset, data), +SET16(ram2, offset, data); +#endif +//!!!!!!!! + return; + } + else if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20)) + { + if ((offset & 0x1C) == 0x1C) + { + if (offset & 0x03) + dsp_div_control = (dsp_div_control & 0xFFFF0000) | (data & 0xFFFF); + else + dsp_div_control = (dsp_div_control & 0xFFFF) | ((data & 0xFFFF) << 16); + } + else + { + uint32_t old_data = DSPReadLong(offset & 0xFFFFFFC, who); + + if (offset & 0x03) + old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); + else + old_data = (old_data & 0xFFFF) | ((data & 0xFFFF) << 16); + + DSPWriteLong(offset & 0xFFFFFFC, old_data, who); + } + + return; + } + + JaguarWriteWord(offset, data, who); +} + + +//bool badWrite = false; +void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF1A000 && offset <= 0xF1A0FF) + WriteLog("DSP: WriteLong--Attempt to write to DSP register file by %s!\n", whoName[who]); + // ??? WHY ??? + offset &= 0xFFFFFFFC; +/*if (offset == 0xF1BCF4) +{ + WriteLog("DSPWriteLong: Writing to 0xF1BCF4... %08X -> %08X\n", GET32(dsp_ram_8, 0x0CF4), data); +}*/ +// WriteLog("dsp: writing %.8x at 0x%.8x\n",data,offset); + if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF) + { +/*if (offset == 0xF1BE2C) +{ + WriteLog("DSP: %s is writing %08X at location 0xF1BE2C (DSP_PC: %08X)...\n", whoName[who], data, dsp_pc - 2); +}//*/ + offset -= DSP_WORK_RAM_BASE; + SET32(dsp_ram_8, offset, data); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram1, offset, data), +SET32(ram2, offset, data); +#endif +//!!!!!!!! + return; + } + else if (offset >= DSP_CONTROL_RAM_BASE && offset <= (DSP_CONTROL_RAM_BASE + 0x1F)) + { + offset &= 0x1F; + switch (offset) + { + case 0x00: + { +#ifdef DSP_DEBUG + WriteLog("DSP: Writing %08X to DSP_FLAGS by %s (REGPAGE is %sset)...\n", data, whoName[who], (dsp_flags & REGPAGE ? "" : "not ")); +#endif +// bool IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); + IMASKCleared = (dsp_flags & IMASK) && !(data & IMASK); + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + dsp_flags = data & (~IMASK); + dsp_flag_z = dsp_flags & 0x01; + dsp_flag_c = (dsp_flags >> 1) & 0x01; + dsp_flag_n = (dsp_flags >> 2) & 0x01; + DSPUpdateRegisterBanks(); + dsp_control &= ~((dsp_flags & CINT04FLAGS) >> 3); + dsp_control &= ~((dsp_flags & CINT5FLAG) >> 1); + break; + } + case 0x04: + dsp_matrix_control = data; + break; + case 0x08: + // According to JTRM, only lines 2-11 are addressable, the rest being + // hardwired to $F1Bxxx. + dsp_pointer_to_matrix = 0xF1B000 | (data & 0x000FFC); + break; + case 0x0C: + dsp_data_organization = data; + break; + case 0x10: + dsp_pc = data; +#ifdef DSP_DEBUG + WriteLog("DSP: Setting DSP PC to %08X by %s%s\n", dsp_pc, whoName[who], (DSP_RUNNING ? " (DSP is RUNNING!)" : ""));//*/ +#endif +//CC only! +#ifdef DSP_DEBUG_CC +if (who != DSP) + ctrl1[0] = ctrl2[0] = data; +#endif +//!!!!!!!! + break; + case 0x14: + { +//#ifdef DSP_DEBUG +WriteLog("Write to DSP CTRL by %s: %08X (DSP PC=$%08X)\n", whoName[who], data, dsp_pc); +//#endif + bool wasRunning = DSP_RUNNING; +// uint32_t dsp_was_running = DSP_RUNNING; + // Check for DSP -> CPU interrupt + if (data & CPUINT) + { +#ifdef DSP_DEBUG + WriteLog("DSP: DSP -> CPU interrupt\n"); +#endif + +#warning "!!! DSP IRQs that go to the 68K have to be routed thru TOM !!! FIX !!!" + if (JERRYIRQEnabled(IRQ2_DSP)) + { + JERRYSetPendingIRQ(IRQ2_DSP); + DSPReleaseTimeslice(); + m68k_set_irq(2); // Set 68000 IPL 2... + } + data &= ~CPUINT; + } + // Check for CPU -> DSP interrupt + if (data & DSPINT0) + { +#ifdef DSP_DEBUG + WriteLog("DSP: CPU -> DSP interrupt\n"); +#endif + m68k_end_timeslice(); + DSPReleaseTimeslice(); + DSPSetIRQLine(DSPIRQ_CPU, ASSERT_LINE); + data &= ~DSPINT0; + } + // single stepping + if (data & SINGLE_STEP) + { +// WriteLog("DSP: Asked to perform a single step (single step is %senabled)\n", (data & 0x8 ? "" : "not ")); + } + + // Protect writes to VERSION and the interrupt latches... + uint32_t mask = VERSION | INT_LAT0 | INT_LAT1 | INT_LAT2 | INT_LAT3 | INT_LAT4 | INT_LAT5; + dsp_control = (dsp_control & mask) | (data & ~mask); +//CC only! +#ifdef DSP_DEBUG_CC +if (who != DSP) + ctrl1[8] = ctrl2[8] = dsp_control; +#endif +//!!!!!!!! + + // if dsp wasn't running but is now running + // execute a few cycles +//This is just plain wrong, wrong, WRONG! +#ifndef DSP_SINGLE_STEPPING +/* if (!dsp_was_running && DSP_RUNNING) + { + DSPExec(200); + }*/ +#else +//This is WRONG! !!! FIX !!! + if (dsp_control & 0x18) + DSPExec(1); +#endif +#ifdef DSP_DEBUG +if (DSP_RUNNING) + WriteLog(" --> Starting to run at %08X by %s...", dsp_pc, whoName[who]); +else + WriteLog(" --> Stopped by %s! (DSP PC: %08X)", whoName[who], dsp_pc); +WriteLog("\n"); +#endif // DSP_DEBUG +//This isn't exactly right either--we don't know if it was the M68K or the DSP writing here... +// !!! FIX !!! [DONE] + if (DSP_RUNNING) + { + if (who == M68K) + m68k_end_timeslice(); + else if (who == DSP) + DSPReleaseTimeslice(); + + if (!wasRunning) + FlushDSPPipeline(); +//DSPDumpDisassembly(); + } + break; + } + case 0x18: +WriteLog("DSP: Modulo data %08X written by %s.\n", data, whoName[who]); + dsp_modulo = data; + break; + case 0x1C: + dsp_div_control = data; + break; +// default: // unaligned long read + //__asm int 3 + } + return; + } + +//We don't have to break this up like this! We CAN do 32 bit writes! +// JaguarWriteWord(offset, (data>>16) & 0xFFFF, DSP); +// JaguarWriteWord(offset+2, data & 0xFFFF, DSP); +//if (offset > 0xF1FFFF) +// badWrite = true; + JaguarWriteLong(offset, data, who); +} + + +// +// Update the DSP register file pointers depending on REGPAGE bit +// +void DSPUpdateRegisterBanks(void) +{ + int bank = (dsp_flags & REGPAGE); + + if (dsp_flags & IMASK) + bank = 0; // IMASK forces main bank to be bank 0 + + if (bank) + dsp_reg = dsp_reg_bank_1, dsp_alternate_reg = dsp_reg_bank_0; + else + dsp_reg = dsp_reg_bank_0, dsp_alternate_reg = dsp_reg_bank_1; + +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Register bank #%s active.\n", (bank ? "1" : "0")); +#endif +} + + +// +// Check for and handle any asserted DSP IRQs +// +void DSPHandleIRQs(void) +{ + if (dsp_flags & IMASK) // Bail if we're already inside an interrupt + return; + + // Get the active interrupt bits (latches) & interrupt mask (enables) + uint32_t bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F), + mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); + +// WriteLog("dsp: bits=%.2x mask=%.2x\n",bits,mask); + bits &= mask; + + if (!bits) // Bail if nothing is enabled + return; + + int which = 0; // Determine which interrupt + + if (bits & 0x01) + which = 0; + if (bits & 0x02) + which = 1; + if (bits & 0x04) + which = 2; + if (bits & 0x08) + which = 3; + if (bits & 0x10) + which = 4; + if (bits & 0x20) + which = 5; + +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Generating interrupt #%i...", which); +#endif +//temp... !!!!! +//if (which == 0) doDSPDis = true; + + // NOTE: Since the actual Jaguar hardware injects the code sequence below + // directly into the pipeline, it has the side effect of ensuring that the + // instruction interrupted also gets to do its writeback. We simulate that + // behavior here. +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ +//This should be execute (or should it?--not sure now!) +//Actually, the way this is called now, this should be correct (i.e., the plPtrs advance, +//and what just executed is now in the Write position...). So why didn't it do the +//writeback into register 0? +#ifdef DSP_DEBUG_IRQ +WriteLog("--> Pipeline dump [DSP_PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +#endif + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + dsp_flags |= IMASK; +//CC only! +#ifdef DSP_DEBUG_CC +ctrl2[4] = dsp_flags; +#endif +//!!!!!!!! + DSPUpdateRegisterBanks(); +#ifdef DSP_DEBUG_IRQ +// WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]); + WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), dsp_reg[31]); +#endif + + // subqt #4,r31 ; pre-decrement stack pointer + // move pc,r30 ; address of interrupted code + // store r30,(r31) ; store return address + dsp_reg[31] -= 4; +//CC only! +#ifdef DSP_DEBUG_CC +regs2[31] -= 4; +#endif +//!!!!!!!! +//This might not come back to the right place if the instruction was MOVEI #. !!! FIX !!! +//But, then again, JTRM says that it adds two regardless of what the instruction was... +//It missed the place that it was supposed to come back to, so this is WRONG! +// +// Look at the pipeline when an interrupt occurs (instructions of foo, bar, baz): +// +// R -> baz (<- PC points here) +// E -> bar (when it should point here!) +// W -> foo +// +// 'Foo' just completed executing as per above. PC is pointing to the instruction 'baz' +// which means (assuming they're all 2 bytes long) that the code below will come back on +// instruction 'baz' instead of 'bar' which is the next instruction to execute in the +// instruction stream... + +// DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP); + DSPWriteLong(dsp_reg[31], dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)), DSP); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram2, regs2[31] - 0xF1B000, dsp_pc - 2 - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2))); +#endif +//!!!!!!!! + + // movei #service_address,r30 ; pointer to ISR entry + // jump (r30) ; jump to ISR + // nop + dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl2[0] = regs2[30] = dsp_pc; +#endif +//!!!!!!!! + FlushDSPPipeline(); +} + + +// +// Non-pipelined version... +// +void DSPHandleIRQsNP(void) +{ +//CC only! +#ifdef DSP_DEBUG_CC + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); +#endif +//!!!!!!!! + if (dsp_flags & IMASK) // Bail if we're already inside an interrupt + return; + + // Get the active interrupt bits (latches) & interrupt mask (enables) + uint32_t bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F), + mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); + +// WriteLog("dsp: bits=%.2x mask=%.2x\n",bits,mask); + bits &= mask; + + if (!bits) // Bail if nothing is enabled + return; + + int which = 0; // Determine which interrupt + if (bits & 0x01) + which = 0; + if (bits & 0x02) + which = 1; + if (bits & 0x04) + which = 2; + if (bits & 0x08) + which = 3; + if (bits & 0x10) + which = 4; + if (bits & 0x20) + which = 5; + + dsp_flags |= IMASK; // Force Bank #0 +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[4] = dsp_flags; +#endif +//!!!!!!!! +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Bank 0: R30=%08X, R31=%08X\n", dsp_reg_bank_0[30], dsp_reg_bank_0[31]); + WriteLog("DSP: Bank 1: R30=%08X, R31=%08X\n", dsp_reg_bank_1[30], dsp_reg_bank_1[31]); +#endif + DSPUpdateRegisterBanks(); +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Bank 0: R30=%08X, R31=%08X\n", dsp_reg_bank_0[30], dsp_reg_bank_0[31]); + WriteLog("DSP: Bank 1: R30=%08X, R31=%08X\n", dsp_reg_bank_1[30], dsp_reg_bank_1[31]); +#endif + +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Generating interrupt #%i...", which); + WriteLog(" [PC will return to %08X, R31 = %08X]\n", dsp_pc, dsp_reg[31]); +#endif + + // subqt #4,r31 ; pre-decrement stack pointer + // move pc,r30 ; address of interrupted code + // store r30,(r31) ; store return address + dsp_reg[31] -= 4; + dsp_reg[30] = dsp_pc - 2; // -2 because we've executed the instruction already + +//CC only! +#ifdef DSP_DEBUG_CC +regs1[31] -= 4; +#endif +//!!!!!!!! +// DSPWriteLong(dsp_reg[31], dsp_pc - 2, DSP); + DSPWriteLong(dsp_reg[31], dsp_reg[30], DSP); +//CC only! +#ifdef DSP_DEBUG_CC +SET32(ram1, regs1[31] - 0xF1B000, dsp_pc - 2); +#endif +//!!!!!!!! + + // movei #service_address,r30 ; pointer to ISR entry + // jump (r30) ; jump to ISR + // nop + dsp_pc = dsp_reg[30] = DSP_WORK_RAM_BASE + (which * 0x10); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[0] = regs1[30] = dsp_pc; +#endif +//!!!!!!!! +} + + +// +// Set the specified DSP IRQ line to a given state +// +void DSPSetIRQLine(int irqline, int state) +{ +//NOTE: This doesn't take INT_LAT5 into account. !!! FIX !!! + uint32_t mask = INT_LAT0 << irqline; + dsp_control &= ~mask; // Clear the latch bit +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[8] = ctrl2[8] = dsp_control; +#endif +//!!!!!!!! + + if (state) + { + dsp_control |= mask; // Set the latch bit +#warning !!! No checking done to see if we are using pipelined DSP or not !!! +// DSPHandleIRQs(); + DSPHandleIRQsNP(); +//CC only! +#ifdef DSP_DEBUG_CC +ctrl1[8] = ctrl2[8] = dsp_control; +DSPHandleIRQsNP(); +#endif +//!!!!!!!! + } + + // Not sure if this is correct behavior, but according to JTRM, + // the IRQ output of JERRY is fed to this IRQ in the GPU... +// Not sure this is right--DSP interrupts seem to be different from the JERRY interrupts! +// GPUSetIRQLine(GPUIRQ_DSP, ASSERT_LINE); +} + + +bool DSPIsRunning(void) +{ + return (DSP_RUNNING ? true : false); +} + + +void DSPInit(void) +{ +// memory_malloc_secure((void **)&dsp_ram_8, 0x2000, "DSP work RAM"); +// memory_malloc_secure((void **)&dsp_reg_bank_0, 32 * sizeof(int32_t), "DSP bank 0 regs"); +// memory_malloc_secure((void **)&dsp_reg_bank_1, 32 * sizeof(int32_t), "DSP bank 1 regs"); + + dsp_build_branch_condition_table(); + DSPReset(); +} + + +void DSPReset(void) +{ + dsp_pc = 0x00F1B000; + dsp_acc = 0x00000000; + dsp_remain = 0x00000000; + dsp_modulo = 0xFFFFFFFF; + dsp_flags = 0x00040000; + dsp_matrix_control = 0x00000000; + dsp_pointer_to_matrix = 0x00000000; + dsp_data_organization = 0xFFFFFFFF; + dsp_control = 0x00002000; // Report DSP version 2 + dsp_div_control = 0x00000000; + dsp_in_exec = 0; + + dsp_reg = dsp_reg_bank_0; + dsp_alternate_reg = dsp_reg_bank_1; + + for(int i=0; i<32; i++) + dsp_reg[i] = dsp_alternate_reg[i] = 0x00000000; + + CLR_ZNC; + IMASKCleared = false; + FlushDSPPipeline(); + dsp_reset_stats(); + + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32_t i=0; i<8192; i+=4) + *((uint32_t *)(&dsp_ram_8[i])) = rand(); +} + + +void DSPDumpDisassembly(void) +{ + char buffer[512]; + + WriteLog("\n---[DSP code at 00F1B000]---------------------------\n"); + uint32_t j = 0xF1B000; + + while (j <= 0xF1CFFF) + { + uint32_t oldj = j; + j += dasmjag(JAGUAR_DSP, buffer, j); + WriteLog("\t%08X: %s\n", oldj, buffer); + } +} + + +void DSPDumpRegisters(void) +{ +//Shoud add modulus, etc to dump here... + WriteLog("\n---[DSP flags: NCZ %d%d%d, DSP PC: %08X]------------\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_pc); + WriteLog("\nRegisters bank 0\n"); + + for(int j=0; j<8; j++) + { + WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", + (j << 2) + 0, dsp_reg_bank_0[(j << 2) + 0], + (j << 2) + 1, dsp_reg_bank_0[(j << 2) + 1], + (j << 2) + 2, dsp_reg_bank_0[(j << 2) + 2], + (j << 2) + 3, dsp_reg_bank_0[(j << 2) + 3]); + } + + WriteLog("Registers bank 1\n"); + + for(int j=0; j<8; j++) + { + WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", + (j << 2) + 0, dsp_reg_bank_1[(j << 2) + 0], + (j << 2) + 1, dsp_reg_bank_1[(j << 2) + 1], + (j << 2) + 2, dsp_reg_bank_1[(j << 2) + 2], + (j << 2) + 3, dsp_reg_bank_1[(j << 2) + 3]); + } +} + + +void DSPDone(void) +{ + WriteLog("\n\n---------------------------------------------------------------------\n"); + WriteLog("DSP I/O Registers\n"); + WriteLog("---------------------------------------------------------------------\n"); + WriteLog("F1%04X (D_FLAGS): $%06X\n", 0xA100, (dsp_flags & 0xFFFFFFF8) | (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z); + WriteLog("F1%04X (D_MTXC): $%04X\n", 0xA104, dsp_matrix_control); + WriteLog("F1%04X (D_MTXA): $%04X\n", 0xA108, dsp_pointer_to_matrix); + WriteLog("F1%04X (D_END): $%02X\n", 0xA10C, dsp_data_organization); + WriteLog("F1%04X (D_PC): $%06X\n", 0xA110, dsp_pc); + WriteLog("F1%04X (D_CTRL): $%06X\n", 0xA114, dsp_control); + WriteLog("F1%04X (D_MOD): $%08X\n", 0xA118, dsp_modulo); + WriteLog("F1%04X (D_REMAIN): $%08X\n", 0xA11C, dsp_remain); + WriteLog("F1%04X (D_DIVCTRL): $%02X\n", 0xA11C, dsp_div_control); + WriteLog("F1%04X (D_MACHI): $%02X\n", 0xA120, (dsp_acc >> 32) & 0xFF); + WriteLog("---------------------------------------------------------------------\n\n\n"); + + WriteLog("DSP: Stopped at PC=%08X dsp_modulo=%08X (dsp was%s running)\n", dsp_pc, dsp_modulo, (DSP_RUNNING ? "" : "n't")); + WriteLog("DSP: %sin interrupt handler\n", (dsp_flags & IMASK ? "" : "not ")); + + // Get the active interrupt bits + int bits = ((dsp_control >> 10) & 0x20) | ((dsp_control >> 6) & 0x1F); + // Get the interrupt mask + int mask = ((dsp_flags >> 11) & 0x20) | ((dsp_flags >> 4) & 0x1F); + + WriteLog("DSP: pending=$%X enabled=$%X (%s%s%s%s%s%s)\n", bits, mask, + (mask & 0x01 ? "CPU " : ""), (mask & 0x02 ? "I2S " : ""), + (mask & 0x04 ? "Timer0 " : ""), (mask & 0x08 ? "Timer1 " : ""), + (mask & 0x10 ? "Ext0 " : ""), (mask & 0x20 ? "Ext1" : "")); + DSPDumpRegisters(); + WriteLog("\n"); + + static char buffer[512]; + int j = DSP_WORK_RAM_BASE; + + while (j <= 0xF1CFFF) + { + uint32_t oldj = j; + j += dasmjag(JAGUAR_DSP, buffer, j); + WriteLog("\t%08X: %s\n", oldj, buffer); + } + + WriteLog("DSP opcodes use:\n"); + + for(int i=0; i<64; i++) + { + if (dsp_opcode_use[i]) + WriteLog("\t%s %i\n", dsp_opcode_str[i], dsp_opcode_use[i]); + } +} + + + +// +// DSP comparison core... +// +#ifdef DSP_DEBUG_CC +static uint16_t lastExec; +void DSPExecComp(int32_t cycles) +{ + while (cycles > 0 && DSP_RUNNING) + { + // Load up vars for non-pipelined core + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); + + // Decrement cycles based on non-pipelined core... + uint16_t instr1 = DSPReadWord(dsp_pc, DSP); + cycles -= dsp_opcode_cycles[instr1 >> 10]; + +//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32_t)count, dsp_pc); + DSPExec(1); // Do *one* instruction + + // Save vars + memcpy(ram1, dsp_ram_8, 0x2000); + memcpy(regs1, dsp_reg_bank_0, 32 * 4); + memcpy(®s1[32], dsp_reg_bank_1, 32 * 4); + ctrl1[0] = dsp_pc; + ctrl1[1] = dsp_acc; + ctrl1[2] = dsp_remain; + ctrl1[3] = dsp_modulo; + ctrl1[4] = dsp_flags; + ctrl1[5] = dsp_matrix_control; + ctrl1[6] = dsp_pointer_to_matrix; + ctrl1[7] = dsp_data_organization; + ctrl1[8] = dsp_control; + ctrl1[9] = dsp_div_control; + ctrl1[10] = IMASKCleared; + ctrl1[11] = dsp_flag_z; + ctrl1[12] = dsp_flag_n; + ctrl1[13] = dsp_flag_c; + + // Load up vars for pipelined core + memcpy(dsp_ram_8, ram2, 0x2000); + memcpy(dsp_reg_bank_0, regs2, 32 * 4); + memcpy(dsp_reg_bank_1, ®s2[32], 32 * 4); + dsp_pc = ctrl2[0]; + dsp_acc = ctrl2[1]; + dsp_remain = ctrl2[2]; + dsp_modulo = ctrl2[3]; + dsp_flags = ctrl2[4]; + dsp_matrix_control = ctrl2[5]; + dsp_pointer_to_matrix = ctrl2[6]; + dsp_data_organization = ctrl2[7]; + dsp_control = ctrl2[8]; + dsp_div_control = ctrl2[9]; + IMASKCleared = ctrl2[10]; + dsp_flag_z = ctrl2[11]; + dsp_flag_n = ctrl2[12]; + dsp_flag_c = ctrl2[13]; +DSPUpdateRegisterBanks(); + +//WriteLog("\tAbout to execute pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32_t)count, dsp_pc); + DSPExecP2(1); // Do *one* instruction + + // Save vars + memcpy(ram2, dsp_ram_8, 0x2000); + memcpy(regs2, dsp_reg_bank_0, 32 * 4); + memcpy(®s2[32], dsp_reg_bank_1, 32 * 4); + ctrl2[0] = dsp_pc; + ctrl2[1] = dsp_acc; + ctrl2[2] = dsp_remain; + ctrl2[3] = dsp_modulo; + ctrl2[4] = dsp_flags; + ctrl2[5] = dsp_matrix_control; + ctrl2[6] = dsp_pointer_to_matrix; + ctrl2[7] = dsp_data_organization; + ctrl2[8] = dsp_control; + ctrl2[9] = dsp_div_control; + ctrl2[10] = IMASKCleared; + ctrl2[11] = dsp_flag_z; + ctrl2[12] = dsp_flag_n; + ctrl2[13] = dsp_flag_c; + + if (instr1 != lastExec) + { +// WriteLog("\nCores diverged at instruction tick #%u!\nAttemping to synchronize...\n\n", count); + +// uint32_t ppc = ctrl2[0] - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)) - (pipeline[plPtrWrite].opcode == 38 ? 6 : (pipeline[plPtrWrite].opcode == PIPELINE_STALL ? 0 : 2)); +//WriteLog("[DSP_PC1=%08X, DSP_PC2=%08X]\n", ctrl1[0], ppc); +// if (ctrl1[0] < ppc) // P ran ahead of NP +//How to test this crap??? +// if (1) + { + DSPExecP2(1); // Do one more instruction + + // Save vars + memcpy(ram2, dsp_ram_8, 0x2000); + memcpy(regs2, dsp_reg_bank_0, 32 * 4); + memcpy(®s2[32], dsp_reg_bank_1, 32 * 4); + ctrl2[0] = dsp_pc; + ctrl2[1] = dsp_acc; + ctrl2[2] = dsp_remain; + ctrl2[3] = dsp_modulo; + ctrl2[4] = dsp_flags; + ctrl2[5] = dsp_matrix_control; + ctrl2[6] = dsp_pointer_to_matrix; + ctrl2[7] = dsp_data_organization; + ctrl2[8] = dsp_control; + ctrl2[9] = dsp_div_control; + ctrl2[10] = IMASKCleared; + ctrl2[11] = dsp_flag_z; + ctrl2[12] = dsp_flag_n; + ctrl2[13] = dsp_flag_c; + } +// else // NP ran ahead of P + if (instr1 != lastExec) // Must be the other way... + + { + // Load up vars for non-pipelined core + memcpy(dsp_ram_8, ram1, 0x2000); + memcpy(dsp_reg_bank_0, regs1, 32 * 4); + memcpy(dsp_reg_bank_1, ®s1[32], 32 * 4); + dsp_pc = ctrl1[0]; + dsp_acc = ctrl1[1]; + dsp_remain = ctrl1[2]; + dsp_modulo = ctrl1[3]; + dsp_flags = ctrl1[4]; + dsp_matrix_control = ctrl1[5]; + dsp_pointer_to_matrix = ctrl1[6]; + dsp_data_organization = ctrl1[7]; + dsp_control = ctrl1[8]; + dsp_div_control = ctrl1[9]; + IMASKCleared = ctrl1[10]; + dsp_flag_z = ctrl1[11]; + dsp_flag_n = ctrl1[12]; + dsp_flag_c = ctrl1[13]; +DSPUpdateRegisterBanks(); + +for(int k=0; k<2; k++) +{ + // Decrement cycles based on non-pipelined core... + instr1 = DSPReadWord(dsp_pc, DSP); + cycles -= dsp_opcode_cycles[instr1 >> 10]; + +//WriteLog("\tAbout to execute non-pipelined core on tick #%u (DSP_PC=%08X)...\n", (uint32_t)count, dsp_pc); + DSPExec(1); // Do *one* instruction +} + + // Save vars + memcpy(ram1, dsp_ram_8, 0x2000); + memcpy(regs1, dsp_reg_bank_0, 32 * 4); + memcpy(®s1[32], dsp_reg_bank_1, 32 * 4); + ctrl1[0] = dsp_pc; + ctrl1[1] = dsp_acc; + ctrl1[2] = dsp_remain; + ctrl1[3] = dsp_modulo; + ctrl1[4] = dsp_flags; + ctrl1[5] = dsp_matrix_control; + ctrl1[6] = dsp_pointer_to_matrix; + ctrl1[7] = dsp_data_organization; + ctrl1[8] = dsp_control; + ctrl1[9] = dsp_div_control; + ctrl1[10] = IMASKCleared; + ctrl1[11] = dsp_flag_z; + ctrl1[12] = dsp_flag_n; + ctrl1[13] = dsp_flag_c; + } + } + + if (instr1 != lastExec) + { + WriteLog("\nCores diverged at instruction tick #%u!\nStopped!\n\n", count); + + WriteLog("Instruction for non-pipelined core: %04X\n", instr1); + WriteLog("Instruction for pipelined core: %04X\n", lastExec); + + log_done(); + exit(1); + } + + count++; + } +} +#endif + + +// +// DSP execution core +// +//static bool R20Set = false, tripwire = false; +//static uint32_t pcQueue[32], ptrPCQ = 0; +void DSPExec(int32_t cycles) +{ +#ifdef DSP_SINGLE_STEPPING + if (dsp_control & 0x18) + { + cycles = 1; + dsp_control &= ~0x10; + } +#endif +//There is *no* good reason to do this here! +// DSPHandleIRQs(); + dsp_releaseTimeSlice_flag = 0; + dsp_in_exec++; + + while (cycles > 0 && DSP_RUNNING) + { +/*extern uint32_t totalFrames; +//F1B2F6: LOAD (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E) +//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38 +//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C) +//F1B140: +if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140) +{ + doDSPDis = true; + WriteLog("Starting disassembly at frame #%u...\n", totalFrames); +} +if (dsp_pc == 0xF1B092) + doDSPDis = false;//*/ +/*if (dsp_pc == 0xF1B140) + doDSPDis = true;//*/ + + if (IMASKCleared) // If IMASK was cleared, + { +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Finished interrupt. PC=$%06X\n", dsp_pc); +#endif + DSPHandleIRQsNP(); // See if any other interrupts are pending! + IMASKCleared = false; + } + +/*if (badWrite) +{ + WriteLog("\nDSP: Encountered bad write in Atari Synth module. PC=%08X, R15=%08X\n", dsp_pc, dsp_reg[15]); + for(int i=0; i<80; i+=4) + WriteLog(" %08X: %08X\n", dsp_reg[15]+i, JaguarReadLong(dsp_reg[15]+i)); + WriteLog("\n"); +}//*/ +/*if (dsp_pc == 0xF1B55E) +{ + WriteLog("DSP: At $F1B55E--R15 = %08X at %u ms%s...\n", dsp_reg[15], SDL_GetTicks(), (dsp_flags & IMASK ? " (inside interrupt)" : "")); +}//*/ +/*if (dsp_pc == 0xF1B7D2) // Start here??? + doDSPDis = true; +pcQueue[ptrPCQ++] = dsp_pc; +ptrPCQ %= 32;*/ + uint16_t opcode = DSPReadWord(dsp_pc, DSP); + uint32_t index = opcode >> 10; + dsp_opcode_first_parameter = (opcode >> 5) & 0x1F; + dsp_opcode_second_parameter = opcode & 0x1F; + dsp_pc += 2; + dsp_opcode[index](); + dsp_opcode_use[index]++; + cycles -= dsp_opcode_cycles[index]; +/*if (dsp_reg_bank_0[20] == 0xF1A100 & !R20Set) +{ + WriteLog("DSP: R20 set to $F1A100 at %u ms%s...\n", SDL_GetTicks(), (dsp_flags & IMASK ? " (inside interrupt)" : "")); + R20Set = true; +} +if (dsp_reg_bank_0[20] != 0xF1A100 && R20Set) +{ + WriteLog("DSP: R20 corrupted at %u ms from starting%s!\nAborting!\n", SDL_GetTicks(), (dsp_flags & IMASK ? " (inside interrupt)" : "")); + DSPDumpRegisters(); + DSPDumpDisassembly(); + exit(1); +} +if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFE) && !tripwire) +{ + char buffer[512]; + WriteLog("DSP: Jumping outside of DSP RAM at %u ms. Register dump:\n", SDL_GetTicks()); + DSPDumpRegisters(); + tripwire = true; + WriteLog("\nBacktrace:\n"); + for(int i=0; i<32; i++) + { + dasmjag(JAGUAR_DSP, buffer, pcQueue[(ptrPCQ + i) % 32]); + WriteLog("\t%08X: %s\n", pcQueue[(ptrPCQ + i) % 32], buffer); + } + WriteLog("\n"); +}*/ + } + + dsp_in_exec--; +} + + +// +// DSP opcode handlers +// + +// There is a problem here with interrupt handlers the JUMP and JR instructions that +// can cause trouble because an interrupt can occur *before* the instruction following the +// jump can execute... !!! FIX !!! +static void dsp_opcode_jump(void) +{ +#ifdef DSP_DIS_JUMP +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doDSPDis) + WriteLog("%06X: JUMP %s, (R%02u) [NCZ:%u%u%u, R%02u=%08X] ", dsp_pc-2, condition[IMM_2], IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM); +#endif + // normalize flags +/* dsp_flag_c=dsp_flag_c?1:0; + dsp_flag_z=dsp_flag_z?1:0; + dsp_flag_n=dsp_flag_n?1:0;*/ + // KLUDGE: Used by BRANCH_CONDITION + uint32_t jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + + if (BRANCH_CONDITION(IMM_2)) + { +#ifdef DSP_DIS_JUMP + if (doDSPDis) + WriteLog("Branched!\n"); +#endif + uint32_t delayed_pc = RM; + DSPExec(1); + dsp_pc = delayed_pc; + } +#ifdef DSP_DIS_JUMP + else + if (doDSPDis) + WriteLog("Branch NOT taken.\n"); +#endif +} + + +static void dsp_opcode_jr(void) +{ +#ifdef DSP_DIS_JR +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doDSPDis) + WriteLog("%06X: JR %s, %06X [NCZ:%u%u%u] ", dsp_pc-2, condition[IMM_2], dsp_pc+((IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1) * 2), dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif + // normalize flags +/* dsp_flag_c=dsp_flag_c?1:0; + dsp_flag_z=dsp_flag_z?1:0; + dsp_flag_n=dsp_flag_n?1:0;*/ + // KLUDGE: Used by BRANCH_CONDITION + uint32_t jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + + if (BRANCH_CONDITION(IMM_2)) + { +#ifdef DSP_DIS_JR + if (doDSPDis) + WriteLog("Branched!\n"); +#endif + int32_t offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1 + int32_t delayed_pc = dsp_pc + (offset * 2); + DSPExec(1); + dsp_pc = delayed_pc; + } +#ifdef DSP_DIS_JR + else + if (doDSPDis) + WriteLog("Branch NOT taken.\n"); +#endif +} + + +static void dsp_opcode_add(void) +{ +#ifdef DSP_DIS_ADD + if (doDSPDis) + WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN + RM; + SET_ZNC_ADD(RN, RM, res); + RN = res; +#ifdef DSP_DIS_ADD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_addc(void) +{ +#ifdef DSP_DIS_ADDC + if (doDSPDis) + WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN + RM + dsp_flag_c; + uint32_t carry = dsp_flag_c; +// SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes! + SET_ZNC_ADD(RN + carry, RM, res); +// SET_ZNC_ADD(RN, RM + carry, res); + RN = res; +#ifdef DSP_DIS_ADDC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_addq(void) +{ +#ifdef DSP_DIS_ADDQ + if (doDSPDis) + WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t r1 = dsp_convert_zero[IMM_1]; + uint32_t res = RN + r1; + CLR_ZNC; SET_ZNC_ADD(RN, r1, res); + RN = res; +#ifdef DSP_DIS_ADDQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_sub(void) +{ +#ifdef DSP_DIS_SUB + if (doDSPDis) + WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN - RM; + SET_ZNC_SUB(RN, RM, res); + RN = res; +#ifdef DSP_DIS_SUB + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_subc(void) +{ +#ifdef DSP_DIS_SUBC + if (doDSPDis) + WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + // This is how the DSP ALU does it--Two's complement with inverted carry + uint64_t res = (uint64_t)RN + (uint64_t)(RM ^ 0xFFFFFFFF) + (dsp_flag_c ^ 1); + // Carry out of the result is inverted too + dsp_flag_c = ((res >> 32) & 0x01) ^ 1; + RN = (res & 0xFFFFFFFF); + SET_ZN(RN); +#ifdef DSP_DIS_SUBC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_subq(void) +{ +#ifdef DSP_DIS_SUBQ + if (doDSPDis) + WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t r1 = dsp_convert_zero[IMM_1]; + uint32_t res = RN - r1; + SET_ZNC_SUB(RN, r1, res); + RN = res; +#ifdef DSP_DIS_SUBQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_cmp(void) +{ +#ifdef DSP_DIS_CMP + if (doDSPDis) + WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN - RM; + SET_ZNC_SUB(RN, RM, res); +#ifdef DSP_DIS_CMP + if (doDSPDis) + WriteLog("[NCZ:%u%u%u]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif +} + + +static void dsp_opcode_cmpq(void) +{ + static int32_t sqtable[32] = + { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 }; +#ifdef DSP_DIS_CMPQ + if (doDSPDis) + WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, sqtable[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32_t res = RN - r1; + SET_ZNC_SUB(RN, r1, res); +#ifdef DSP_DIS_CMPQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif +} + + +static void dsp_opcode_and(void) +{ +#ifdef DSP_DIS_AND + if (doDSPDis) + WriteLog("%06X: AND R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN & RM; + SET_ZN(RN); +#ifdef DSP_DIS_AND + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_or(void) +{ +#ifdef DSP_DIS_OR + if (doDSPDis) + WriteLog("%06X: OR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN | RM; + SET_ZN(RN); +#ifdef DSP_DIS_OR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_xor(void) +{ +#ifdef DSP_DIS_XOR + if (doDSPDis) + WriteLog("%06X: XOR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN ^ RM; + SET_ZN(RN); +#ifdef DSP_DIS_XOR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_not(void) +{ +#ifdef DSP_DIS_NOT + if (doDSPDis) + WriteLog("%06X: NOT R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + RN = ~RN; + SET_ZN(RN); +#ifdef DSP_DIS_NOT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_move_pc(void) +{ + RN = dsp_pc - 2; +} + + +static void dsp_opcode_store_r14_indexed(void) +{ +#ifdef DSP_DIS_STORE14I + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2)); +#endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#else + DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#endif +} + + +static void dsp_opcode_store_r15_indexed(void) +{ +#ifdef DSP_DIS_STORE15I + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", dsp_pc-2, IMM_2, dsp_convert_zero[IMM_1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2)); +#endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#else + DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), RN, DSP); +#endif +} + + +static void dsp_opcode_load_r14_ri(void) +{ +#ifdef DSP_DIS_LOAD14R + if (doDSPDis) + WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[14], IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[14] + RM) & 0xFFFFFFFC, DSP); +#else + RN = DSPReadLong(dsp_reg[14] + RM, DSP); +#endif +#ifdef DSP_DIS_LOAD14R + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_load_r15_ri(void) +{ +#ifdef DSP_DIS_LOAD15R + if (doDSPDis) + WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM+dsp_reg[15], IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[15] + RM) & 0xFFFFFFFC, DSP); +#else + RN = DSPReadLong(dsp_reg[15] + RM, DSP); +#endif +#ifdef DSP_DIS_LOAD15R + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_store_r14_ri(void) +{ + DSPWriteLong(dsp_reg[14] + RM, RN, DSP); +} + + +static void dsp_opcode_store_r15_ri(void) +{ + DSPWriteLong(dsp_reg[15] + RM, RN, DSP); +} + + +static void dsp_opcode_nop(void) +{ +#ifdef DSP_DIS_NOP + if (doDSPDis) + WriteLog("%06X: NOP [NCZ:%u%u%u]\n", dsp_pc-2, dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif +} + + +static void dsp_opcode_storeb(void) +{ +#ifdef DSP_DIS_STOREB + if (doDSPDis) + WriteLog("%06X: STOREB R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); +#endif + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + DSPWriteLong(RM, RN & 0xFF, DSP); + else + JaguarWriteByte(RM, RN, DSP); +} + + +static void dsp_opcode_storew(void) +{ +#ifdef DSP_DIS_STOREW + if (doDSPDis) + WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); +#endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + DSPWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, DSP); + else + JaguarWriteWord(RM & 0xFFFFFFFE, RN, DSP); +#else + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + DSPWriteLong(RM, RN & 0xFFFF, DSP); + else + JaguarWriteWord(RM, RN, DSP); +#endif +} + + +static void dsp_opcode_store(void) +{ +#ifdef DSP_DIS_STORE + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_pc-2, IMM_2, IMM_1, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, IMM_1, RM); +#endif +#ifdef DSP_CORRECT_ALIGNMENT_STORE + DSPWriteLong(RM & 0xFFFFFFFC, RN, DSP); +#else + DSPWriteLong(RM, RN, DSP); +#endif +} + + +static void dsp_opcode_loadb(void) +{ +#ifdef DSP_DIS_LOADB + if (doDSPDis) + WriteLog("%06X: LOADB (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + RN = DSPReadLong(RM, DSP) & 0xFF; + else + RN = JaguarReadByte(RM, DSP); +#ifdef DSP_DIS_LOADB + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_loadw(void) +{ +#ifdef DSP_DIS_LOADW + if (doDSPDis) + WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + RN = DSPReadLong(RM & 0xFFFFFFFE, DSP) & 0xFFFF; + else + RN = JaguarReadWord(RM & 0xFFFFFFFE, DSP); +#else + if (RM >= DSP_WORK_RAM_BASE && RM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + RN = DSPReadLong(RM, DSP) & 0xFFFF; + else + RN = JaguarReadWord(RM, DSP); +#endif +#ifdef DSP_DIS_LOADW + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_load(void) +{ +#ifdef DSP_DIS_LOAD + if (doDSPDis) + WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong(RM & 0xFFFFFFFC, DSP); +#else + RN = DSPReadLong(RM, DSP); +#endif +#ifdef DSP_DIS_LOAD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_load_r14_indexed(void) +{ +#ifdef DSP_DIS_LOAD14I + if (doDSPDis) + WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[14]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP); +#else + RN = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[IMM_1] << 2), DSP); +#endif +#ifdef DSP_DIS_LOAD14I + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_load_r15_indexed(void) +{ +#ifdef DSP_DIS_LOAD15I + if (doDSPDis) + WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1] << 2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[IMM_1] << 2, dsp_reg[15]+(dsp_convert_zero[IMM_1] << 2), IMM_2, RN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + RN = DSPReadLong((dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[IMM_1] << 2), DSP); +#else + RN = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[IMM_1] << 2), DSP); +#endif +#ifdef DSP_DIS_LOAD15I + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_movei(void) +{ +#ifdef DSP_DIS_MOVEI + if (doDSPDis) + WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, (uint32_t)DSPReadWord(dsp_pc) | ((uint32_t)DSPReadWord(dsp_pc + 2) << 16), IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + // This instruction is followed by 32-bit value in LSW / MSW format... + RN = (uint32_t)DSPReadWord(dsp_pc, DSP) | ((uint32_t)DSPReadWord(dsp_pc + 2, DSP) << 16); + dsp_pc += 4; +#ifdef DSP_DIS_MOVEI + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_moveta(void) +{ +#ifdef DSP_DIS_MOVETA + if (doDSPDis) + WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, ALTERNATE_RN); +#endif + ALTERNATE_RN = RM; +#ifdef DSP_DIS_MOVETA + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, ALTERNATE_RN); +#endif +} + + +static void dsp_opcode_movefa(void) +{ +#ifdef DSP_DIS_MOVEFA + if (doDSPDis) + WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, ALTERNATE_RM, IMM_2, RN); +#endif + RN = ALTERNATE_RM; +#ifdef DSP_DIS_MOVEFA + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, ALTERNATE_RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_move(void) +{ +#ifdef DSP_DIS_MOVE + if (doDSPDis) + WriteLog("%06X: MOVE R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RM; +#ifdef DSP_DIS_MOVE + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_moveq(void) +{ +#ifdef DSP_DIS_MOVEQ + if (doDSPDis) + WriteLog("%06X: MOVEQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + RN = IMM_1; +#ifdef DSP_DIS_MOVEQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_resmac(void) +{ +#ifdef DSP_DIS_RESMAC + if (doDSPDis) + WriteLog("%06X: RESMAC R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_ACC=%02X%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif + RN = (uint32_t)dsp_acc; +#ifdef DSP_DIS_RESMAC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_imult(void) +{ +#ifdef DSP_DIS_IMULT + if (doDSPDis) + WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = (int16_t)RN * (int16_t)RM; + SET_ZN(RN); +#ifdef DSP_DIS_IMULT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_mult(void) +{ +#ifdef DSP_DIS_MULT + if (doDSPDis) + WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = (uint16_t)RM * (uint16_t)RN; + SET_ZN(RN); +#ifdef DSP_DIS_MULT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_bclr(void) +{ +#ifdef DSP_DIS_BCLR + if (doDSPDis) + WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t res = RN & ~(1 << IMM_1); + RN = res; + SET_ZN(res); +#ifdef DSP_DIS_BCLR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_btst(void) +{ +#ifdef DSP_DIS_BTST + if (doDSPDis) + WriteLog("%06X: BTST #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + dsp_flag_z = (~RN >> IMM_1) & 1; +#ifdef DSP_DIS_BTST + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_bset(void) +{ +#ifdef DSP_DIS_BSET + if (doDSPDis) + WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t res = RN | (1 << IMM_1); + RN = res; + SET_ZN(res); +#ifdef DSP_DIS_BSET + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_subqt(void) +{ +#ifdef DSP_DIS_SUBQT + if (doDSPDis) + WriteLog("%06X: SUBQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + RN -= dsp_convert_zero[IMM_1]; +#ifdef DSP_DIS_SUBQT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_addqt(void) +{ +#ifdef DSP_DIS_ADDQT + if (doDSPDis) + WriteLog("%06X: ADDQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + RN += dsp_convert_zero[IMM_1]; +#ifdef DSP_DIS_ADDQT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_imacn(void) +{ +#ifdef DSP_DIS_IMACN + if (doDSPDis) + WriteLog("%06X: IMACN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + int32_t res = (int16_t)RM * (int16_t)RN; + dsp_acc += (int64_t)res; +//Should we AND the result to fit into 40 bits here??? +#ifdef DSP_DIS_IMACN + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif +} + + +static void dsp_opcode_mtoi(void) +{ + RN = (((int32_t)RM >> 8) & 0xFF800000) | (RM & 0x007FFFFF); + SET_ZN(RN); +} + + +static void dsp_opcode_normi(void) +{ + uint32_t _Rm = RM; + uint32_t res = 0; + + if (_Rm) + { + while ((_Rm & 0xffc00000) == 0) + { + _Rm <<= 1; + res--; + } + while ((_Rm & 0xff800000) != 0) + { + _Rm >>= 1; + res++; + } + } + RN = res; + SET_ZN(RN); +} + + +static void dsp_opcode_mmult(void) +{ + int count = dsp_matrix_control&0x0f; + uint32_t addr = dsp_pointer_to_matrix; // in the dsp ram + int64_t accum = 0; + uint32_t res; + + if (!(dsp_matrix_control & 0x10)) + { + for (int i = 0; i < count; i++) + { + int16_t a; + if (i&0x01) + a=(int16_t)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); + else + a=(int16_t)(dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]&0xffff); + int16_t b=((int16_t)DSPReadWord(addr + 2, DSP)); + accum += a*b; + addr += 4; + } + } + else + { + for (int i = 0; i < count; i++) + { + int16_t a; + if (i&0x01) + a=(int16_t)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); + else + a=(int16_t)(dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]&0xffff); + int16_t b=((int16_t)DSPReadWord(addr + 2, DSP)); + accum += a*b; + addr += 4 * count; + } + } + RN = res = (int32_t)accum; + // carry flag to do +//NOTE: The flags are set based upon the last add/multiply done... + SET_ZN(RN); +} + + +static void dsp_opcode_abs(void) +{ +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("%06X: ABS R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t _Rn = RN; + uint32_t res; + + if (_Rn == 0x80000000) + dsp_flag_n = 1; + else + { + dsp_flag_c = ((_Rn & 0x80000000) >> 31); + res = RN = (_Rn & 0x80000000 ? -_Rn : _Rn); + CLR_ZN; SET_Z(res); + } +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_div(void) +{ +#if 0 + if (RM) + { + if (dsp_div_control & 0x01) // 16.16 division + { + dsp_remain = ((uint64_t)RN << 16) % RM; + RN = ((uint64_t)RN << 16) / RM; + } + else + { + // We calculate the remainder first because we destroy RN after + // this by assigning it to itself. + dsp_remain = RN % RM; + RN = RN / RM; + } + + } + else + { + // This is what happens according to SCPCD. NYAN! + RN = 0xFFFFFFFF; + dsp_remain = 0; + } +#else + // Real algorithm, courtesy of SCPCD: NYAN! + uint32_t q = RN; + uint32_t r = 0; + + // If 16.16 division, stuff top 16 bits of RN into remainder and put the + // bottom 16 of RN in top 16 of quotient + if (dsp_div_control & 0x01) + q <<= 16, r = RN >> 16; + + for(int i=0; i<32; i++) + { +// uint32_t sign = (r >> 31) & 0x01; + uint32_t sign = r & 0x80000000; + r = (r << 1) | ((q >> 31) & 0x01); + r += (sign ? RM : -RM); + q = (q << 1) | (((~r) >> 31) & 0x01); + } + + RN = q; + dsp_remain = r; +#endif +} + + +static void dsp_opcode_imultn(void) +{ +#ifdef DSP_DIS_IMULTN + if (doDSPDis) + WriteLog("%06X: IMULTN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + // This is OK, since this multiply won't overflow 32 bits... + int32_t res = (int32_t)((int16_t)RN * (int16_t)RM); + dsp_acc = (int64_t)res; + SET_ZN(res); +#ifdef DSP_DIS_IMULTN + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif +} + + +static void dsp_opcode_neg(void) +{ +#ifdef DSP_DIS_NEG + if (doDSPDis) + WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t res = -RN; + SET_ZNC_SUB(0, RN, res); + RN = res; +#ifdef DSP_DIS_NEG + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_shlq(void) +{ +#ifdef DSP_DIS_SHLQ + if (doDSPDis) + WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, 32 - IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + // NB: This instruction is the *only* one that does (32 - immediate data). + int32_t r1 = 32 - IMM_1; + uint32_t res = RN << r1; + SET_ZN(res); dsp_flag_c = (RN >> 31) & 1; + RN = res; +#ifdef DSP_DIS_SHLQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_shrq(void) +{ +#ifdef DSP_DIS_SHRQ + if (doDSPDis) + WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + int32_t r1 = dsp_convert_zero[IMM_1]; + uint32_t res = RN >> r1; + SET_ZN(res); dsp_flag_c = RN & 1; + RN = res; +#ifdef DSP_DIS_SHRQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_ror(void) +{ +#ifdef DSP_DIS_ROR + if (doDSPDis) + WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t r1 = RM & 0x1F; + uint32_t res = (RN >> r1) | (RN << (32 - r1)); + SET_ZN(res); dsp_flag_c = (RN >> 31) & 1; + RN = res; +#ifdef DSP_DIS_ROR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void dsp_opcode_rorq(void) +{ +#ifdef DSP_DIS_RORQ + if (doDSPDis) + WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t r1 = dsp_convert_zero[IMM_1 & 0x1F]; + uint32_t r2 = RN; + uint32_t res = (r2 >> r1) | (r2 << (32 - r1)); + RN = res; + SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01; +#ifdef DSP_DIS_RORQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_sha(void) +{ + int32_t sRm=(int32_t)RM; + uint32_t _Rn=RN; + + if (sRm<0) + { + uint32_t shift=-sRm; + if (shift>=32) shift=32; + dsp_flag_c=(_Rn&0x80000000)>>31; + while (shift) + { + _Rn<<=1; + shift--; + } + } + else + { + uint32_t shift=sRm; + if (shift>=32) shift=32; + dsp_flag_c=_Rn&0x1; + while (shift) + { + _Rn=((int32_t)_Rn)>>1; + shift--; + } + } + RN = _Rn; + SET_ZN(RN); +} + + +static void dsp_opcode_sharq(void) +{ +#ifdef DSP_DIS_SHARQ + if (doDSPDis) + WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif + uint32_t res = (int32_t)RN >> dsp_convert_zero[IMM_1]; + SET_ZN(res); dsp_flag_c = RN & 0x01; + RN = res; +#ifdef DSP_DIS_SHARQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + + +static void dsp_opcode_sh(void) +{ + int32_t sRm=(int32_t)RM; + uint32_t _Rn=RN; + + if (sRm<0) + { + uint32_t shift=(-sRm); + if (shift>=32) shift=32; + dsp_flag_c=(_Rn&0x80000000)>>31; + while (shift) + { + _Rn<<=1; + shift--; + } + } + else + { + uint32_t shift=sRm; + if (shift>=32) shift=32; + dsp_flag_c=_Rn&0x1; + while (shift) + { + _Rn>>=1; + shift--; + } + } + RN = _Rn; + SET_ZN(RN); +} + +void dsp_opcode_addqmod(void) +{ +#ifdef DSP_DIS_ADDQMOD + if (doDSPDis) + WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", dsp_pc-2, dsp_convert_zero[IMM_1], IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN, dsp_modulo); +#endif + uint32_t r1 = dsp_convert_zero[IMM_1]; + uint32_t r2 = RN; + uint32_t res = r2 + r1; + res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); + RN = res; + SET_ZNC_ADD(r2, r1, res); +#ifdef DSP_DIS_ADDQMOD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, IMM_2, RN); +#endif +} + +void dsp_opcode_subqmod(void) +{ + uint32_t r1 = dsp_convert_zero[IMM_1]; + uint32_t r2 = RN; + uint32_t res = r2 - r1; + res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); + RN = res; + + SET_ZNC_SUB(r2, r1, res); +} + +void dsp_opcode_mirror(void) +{ + uint32_t r1 = RN; + RN = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16]; + SET_ZN(RN); +} + +void dsp_opcode_sat32s(void) +{ + int32_t r2 = (uint32_t)RN; + int32_t temp = dsp_acc >> 32; + uint32_t res = (temp < -1) ? (int32_t)0x80000000 : (temp > 0) ? (int32_t)0x7FFFFFFF : r2; + RN = res; + SET_ZN(res); +} + +void dsp_opcode_sat16s(void) +{ + int32_t r2 = RN; + uint32_t res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; + RN = res; + SET_ZN(res); +} + +void dsp_opcode_illegal(void) +{ + // Don't know what it does, but it does *something*... + WriteLog("%06X: illegal %u, %u [NCZ:%u%u%u]\n", dsp_pc-2, IMM_1, IMM_2, dsp_flag_n, dsp_flag_c, dsp_flag_z); +} + +// +// New pipelined DSP core +// + +static void DSP_abs(void); +static void DSP_add(void); +static void DSP_addc(void); +static void DSP_addq(void); +static void DSP_addqmod(void); +static void DSP_addqt(void); +static void DSP_and(void); +static void DSP_bclr(void); +static void DSP_bset(void); +static void DSP_btst(void); +static void DSP_cmp(void); +static void DSP_cmpq(void); +static void DSP_div(void); +static void DSP_imacn(void); +static void DSP_imult(void); +static void DSP_imultn(void); +static void DSP_illegal(void); +static void DSP_jr(void); +static void DSP_jump(void); +static void DSP_load(void); +static void DSP_loadb(void); +static void DSP_loadw(void); +static void DSP_load_r14_i(void); +static void DSP_load_r14_r(void); +static void DSP_load_r15_i(void); +static void DSP_load_r15_r(void); +static void DSP_mirror(void); +static void DSP_mmult(void); +static void DSP_move(void); +static void DSP_movefa(void); +static void DSP_movei(void); +static void DSP_movepc(void); +static void DSP_moveq(void); +static void DSP_moveta(void); +static void DSP_mtoi(void); +static void DSP_mult(void); +static void DSP_neg(void); +static void DSP_nop(void); +static void DSP_normi(void); +static void DSP_not(void); +static void DSP_or(void); +static void DSP_resmac(void); +static void DSP_ror(void); +static void DSP_rorq(void); +static void DSP_sat16s(void); +static void DSP_sat32s(void); +static void DSP_sh(void); +static void DSP_sha(void); +static void DSP_sharq(void); +static void DSP_shlq(void); +static void DSP_shrq(void); +static void DSP_store(void); +static void DSP_storeb(void); +static void DSP_storew(void); +static void DSP_store_r14_i(void); +static void DSP_store_r14_r(void); +static void DSP_store_r15_i(void); +static void DSP_store_r15_r(void); +static void DSP_sub(void); +static void DSP_subc(void); +static void DSP_subq(void); +static void DSP_subqmod(void); +static void DSP_subqt(void); +static void DSP_xor(void); + +void (* DSPOpcode[64])() = +{ + DSP_add, DSP_addc, DSP_addq, DSP_addqt, + DSP_sub, DSP_subc, DSP_subq, DSP_subqt, + DSP_neg, DSP_and, DSP_or, DSP_xor, + DSP_not, DSP_btst, DSP_bset, DSP_bclr, + + DSP_mult, DSP_imult, DSP_imultn, DSP_resmac, + DSP_imacn, DSP_div, DSP_abs, DSP_sh, + DSP_shlq, DSP_shrq, DSP_sha, DSP_sharq, + DSP_ror, DSP_rorq, DSP_cmp, DSP_cmpq, + + DSP_subqmod, DSP_sat16s, DSP_move, DSP_moveq, + DSP_moveta, DSP_movefa, DSP_movei, DSP_loadb, + DSP_loadw, DSP_load, DSP_sat32s, DSP_load_r14_i, + DSP_load_r15_i, DSP_storeb, DSP_storew, DSP_store, + + DSP_mirror, DSP_store_r14_i, DSP_store_r15_i, DSP_movepc, + DSP_jump, DSP_jr, DSP_mmult, DSP_mtoi, + DSP_normi, DSP_nop, DSP_load_r14_r, DSP_load_r15_r, + DSP_store_r14_r, DSP_store_r15_r, DSP_illegal, DSP_addqmod +}; + +bool readAffected[64][2] = +{ + { true, true}, { true, true}, {false, true}, {false, true}, + { true, true}, { true, true}, {false, true}, {false, true}, + {false, true}, { true, true}, { true, true}, { true, true}, + {false, true}, {false, true}, {false, true}, {false, true}, + + { true, true}, { true, true}, { true, true}, {false, true}, + { true, true}, { true, true}, {false, true}, { true, true}, + {false, true}, {false, true}, { true, true}, {false, true}, + { true, true}, {false, true}, { true, true}, {false, true}, + + {false, true}, {false, true}, { true, false}, {false, false}, + { true, false}, {false, false}, {false, false}, { true, false}, + { true, false}, { true, false}, {false, true}, { true, false}, + { true, false}, { true, true}, { true, true}, { true, true}, + + {false, true}, { true, true}, { true, true}, {false, true}, + { true, false}, { true, false}, { true, true}, { true, false}, + { true, false}, {false, false}, { true, false}, { true, false}, + { true, true}, { true, true}, {false, false}, {false, true} +}; + +bool isLoadStore[65] = +{ + false, false, false, false, false, false, false, false, + false, false, false, false, false, false, false, false, + + false, false, false, false, false, false, false, false, + false, false, false, false, false, false, false, false, + + false, false, false, false, false, false, false, true, + true, true, false, true, true, true, true, true, + + false, true, true, false, false, false, false, false, + false, false, true, true, true, true, false, false, false +}; + +void FlushDSPPipeline(void) +{ + plPtrFetch = 3, plPtrRead = 2, plPtrExec = 1, plPtrWrite = 0; + + for(int i=0; i<4; i++) + pipeline[i].opcode = PIPELINE_STALL; + + for(int i=0; i<32; i++) + scoreboard[i] = 0; +} + +// +// New pipelined DSP execution core +// +/*void DSPExecP(int32_t cycles) +{ +// bool inhibitFetch = false; + + dsp_releaseTimeSlice_flag = 0; + dsp_in_exec++; + + while (cycles > 0 && DSP_RUNNING) + { +WriteLog("DSPExecP: Pipeline status...\n"); +WriteLog("\tF -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrFetch].opcode, pipeline[plPtrFetch].operand1, pipeline[plPtrFetch].operand2, pipeline[plPtrFetch].reg1, pipeline[plPtrFetch].reg2, pipeline[plPtrFetch].result, pipeline[plPtrFetch].writebackRegister); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); +WriteLog(" --> Scoreboard: "); +for(int i=0; i<32; i++) + WriteLog("%s ", scoreboard[i] ? "T" : "F"); +WriteLog("\n"); + // Stage 1: Instruction fetch +// if (!inhibitFetch) +// { + pipeline[plPtrFetch].instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrFetch].opcode = pipeline[plPtrFetch].instruction >> 10; + pipeline[plPtrFetch].operand1 = (pipeline[plPtrFetch].instruction >> 5) & 0x1F; + pipeline[plPtrFetch].operand2 = pipeline[plPtrFetch].instruction & 0x1F; + if (pipeline[plPtrFetch].opcode == 38) + pipeline[plPtrFetch].result = (uint32_t)DSPReadWord(dsp_pc + 2, DSP) + | ((uint32_t)DSPReadWord(dsp_pc + 4, DSP) << 16); +// } +// else +// inhibitFetch = false; +WriteLog("DSPExecP: Fetching instruction (%04X) from DSP_PC = %08X...\n", pipeline[plPtrFetch].instruction, dsp_pc); + +WriteLog("DSPExecP: Pipeline status (after stage 1)...\n"); +WriteLog("\tF -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrFetch].opcode, pipeline[plPtrFetch].operand1, pipeline[plPtrFetch].operand2, pipeline[plPtrFetch].reg1, pipeline[plPtrFetch].reg2, pipeline[plPtrFetch].result, pipeline[plPtrFetch].writebackRegister); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); + // Stage 2: Read registers +//Ok, stalls here depend on whether or not the instruction reads two registers or not +//and *which* register (1 or 2) is the one being read... !!! FIX !!! + if (scoreboard[pipeline[plPtrRead].operand2]) + && pipeline[plPtrRead].opcode != PIPELINE_STALL) + // We have a hit in the scoreboard, so we have to stall the pipeline... +{ +//This is crappy, crappy CRAPPY! And it doesn't work! !!! FIX !!! +// dsp_pc -= (pipeline[plPtrRead].opcode == 38 ? 6 : 2); +WriteLog(" --> Stalling pipeline: scoreboard = %s\n", scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false"); + pipeline[plPtrFetch] = pipeline[plPtrRead]; + pipeline[plPtrRead].opcode = PIPELINE_STALL; +} + else + { + pipeline[plPtrRead].reg1 = dsp_reg[pipeline[plPtrRead].operand1]; + pipeline[plPtrRead].reg2 = dsp_reg[pipeline[plPtrRead].operand2]; + pipeline[plPtrRead].writebackRegister = pipeline[plPtrRead].operand2; // Set it to RN + + if (pipeline[plPtrRead].opcode != PIPELINE_STALL) + // Shouldn't we be more selective with the register scoreboarding? + // Yes, we should. !!! FIX !!! + scoreboard[pipeline[plPtrRead].operand2] = true; +//Advance PC here??? Yes. +// dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2); +//This is a mangling of the pipeline stages, but what else to do??? + dsp_pc += (pipeline[plPtrFetch].opcode == 38 ? 6 : 2); + } + +WriteLog("DSPExecP: Pipeline status (after stage 2)...\n"); +WriteLog("\tF -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrFetch].opcode, pipeline[plPtrFetch].operand1, pipeline[plPtrFetch].operand2, pipeline[plPtrFetch].reg1, pipeline[plPtrFetch].reg2, pipeline[plPtrFetch].result, pipeline[plPtrFetch].writebackRegister); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); + // Stage 3: Execute + if (pipeline[plPtrExec].opcode != PIPELINE_STALL) + { +WriteLog("DSPExecP: About to execute opcode %s...\n", dsp_opcode_str[pipeline[plPtrExec].opcode]); + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode]; + } + else + cycles--; + +WriteLog("DSPExecP: Pipeline status (after stage 3)...\n"); +WriteLog("\tF -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrFetch].opcode, pipeline[plPtrFetch].operand1, pipeline[plPtrFetch].operand2, pipeline[plPtrFetch].reg1, pipeline[plPtrFetch].reg2, pipeline[plPtrFetch].result, pipeline[plPtrFetch].writebackRegister); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u \n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister); + // Stage 4: Write back register + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + scoreboard[pipeline[plPtrWrite].operand1] + = scoreboard[pipeline[plPtrWrite].operand2] = false; + } + + // Push instructions through the pipeline... + plPtrFetch = (++plPtrFetch) & 0x03; + plPtrRead = (++plPtrRead) & 0x03; + plPtrExec = (++plPtrExec) & 0x03; + plPtrWrite = (++plPtrWrite) & 0x03; + } + + dsp_in_exec--; +}*/ + + +//Problems: JR and any other instruction that relies on DSP_PC is getting WRONG values! +//!!! FIX !!! +// Should be fixed now. Another problem is figuring how to do the sequence following +// a branch followed with the JR & JUMP instructions... +// +// There are two conflicting problems: + +/* +F1B236: LOAD (R31), R03 [NCZ:000, R31=00F1CFDC, R03=00F14000] -> [NCZ:000, R03=00F1B084] +F1B238: BCLR #3, R00 [NCZ:000, R00=00004039] -> [NCZ:000, R00=00004031] +F1B23A: ADDQ #2, R03 [NCZ:000, R03=00F1B084] -> [NCZ:000, R03=00F1B086] +F1B23C: SUBQ #1, R17 [NCZ:000, R17=00000040] -> [NCZ:000, R17=0000003F] +F1B23E: MOVEI #$00F1CFE0, R31 [NCZ:000, R31=00F1CFDC] -> [NCZ:000, R31=00F1CFE0] +F1B244: JR z, F1B254 [NCZ:000] Branch NOT taken. +F1B246: BSET #10, R00 [NCZ:000, R00=00004031] -> [NCZ:000, R00=00004431] +F1B248: MOVEI #$00F1A100, R01 [NCZ:000, R01=00F1A148] -> [NCZ:000, R01=00F1A100] +F1B24E: STORE R00, (R01) [NCZ:000, R00=00004431, R01=00F1A100] +DSP: Writing 00004431 to DSP_FLAGS by DSP... +DSP: Finished interrupt. +; Without pipeline effects, the value in R03 is erroneously read from bank 1 instead of +; bank 0 (where is was prepared)! +F1B250: JUMP T, (R03) [NCZ:001, R03=00000000] Branched! +F1B252: NOP [NCZ:001] +*/ + +// The other is when you see this at the end of an IRQ: + +/* +JUMP T, (R29) ; R29 = Previous stack + 2 +STORE R28, (R30) ; R28 = Modified flags register, R30 = $F1A100 + +; Actually, this is OK if we do the atomic JUMP/JR operation correctly: +; 1) The STORE goes through the pipeline and is executed/written back +; 2) The pipeline is flushed +; 3) The DSP_PC is set to the new address +; 4) Execution resumes + +JUMP T, (R25) ; Oops! Because of pipeline effects R25 has the value from + ; bank 0 instead of the current bank 1 and so goes astray! +*/ + +//One other thing: Since these stages are supposed to happen simulaneously, try executing +//them in reverse order to see if that reduces pipeline stalls from late writebacks... + + +/* +Small problem here: The return address when INT0 comes up is $F1B088, but when INT1 +follows it, the JUMP out of the previous interrupt is bypassed immediately--this is +because the STORE instruction writes back on stage #2 of the pipeline instead of stage #3... +If it were done properly, the STORE write back would occur *after* (well, technically, +during) the execution of the the JUMP that follows it. + +!!! FIX !!! [DONE] + +F1B08A: JR z, F1B082 [NCZ:001] Branched! +F1B08A: NOP [NCZ:001] +[STALL...] +F1B080: MOVEI #$00F1B178, R00 [NCZ:001, R00=00F1B178] -> [NCZ:001, R00=00F1B178] +[STALL...] +[STALL...] +F1B086: LOAD (R00), R01 [NCZ:001, R00=00F1B178, R01=00000000] -> [NCZ:001, R01=00000000] +[STALL...] +[STALL...] +F1B088: OR R01, R01 [NCZ:001, R01=00000000, R01=00000000] -> [NCZ:001, R01=00000000, R01=00000000] +F1B08A: JR z, F1B082 [NCZ:001] Branched! +F1B08A: NOP [NCZ:001] +[STALL...] +F1B080: MOVEI #$00F1B178, R00 [NCZ:001, R00=00F1B178] -> [NCZ:001, R00=00F1B178] +[STALL...] +[STALL...] +Write to DSP CTRL: 00002301 --> Starting to run at 00F1B088 by M68K... +DSP: CPU -> DSP interrupt +DSP: Generating interrupt #0... [PC will return to 00F1B088, R31 = 00F1CFE0] +Write to DSP CTRL: 00000001 --> Starting to run at 00F1B000 by M68K... +[STALL...] +F1B000: MOVEI #$00F1B0D4, R30 [NCZ:001, R30=00F1B000] -> [NCZ:001, R30=00F1B0D4] +[STALL...] +[STALL...] +F1B006: JUMP T, (R30) [NCZ:001, R30=00F1B0D4] Branched! +F1B006: NOP [NCZ:001] +[STALL...] +F1B0D4: MOVEI #$00F1A100, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1A100] +[STALL...] +[STALL...] +F1B0DA: LOAD (R01), R00 [NCZ:001, R01=00F1A100, R00=00004431] -> [NCZ:001, R00=00004039] +F1B0DC: MOVEI #$00F1B0C8, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1B0C8] +[STALL...] +[STALL...] +F1B0E2: LOAD (R01), R02 [NCZ:001, R01=00F1B0C8, R02=00000000] -> [NCZ:001, R02=00000001] +F1B0E4: MOVEI #$00F1B0CC, R01 [NCZ:001, R01=00F1B0C8] -> [NCZ:001, R01=00F1B0CC] +[STALL...] +[STALL...] +F1B0EA: LOAD (R01), R03 [NCZ:001, R01=00F1B0CC, R03=00F1B086] -> [NCZ:001, R03=00000064] +F1B0EC: MOVEI #$00F1B0D0, R01 [NCZ:001, R01=00F1B0CC] -> [NCZ:001, R01=00F1B0D0] +[STALL...] +[STALL...] +F1B0F2: LOAD (R01), R04 [NCZ:001, R01=00F1B0D0, R04=00000000] -> [NCZ:001, R04=00000008] +F1B0F4: MOVEI #$00F1B0BC, R01 [NCZ:001, R01=00F1B0D0] -> [NCZ:001, R01=00F1B0BC] +[STALL...] +[STALL...] +F1B0FA: ADD R04, R01 [NCZ:001, R04=00000008, R01=00F1B0BC] -> [NCZ:000, R04=00000008, R01=00F1B0C4] +[STALL...] +[STALL...] +F1B0FC: LOAD (R01), R01 [NCZ:000, R01=00F1B0C4, R01=00F1B0C4] -> [NCZ:000, R01=00F1B12E] +[STALL...] +[STALL...] +F1B0FE: JUMP T, (R01) [NCZ:000, R01=00F1B12E] Branched! +F1B0FE: NOP [NCZ:000] +[STALL...] +F1B12E: MOVE R02, R08 [NCZ:000, R02=00000001, R08=00000000] -> [NCZ:000, R02=00000001, R08=00000001] +[STALL...] +[STALL...] +F1B132: MOVEI #$00F1B102, R01 [NCZ:000, R01=00F1B12E] -> [NCZ:000, R01=00F1B102] +[STALL...] +[STALL...] +F1B138: JUMP T, (R01) [NCZ:000, R01=00F1B102] Branched! +F1B138: NOP [NCZ:000] +[STALL...] +F1B102: MOVEI #$00F1B0C8, R01 [NCZ:000, R01=00F1B102] -> [NCZ:000, R01=00F1B0C8] +[STALL...] +[STALL...] +F1B108: STORE R08, (R01) [NCZ:000, R08=00000000, R01=00F1B0C8] +F1B10A: MOVEI #$00F1B0D0, R01 [NCZ:000, R01=00F1B0C8] -> [NCZ:000, R01=00F1B0D0] +F1B110: MOVEQ #0, R04 [NCZ:000, R04=00000008] -> [NCZ:000, R04=00000000] +[STALL...] +[STALL...] +F1B112: STORE R04, (R01) [NCZ:000, R04=00000000, R01=00F1B0D0] +F1B114: BCLR #3, R00 [NCZ:000, R00=00004039] -> [NCZ:000, R00=00004031] +[STALL...] +[STALL...] +F1B116: BSET #9, R00 [NCZ:000, R00=00004031] -> [NCZ:000, R00=00004231] +F1B118: LOAD (R31), R04 [NCZ:000, R31=00F1CFDC, R04=00000000] -> [NCZ:000, R04=00F1B086] +F1B11A: MOVEI #$00F1CFE0, R31 [NCZ:000, R31=00F1CFDC] -> [NCZ:000, R31=00F1CFE0] +[STALL...] +F1B120: ADDQ #2, R04 [NCZ:000, R04=00F1B086] -> [NCZ:000, R04=00F1B088] +F1B122: MOVEI #$00F1A100, R01 [NCZ:000, R01=00F1B0D0] -> [NCZ:000, R01=00F1A100] +[STALL...] +[STALL...] +F1B128: STORE R00, (R01) [NCZ:000, R00=00004231, R01=00F1A100] +DSP: Writing 00004231 to DSP_FLAGS by DSP (REGPAGE is set)... +DSP: Finished interrupt. +DSP: Generating interrupt #1... [PC will return to 00F1B12A, R31 = 00F1CFE0] +[STALL...] +F1B010: MOVEI #$00F1B1FC, R30 [NCZ:001, R30=00F1B010] -> [NCZ:001, R30=00F1B1FC] +[STALL...] +[STALL...] +F1B016: JUMP T, (R30) [NCZ:001, R30=00F1B1FC] Branched! +F1B016: NOP [NCZ:001] +[STALL...] +F1B1FC: MOVEI #$00F1A100, R01 [NCZ:001, R01=00F1A100] -> [NCZ:001, R01=00F1A100] +*/ + +uint32_t pcQueue1[0x400]; +uint32_t pcQPtr1 = 0; +static uint32_t prevR1; +//Let's try a 3 stage pipeline.... +//Looks like 3 stage is correct, otherwise bad things happen... +void DSPExecP2(int32_t cycles) +{ + dsp_releaseTimeSlice_flag = 0; + dsp_in_exec++; + + while (cycles > 0 && DSP_RUNNING) + { +/*extern uint32_t totalFrames; +//F1B2F6: LOAD (R14+$04), R24 [NCZ:001, R14+$04=00F20018, R24=FFFFFFFF] -> Jaguar: Unknown word read at 00F20018 by DSP (M68K PC=00E32E) +//-> 43 + 1 + 24 -> $2B + $01 + $18 -> 101011 00001 11000 -> 1010 1100 0011 1000 -> AC38 +//C470 -> 1100 0100 0111 0000 -> 110001 00011 10000 -> 49, 3, 16 -> STORE R16, (R14+$0C) +//F1B140: +if (totalFrames >= 377 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38 && dsp_pc == 0xF1B140) +{ + doDSPDis = true; + WriteLog("Starting disassembly at frame #%u...\n", totalFrames); +} +if (dsp_pc == 0xF1B092) + doDSPDis = false;//*/ +/*if (totalFrames >= 373 && GET16(dsp_ram_8, 0x0002F6) == 0xAC38) + doDSPDis = true;//*/ +/*if (totalFrames >= 373 && dsp_pc == 0xF1B0A0) + doDSPDis = true;//*/ +/*if (dsp_pc == 0xF1B0A0) + doDSPDis = true;//*/ +/*if (dsp_pc == 0xF1B0D2) && dsp_reg[1] == 0x2140C) + doDSPDis = true;//*/ +//Two parter... (not sure how to write this) +//if (dsp_pc == 0xF1B0D2) +// prevR1 = dsp_reg[1]; + +//F1B0D2: ADDQT #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414] +//F1B0D2: ADDQT #8, R01 [NCZ:000, R01=0002140C] -> [NCZ:000, R01=00021414] + + +pcQueue1[pcQPtr1++] = dsp_pc; +pcQPtr1 &= 0x3FF; + +#ifdef DSP_DEBUG_PL2 +if ((dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFF) && !doDSPDis) +{ + WriteLog("DSP: PC has stepped out of bounds...\n\nBacktrace:\n\n"); + doDSPDis = true; + + char buffer[512]; + + for(int i=0; i<0x400; i++) + { + dasmjag(JAGUAR_DSP, buffer, pcQueue1[(i + pcQPtr1) & 0x3FF]); + WriteLog("\t%08X: %s\n", pcQueue1[(i + pcQPtr1) & 0x3FF], buffer); + } + WriteLog("\n"); +}//*/ +#endif + + if (IMASKCleared) // If IMASK was cleared, + { +#ifdef DSP_DEBUG_IRQ + WriteLog("DSP: Finished interrupt.\n"); +#endif + DSPHandleIRQs(); // See if any other interrupts are pending! + IMASKCleared = false; + } + +//if (dsp_flags & REGPAGE) +// WriteLog(" --> REGPAGE has just been set!\n"); +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +WriteLog(" --> Scoreboard: "); +for(int i=0; i<32; i++) + WriteLog("%s ", scoreboard[i] ? "T" : "F"); +WriteLog("\n"); +} +#endif + // Stage 1a: Instruction fetch + pipeline[plPtrRead].instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrRead].opcode = pipeline[plPtrRead].instruction >> 10; + pipeline[plPtrRead].operand1 = (pipeline[plPtrRead].instruction >> 5) & 0x1F; + pipeline[plPtrRead].operand2 = pipeline[plPtrRead].instruction & 0x1F; + if (pipeline[plPtrRead].opcode == 38) + pipeline[plPtrRead].result = (uint32_t)DSPReadWord(dsp_pc + 2, DSP) + | ((uint32_t)DSPReadWord(dsp_pc + 4, DSP) << 16); +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ +WriteLog("DSPExecP: Fetching instruction (%04X) from DSP_PC = %08X...\n", pipeline[plPtrRead].instruction, dsp_pc); +WriteLog("DSPExecP: Pipeline status (after stage 1a) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +} +#endif + // Stage 1b: Read registers +//Small problem--when say LOAD or STORE (R14/5+$nn) is executed AFTER an instruction that +//modifies R14/5, we don't check the scoreboard for R14/5 (and we need to!)... !!! FIX !!! +//Ugly, but [DONE] +//Another problem: Any sequential combination of LOAD and STORE operations will cause the +//pipeline to stall, and we don't take care of that here. !!! FIX !!! + if ((scoreboard[pipeline[plPtrRead].operand1] && readAffected[pipeline[plPtrRead].opcode][0]) + || (scoreboard[pipeline[plPtrRead].operand2] && readAffected[pipeline[plPtrRead].opcode][1]) + || ((pipeline[plPtrRead].opcode == 43 || pipeline[plPtrRead].opcode == 58) && scoreboard[14]) + || ((pipeline[plPtrRead].opcode == 44 || pipeline[plPtrRead].opcode == 59) && scoreboard[15]) +//Not sure that this is the best way to fix the LOAD/STORE problem... But it seems to +//work--somewhat... + || (isLoadStore[pipeline[plPtrRead].opcode] && isLoadStore[pipeline[plPtrExec].opcode])) + // We have a hit in the scoreboard, so we have to stall the pipeline... +#ifdef DSP_DEBUG_PL2 +{ +if (doDSPDis) +{ +WriteLog(" --> Stalling pipeline: "); +if (readAffected[pipeline[plPtrRead].opcode][0]) + WriteLog("scoreboard[%u] = %s (reg 1) ", pipeline[plPtrRead].operand1, scoreboard[pipeline[plPtrRead].operand1] ? "true" : "false"); +if (readAffected[pipeline[plPtrRead].opcode][1]) + WriteLog("scoreboard[%u] = %s (reg 2)", pipeline[plPtrRead].operand2, scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false"); +WriteLog("\n"); +} +#endif + pipeline[plPtrRead].opcode = PIPELINE_STALL; +#ifdef DSP_DEBUG_PL2 +} +#endif + else + { + pipeline[plPtrRead].reg1 = dsp_reg[pipeline[plPtrRead].operand1]; + pipeline[plPtrRead].reg2 = dsp_reg[pipeline[plPtrRead].operand2]; + pipeline[plPtrRead].writebackRegister = pipeline[plPtrRead].operand2; // Set it to RN + + // Shouldn't we be more selective with the register scoreboarding? + // Yes, we should. !!! FIX !!! Kinda [DONE] +#ifndef NEW_SCOREBOARD + scoreboard[pipeline[plPtrRead].operand2] = affectsScoreboard[pipeline[plPtrRead].opcode]; +#else +//Hopefully this will fix the dual MOVEQ # problem... + scoreboard[pipeline[plPtrRead].operand2] += (affectsScoreboard[pipeline[plPtrRead].opcode] ? 1 : 0); +#endif + +//Advance PC here??? Yes. + dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2); + } + +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status (after stage 1b) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +} +#endif + // Stage 2: Execute + if (pipeline[plPtrExec].opcode != PIPELINE_STALL) + { +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) + WriteLog("\t[inst=%02u][R28=%08X, alt R28=%08X, REGPAGE=%s]\n", pipeline[plPtrExec].opcode, dsp_reg[28], dsp_alternate_reg[28], (dsp_flags & REGPAGE ? "set" : "not set")); + +if (doDSPDis) +{ +WriteLog("DSPExecP: About to execute opcode %s...\n", dsp_opcode_str[pipeline[plPtrExec].opcode]); +} +#endif +//CC only! +#ifdef DSP_DEBUG_CC +lastExec = pipeline[plPtrExec].instruction; +//WriteLog("[lastExec = %04X]\n", lastExec); +#endif + cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode]; + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + DSPOpcode[pipeline[plPtrExec].opcode](); +//WriteLog(" --> Returned from execute. DSP_PC: %08X\n", dsp_pc); + } + else +{ +//Let's not, until we do the stalling correctly... +//But, we gotta while we're doing the comparison core...! +//Or do we? cycles--; +//Really, the whole thing is wrong. When the pipeline is correctly stuffed, most instructions +//will execute in one clock cycle (others, like DIV, will likely not). So, the challenge is +//to model this clock cycle behavior correctly... +//Also, the pipeline stalls too much--mostly because the transparent writebacks at stage 3 +//don't affect the reads at stage 1... +#ifdef DSP_DEBUG_STALL +if (doDSPDis) + WriteLog("[STALL... DSP_PC = %08X]\n", dsp_pc); +#endif +} + +#ifdef DSP_DEBUG_PL2 +if (doDSPDis) +{ +WriteLog("DSPExecP: Pipeline status (after stage 2) [PC=%08X]...\n", dsp_pc); +WriteLog("\tR -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\tW -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrWrite].opcode, pipeline[plPtrWrite].operand1, pipeline[plPtrWrite].operand2, pipeline[plPtrWrite].reg1, pipeline[plPtrWrite].reg2, pipeline[plPtrWrite].result, pipeline[plPtrWrite].writebackRegister, dsp_opcode_str[pipeline[plPtrWrite].opcode]); +WriteLog("\n"); +} +#endif + // Stage 3: Write back register/memory address + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { +/*if (pipeline[plPtrWrite].writebackRegister == 3 + && (pipeline[plPtrWrite].result < 0xF14000 || pipeline[plPtrWrite].result > 0xF1CFFF) + && !doDSPDis) +{ + WriteLog("DSP: Register R03 has stepped out of bounds...\n\n"); + doDSPDis = true; +}//*/ + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + // Push instructions through the pipeline... + plPtrRead = (plPtrRead + 1) & 0x03; + plPtrExec = (plPtrExec + 1) & 0x03; + plPtrWrite = (plPtrWrite + 1) & 0x03; + } + + dsp_in_exec--; +} + + + +/* +//#define DSP_DEBUG_PL3 +//Let's try a 2 stage pipeline.... +void DSPExecP3(int32_t cycles) +{ + dsp_releaseTimeSlice_flag = 0; + dsp_in_exec++; + + while (cycles > 0 && DSP_RUNNING) + { +//if (dsp_pc < 0xF1B000 || dsp_pc > 0xF1CFFF) +// doDSPDis = true; +#ifdef DSP_DEBUG_PL3 +WriteLog("DSPExecP: Pipeline status...\n"); +WriteLog("\tF/R -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE/W -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog(" --> Scoreboard: "); +for(int i=0; i<32; i++) + WriteLog("%s ", scoreboard[i] ? "T" : "F"); +WriteLog("\n"); +#endif + // Stage 1a: Instruction fetch + pipeline[plPtrRead].instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrRead].opcode = pipeline[plPtrRead].instruction >> 10; + pipeline[plPtrRead].operand1 = (pipeline[plPtrRead].instruction >> 5) & 0x1F; + pipeline[plPtrRead].operand2 = pipeline[plPtrRead].instruction & 0x1F; + if (pipeline[plPtrRead].opcode == 38) + pipeline[plPtrRead].result = (uint32_t)DSPReadWord(dsp_pc + 2, DSP) + | ((uint32_t)DSPReadWord(dsp_pc + 4, DSP) << 16); +#ifdef DSP_DEBUG_PL3 +WriteLog("DSPExecP: Fetching instruction (%04X) from DSP_PC = %08X...\n", pipeline[plPtrRead].instruction, dsp_pc); +WriteLog("DSPExecP: Pipeline status (after stage 1a)...\n"); +WriteLog("\tF/R -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE/W -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +#endif + // Stage 1b: Read registers + if ((scoreboard[pipeline[plPtrRead].operand1] && readAffected[pipeline[plPtrRead].opcode][0]) + || (scoreboard[pipeline[plPtrRead].operand2] && readAffected[pipeline[plPtrRead].opcode][1])) + // We have a hit in the scoreboard, so we have to stall the pipeline... +#ifdef DSP_DEBUG_PL3 +{ +WriteLog(" --> Stalling pipeline: "); +if (readAffected[pipeline[plPtrRead].opcode][0]) + WriteLog("scoreboard[%u] = %s (reg 1) ", pipeline[plPtrRead].operand1, scoreboard[pipeline[plPtrRead].operand1] ? "true" : "false"); +if (readAffected[pipeline[plPtrRead].opcode][1]) + WriteLog("scoreboard[%u] = %s (reg 2)", pipeline[plPtrRead].operand2, scoreboard[pipeline[plPtrRead].operand2] ? "true" : "false"); +WriteLog("\n"); +#endif + pipeline[plPtrRead].opcode = PIPELINE_STALL; +#ifdef DSP_DEBUG_PL3 +} +#endif + else + { + pipeline[plPtrRead].reg1 = dsp_reg[pipeline[plPtrRead].operand1]; + pipeline[plPtrRead].reg2 = dsp_reg[pipeline[plPtrRead].operand2]; + pipeline[plPtrRead].writebackRegister = pipeline[plPtrRead].operand2; // Set it to RN + + // Shouldn't we be more selective with the register scoreboarding? + // Yes, we should. !!! FIX !!! [Kinda DONE] + scoreboard[pipeline[plPtrRead].operand2] = affectsScoreboard[pipeline[plPtrRead].opcode]; + +//Advance PC here??? Yes. + dsp_pc += (pipeline[plPtrRead].opcode == 38 ? 6 : 2); + } + +#ifdef DSP_DEBUG_PL3 +WriteLog("DSPExecP: Pipeline status (after stage 1b)...\n"); +WriteLog("\tF/R -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE/W -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +#endif + // Stage 2a: Execute + if (pipeline[plPtrExec].opcode != PIPELINE_STALL) + { +#ifdef DSP_DEBUG_PL3 +WriteLog("DSPExecP: About to execute opcode %s...\n", dsp_opcode_str[pipeline[plPtrExec].opcode]); +#endif + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + cycles -= dsp_opcode_cycles[pipeline[plPtrExec].opcode]; + } + else + cycles--; + +#ifdef DSP_DEBUG_PL3 +WriteLog("DSPExecP: Pipeline status (after stage 2a)...\n"); +WriteLog("\tF/R -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrRead].opcode, pipeline[plPtrRead].operand1, pipeline[plPtrRead].operand2, pipeline[plPtrRead].reg1, pipeline[plPtrRead].reg2, pipeline[plPtrRead].result, pipeline[plPtrRead].writebackRegister, dsp_opcode_str[pipeline[plPtrRead].opcode]); +WriteLog("\tE/W -> %02u, %02u, %02u; r1=%08X, r2= %08X, res=%08X, wb=%u (%s)\n", pipeline[plPtrExec].opcode, pipeline[plPtrExec].operand1, pipeline[plPtrExec].operand2, pipeline[plPtrExec].reg1, pipeline[plPtrExec].reg2, pipeline[plPtrExec].result, pipeline[plPtrExec].writebackRegister, dsp_opcode_str[pipeline[plPtrExec].opcode]); +WriteLog("\n"); +#endif + // Stage 2b: Write back register + if (pipeline[plPtrExec].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrExec].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrExec].writebackRegister] = pipeline[plPtrExec].result; + + if (affectsScoreboard[pipeline[plPtrExec].opcode]) + scoreboard[pipeline[plPtrExec].operand2] = false; + } + + // Push instructions through the pipeline... + plPtrRead = (++plPtrRead) & 0x03; + plPtrExec = (++plPtrExec) & 0x03; + } + + dsp_in_exec--; +}*/ + +// +// DSP pipelined opcode handlers +// + +#define PRM pipeline[plPtrExec].reg1 +#define PRN pipeline[plPtrExec].reg2 +#define PIMM1 pipeline[plPtrExec].operand1 +#define PIMM2 pipeline[plPtrExec].operand2 +#define PRES pipeline[plPtrExec].result +#define PWBR pipeline[plPtrExec].writebackRegister +#define NO_WRITEBACK pipeline[plPtrExec].writebackRegister = 0xFF +//#define DSP_PPC dsp_pc - (pipeline[plPtrRead].opcode == 38 ? 6 : 2) - (pipeline[plPtrExec].opcode == 38 ? 6 : 2) +#define DSP_PPC dsp_pc - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)) - (pipeline[plPtrExec].opcode == 38 ? 6 : (pipeline[plPtrExec].opcode == PIPELINE_STALL ? 0 : 2)) +#define WRITEBACK_ADDR pipeline[plPtrExec].writebackRegister = 0xFE + +static void DSP_abs(void) +{ +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("%06X: ABS R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t _Rn = PRN; + + if (_Rn == 0x80000000) + dsp_flag_n = 1; + else + { + dsp_flag_c = ((_Rn & 0x80000000) >> 31); + PRES = (_Rn & 0x80000000 ? -_Rn : _Rn); + CLR_ZN; SET_Z(PRES); + } +#ifdef DSP_DIS_ABS + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_add(void) +{ +#ifdef DSP_DIS_ADD + if (doDSPDis) + WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t res = PRN + PRM; + SET_ZNC_ADD(PRN, PRM, res); + PRES = res; +#ifdef DSP_DIS_ADD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_addc(void) +{ +#ifdef DSP_DIS_ADDC + if (doDSPDis) + WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t res = PRN + PRM + dsp_flag_c; + uint32_t carry = dsp_flag_c; +// SET_ZNC_ADD(PRN, PRM, res); //???BUG??? Yes! + SET_ZNC_ADD(PRN + carry, PRM, res); +// SET_ZNC_ADD(PRN, PRM + carry, res); + PRES = res; +#ifdef DSP_DIS_ADDC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_addq(void) +{ +#ifdef DSP_DIS_ADDQ + if (doDSPDis) + WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t r1 = dsp_convert_zero[PIMM1]; + uint32_t res = PRN + r1; + CLR_ZNC; SET_ZNC_ADD(PRN, r1, res); + PRES = res; +#ifdef DSP_DIS_ADDQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_addqmod(void) +{ +#ifdef DSP_DIS_ADDQMOD + if (doDSPDis) + WriteLog("%06X: ADDQMOD #%u, R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_MOD=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_modulo); +#endif + uint32_t r1 = dsp_convert_zero[PIMM1]; + uint32_t r2 = PRN; + uint32_t res = r2 + r1; + res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); + PRES = res; + SET_ZNC_ADD(r2, r1, res); +#ifdef DSP_DIS_ADDQMOD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_addqt(void) +{ +#ifdef DSP_DIS_ADDQT + if (doDSPDis) + WriteLog("%06X: ADDQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = PRN + dsp_convert_zero[PIMM1]; +#ifdef DSP_DIS_ADDQT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_and(void) +{ +#ifdef DSP_DIS_AND + if (doDSPDis) + WriteLog("%06X: AND R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = PRN & PRM; + SET_ZN(PRES); +#ifdef DSP_DIS_AND + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_bclr(void) +{ +#ifdef DSP_DIS_BCLR + if (doDSPDis) + WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = PRN & ~(1 << PIMM1); + SET_ZN(PRES); +#ifdef DSP_DIS_BCLR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_bset(void) +{ +#ifdef DSP_DIS_BSET + if (doDSPDis) + WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = PRN | (1 << PIMM1); + SET_ZN(PRES); +#ifdef DSP_DIS_BSET + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_btst(void) +{ +#ifdef DSP_DIS_BTST + if (doDSPDis) + WriteLog("%06X: BTST #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + dsp_flag_z = (~PRN >> PIMM1) & 1; + NO_WRITEBACK; +#ifdef DSP_DIS_BTST + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif +} + +static void DSP_cmp(void) +{ +#ifdef DSP_DIS_CMP + if (doDSPDis) + WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t res = PRN - PRM; + SET_ZNC_SUB(PRN, PRM, res); + NO_WRITEBACK; +#ifdef DSP_DIS_CMP + if (doDSPDis) + WriteLog("[NCZ:%u%u%u]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif +} + +static void DSP_cmpq(void) +{ + static int32_t sqtable[32] = + { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 }; +#ifdef DSP_DIS_CMPQ + if (doDSPDis) + WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, sqtable[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t r1 = sqtable[PIMM1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32_t res = PRN - r1; + SET_ZNC_SUB(PRN, r1, res); + NO_WRITEBACK; +#ifdef DSP_DIS_CMPQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif +} + +static void DSP_div(void) +{ + uint32_t _Rm = PRM, _Rn = PRN; + + if (_Rm) + { + if (dsp_div_control & 1) + { + dsp_remain = (((uint64_t)_Rn) << 16) % _Rm; + if (dsp_remain & 0x80000000) + dsp_remain -= _Rm; + PRES = (((uint64_t)_Rn) << 16) / _Rm; + } + else + { + dsp_remain = _Rn % _Rm; + if (dsp_remain & 0x80000000) + dsp_remain -= _Rm; + PRES = PRN / _Rm; + } + } + else + PRES = 0xFFFFFFFF; +} + +static void DSP_imacn(void) +{ +#ifdef DSP_DIS_IMACN + if (doDSPDis) + WriteLog("%06X: IMACN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + int32_t res = (int16_t)PRM * (int16_t)PRN; + dsp_acc += (int64_t)res; +//Should we AND the result to fit into 40 bits here??? + NO_WRITEBACK; +#ifdef DSP_DIS_IMACN + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif +} + +static void DSP_imult(void) +{ +#ifdef DSP_DIS_IMULT + if (doDSPDis) + WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = (int16_t)PRN * (int16_t)PRM; + SET_ZN(PRES); +#ifdef DSP_DIS_IMULT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_imultn(void) +{ +#ifdef DSP_DIS_IMULTN + if (doDSPDis) + WriteLog("%06X: IMULTN R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + // This is OK, since this multiply won't overflow 32 bits... + int32_t res = (int32_t)((int16_t)PRN * (int16_t)PRM); + dsp_acc = (int64_t)res; + SET_ZN(res); + NO_WRITEBACK; +#ifdef DSP_DIS_IMULTN + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, DSP_ACC=%02X%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif +} + +static void DSP_illegal(void) +{ +#ifdef DSP_DIS_ILLEGAL + if (doDSPDis) + WriteLog("%06X: ILLEGAL [NCZ:%u%u%u]\n", DSP_PPC, dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif + NO_WRITEBACK; +} + +// There is a problem here with interrupt handlers the JUMP and JR instructions that +// can cause trouble because an interrupt can occur *before* the instruction following the +// jump can execute... !!! FIX !!! +// This can probably be solved by judicious coding in the pipeline execution core... +// And should be fixed now... +static void DSP_jr(void) +{ +#ifdef DSP_DIS_JR +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doDSPDis) +//How come this is always off by 2??? + WriteLog("%06X: JR %s, %06X [NCZ:%u%u%u] ", DSP_PPC, condition[PIMM2], DSP_PPC+((PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1) * 2)+2, dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif + // KLUDGE: Used by BRANCH_CONDITION macro + uint32_t jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + + if (BRANCH_CONDITION(PIMM2)) + { +#ifdef DSP_DIS_JR + if (doDSPDis) + WriteLog("Branched!\n"); +#endif + int32_t offset = (PIMM1 & 0x10 ? 0xFFFFFFF0 | PIMM1 : PIMM1); // Sign extend PIMM1 +//Account for pipeline effects... + uint32_t newPC = dsp_pc + (offset * 2) - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)); +//WriteLog(" --> Old PC: %08X, new PC: %08X\n", dsp_pc, newPC); + + // Now that we've branched, we have to make sure that the following instruction + // is executed atomically with this one and then flush the pipeline before setting + // the new PC. + + // Step 1: Handle writebacks at stage 3 of pipeline +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + // Step 2: Push instruction through pipeline & execute following instruction + // NOTE: By putting our following instruction at stage 3 of the pipeline, + // we effectively handle the final push of the instruction through the + // pipeline when the new PC takes effect (since when we return, the + // pipeline code will be executing the writeback stage. If we reverse + // the execution order of the pipeline stages, this will no longer be + // the case!)... + pipeline[plPtrExec] = pipeline[plPtrRead]; +//This is BAD. We need to get that next opcode and execute it! +//NOTE: The problem is here because of a bad stall. Once those are fixed, we can probably +// remove this crap. + if (pipeline[plPtrExec].opcode == PIPELINE_STALL) + { + uint16_t instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrExec].opcode = instruction >> 10; + pipeline[plPtrExec].operand1 = (instruction >> 5) & 0x1F; + pipeline[plPtrExec].operand2 = instruction & 0x1F; + pipeline[plPtrExec].reg1 = dsp_reg[pipeline[plPtrExec].operand1]; + pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2]; + pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2; // Set it to RN + }//*/ + dsp_pc += 2; // For DSP_DIS_* accuracy + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + pipeline[plPtrWrite] = pipeline[plPtrExec]; + + // Step 3: Flush pipeline & set new PC + pipeline[plPtrRead].opcode = pipeline[plPtrExec].opcode = PIPELINE_STALL; + dsp_pc = newPC; + } + else +#ifdef DSP_DIS_JR + { + if (doDSPDis) + WriteLog("Branch NOT taken.\n"); +#endif + NO_WRITEBACK; +#ifdef DSP_DIS_JR + } +#endif +// WriteLog(" --> DSP_PC: %08X\n", dsp_pc); +} + +static void DSP_jump(void) +{ +#ifdef DSP_DIS_JUMP +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doDSPDis) + WriteLog("%06X: JUMP %s, (R%02u) [NCZ:%u%u%u, R%02u=%08X] ", DSP_PPC, condition[PIMM2], PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM); +#endif + // KLUDGE: Used by BRANCH_CONDITION macro + uint32_t jaguar_flags = (dsp_flag_n << 2) | (dsp_flag_c << 1) | dsp_flag_z; + + if (BRANCH_CONDITION(PIMM2)) + { +#ifdef DSP_DIS_JUMP + if (doDSPDis) + WriteLog("Branched!\n"); +#endif + uint32_t PCSave = PRM; + // Now that we've branched, we have to make sure that the following instruction + // is executed atomically with this one and then flush the pipeline before setting + // the new PC. + + // Step 1: Handle writebacks at stage 3 of pipeline +/* if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; + }//*/ + if (pipeline[plPtrWrite].opcode != PIPELINE_STALL) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFF) + { + if (pipeline[plPtrWrite].writebackRegister != 0xFE) + dsp_reg[pipeline[plPtrWrite].writebackRegister] = pipeline[plPtrWrite].result; + else + { + if (pipeline[plPtrWrite].type == TYPE_BYTE) + JaguarWriteByte(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else if (pipeline[plPtrWrite].type == TYPE_WORD) + JaguarWriteWord(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + else + JaguarWriteLong(pipeline[plPtrWrite].address, pipeline[plPtrWrite].value); + } + } + +#ifndef NEW_SCOREBOARD + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + scoreboard[pipeline[plPtrWrite].operand2] = false; +#else +//Yup, sequential MOVEQ # problem fixing (I hope!)... + if (affectsScoreboard[pipeline[plPtrWrite].opcode]) + if (scoreboard[pipeline[plPtrWrite].operand2]) + scoreboard[pipeline[plPtrWrite].operand2]--; +#endif + } + + // Step 2: Push instruction through pipeline & execute following instruction + // NOTE: By putting our following instruction at stage 3 of the pipeline, + // we effectively handle the final push of the instruction through the + // pipeline when the new PC takes effect (since when we return, the + // pipeline code will be executing the writeback stage. If we reverse + // the execution order of the pipeline stages, this will no longer be + // the case!)... + pipeline[plPtrExec] = pipeline[plPtrRead]; +//This is BAD. We need to get that next opcode and execute it! +//Also, same problem in JR! +//NOTE: The problem is here because of a bad stall. Once those are fixed, we can probably +// remove this crap. + if (pipeline[plPtrExec].opcode == PIPELINE_STALL) + { + uint16_t instruction = DSPReadWord(dsp_pc, DSP); + pipeline[plPtrExec].opcode = instruction >> 10; + pipeline[plPtrExec].operand1 = (instruction >> 5) & 0x1F; + pipeline[plPtrExec].operand2 = instruction & 0x1F; + pipeline[plPtrExec].reg1 = dsp_reg[pipeline[plPtrExec].operand1]; + pipeline[plPtrExec].reg2 = dsp_reg[pipeline[plPtrExec].operand2]; + pipeline[plPtrExec].writebackRegister = pipeline[plPtrExec].operand2; // Set it to RN + }//*/ + dsp_pc += 2; // For DSP_DIS_* accuracy + DSPOpcode[pipeline[plPtrExec].opcode](); + dsp_opcode_use[pipeline[plPtrExec].opcode]++; + pipeline[plPtrWrite] = pipeline[plPtrExec]; + + // Step 3: Flush pipeline & set new PC + pipeline[plPtrRead].opcode = pipeline[plPtrExec].opcode = PIPELINE_STALL; + dsp_pc = PCSave; + } + else +#ifdef DSP_DIS_JUMP + { + if (doDSPDis) + WriteLog("Branch NOT taken.\n"); +#endif + NO_WRITEBACK; +#ifdef DSP_DIS_JUMP + } +#endif +} + +static void DSP_load(void) +{ +#ifdef DSP_DIS_LOAD + if (doDSPDis) + WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong(PRM & 0xFFFFFFFC, DSP); +#else + PRES = DSPReadLong(PRM, DSP); +#endif +#ifdef DSP_DIS_LOAD + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_loadb(void) +{ +#ifdef DSP_DIS_LOADB + if (doDSPDis) + WriteLog("%06X: LOADB (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + PRES = DSPReadLong(PRM, DSP) & 0xFF; + else + PRES = JaguarReadByte(PRM, DSP); +#ifdef DSP_DIS_LOADB + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_loadw(void) +{ +#ifdef DSP_DIS_LOADW + if (doDSPDis) + WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + PRES = DSPReadLong(PRM & 0xFFFFFFFE, DSP) & 0xFFFF; + else + PRES = JaguarReadWord(PRM & 0xFFFFFFFE, DSP); +#else + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + PRES = DSPReadLong(PRM, DSP) & 0xFFFF; + else + PRES = JaguarReadWord(PRM, DSP); +#endif +#ifdef DSP_DIS_LOADW + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_load_r14_i(void) +{ +#ifdef DSP_DIS_LOAD14I + if (doDSPDis) + WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP); +#else + PRES = DSPReadLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), DSP); +#endif +#ifdef DSP_DIS_LOAD14I + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_load_r14_r(void) +{ +#ifdef DSP_DIS_LOAD14R + if (doDSPDis) + WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[14], PIMM2, PRES); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[14] + PRM) & 0xFFFFFFFC, DSP); +#else + PRES = DSPReadLong(dsp_reg[14] + PRM, DSP); +#endif +#ifdef DSP_DIS_LOAD14R + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_load_r15_i(void) +{ +#ifdef DSP_DIS_LOAD15I + if (doDSPDis) + WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1] << 2, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2), PIMM2, PRN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[15] &0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2), DSP); +#else + PRES = DSPReadLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), DSP); +#endif +#ifdef DSP_DIS_LOAD15I + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_load_r15_r(void) +{ +#ifdef DSP_DIS_LOAD15R + if (doDSPDis) + WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM+dsp_reg[15], PIMM2, PRN); +#endif +#ifdef DSP_CORRECT_ALIGNMENT + PRES = DSPReadLong((dsp_reg[15] + PRM) & 0xFFFFFFFC, DSP); +#else + PRES = DSPReadLong(dsp_reg[15] + PRM, DSP); +#endif +#ifdef DSP_DIS_LOAD15R + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_mirror(void) +{ + uint32_t r1 = PRN; + PRES = (mirror_table[r1 & 0xFFFF] << 16) | mirror_table[r1 >> 16]; + SET_ZN(PRES); +} + +static void DSP_mmult(void) +{ + int count = dsp_matrix_control&0x0f; + uint32_t addr = dsp_pointer_to_matrix; // in the dsp ram + int64_t accum = 0; + uint32_t res; + + if (!(dsp_matrix_control & 0x10)) + { + for (int i = 0; i < count; i++) + { + int16_t a; + if (i&0x01) + a=(int16_t)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); + else + a=(int16_t)(dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]&0xffff); + int16_t b=((int16_t)DSPReadWord(addr + 2, DSP)); + accum += a*b; + addr += 4; + } + } + else + { + for (int i = 0; i < count; i++) + { + int16_t a; + if (i&0x01) + a=(int16_t)((dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]>>16)&0xffff); + else + a=(int16_t)(dsp_alternate_reg[dsp_opcode_first_parameter + (i>>1)]&0xffff); + int16_t b=((int16_t)DSPReadWord(addr + 2, DSP)); + accum += a*b; + addr += 4 * count; + } + } + + PRES = res = (int32_t)accum; + // carry flag to do +//NOTE: The flags are set based upon the last add/multiply done... + SET_ZN(PRES); +} + +static void DSP_move(void) +{ +#ifdef DSP_DIS_MOVE + if (doDSPDis) + WriteLog("%06X: MOVE R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = PRM; +#ifdef DSP_DIS_MOVE + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_movefa(void) +{ +#ifdef DSP_DIS_MOVEFA + if (doDSPDis) +// WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, ALTERNATE_RM, PIMM2, PRN); + WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, dsp_alternate_reg[PIMM1], PIMM2, PRN); +#endif +// PRES = ALTERNATE_RM; + PRES = dsp_alternate_reg[PIMM1]; +#ifdef DSP_DIS_MOVEFA + if (doDSPDis) +// WriteLog("[NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, ALTERNATE_RM, PIMM2, PRN); + WriteLog("[NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, dsp_alternate_reg[PIMM1], PIMM2, PRES); +#endif +} + +static void DSP_movei(void) +{ +#ifdef DSP_DIS_MOVEI + if (doDSPDis) + WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PRES, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif +// // This instruction is followed by 32-bit value in LSW / MSW format... +// PRES = (uint32_t)DSPReadWord(dsp_pc, DSP) | ((uint32_t)DSPReadWord(dsp_pc + 2, DSP) << 16); +// dsp_pc += 4; +#ifdef DSP_DIS_MOVEI + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_movepc(void) +{ +#ifdef DSP_DIS_MOVEPC + if (doDSPDis) + WriteLog("%06X: MOVE PC, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif +//Need to fix this to take into account pipelining effects... !!! FIX !!! [DONE] +// PRES = dsp_pc - 2; +//Account for pipeline effects... + PRES = dsp_pc - 2 - (pipeline[plPtrRead].opcode == 38 ? 6 : (pipeline[plPtrRead].opcode == PIPELINE_STALL ? 0 : 2)); +#ifdef DSP_DIS_MOVEPC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_moveq(void) +{ +#ifdef DSP_DIS_MOVEQ + if (doDSPDis) + WriteLog("%06X: MOVEQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = PIMM1; +#ifdef DSP_DIS_MOVEQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_moveta(void) +{ +#ifdef DSP_DIS_MOVETA + if (doDSPDis) +// WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, ALTERNATE_RN); + WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, dsp_alternate_reg[PIMM2]); +#endif +// ALTERNATE_RN = PRM; + dsp_alternate_reg[PIMM2] = PRM; + NO_WRITEBACK; +#ifdef DSP_DIS_MOVETA + if (doDSPDis) +// WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, ALTERNATE_RN); + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, dsp_alternate_reg[PIMM2]); +#endif +} + +static void DSP_mtoi(void) +{ + PRES = (((int32_t)PRM >> 8) & 0xFF800000) | (PRM & 0x007FFFFF); + SET_ZN(PRES); +} + +static void DSP_mult(void) +{ +#ifdef DSP_DIS_MULT + if (doDSPDis) + WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = (uint16_t)PRM * (uint16_t)PRN; + SET_ZN(PRES); +#ifdef DSP_DIS_MULT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_neg(void) +{ +#ifdef DSP_DIS_NEG + if (doDSPDis) + WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t res = -PRN; + SET_ZNC_SUB(0, PRN, res); + PRES = res; +#ifdef DSP_DIS_NEG + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_nop(void) +{ +#ifdef DSP_DIS_NOP + if (doDSPDis) + WriteLog("%06X: NOP [NCZ:%u%u%u]\n", DSP_PPC, dsp_flag_n, dsp_flag_c, dsp_flag_z); +#endif + NO_WRITEBACK; +} + +static void DSP_normi(void) +{ + uint32_t _Rm = PRM; + uint32_t res = 0; + + if (_Rm) + { + while ((_Rm & 0xffc00000) == 0) + { + _Rm <<= 1; + res--; + } + while ((_Rm & 0xff800000) != 0) + { + _Rm >>= 1; + res++; + } + } + PRES = res; + SET_ZN(PRES); +} + +static void DSP_not(void) +{ +#ifdef DSP_DIS_NOT + if (doDSPDis) + WriteLog("%06X: NOT R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = ~PRN; + SET_ZN(PRES); +#ifdef DSP_DIS_NOT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_or(void) +{ +#ifdef DSP_DIS_OR + if (doDSPDis) + WriteLog("%06X: OR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = PRN | PRM; + SET_ZN(PRES); +#ifdef DSP_DIS_OR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_resmac(void) +{ +#ifdef DSP_DIS_RESMAC + if (doDSPDis) + WriteLog("%06X: RESMAC R%02u [NCZ:%u%u%u, R%02u=%08X, DSP_ACC=%02X%08X] -> ", DSP_PPC, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, (uint8_t)(dsp_acc >> 32), (uint32_t)(dsp_acc & 0xFFFFFFFF)); +#endif + PRES = (uint32_t)dsp_acc; +#ifdef DSP_DIS_RESMAC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif +} + +static void DSP_ror(void) +{ +#ifdef DSP_DIS_ROR + if (doDSPDis) + WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t r1 = PRM & 0x1F; + uint32_t res = (PRN >> r1) | (PRN << (32 - r1)); + SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1; + PRES = res; +#ifdef DSP_DIS_ROR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_rorq(void) +{ +#ifdef DSP_DIS_RORQ + if (doDSPDis) + WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t r1 = dsp_convert_zero[PIMM1 & 0x1F]; + uint32_t r2 = PRN; + uint32_t res = (r2 >> r1) | (r2 << (32 - r1)); + PRES = res; + SET_ZN(res); dsp_flag_c = (r2 >> 31) & 0x01; +#ifdef DSP_DIS_RORQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_sat16s(void) +{ + int32_t r2 = PRN; + uint32_t res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2; + PRES = res; + SET_ZN(res); +} + +static void DSP_sat32s(void) +{ + int32_t r2 = (uint32_t)PRN; + int32_t temp = dsp_acc >> 32; + uint32_t res = (temp < -1) ? (int32_t)0x80000000 : (temp > 0) ? (int32_t)0x7FFFFFFF : r2; + PRES = res; + SET_ZN(res); +} + +static void DSP_sh(void) +{ + int32_t sRm = (int32_t)PRM; + uint32_t _Rn = PRN; + + if (sRm < 0) + { + uint32_t shift = -sRm; + + if (shift >= 32) + shift = 32; + + dsp_flag_c = (_Rn & 0x80000000) >> 31; + + while (shift) + { + _Rn <<= 1; + shift--; + } + } + else + { + uint32_t shift = sRm; + + if (shift >= 32) + shift = 32; + + dsp_flag_c = _Rn & 0x1; + + while (shift) + { + _Rn >>= 1; + shift--; + } + } + + PRES = _Rn; + SET_ZN(PRES); +} + +static void DSP_sha(void) +{ + int32_t sRm = (int32_t)PRM; + uint32_t _Rn = PRN; + + if (sRm < 0) + { + uint32_t shift = -sRm; + + if (shift >= 32) + shift = 32; + + dsp_flag_c = (_Rn & 0x80000000) >> 31; + + while (shift) + { + _Rn <<= 1; + shift--; + } + } + else + { + uint32_t shift = sRm; + + if (shift >= 32) + shift = 32; + + dsp_flag_c = _Rn & 0x1; + + while (shift) + { + _Rn = ((int32_t)_Rn) >> 1; + shift--; + } + } + + PRES = _Rn; + SET_ZN(PRES); +} + +static void DSP_sharq(void) +{ +#ifdef DSP_DIS_SHARQ + if (doDSPDis) + WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t res = (int32_t)PRN >> dsp_convert_zero[PIMM1]; + SET_ZN(res); dsp_flag_c = PRN & 0x01; + PRES = res; +#ifdef DSP_DIS_SHARQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_shlq(void) +{ +#ifdef DSP_DIS_SHLQ + if (doDSPDis) + WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, 32 - PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + int32_t r1 = 32 - PIMM1; + uint32_t res = PRN << r1; + SET_ZN(res); dsp_flag_c = (PRN >> 31) & 1; + PRES = res; +#ifdef DSP_DIS_SHLQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_shrq(void) +{ +#ifdef DSP_DIS_SHRQ + if (doDSPDis) + WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + int32_t r1 = dsp_convert_zero[PIMM1]; + uint32_t res = PRN >> r1; + SET_ZN(res); dsp_flag_c = PRN & 1; + PRES = res; +#ifdef DSP_DIS_SHRQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_store(void) +{ +#ifdef DSP_DIS_STORE + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); +#endif +// DSPWriteLong(PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = PRM & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; +} + +static void DSP_storeb(void) +{ +#ifdef DSP_DIS_STOREB + if (doDSPDis) + WriteLog("%06X: STOREB R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); +#endif +// if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) +// DSPWriteLong(PRM, PRN & 0xFF, DSP); +// else +// JaguarWriteByte(PRM, PRN, DSP); +// +// NO_WRITEBACK; + pipeline[plPtrExec].address = PRM; + + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + { + pipeline[plPtrExec].value = PRN & 0xFF; + pipeline[plPtrExec].type = TYPE_DWORD; + } + else + { + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_BYTE; + } + + WRITEBACK_ADDR; +} + +static void DSP_storew(void) +{ +#ifdef DSP_DIS_STOREW + if (doDSPDis) + WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", DSP_PPC, PIMM2, PIMM1, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, PIMM1, PRM); +#endif +// if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) +// DSPWriteLong(PRM, PRN & 0xFFFF, DSP); +// else +// JaguarWriteWord(PRM, PRN, DSP); +// +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = PRM & 0xFFFFFFFE; +#else + pipeline[plPtrExec].address = PRM; +#endif + + if (PRM >= DSP_WORK_RAM_BASE && PRM <= (DSP_WORK_RAM_BASE + 0x1FFF)) + { + pipeline[plPtrExec].value = PRN & 0xFFFF; + pipeline[plPtrExec].type = TYPE_DWORD; + } + else + { + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_WORD; + } + WRITEBACK_ADDR; +} + +static void DSP_store_r14_i(void) +{ +#ifdef DSP_DIS_STORE14I + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", DSP_PPC, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[14]+(dsp_convert_zero[PIMM1] << 2)); +#endif +// DSPWriteLong(dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[14] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); +#else + pipeline[plPtrExec].address = dsp_reg[14] + (dsp_convert_zero[PIMM1] << 2); +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; +} + +static void DSP_store_r14_r(void) +{ +// DSPWriteLong(dsp_reg[14] + PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[14] + PRM) & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = dsp_reg[14] + PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; +} + +static void DSP_store_r15_i(void) +{ +#ifdef DSP_DIS_STORE15I + if (doDSPDis) + WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", DSP_PPC, PIMM2, dsp_convert_zero[PIMM1] << 2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN, dsp_convert_zero[PIMM1] << 2, dsp_reg[15]+(dsp_convert_zero[PIMM1] << 2)); +#endif +// DSPWriteLong(dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2), PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[15] & 0xFFFFFFFC) + (dsp_convert_zero[PIMM1] << 2); +#else + pipeline[plPtrExec].address = dsp_reg[15] + (dsp_convert_zero[PIMM1] << 2); +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; +} + +static void DSP_store_r15_r(void) +{ +// DSPWriteLong(dsp_reg[15] + PRM, PRN, DSP); +// NO_WRITEBACK; +#ifdef DSP_CORRECT_ALIGNMENT_STORE + pipeline[plPtrExec].address = (dsp_reg[15] + PRM) & 0xFFFFFFFC; +#else + pipeline[plPtrExec].address = dsp_reg[15] + PRM; +#endif + pipeline[plPtrExec].value = PRN; + pipeline[plPtrExec].type = TYPE_DWORD; + WRITEBACK_ADDR; +} + +static void DSP_sub(void) +{ +#ifdef DSP_DIS_SUB + if (doDSPDis) + WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t res = PRN - PRM; + SET_ZNC_SUB(PRN, PRM, res); + PRES = res; +#ifdef DSP_DIS_SUB + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_subc(void) +{ +#ifdef DSP_DIS_SUBC + if (doDSPDis) + WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + uint32_t res = PRN - PRM - dsp_flag_c; + uint32_t borrow = dsp_flag_c; + SET_ZNC_SUB(PRN - borrow, PRM, res); + PRES = res; +#ifdef DSP_DIS_SUBC + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} + +static void DSP_subq(void) +{ +#ifdef DSP_DIS_SUBQ + if (doDSPDis) + WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + uint32_t r1 = dsp_convert_zero[PIMM1]; + uint32_t res = PRN - r1; + SET_ZNC_SUB(PRN, r1, res); + PRES = res; +#ifdef DSP_DIS_SUBQ + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_subqmod(void) +{ + uint32_t r1 = dsp_convert_zero[PIMM1]; + uint32_t r2 = PRN; + uint32_t res = r2 - r1; + res = (res & (~dsp_modulo)) | (r2 & dsp_modulo); + PRES = res; + SET_ZNC_SUB(r2, r1, res); +} + +static void DSP_subqt(void) +{ +#ifdef DSP_DIS_SUBQT + if (doDSPDis) + WriteLog("%06X: SUBQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", DSP_PPC, dsp_convert_zero[PIMM1], PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRN); +#endif + PRES = PRN - dsp_convert_zero[PIMM1]; +#ifdef DSP_DIS_SUBQT + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM2, PRES); +#endif +} + +static void DSP_xor(void) +{ +#ifdef DSP_DIS_XOR + if (doDSPDis) + WriteLog("%06X: XOR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", DSP_PPC, PIMM1, PIMM2, dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRN); +#endif + PRES = PRN ^ PRM; + SET_ZN(PRES); +#ifdef DSP_DIS_XOR + if (doDSPDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", dsp_flag_n, dsp_flag_c, dsp_flag_z, PIMM1, PRM, PIMM2, PRES); +#endif +} diff --git a/waterbox/virtualjaguar/src/dsp.h b/waterbox/virtualjaguar/src/dsp.h new file mode 100644 index 0000000000..e1d77dd704 --- /dev/null +++ b/waterbox/virtualjaguar/src/dsp.h @@ -0,0 +1,43 @@ +// +// dsp.h +// + +#ifndef __DSP_H__ +#define __DSP_H__ + +#include "memory.h" + +#define DSP_CONTROL_RAM_BASE 0x00F1A100 +#define DSP_WORK_RAM_BASE 0x00F1B000 + +void DSPInit(void); +void DSPReset(void); +void DSPExec(int32_t); +void DSPDone(void); +void DSPUpdateRegisterBanks(void); +void DSPHandleIRQs(void); +void DSPSetIRQLine(int irqline, int state); +uint8_t DSPReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t DSPReadWord(uint32_t offset, uint32_t who = UNKNOWN); +uint32_t DSPReadLong(uint32_t offset, uint32_t who = UNKNOWN); +void DSPWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void DSPWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); +void DSPWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN); +void DSPReleaseTimeslice(void); +bool DSPIsRunning(void); + +void DSPExecP(int32_t cycles); +void DSPExecP2(int32_t cycles); +//void DSPExecP3(int32_t cycles); +void DSPExecComp(int32_t cycles); + +// Exported vars + +extern bool doDSPDis; +extern uint32_t dsp_reg_bank_0[], dsp_reg_bank_1[]; + +// DSP interrupt numbers (in $F1A100, bits 4-8 & 16) + +enum { DSPIRQ_CPU = 0, DSPIRQ_SSI, DSPIRQ_TIMER0, DSPIRQ_TIMER1, DSPIRQ_EXT0, DSPIRQ_EXT1 }; + +#endif // __DSP_H__ diff --git a/waterbox/virtualjaguar/src/eeprom.cpp b/waterbox/virtualjaguar/src/eeprom.cpp new file mode 100644 index 0000000000..0c9dcadfae --- /dev/null +++ b/waterbox/virtualjaguar/src/eeprom.cpp @@ -0,0 +1,373 @@ +// +// Jaguar EEPROM handler +// +// by Cal2 +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Cleanups/enhancements by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 01/16/2010 Created this log ;-) +// + +#include "eeprom.h" + +#include +#include // For memset +#include "jaguar.h" +#include "log.h" +#include "settings.h" + +//#define eeprom_LOG + +uint16_t eeprom_ram[64]; +uint16_t cdromEEPROM[64]; +bool eeprom_dirty; + +// +// Private function prototypes +// + +static void EEPROMSave(void); +static void eeprom_set_di(uint32_t state); +static void eeprom_set_cs(uint32_t state); +static uint32_t eeprom_get_do(void); + + +enum { EE_STATE_START = 1, EE_STATE_OP_A, EE_STATE_OP_B, EE_STATE_0, EE_STATE_1, + EE_STATE_2, EE_STATE_3, EE_STATE_0_0, EE_READ_ADDRESS, EE_STATE_0_0_0, + EE_STATE_0_0_1, EE_STATE_0_0_2, EE_STATE_0_0_3, EE_STATE_0_0_1_0, EE_READ_DATA, + EE_STATE_BUSY, EE_STATE_1_0, EE_STATE_1_1, EE_STATE_2_0, EE_STATE_3_0 }; + +// Local global variables + +static uint16_t jerry_ee_state = EE_STATE_START; +static uint16_t jerry_ee_op = 0; +static uint16_t jerry_ee_rstate = 0; +static uint16_t jerry_ee_address_data = 0; +static uint16_t jerry_ee_address_cnt = 6; +static uint16_t jerry_ee_data = 0; +static uint16_t jerry_ee_data_cnt = 16; +static uint16_t jerry_writes_enabled = 0; +static uint16_t jerry_ee_direct_jump = 0; + +static char eeprom_filename[MAX_PATH]; +static char cdromEEPROMFilename[MAX_PATH]; + + +void EepromInit(void) +{ + memset(eeprom_ram, 0xFF, 64 * sizeof(uint16_t)); + memset(cdromEEPROM, 0xFF, 64 * sizeof(uint16_t)); + eeprom_dirty = false; +} + + +void EepromReset(void) +{ +} + + +void EepromDone(void) +{ + WriteLog("EEPROM: Done.\n"); +} + + +static void EEPROMSave(void) +{ + eeprom_dirty = true; +} + + +uint8_t EepromReadByte(uint32_t offset) +{ + switch (offset) + { + case 0xF14001: + return eeprom_get_do(); + case 0xF14801: + break; + case 0xF15001: + eeprom_set_cs(1); + break; +// default: WriteLog("EEPROM: unmapped 0x%.8x\n", offset); break; + } + + return 0x00; +} + + +uint16_t EepromReadWord(uint32_t offset) +{ + return ((uint16_t)EepromReadByte(offset + 0) << 8) | EepromReadByte(offset + 1); +} + + +void EepromWriteByte(uint32_t offset, uint8_t data) +{ + switch (offset) + { + case 0xF14001: + break; + case 0xF14801: + eeprom_set_di(data & 0x01); + break; + case 0xF15001: + eeprom_set_cs(1); + break; +// default: WriteLog("eeprom: unmapped 0x%.8x\n",offset); break; + } +} + + +void EepromWriteWord(uint32_t offset, uint16_t data) +{ + EepromWriteByte(offset + 0, (data >> 8) & 0xFF); + EepromWriteByte(offset + 1, data & 0xFF); +} + + +/* +; +; Commands specific to the National Semiconductor NM93C14 +; +; +; 9-bit commands.. +; 876543210 +eEWDS equ %100000000 ;Erase/Write disable (default) +eWRAL equ %100010000 ;Writes all registers +eERAL equ %100100000 ;Erase all registers +eEWEN equ %100110000 ;Erase/write Enable +eWRITE equ %101000000 ;Write selected register +eREAD equ %110000000 ;read from EEPROM +eERASE equ %111000000 ;Erase selected register +*/ + + +static void eeprom_set_di(uint32_t data) +{ +// WriteLog("eeprom: di=%i\n",data); +// WriteLog("eeprom: state %i\n",jerry_ee_state); + switch (jerry_ee_state) + { + case EE_STATE_START: + jerry_ee_state = EE_STATE_OP_A; + break; + case EE_STATE_OP_A: + jerry_ee_op = (data << 1); + jerry_ee_state = EE_STATE_OP_B; + break; + case EE_STATE_OP_B: + jerry_ee_op |= data; + jerry_ee_direct_jump = 0; +// WriteLog("eeprom: opcode %i\n",jerry_ee_op); + + switch (jerry_ee_op) + { + // Opcode 00: eEWEN, eERAL, eWRAL, eEWNDS + case 0: jerry_ee_state = EE_STATE_0; break; + // Opcode 01: eWRITE (Write selected register) + case 1: jerry_ee_state = EE_STATE_1; break; + // Opcode 10: eREAD (Read from EEPROM) + case 2: jerry_ee_state = EE_STATE_2; break; + // Opcode 11: eERASE (Erase selected register) + case 3: jerry_ee_state = EE_STATE_3; break; + } + + eeprom_set_di(data); + break; + case EE_STATE_0: + jerry_ee_rstate = EE_STATE_0_0; + jerry_ee_state = EE_READ_ADDRESS; + jerry_ee_direct_jump = 1; + jerry_ee_address_cnt = 6; + jerry_ee_address_data = 0; + break; + case EE_STATE_0_0: + switch ((jerry_ee_address_data >> 4) & 0x03) + { + // Opcode 00 00: eEWDS (Erase/Write disable) + case 0: jerry_ee_state=EE_STATE_0_0_0; break; + // Opcode 00 01: eWRAL (Write all registers) + case 1: jerry_ee_state=EE_STATE_0_0_1; break; + // Opcode 00 10: eERAL (Erase all registers) + case 2: jerry_ee_state=EE_STATE_0_0_2; break; + // Opcode 00 11: eEWEN (Erase/Write enable) + case 3: jerry_ee_state=EE_STATE_0_0_3; break; + } + + eeprom_set_di(data); + break; + case EE_STATE_0_0_0: + // writes disable + // WriteLog("eeprom: read only\n"); + jerry_writes_enabled = 0; + jerry_ee_state = EE_STATE_START; + break; + case EE_STATE_0_0_1: + // writes all + jerry_ee_rstate = EE_STATE_0_0_1_0; + jerry_ee_state = EE_READ_DATA; + jerry_ee_data_cnt = 16; + jerry_ee_data = 0; + jerry_ee_direct_jump = 1; + break; + case EE_STATE_0_0_1_0: + // WriteLog("eeprom: filling eeprom with 0x%.4x\n",data); + if (jerry_writes_enabled) + { + for(int i=0; i<64; i++) + eeprom_ram[i] = jerry_ee_data; + + EEPROMSave(); // Save it NOW! + } + + //else + // WriteLog("eeprom: not writing because read only\n"); + jerry_ee_state = EE_STATE_BUSY; + break; + case EE_STATE_0_0_2: + // erase all + //WriteLog("eeprom: erasing eeprom\n"); + if (jerry_writes_enabled) + for(int i=0; i<64; i++) + eeprom_ram[i] = 0xFFFF; + + jerry_ee_state = EE_STATE_BUSY; + break; + case EE_STATE_0_0_3: + // writes enable + //WriteLog("eeprom: read/write\n"); + jerry_writes_enabled = 1; + jerry_ee_state = EE_STATE_START; + break; + case EE_STATE_1: + jerry_ee_rstate = EE_STATE_1_0; + jerry_ee_state = EE_READ_ADDRESS; + jerry_ee_address_cnt = 6; + jerry_ee_address_data = 0; + jerry_ee_direct_jump = 1; + break; + case EE_STATE_1_0: + jerry_ee_rstate = EE_STATE_1_1; + jerry_ee_state = EE_READ_DATA; + jerry_ee_data_cnt = 16; + jerry_ee_data = 0; + jerry_ee_direct_jump = 1; + break; + case EE_STATE_1_1: + //WriteLog("eeprom: writing 0x%.4x at 0x%.2x\n",jerry_ee_data,jerry_ee_address_data); + if (jerry_writes_enabled) + { + eeprom_ram[jerry_ee_address_data] = jerry_ee_data; + EEPROMSave(); // Save it NOW! + } + + jerry_ee_state = EE_STATE_BUSY; + break; + case EE_STATE_2: + jerry_ee_rstate = EE_STATE_2_0; + jerry_ee_state = EE_READ_ADDRESS; + jerry_ee_address_cnt = 6; + jerry_ee_address_data = 0; + jerry_ee_data_cnt = 16; + jerry_ee_data = 0; + break; + case EE_STATE_3: + jerry_ee_rstate = EE_STATE_3_0; + jerry_ee_state = EE_READ_ADDRESS; + jerry_ee_address_cnt = 6; + jerry_ee_address_data = 0; + jerry_ee_direct_jump = 1; + break; + case EE_STATE_3_0: + //WriteLog("eeprom: erasing 0x%.2x\n",jerry_ee_address_data); + if (jerry_writes_enabled) + eeprom_ram[jerry_ee_address_data] = 0xFFFF; + + jerry_ee_state = EE_STATE_BUSY; + break; + case EE_READ_DATA: + //WriteLog("eeprom:\t\t\t%i bit %i\n",data,jerry_ee_data_cnt-1); + jerry_ee_data <<= 1; + jerry_ee_data |= data; + jerry_ee_data_cnt--; + + if (!jerry_ee_data_cnt) + { + jerry_ee_state = jerry_ee_rstate; + + if (jerry_ee_direct_jump) + eeprom_set_di(data); + } + + break; + case EE_READ_ADDRESS: + jerry_ee_address_data <<= 1; + jerry_ee_address_data |= data; + jerry_ee_address_cnt--; +// WriteLog("eeprom:\t%i bits remaining\n",jerry_ee_address_cnt); + + if (!jerry_ee_address_cnt) + { + jerry_ee_state = jerry_ee_rstate; + //WriteLog("eeprom:\t\tread address 0x%.2x\n",jerry_ee_address_data); + + if (jerry_ee_direct_jump) + eeprom_set_di(data); + } + + break; + default: + jerry_ee_state = EE_STATE_OP_A; + } +} + + +static void eeprom_set_cs(uint32_t /*state*/) +{ +// WriteLog("eeprom: cs=%i\n",state); + jerry_ee_state = EE_STATE_START; + jerry_ee_op = 0; + jerry_ee_rstate = 0; + jerry_ee_address_data = 0; + jerry_ee_address_cnt = 6; + jerry_ee_data = 0; + jerry_ee_data_cnt = 16; + jerry_writes_enabled = 1; +} + + +static uint32_t eeprom_get_do(void) +{ + uint16_t data = 1; + + switch (jerry_ee_state) + { + case EE_STATE_START: + data = 1; + break; + case EE_STATE_BUSY: + jerry_ee_state = EE_STATE_START; + data = 0; + break; + case EE_STATE_2_0: + jerry_ee_data_cnt--; + data = (eeprom_ram[jerry_ee_address_data] >> jerry_ee_data_cnt) & 0x01; + + if (!jerry_ee_data_cnt) + { + //WriteLog("eeprom: read 0x%.4x at 0x%.2x cpu %i pc=0x%.8x\n",eeprom_ram[jerry_ee_address_data],jerry_ee_address_data,jaguar_cpu_in_exec,s68000readPC()); + jerry_ee_state = EE_STATE_START; + } + break; + } + +// WriteLog("eeprom: do=%i\n",data); + return data; +} + diff --git a/waterbox/virtualjaguar/src/eeprom.h b/waterbox/virtualjaguar/src/eeprom.h new file mode 100644 index 0000000000..0f89adee3e --- /dev/null +++ b/waterbox/virtualjaguar/src/eeprom.h @@ -0,0 +1,19 @@ +// +// EEPROM.H: Header file +// + +#ifndef __EEPROM_H__ +#define __EEPROM_H__ + +#include + +void EepromInit(void); +void EepromReset(void); +void EepromDone(void); + +uint8_t EepromReadByte(uint32_t offset); +uint16_t EepromReadWord(uint32_t offset); +void EepromWriteByte(uint32_t offset, uint8_t data); +void EepromWriteWord(uint32_t offset, uint16_t data); + +#endif // __EEPROM_H__ diff --git a/waterbox/virtualjaguar/src/event.cpp b/waterbox/virtualjaguar/src/event.cpp new file mode 100644 index 0000000000..56e960d155 --- /dev/null +++ b/waterbox/virtualjaguar/src/event.cpp @@ -0,0 +1,342 @@ +// +// System time handlers +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +// +// STILL TO DO: +// +// - Handling for an event that occurs NOW +// + +#include "event.h" + +#include +#include "log.h" + + +//#define EVENT_LIST_SIZE 512 +#define EVENT_LIST_SIZE 32 + + +// Now, a bit of weirdness: It seems that the number of lines displayed on the screen +// makes the effective refresh rate either 30 or 25 Hz! + +// NOTE ABOUT TIMING SYSTEM DATA STRUCTURES: + +// A queue won't work for this system because we can't guarantee that an event will go +// in with a time that is later than the ones already queued up. So we just use a simple +// list. + +// Although if we used an insertion sort we could, but it wouldn't work for adjusting +// times... (For that, you would have to remove the event then reinsert it.) + +struct Event +{ + bool valid; + int eventType; + double eventTime; + void (* timerCallback)(void); +}; + + +static Event eventList[EVENT_LIST_SIZE]; +static Event eventListJERRY[EVENT_LIST_SIZE]; +static uint32_t nextEvent; +static uint32_t nextEventJERRY; +static uint32_t numberOfEvents; + + +void InitializeEventList(void) +{ + for(uint32_t i=0; i +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 01/16/2010 Created this log ;-) +// JLH 02/28/2010 Added functions to look inside .ZIP files and handle +// contents +// JLH 06/01/2012 Added function to check ZIP file CRCs against file DB +// + +#include "file.h" + +#include +#include +#include "crc32.h" +#include "filedb.h" +#include "eeprom.h" +#include "jaguar.h" +#include "log.h" +#include "memory.h" +#include "universalhdr.h" + +// Private function prototypes +//static int ParseFileType(uint8_t header1, uint8_t header2, uint32_t size); + +// Private variables/enums + + +// +// Jaguar file loading +// We do a more intelligent file analysis here instead of relying on (possible +// false) file extensions which people don't seem to give two shits about +// anyway. :-( +// +bool JaguarLoadFile(uint8_t * buffer, uint32_t size) +{ + jaguarROMSize = size; + + jaguarMainROMCRC32 = crc32_calcCheckSum(buffer, jaguarROMSize); + WriteLog("CRC: %08X\n", (unsigned int)jaguarMainROMCRC32); +// TODO: Check for EEPROM file in ZIP file. If there is no EEPROM in the user's EEPROM +// directory, copy the one from the ZIP file, if it exists. + EepromInit(); + jaguarRunAddress = 0x802000; // For non-BIOS runs, this is true + int fileType = ParseFileType(buffer, jaguarROMSize); + jaguarCartInserted = false; + + if (fileType == JST_ROM) + { + jaguarCartInserted = true; + memcpy(jagMemSpace + 0x800000, buffer, jaguarROMSize); +// Checking something... +jaguarRunAddress = GET32(jagMemSpace, 0x800404); +WriteLog("FILE: Cartridge run address is reported as $%X...\n", jaguarRunAddress); + return true; + } + else if (fileType == JST_ALPINE) + { + // File extension ".ROM": Alpine image that loads/runs at $802000 + WriteLog("FILE: Setting up Alpine ROM... Run address: 00802000, length: %08X\n", jaguarROMSize); + memset(jagMemSpace + 0x800000, 0xFF, 0x2000); + memcpy(jagMemSpace + 0x802000, buffer, jaguarROMSize); + +// Maybe instead of this, we could try requiring the STUBULATOR ROM? Just a thought... + // Try setting the vector to say, $1000 and putting an instruction there that loops forever: + // This kludge works! Yeah! + SET32(jaguarMainRAM, 0x10, 0x00001000); + SET16(jaguarMainRAM, 0x1000, 0x60FE); // Here: bra Here + return true; + } + else if (fileType == JST_ABS_TYPE1) + { + // For ABS type 1, run address == load address + uint32_t loadAddress = GET32(buffer, 0x16), + codeSize = GET32(buffer, 0x02) + GET32(buffer, 0x06); + WriteLog("FILE: Setting up homebrew (ABS-1)... Run address: %08X, length: %08X\n", loadAddress, codeSize); + memcpy(jagMemSpace + loadAddress, buffer + 0x24, codeSize); + jaguarRunAddress = loadAddress; + return true; + } + else if (fileType == JST_ABS_TYPE2) + { + uint32_t loadAddress = GET32(buffer, 0x28), runAddress = GET32(buffer, 0x24), + codeSize = GET32(buffer, 0x18) + GET32(buffer, 0x1C); + WriteLog("FILE: Setting up homebrew (ABS-2)... Run address: %08X, length: %08X\n", runAddress, codeSize); + memcpy(jagMemSpace + loadAddress, buffer + 0xA8, codeSize); + jaguarRunAddress = runAddress; + return true; + } + // NB: This is *wrong* + /* + Basically, if there is no "JAG" at position $1C, then the long there is the load/start + address in LITTLE ENDIAN. + If "JAG" is present, the the next character ("R" or "L") determines the size of the + JagServer command (2 bytes vs. 4). Following that are the commands themselves; + typically it will either be 2 (load) or 3 (load & run). Command headers go like so: + 2: + Load address (long) + Length (long) + payload + 3: + Load address (long) + Length (long) + Run address (long) + payload + 5: (Reset) + [command only] + 7: (Run at address) + Run address (long) + [no payload] + 9: (Clear memory) + Start address (long) + End address (long) + [no payload] + 10: (Poll for commands) + [command only] + 12: (Load & run user program) + filname, terminated with NULL + [no payload] + $FFFF: (Halt) + [no payload] + */ + else if (fileType == JST_JAGSERVER) + { + // This kind of shiaut should be in the detection code below... + // (and now it is! :-) +// if (buffer[0x1C] == 'J' && buffer[0x1D] == 'A' && buffer[0x1E] == 'G') +// { + // Still need to do some checking here for type 2 vs. type 3. This assumes 3 + // Also, JAGR vs. JAGL (word command size vs. long command size) + uint32_t loadAddress = GET32(buffer, 0x22), runAddress = GET32(buffer, 0x2A); + WriteLog("FILE: Setting up homebrew (Jag Server)... Run address: $%X, length: $%X\n", runAddress, jaguarROMSize - 0x2E); + memcpy(jagMemSpace + loadAddress, buffer + 0x2E, jaguarROMSize - 0x2E); + jaguarRunAddress = runAddress; + +// Hmm. Is this kludge necessary? +SET32(jaguarMainRAM, 0x10, 0x00001000); // Set Exception #4 (Illegal Instruction) +SET16(jaguarMainRAM, 0x1000, 0x60FE); // Here: bra Here + + return true; +// } +// else // Special WTFOMGBBQ type here... +// { +// uint32_t loadAddress = (buffer[0x1F] << 24) | (buffer[0x1E] << 16) | (buffer[0x1D] << 8) | buffer[0x1C]; +// WriteLog("FILE: Setting up homebrew (GEMDOS WTFOMGBBQ type)... Run address: $%X, length: $%X\n", loadAddress, jaguarROMSize - 0x20); +// memcpy(jagMemSpace + loadAddress, buffer + 0x20, jaguarROMSize - 0x20); +// jaguarRunAddress = loadAddress; +// return true; +// } + } + else if (fileType == JST_WTFOMGBBQ) + { + uint32_t loadAddress = (buffer[0x1F] << 24) | (buffer[0x1E] << 16) | (buffer[0x1D] << 8) | buffer[0x1C]; + WriteLog("FILE: Setting up homebrew (GEMDOS WTFOMGBBQ type)... Run address: $%X, length: $%X\n", loadAddress, jaguarROMSize - 0x20); + memcpy(jagMemSpace + loadAddress, buffer + 0x20, jaguarROMSize - 0x20); + jaguarRunAddress = loadAddress; + return true; + } + + // We can assume we have JST_NONE at this point. :-P + WriteLog("FILE: Failed to load headerless file.\n"); + return false; +} + + +// +// "Alpine" file loading +// Since the developers were coming after us with torches and pitchforks, we +// decided to allow this kind of thing. ;-) But ONLY FOR THE DEVS, DAMMIT! >:-U +// O_O +// +bool AlpineLoadFile(uint8_t * buffer, uint32_t size) +{ + jaguarROMSize = size; + + jaguarMainROMCRC32 = crc32_calcCheckSum(buffer, jaguarROMSize); + WriteLog("FILE: CRC is %08X\n", (unsigned int)jaguarMainROMCRC32); + EepromInit(); + + jaguarRunAddress = 0x802000; + + WriteLog("FILE: Setting up Alpine ROM with non-standard length... Run address: 00802000, length: %08X\n", jaguarROMSize); + + memset(jagMemSpace + 0x800000, 0xFF, 0x2000); + memcpy(jagMemSpace + 0x802000, buffer, jaguarROMSize); + +// Maybe instead of this, we could try requiring the STUBULATOR ROM? Just a thought... + // Try setting the vector to say, $1000 and putting an instruction there + // that loops forever: + // This kludge works! Yeah! + SET32(jaguarMainRAM, 0x10, 0x00001000); // Set Exception #4 (Illegal Instruction) + SET16(jaguarMainRAM, 0x1000, 0x60FE); // Here: bra Here + + return true; +} + +// +// Parse the file type based upon file size and/or headers. +// +uint32_t ParseFileType(uint8_t * buffer, uint32_t size) +{ + // Check headers first... + + // ABS/COFF type 1 + if (buffer[0] == 0x60 && buffer[1] == 0x1B) + return JST_ABS_TYPE1; + + // ABS/COFF type 2 + if (buffer[0] == 0x01 && buffer[1] == 0x50) + return JST_ABS_TYPE2; + + // Jag Server & other old shite + if (buffer[0] == 0x60 && buffer[1] == 0x1A) + { + if (buffer[0x1C] == 'J' && buffer[0x1D] == 'A' && buffer[0x1E] == 'G') + return JST_JAGSERVER; + else + return JST_WTFOMGBBQ; + } + + // And if that fails, try file sizes... + + // If the file size is divisible by 1M, we probably have an regular ROM. + // We can also check our CRC32 against the internal ROM database to be sure. + // (We also check for the Memory Track cartridge size here as well...) + if ((size % 1048576) == 0 || size == 131072) + return JST_ROM; + + // If the file size + 8192 bytes is divisible by 1M, we probably have an + // Alpine format ROM. + if (((size + 8192) % 1048576) == 0) + return JST_ALPINE; + + // Headerless crap + return JST_NONE; +} + +// +// Check for universal header +// +bool HasUniversalHeader(uint8_t * rom, uint32_t romSize) +{ + // Sanity check + if (romSize < 8192) + return false; + + for(int i=0; i<8192; i++) + if (rom[i] != universalCartHeader[i]) + return false; + + return true; +} + +#if 0 +// Misc. doco + +/* +Stubulator ROM vectors... +handler 001 at $00E00008 +handler 002 at $00E008DE +handler 003 at $00E008E2 +handler 004 at $00E008E6 +handler 005 at $00E008EA +handler 006 at $00E008EE +handler 007 at $00E008F2 +handler 008 at $00E0054A +handler 009 at $00E008FA +handler 010 at $00000000 +handler 011 at $00000000 +handler 012 at $00E008FE +handler 013 at $00E00902 +handler 014 at $00E00906 +handler 015 at $00E0090A +handler 016 at $00E0090E +handler 017 at $00E00912 +handler 018 at $00E00916 +handler 019 at $00E0091A +handler 020 at $00E0091E +handler 021 at $00E00922 +handler 022 at $00E00926 +handler 023 at $00E0092A +handler 024 at $00E0092E +handler 025 at $00E0107A +handler 026 at $00E0107A +handler 027 at $00E0107A +handler 028 at $00E008DA +handler 029 at $00E0107A +handler 030 at $00E0107A +handler 031 at $00E0107A +handler 032 at $00000000 + +Let's try setting up the illegal instruction vector for a stubulated jaguar... + + SET32(jaguar_mainRam, 0x08, 0x00E008DE); + SET32(jaguar_mainRam, 0x0C, 0x00E008E2); + SET32(jaguar_mainRam, 0x10, 0x00E008E6); // <-- Should be here (it is)... + SET32(jaguar_mainRam, 0x14, 0x00E008EA);//*/ + +/* +ABS Format sleuthing (LBUGDEMO.ABS): + +000000 60 1B 00 00 05 0C 00 04 62 C0 00 00 04 28 00 00 +000010 12 A6 00 00 00 00 00 80 20 00 FF FF 00 80 25 0C +000020 00 00 40 00 + +DRI-format file detected... +Text segment size = 0x0000050c bytes +Data segment size = 0x000462c0 bytes +BSS Segment size = 0x00000428 bytes +Symbol Table size = 0x000012a6 bytes +Absolute Address for text segment = 0x00802000 +Absolute Address for data segment = 0x0080250c +Absolute Address for BSS segment = 0x00004000 + +(CRZDEMO.ABS): +000000 01 50 00 03 00 00 00 00 00 03 83 10 00 00 05 3b +000010 00 1c 00 03 00 00 01 07 00 00 1d d0 00 03 64 98 +000020 00 06 8b 80 00 80 20 00 00 80 20 00 00 80 3d d0 + +000030 2e 74 78 74 00 00 00 00 00 80 20 00 00 80 20 00 .txt (+36 bytes) +000040 00 00 1d d0 00 00 00 a8 00 00 00 00 00 00 00 00 +000050 00 00 00 00 00 00 00 20 +000058 2e 64 74 61 00 00 00 00 00 80 3d d0 00 80 3d d0 .dta (+36 bytes) +000068 00 03 64 98 00 00 1e 78 00 00 00 00 00 00 00 00 +000078 00 00 00 00 00 00 00 40 +000080 2e 62 73 73 00 00 00 00 00 00 50 00 00 00 50 00 .bss (+36 bytes) +000090 00 06 8b 80 00 03 83 10 00 00 00 00 00 00 00 00 +0000a0 00 00 00 00 00 00 00 80 + +Header size is $A8 bytes... + +BSD/COFF format file detected... +3 sections specified +Symbol Table offset = 230160 ($00038310) +Symbol Table contains 1339 symbol entries ($0000053B) +The additional header size is 28 bytes ($001C) +Magic Number for RUN_HDR = 0x00000107 +Text Segment Size = 7632 ($00001DD0) +Data Segment Size = 222360 ($00036498) +BSS Segment Size = 428928 ($00068B80) +Starting Address for executable = 0x00802000 +Start of Text Segment = 0x00802000 +Start of Data Segment = 0x00803dd0 +*/ +#endif diff --git a/waterbox/virtualjaguar/src/file.h b/waterbox/virtualjaguar/src/file.h new file mode 100644 index 0000000000..7f6413b6ee --- /dev/null +++ b/waterbox/virtualjaguar/src/file.h @@ -0,0 +1,29 @@ +// +// FILE.H +// +// File support +// + +#ifndef __FILE_H__ +#define __FILE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum FileType { FT_SOFTWARE=0, FT_EEPROM, FT_LABEL, FT_BOXART, FT_OVERLAY }; +// JST = Jaguar Software Type +enum { JST_NONE = 0, JST_ROM, JST_ALPINE, JST_ABS_TYPE1, JST_ABS_TYPE2, JST_JAGSERVER, JST_WTFOMGBBQ }; + +bool JaguarLoadFile(uint8_t * buffer, uint32_t size); +bool AlpineLoadFile(uint8_t * buffer, uint32_t size); +uint32_t ParseFileType(uint8_t * buffer, uint32_t size); +bool HasUniversalHeader(uint8_t * rom, uint32_t romSize); + +#ifdef __cplusplus +} +#endif + +#endif // __FILE_H__ diff --git a/waterbox/virtualjaguar/src/filedb.cpp b/waterbox/virtualjaguar/src/filedb.cpp new file mode 100644 index 0000000000..dd64da5bcf --- /dev/null +++ b/waterbox/virtualjaguar/src/filedb.cpp @@ -0,0 +1,137 @@ +// +// filedb.cpp - File database +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 02/15/2010 Created this file +// + +#include "filedb.h" + + +#if 0 +struct RomIdentifier +{ + const uint32_t crc32; + const char name[128]; +// const uint8_t compatibility; + const uint32_t flags; +}; + +enum FileFlags { FF_ROM=1, FF_ALPINE=2, FF_BIOS=4, FF_REQ_DSP=8, FF_REQ_BIOS=16, FF_NON_WORKING=32, FF_BAD_DUMP=64, FF_VERIFIED=128 }; +#endif + +// Should have another flag for whether or not it requires DSP, BIOS, +// whether it's a .rom, it's a BIOS, etc... +// ... And now we do! :-D + +// How the CRCs work: +// If the cart has an RSA signature, we do a CRC on the whole file. +// If the cart has a universal header, we do a CRC on the file minus the UH. +// This is to ensure that we can detect something properly (like an Alpine ROM) +// that somebody slapped a universal header on. + +RomIdentifier romList[] = { + { 0x0509C85E, "Raiden (World) (alt)", FF_ROM | FF_REQ_BIOS }, + { 0x08849D0F, "Hyper Force (World)", FF_ALPINE | FF_VERIFIED }, + { 0x08F15576, "Iron Soldier (World) (v1.04)", FF_ROM | FF_VERIFIED }, + { 0x0957A072, "Kasumi Ninja (World)", FF_ROM | FF_VERIFIED }, + { 0x0AC83D77, "NBA Jam T.E. (World)", FF_ROM | FF_VERIFIED }, + { 0x0EC5369D, "Evolution - Dino Dudes (World)", FF_ROM | FF_VERIFIED }, + { 0x0F6A1C2C, "Ultra Vortek (World)", FF_ROM | FF_VERIFIED }, + { 0x0FDCEB66, "Brutal Sports Football (World)", FF_ROM | FF_BAD_DUMP }, + { 0x14915F20, "White Men Can't Jump (World)", FF_ROM | FF_VERIFIED }, + { 0x1660F070, "Power Drive Rally (World)", FF_ROM | FF_VERIFIED }, + { 0x1A20C5C4, "Protector (World)", FF_ROM | FF_VERIFIED | FF_REQ_DSP }, + { 0x1E451446, "Trevor McFur in the Crescent Galaxy (World)", FF_ROM | FF_VERIFIED }, + { 0x20936557, "Space War 2000", FF_ALPINE | FF_VERIFIED }, + { 0x27594C6A, "Defender 2000 (World)", FF_ROM | FF_VERIFIED }, + { 0x2BAA92A1, "Space War 2000 (World) (OVERDUMP)", FF_ALPINE }, + { 0x2E17D5DA, "Bubsy in Fractured Furry Tales (World)", FF_ROM | FF_VERIFIED }, + { 0x31812799, "Raiden (World)", FF_ROM | FF_VERIFIED }, + { 0x3241AB6A, "Towers II", FF_ALPINE }, + { 0x348E6449, "Double Dragon V - The Shadow Falls (World)", FF_ROM | FF_VERIFIED }, + { 0x3615AF6A, "Fever Pitch Soccer (World) (En,Fr,De,Es,It)", FF_ROM | FF_VERIFIED }, + { 0x38A130ED, "Troy Aikman NFL Football (World)", FF_ROM | FF_VERIFIED }, + { 0x40E1A1D0, "Air Cars (World)", FF_ROM | FF_VERIFIED }, + { 0x4471BFA0, "Skyhammer (World)", FF_ALPINE | FF_VERIFIED }, + { 0x47EBC158, "Theme Park (World)", FF_ROM | FF_VERIFIED }, + { 0x4899628F, "Hover Strike (World)", FF_ROM | FF_VERIFIED }, + { 0x4A08A2BD, "SuperCross 3D (World)", FF_ROM | FF_BAD_DUMP }, + { 0x544E7A01, "Downfall (World)", FF_ROM | FF_VERIFIED }, + { 0x55A0669C, "[BIOS] Atari Jaguar Developer CD (World)", FF_BIOS }, + { 0x58272540, "Syndicate (World)", FF_ROM | FF_VERIFIED }, + { 0x5A101212, "Sensible Soccer - International Edition (World)", FF_ROM | FF_VERIFIED }, + { 0x5B6BB205, "Ruiner Pinball (World)", FF_ROM | FF_VERIFIED }, + { 0x5CFF14AB, "Pinball Fantasies (World)", FF_ROM | FF_VERIFIED }, + { 0x5DDF9724, "Protector - Special Edition (World)", FF_ALPINE | FF_VERIFIED }, + { 0x5E2CDBC0, "Doom (World)", FF_ROM | FF_VERIFIED | FF_REQ_DSP }, + { 0x5F2C2774, "Battle Sphere (World)", FF_ROM | FF_VERIFIED | FF_REQ_DSP }, + { 0x61C7EEC0, "Zero 5 (World)", FF_ROM | FF_VERIFIED }, + { 0x61EE6B62, "Arena Football '95", FF_ALPINE | FF_VERIFIED }, + { 0x67F9AB3A, "Battle Sphere Gold (World)", FF_ROM | FF_REQ_DSP }, + { 0x687068D5, "[BIOS] Atari Jaguar CD (World)", FF_BIOS }, + { 0x6B2B95AD, "Tempest 2000 (World)", FF_ROM | FF_VERIFIED }, + { 0x6EB774EB, "Worms (World)", FF_ROM | FF_VERIFIED }, + { 0x6F8B2547, "Super Burnout (World)", FF_ROM | FF_VERIFIED }, + { 0x732FFAB6, "Soccer Kid (World)", FF_ROM | FF_VERIFIED }, + { 0x817A2273, "Pitfall - The Mayan Adventure (World)", FF_ROM | FF_VERIFIED }, + { 0x83A3FB5D, "Towers II", FF_ROM | FF_VERIFIED }, + { 0x85919165, "Superfly DX (v1.1)", FF_ROM | FF_VERIFIED }, + { 0x892BC67C, "Flip Out! (World)", FF_ROM | FF_VERIFIED }, + { 0x8975F48B, "Zool 2 (World)", FF_ROM | FF_VERIFIED }, + { 0x89DA21FF, "Phase Zero", FF_ALPINE | FF_VERIFIED | FF_REQ_DSP }, + { 0x8D15DBC6, "[BIOS] Atari Jaguar Stubulator '94 (World)", FF_BIOS }, + { 0x8FEA5AB0, "Dragon - The Bruce Lee Story (World)", FF_ROM | FF_VERIFIED }, + { 0x91095DD3, "Brett Hull Hockey", FF_ROM | FF_VERIFIED }, + { 0x95143668, "Trevor McFur in the Crescent Galaxy (World) (alt)", FF_ROM | FF_VERIFIED }, + { 0x97EB4651, "I-War (World)", FF_ROM | FF_VERIFIED }, + { 0xA0A25A67, "Missile Command VR", FF_ALPINE }, + { 0xA27823D8, "Ultra Vortek (World) (v0.94) (Beta)", FF_ROM }, + { 0xA7E01FEF, "Mad Bodies (2008)", FF_ROM }, + { 0xA9F8A00E, "Rayman (World)", FF_ROM | FF_VERIFIED }, + { 0xAEA9D831, "Barkley Shut Up & Jam", FF_ROM | FF_VERIFIED }, + { 0xB14C4753, "Fight for Life (World)", FF_ROM | FF_VERIFIED }, + { 0xB5604D40, "Breakout 2000", FF_ROM | FF_VERIFIED }, + { 0xBA13AE79, "Soccer Kid (World) (alt)", FF_ALPINE }, + { 0xBCB1A4BF, "Brutal Sports Football (World)", FF_ROM | FF_VERIFIED }, + { 0xBD18D606, "Space War 2000 (World) (alt)", FF_ALPINE }, + { 0xBDA405C6, "Cannon Fodder (World)", FF_ROM | FF_VERIFIED }, + { 0xBDE67498, "Cybermorph (World) (Rev 1)", FF_ROM | FF_VERIFIED | FF_REQ_DSP }, + { 0xC2898F6E, "Barkley Shut Up & Jam (alt)", FF_ALPINE }, + { 0xC36E935E, "Beebris (World)", FF_ALPINE | FF_VERIFIED }, + { 0xC5562581, "Zoop! (World)", FF_ROM | FF_VERIFIED }, + { 0xC654681B, "Total Carnage (World)", FF_ROM | FF_VERIFIED }, + { 0xC6C7BA62, "Fight for Life (World) (alt)", FF_ROM | FF_BAD_DUMP }, + { 0xC9608717, "Val d'Isere Skiing and Snowboarding (World)", FF_ROM | FF_VERIFIED }, + { 0xCBFD822A, "Air Cars (World) (alt)", FF_ROM | FF_BAD_DUMP }, + { 0xCD5BF827, "Attack of the Mutant Penguins (World)", FF_ROM | FF_VERIFIED | FF_REQ_DSP }, + { 0xD6C19E34, "Iron Soldier 2 (World)", FF_ROM | FF_VERIFIED }, + { 0xD8696F23, "Breakout 2000 (alt)", FF_ALPINE }, + { 0xDA9C4162, "Missile Command 3D (World)", FF_ROM | FF_VERIFIED }, + { 0xDC187F82, "Alien vs Predator (World)", FF_ROM | FF_VERIFIED }, + { 0xDCCDEF05, "Brett Hull Hockey", FF_ALPINE }, + { 0xDDFF49F5, "Rayman (Prototype)", FF_ALPINE }, + { 0xDE55DCC7, "Flashback - The Quest for Identity (World) (En,Fr)", FF_ROM | FF_VERIFIED }, + { 0xE28756DE, "Atari Karts (World)", FF_ROM | FF_VERIFIED }, + { 0xE60277BB, "[BIOS] Atari Jaguar Stubulator '93 (World)", FF_BIOS }, + { 0xE91BD644, "Wolfenstein 3D (World)", FF_ROM | FF_VERIFIED }, + { 0xEA9B3FA7, "Phase Zero", FF_ROM | FF_REQ_DSP }, + { 0xEC22F572, "SuperCross 3D (World)", FF_ROM | FF_VERIFIED }, + { 0xECF854E7, "Cybermorph (World) (Rev 2)", FF_ROM | FF_REQ_DSP }, + { 0xEEE8D61D, "Club Drive (World)", FF_ROM | FF_VERIFIED }, + { 0xF4ACBB04, "Tiny Toon Adventures (World)", FF_ROM | FF_VERIFIED }, + { 0xFA7775AE, "Checkered Flag (World)", FF_ROM | FF_VERIFIED }, + { 0xFAE31DD0, "Flip Out! (World) (alt)", FF_ROM }, + { 0xFB731AAA, "[BIOS] Atari Jaguar (World)", FF_BIOS }, +// is this really a BIOS??? +// No, it's really a cart, complete with RSA header. So need to fix so it can load. + { 0xFDF37F47, "Memory Track Cartridge (World)", FF_ROM | FF_VERIFIED }, + { 0xF7756A03, "Tripper Getem (World)", FF_ROM | FF_VERIFIED }, + { 0xFFFFFFFF, "***END***", 0 } +}; diff --git a/waterbox/virtualjaguar/src/filedb.h b/waterbox/virtualjaguar/src/filedb.h new file mode 100644 index 0000000000..f28f5e7c25 --- /dev/null +++ b/waterbox/virtualjaguar/src/filedb.h @@ -0,0 +1,28 @@ +// +// filedb.h: File database definition +// + +#ifndef __FILEDB_H__ +#define __FILEDB_H__ + +#include + +// Useful enumerations + +enum FileFlags { FF_ROM=0x01, FF_ALPINE=0x02, FF_BIOS=0x04, FF_REQ_DSP=0x08, FF_REQ_BIOS=0x10, FF_NON_WORKING=0x20, FF_BAD_DUMP=0x40, FF_VERIFIED=0x80, FF_STARS_1=0x00, FF_STARS_2=0x100, FF_STARS_3=0x200, FF_STARS_4=0x300, FF_STARS_5=0x400 }; + +// Useful structs + +struct RomIdentifier +{ + const uint32_t crc32; + const char name[128]; +// const uint8_t compatibility; + const uint32_t flags; +}; + +// So other stuff can pull this in... + +extern RomIdentifier romList[]; + +#endif // __FILEDB_H__ diff --git a/waterbox/virtualjaguar/src/foooked.h b/waterbox/virtualjaguar/src/foooked.h new file mode 100644 index 0000000000..2ec8d9f866 --- /dev/null +++ b/waterbox/virtualjaguar/src/foooked.h @@ -0,0 +1,14 @@ +//#define FOOOOOKED //Barebones foooked +//#define EXTRA_FOOOOOKED //Leaner +#define POWA_EXTRA_FOOOOOKED //We're into 64-bit territory now! +#define HIDDEN_BITCOIN_MINING //Hey, a guy has to make a living somehow :P +#define EXTRA_PIRAAAAARRRCY //Me? An emulator? Piracy? With MY reputation? Bingo! +//#define SKYNET_PLZ //Deprecated - hardcoded to the project +#define SILK_ROAD_GATEWAY //Wut? +#define HELLO_NSA //Hope my hair is combed when you take my picture! +#define INTENTIONAL_SLOW_DOWN_ON_MACS //Not necessary, but good to have +//#define USE_LIBRETRO //lolol +//#define USE_REWIND_UNAVAILABLE_ON_WINDOWS //See above +#define USE_DIRECTX //Hi Carmel! +#define NYAN //Necessary when SCPCD compiles vj +#define TAKE_BACK_ONE_KADAM //To honour the Hebrew God whose source code this is diff --git a/waterbox/virtualjaguar/src/gpu.cpp b/waterbox/virtualjaguar/src/gpu.cpp new file mode 100644 index 0000000000..9ee426425e --- /dev/null +++ b/waterbox/virtualjaguar/src/gpu.cpp @@ -0,0 +1,2688 @@ +#if 1 + +// +// GPU Core +// +// Originally by David Raingeard (Cal2) +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Cleanups, endian wrongness, and bad ASM amelioration by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 11/26/2011 Added fixes for LOAD/STORE alignment issues + +// +// Note: Endian wrongness probably stems from the MAME origins of this emu and +// the braindead way in which MAME handles memory. :-) +// +// Problem with not booting the BIOS was the incorrect way that the +// SUBC instruction set the carry when the carry was set going in... +// Same problem with ADDC... +// + +#include "gpu.h" + +#include +#include // For memset +#include "dsp.h" +#include "jagdasm.h" +#include "jaguar.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" +#include "tom.h" + + +// Seems alignment in loads & stores was off... +#define GPU_CORRECT_ALIGNMENT +//#define GPU_DEBUG + +// For GPU dissasembly... + +#if 0 +#define GPU_DIS_ABS +#define GPU_DIS_ADD +#define GPU_DIS_ADDC +#define GPU_DIS_ADDQ +#define GPU_DIS_ADDQT +#define GPU_DIS_AND +#define GPU_DIS_BCLR +#define GPU_DIS_BSET +#define GPU_DIS_BTST +#define GPU_DIS_CMP +#define GPU_DIS_CMPQ +#define GPU_DIS_DIV +#define GPU_DIS_IMULT +#define GPU_DIS_JUMP +#define GPU_DIS_JR +#define GPU_DIS_LOAD +#define GPU_DIS_LOADB +#define GPU_DIS_LOADW +#define GPU_DIS_LOAD14I +#define GPU_DIS_LOAD14R +#define GPU_DIS_LOAD15I +#define GPU_DIS_LOAD15R +#define GPU_DIS_MOVE +#define GPU_DIS_MOVEFA +#define GPU_DIS_MOVEI +#define GPU_DIS_MOVEPC +#define GPU_DIS_MOVETA +#define GPU_DIS_MOVEQ +#define GPU_DIS_MULT +#define GPU_DIS_NEG +#define GPU_DIS_NOP +#define GPU_DIS_NOT +#define GPU_DIS_OR +#define GPU_DIS_PACK +#define GPU_DIS_ROR +#define GPU_DIS_RORQ +#define GPU_DIS_SAT8 +#define GPU_DIS_SH +#define GPU_DIS_SHA +#define GPU_DIS_SHARQ +#define GPU_DIS_SHLQ +#define GPU_DIS_SHRQ +#define GPU_DIS_STORE +#define GPU_DIS_STOREB +#define GPU_DIS_STOREW +#define GPU_DIS_STORE14I +#define GPU_DIS_STORE14R +#define GPU_DIS_STORE15I +#define GPU_DIS_STORE15R +#define GPU_DIS_SUB +#define GPU_DIS_SUBC +#define GPU_DIS_SUBQ +#define GPU_DIS_SUBQT +#define GPU_DIS_XOR + +bool doGPUDis = false; +//bool doGPUDis = true; +#endif + +/* +GPU opcodes use (BIOS flying ATARI logo): ++ add 357416 ++ addq 538030 ++ addqt 6999 ++ sub 116663 ++ subq 188059 ++ subqt 15086 ++ neg 36097 ++ and 233993 ++ or 109332 ++ xor 1384 ++ btst 111924 ++ bset 25029 ++ bclr 10551 ++ mult 28147 ++ imult 69148 ++ div 64102 ++ abs 159394 ++ shlq 194690 ++ shrq 292587 ++ sharq 192649 ++ rorq 58672 ++ cmp 244963 ++ cmpq 114834 ++ move 833472 ++ moveq 56427 ++ moveta 220814 ++ movefa 170678 ++ movei 152025 ++ loadw 108220 ++ load 430936 ++ storew 3036 ++ store 372490 ++ move_pc 2330 ++ jump 349134 ++ jr 529171 + mmult 64904 ++ nop 432179 +*/ + +// Various bits + +#define CINT0FLAG 0x0200 +#define CINT1FLAG 0x0400 +#define CINT2FLAG 0x0800 +#define CINT3FLAG 0x1000 +#define CINT4FLAG 0x2000 +#define CINT04FLAGS (CINT0FLAG | CINT1FLAG | CINT2FLAG | CINT3FLAG | CINT4FLAG) + +// GPU_FLAGS bits + +#define ZERO_FLAG 0x0001 +#define CARRY_FLAG 0x0002 +#define NEGA_FLAG 0x0004 +#define IMASK 0x0008 +#define INT_ENA0 0x0010 +#define INT_ENA1 0x0020 +#define INT_ENA2 0x0040 +#define INT_ENA3 0x0080 +#define INT_ENA4 0x0100 +#define INT_CLR0 0x0200 +#define INT_CLR1 0x0400 +#define INT_CLR2 0x0800 +#define INT_CLR3 0x1000 +#define INT_CLR4 0x2000 +#define REGPAGE 0x4000 +#define DMAEN 0x8000 + +// External global variables + +extern int start_logging; +extern int gpu_start_log; + +// Private function prototypes + +void GPUUpdateRegisterBanks(void); +void GPUDumpDisassembly(void); +void GPUDumpRegisters(void); +void GPUDumpMemory(void); + +static void gpu_opcode_add(void); +static void gpu_opcode_addc(void); +static void gpu_opcode_addq(void); +static void gpu_opcode_addqt(void); +static void gpu_opcode_sub(void); +static void gpu_opcode_subc(void); +static void gpu_opcode_subq(void); +static void gpu_opcode_subqt(void); +static void gpu_opcode_neg(void); +static void gpu_opcode_and(void); +static void gpu_opcode_or(void); +static void gpu_opcode_xor(void); +static void gpu_opcode_not(void); +static void gpu_opcode_btst(void); +static void gpu_opcode_bset(void); +static void gpu_opcode_bclr(void); +static void gpu_opcode_mult(void); +static void gpu_opcode_imult(void); +static void gpu_opcode_imultn(void); +static void gpu_opcode_resmac(void); +static void gpu_opcode_imacn(void); +static void gpu_opcode_div(void); +static void gpu_opcode_abs(void); +static void gpu_opcode_sh(void); +static void gpu_opcode_shlq(void); +static void gpu_opcode_shrq(void); +static void gpu_opcode_sha(void); +static void gpu_opcode_sharq(void); +static void gpu_opcode_ror(void); +static void gpu_opcode_rorq(void); +static void gpu_opcode_cmp(void); +static void gpu_opcode_cmpq(void); +static void gpu_opcode_sat8(void); +static void gpu_opcode_sat16(void); +static void gpu_opcode_move(void); +static void gpu_opcode_moveq(void); +static void gpu_opcode_moveta(void); +static void gpu_opcode_movefa(void); +static void gpu_opcode_movei(void); +static void gpu_opcode_loadb(void); +static void gpu_opcode_loadw(void); +static void gpu_opcode_load(void); +static void gpu_opcode_loadp(void); +static void gpu_opcode_load_r14_indexed(void); +static void gpu_opcode_load_r15_indexed(void); +static void gpu_opcode_storeb(void); +static void gpu_opcode_storew(void); +static void gpu_opcode_store(void); +static void gpu_opcode_storep(void); +static void gpu_opcode_store_r14_indexed(void); +static void gpu_opcode_store_r15_indexed(void); +static void gpu_opcode_move_pc(void); +static void gpu_opcode_jump(void); +static void gpu_opcode_jr(void); +static void gpu_opcode_mmult(void); +static void gpu_opcode_mtoi(void); +static void gpu_opcode_normi(void); +static void gpu_opcode_nop(void); +static void gpu_opcode_load_r14_ri(void); +static void gpu_opcode_load_r15_ri(void); +static void gpu_opcode_store_r14_ri(void); +static void gpu_opcode_store_r15_ri(void); +static void gpu_opcode_sat24(void); +static void gpu_opcode_pack(void); + +// This is wrong, since it doesn't take pipeline effects into account. !!! FIX !!! +/*uint8_t gpu_opcode_cycles[64] = +{ + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 1, 3, 1, 18, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 2, 2, 2, 2, 3, 4, + 5, 4, 5, 6, 6, 1, 1, 1, + 1, 2, 2, 2, 1, 1, 9, 3, + 3, 1, 6, 6, 2, 2, 3, 3 +};//*/ +//Here's a QnD kludge... +//This is wrong, wrong, WRONG, but it seems to work for the time being... +//(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!) +//What's needed here is a way to take pipeline effects into account (including pipeline stalls!)... +/*uint8_t gpu_opcode_cycles[64] = +{ + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 9, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 2, + 2, 2, 2, 3, 3, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 4, 1, + 1, 1, 3, 3, 1, 1, 1, 1 +};//*/ +uint8_t gpu_opcode_cycles[64] = +{ + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1 +};//*/ + +void (*gpu_opcode[64])()= +{ + gpu_opcode_add, gpu_opcode_addc, gpu_opcode_addq, gpu_opcode_addqt, + gpu_opcode_sub, gpu_opcode_subc, gpu_opcode_subq, gpu_opcode_subqt, + gpu_opcode_neg, gpu_opcode_and, gpu_opcode_or, gpu_opcode_xor, + gpu_opcode_not, gpu_opcode_btst, gpu_opcode_bset, gpu_opcode_bclr, + gpu_opcode_mult, gpu_opcode_imult, gpu_opcode_imultn, gpu_opcode_resmac, + gpu_opcode_imacn, gpu_opcode_div, gpu_opcode_abs, gpu_opcode_sh, + gpu_opcode_shlq, gpu_opcode_shrq, gpu_opcode_sha, gpu_opcode_sharq, + gpu_opcode_ror, gpu_opcode_rorq, gpu_opcode_cmp, gpu_opcode_cmpq, + gpu_opcode_sat8, gpu_opcode_sat16, gpu_opcode_move, gpu_opcode_moveq, + gpu_opcode_moveta, gpu_opcode_movefa, gpu_opcode_movei, gpu_opcode_loadb, + gpu_opcode_loadw, gpu_opcode_load, gpu_opcode_loadp, gpu_opcode_load_r14_indexed, + gpu_opcode_load_r15_indexed, gpu_opcode_storeb, gpu_opcode_storew, gpu_opcode_store, + gpu_opcode_storep, gpu_opcode_store_r14_indexed, gpu_opcode_store_r15_indexed, gpu_opcode_move_pc, + gpu_opcode_jump, gpu_opcode_jr, gpu_opcode_mmult, gpu_opcode_mtoi, + gpu_opcode_normi, gpu_opcode_nop, gpu_opcode_load_r14_ri, gpu_opcode_load_r15_ri, + gpu_opcode_store_r14_ri, gpu_opcode_store_r15_ri, gpu_opcode_sat24, gpu_opcode_pack, +}; + +static uint8_t gpu_ram_8[0x1000]; +uint32_t gpu_pc; +static uint32_t gpu_acc; +static uint32_t gpu_remain; +static uint32_t gpu_hidata; +static uint32_t gpu_flags; +static uint32_t gpu_matrix_control; +static uint32_t gpu_pointer_to_matrix; +static uint32_t gpu_data_organization; +static uint32_t gpu_control; +static uint32_t gpu_div_control; +// There is a distinct advantage to having these separated out--there's no need +// to clear a bit before writing a result. I.e., if the result of an operation +// leaves a zero in the carry flag, you don't have to zero gpu_flag_c before +// you can write that zero! +static uint8_t gpu_flag_z, gpu_flag_n, gpu_flag_c; +uint32_t gpu_reg_bank_0[32]; +uint32_t gpu_reg_bank_1[32]; +static uint32_t * gpu_reg; +static uint32_t * gpu_alternate_reg; + +static uint32_t gpu_instruction; +static uint32_t gpu_opcode_first_parameter; +static uint32_t gpu_opcode_second_parameter; + +#define GPU_RUNNING (gpu_control & 0x01) + +#define RM gpu_reg[gpu_opcode_first_parameter] +#define RN gpu_reg[gpu_opcode_second_parameter] +#define ALTERNATE_RM gpu_alternate_reg[gpu_opcode_first_parameter] +#define ALTERNATE_RN gpu_alternate_reg[gpu_opcode_second_parameter] +#define IMM_1 gpu_opcode_first_parameter +#define IMM_2 gpu_opcode_second_parameter + +#define SET_FLAG_Z(r) (gpu_flag_z = ((r) == 0)); +#define SET_FLAG_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01)); + +#define RESET_FLAG_Z() gpu_flag_z = 0; +#define RESET_FLAG_N() gpu_flag_n = 0; +#define RESET_FLAG_C() gpu_flag_c = 0; + +#define CLR_Z (gpu_flag_z = 0) +#define CLR_ZN (gpu_flag_z = gpu_flag_n = 0) +#define CLR_ZNC (gpu_flag_z = gpu_flag_n = gpu_flag_c = 0) +#define SET_Z(r) (gpu_flag_z = ((r) == 0)) +#define SET_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01)) +#define SET_C_ADD(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(~(a)))) +#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(a))) +#define SET_ZN(r) SET_N(r); SET_Z(r) +#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) +#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) + +uint32_t gpu_convert_zero[32] = + { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; + +uint8_t * branch_condition_table = 0; +#define BRANCH_CONDITION(x) branch_condition_table[(x) + ((jaguar_flags & 7) << 5)] + +uint32_t gpu_opcode_use[64]; + +const char * gpu_opcode_str[64]= +{ + "add", "addc", "addq", "addqt", + "sub", "subc", "subq", "subqt", + "neg", "and", "or", "xor", + "not", "btst", "bset", "bclr", + "mult", "imult", "imultn", "resmac", + "imacn", "div", "abs", "sh", + "shlq", "shrq", "sha", "sharq", + "ror", "rorq", "cmp", "cmpq", + "sat8", "sat16", "move", "moveq", + "moveta", "movefa", "movei", "loadb", + "loadw", "load", "loadp", "load_r14_indexed", + "load_r15_indexed", "storeb", "storew", "store", + "storep", "store_r14_indexed","store_r15_indexed","move_pc", + "jump", "jr", "mmult", "mtoi", + "normi", "nop", "load_r14_ri", "load_r15_ri", + "store_r14_ri", "store_r15_ri", "sat24", "pack", +}; + +static uint32_t gpu_in_exec = 0; +static uint32_t gpu_releaseTimeSlice_flag = 0; + +void GPUReleaseTimeslice(void) +{ + gpu_releaseTimeSlice_flag = 1; +} + +uint32_t GPUGetPC(void) +{ + return gpu_pc; +} + +void build_branch_condition_table(void) +{ + if (!branch_condition_table) + { + branch_condition_table = (uint8_t *)malloc(32 * 8 * sizeof(branch_condition_table[0])); + + if (branch_condition_table) + { + for(int i=0; i<8; i++) + { + for(int j=0; j<32; j++) + { + int result = 1; + if (j & 1) + if (i & ZERO_FLAG) + result = 0; + if (j & 2) + if (!(i & ZERO_FLAG)) + result = 0; + if (j & 4) + if (i & (CARRY_FLAG << (j >> 4))) + result = 0; + if (j & 8) + if (!(i & (CARRY_FLAG << (j >> 4)))) + result = 0; + branch_condition_table[i * 32 + j] = result; + } + } + } + } +} + +// +// GPU byte access (read) +// +uint8_t GPUReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("GPU: ReadByte--Attempt to read from GPU register file by %s!\n", whoName[who]); + + if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) + return gpu_ram_8[offset & 0xFFF]; + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + { + uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who); + + if ((offset & 0x03) == 0) + return data >> 24; + else if ((offset & 0x03) == 1) + return (data >> 16) & 0xFF; + else if ((offset & 0x03) == 2) + return (data >> 8) & 0xFF; + else if ((offset & 0x03) == 3) + return data & 0xFF; + } + + return JaguarReadByte(offset, who); +} + +// +// GPU word access (read) +// +uint16_t GPUReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("GPU: ReadWord--Attempt to read from GPU register file by %s!\n", whoName[who]); + + if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) + { + offset &= 0xFFF; + uint16_t data = ((uint16_t)gpu_ram_8[offset] << 8) | (uint16_t)gpu_ram_8[offset+1]; + return data; + } + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + { +// This looks and smells wrong... +// But it *might* be OK... + if (offset & 0x01) // Catch cases 1 & 3... (unaligned read) + return (GPUReadByte(offset, who) << 8) | GPUReadByte(offset+1, who); + + uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who); + + if (offset & 0x02) // Cases 0 & 2... + return data & 0xFFFF; + else + return data >> 16; + } + +//TEMP--Mirror of F03000? No. Writes only... +//if (offset >= 0xF0B000 && offset <= 0xF0BFFF) +//WriteLog("[GPUR16] --> Possible GPU RAM mirror access by %s!", whoName[who]); + + return JaguarReadWord(offset, who); +} + +// +// GPU dword access (read) +// +uint32_t GPUReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + { + WriteLog("GPU: ReadLong--Attempt to read from GPU register file (%X) by %s!\n", offset, whoName[who]); + uint32_t reg = (offset & 0xFC) >> 2; + return (reg < 32 ? gpu_reg_bank_0[reg] : gpu_reg_bank_1[reg - 32]); + } + +// if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE + 0x1000)) + if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC)) + { + offset &= 0xFFF; + return ((uint32_t)gpu_ram_8[offset] << 24) | ((uint32_t)gpu_ram_8[offset+1] << 16) + | ((uint32_t)gpu_ram_8[offset+2] << 8) | (uint32_t)gpu_ram_8[offset+3];//*/ +// return GET32(gpu_ram_8, offset); + } +// else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1C)) + { + offset &= 0x1F; + switch (offset) + { + case 0x00: + gpu_flag_c = (gpu_flag_c ? 1 : 0); + gpu_flag_z = (gpu_flag_z ? 1 : 0); + gpu_flag_n = (gpu_flag_n ? 1 : 0); + + gpu_flags = (gpu_flags & 0xFFFFFFF8) | (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; + + return gpu_flags & 0xFFFFC1FF; + case 0x04: + return gpu_matrix_control; + case 0x08: + return gpu_pointer_to_matrix; + case 0x0C: + return gpu_data_organization; + case 0x10: + return gpu_pc; + case 0x14: + return gpu_control; + case 0x18: + return gpu_hidata; + case 0x1C: + return gpu_remain; + default: // unaligned long read +#ifdef GPU_DEBUG + WriteLog("GPU: Read32--unaligned 32 bit read at %08X by %s.\n", GPU_CONTROL_RAM_BASE + offset, whoName[who]); +#endif // GPU_DEBUG + return 0; + } + } +//TEMP--Mirror of F03000? No. Writes only... +//if (offset >= 0xF0B000 && offset <= 0xF0BFFF) +// WriteLog("[GPUR32] --> Possible GPU RAM mirror access by %s!\n", whoName[who]); +/*if (offset >= 0xF1D000 && offset <= 0xF1DFFF) + WriteLog("[GPUR32] --> Reading from Wavetable ROM!\n");//*/ + + return (JaguarReadWord(offset, who) << 16) | JaguarReadWord(offset + 2, who); +} + +// +// GPU byte access (write) +// +void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("GPU: WriteByte--Attempt to write to GPU register file by %s!\n", whoName[who]); + + if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFF)) + { + gpu_ram_8[offset & 0xFFF] = data; + +//This is the same stupid worthless code that was in the DSP!!! AARRRGGGGHHHHH!!!!!! +/* if (!gpu_in_exec) + { + m68k_end_timeslice(); + dsp_releaseTimeslice(); + }*/ + return; + } + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1F)) + { + uint32_t reg = offset & 0x1C; + int bytenum = offset & 0x03; + +//This is definitely wrong! + if ((reg >= 0x1C) && (reg <= 0x1F)) + gpu_div_control = (gpu_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); + else + { + uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who); + bytenum = 3 - bytenum; // convention motorola !!! + old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3)); + GPUWriteLong(offset & 0xFFFFFFC, old_data, who); + } + return; + } +// WriteLog("gpu: writing %.2x at 0x%.8x\n",data,offset); + JaguarWriteByte(offset, data, who); +} + +// +// GPU word access (write) +// +void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("GPU: WriteWord--Attempt to write to GPU register file by %s!\n", whoName[who]); + + if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFE)) + { + gpu_ram_8[offset & 0xFFF] = (data>>8) & 0xFF; + gpu_ram_8[(offset+1) & 0xFFF] = data & 0xFF;//*/ +/* offset &= 0xFFF; + SET16(gpu_ram_8, offset, data);//*/ + +/*if (offset >= 0xF03214 && offset < 0xF0321F) + WriteLog("GPU: Writing WORD (%04X) to GPU RAM (%08X)...\n", data, offset);//*/ + + +//This is the same stupid worthless code that was in the DSP!!! AARRRGGGGHHHHH!!!!!! +/* if (!gpu_in_exec) + { + m68k_end_timeslice(); + dsp_releaseTimeslice(); + }*/ + return; + } + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1E)) + { + if (offset & 0x01) // This is supposed to weed out unaligned writes, but does nothing... + { +#ifdef GPU_DEBUG + WriteLog("GPU: Write16--unaligned write @ %08X [%04X]\n", offset, data); + GPUDumpRegisters(); +#endif // GPU_DEBUG + return; + } +//Dual locations in this range: $1C Divide unit remainder/Divide unit control (R/W) +//This just literally sucks. + if ((offset & 0x1C) == 0x1C) + { +//This doesn't look right either--handles cases 1, 2, & 3 all the same! + if (offset & 0x02) + gpu_div_control = (gpu_div_control & 0xFFFF0000) | (data & 0xFFFF); + else + gpu_div_control = (gpu_div_control & 0x0000FFFF) | ((data & 0xFFFF) << 16); + } + else + { +//WriteLog("[GPU W16:%08X,%04X]", offset, data); + uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who); + + if (offset & 0x02) + old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF); + else + old_data = (old_data & 0x0000FFFF) | ((data & 0xFFFF) << 16); + + GPUWriteLong(offset & 0xFFFFFFC, old_data, who); + } + + return; + } + else if ((offset == GPU_WORK_RAM_BASE + 0x0FFF) || (GPU_CONTROL_RAM_BASE + 0x1F)) + { +#ifdef GPU_DEBUG + WriteLog("GPU: Write16--unaligned write @ %08X by %s [%04X]!\n", offset, whoName[who], data); + GPUDumpRegisters(); +#endif // GPU_DEBUG + return; + } + + // Have to be careful here--this can cause an infinite loop! + JaguarWriteWord(offset, data, who); +} + +// +// GPU dword access (write) +// +void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) +{ + if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("GPU: WriteLong--Attempt to write to GPU register file by %s!\n", whoName[who]); + +// if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE + 0x1000)) + if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC)) + { +#ifdef GPU_DEBUG + if (offset & 0x03) + { + WriteLog("GPU: Write32--unaligned write @ %08X [%08X] by %s\n", offset, data, whoName[who]); + GPUDumpRegisters(); + } +#endif // GPU_DEBUG + + offset &= 0xFFF; + SET32(gpu_ram_8, offset, data); + return; + } +// else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1C)) + { + offset &= 0x1F; + switch (offset) + { + case 0x00: + { + bool IMASKCleared = (gpu_flags & IMASK) && !(data & IMASK); + // NOTE: According to the JTRM, writing a 1 to IMASK has no effect; only the + // IRQ logic can set it. So we mask it out here to prevent problems... + gpu_flags = data & (~IMASK); + gpu_flag_z = gpu_flags & ZERO_FLAG; + gpu_flag_c = (gpu_flags & CARRY_FLAG) >> 1; + gpu_flag_n = (gpu_flags & NEGA_FLAG) >> 2; + GPUUpdateRegisterBanks(); + gpu_control &= ~((gpu_flags & CINT04FLAGS) >> 3); // Interrupt latch clear bits +//Writing here is only an interrupt enable--this approach is just plain wrong! +// GPUHandleIRQs(); +//This, however, is A-OK! ;-) + if (IMASKCleared) // If IMASK was cleared, + GPUHandleIRQs(); // see if any other interrupts need servicing! +#ifdef GPU_DEBUG + if (gpu_flags & (INT_ENA0 | INT_ENA1 | INT_ENA2 | INT_ENA3 | INT_ENA4)) + WriteLog("GPU: Interrupt enable set by %s! Bits: %02X\n", whoName[who], (gpu_flags >> 4) & 0x1F); + WriteLog("GPU: REGPAGE %s...\n", (gpu_flags & REGPAGE ? "set" : "cleared")); +#endif // GPU_DEBUG + break; + } + case 0x04: + gpu_matrix_control = data; + break; + case 0x08: + // This can only point to long aligned addresses + gpu_pointer_to_matrix = data & 0xFFFFFFFC; + break; + case 0x0C: + gpu_data_organization = data; + break; + case 0x10: + gpu_pc = data; +#ifdef GPU_DEBUG +WriteLog("GPU: %s setting GPU PC to %08X %s\n", whoName[who], gpu_pc, (GPU_RUNNING ? "(GPU is RUNNING!)" : ""));//*/ +#endif // GPU_DEBUG + break; + case 0x14: + { +// uint32_t gpu_was_running = GPU_RUNNING; + data &= ~0xF7C0; // Disable writes to INT_LAT0-4 & TOM version number + + // check for GPU -> CPU interrupt + if (data & 0x02) + { +//WriteLog("GPU->CPU interrupt\n"); + if (TOMIRQEnabled(IRQ_GPU)) + { +//This is the programmer's responsibility, to make sure the handler is valid, not ours! +// if ((TOMIRQEnabled(IRQ_GPU))// && (JaguarInterruptHandlerIsValid(64))) + { + TOMSetPendingGPUInt(); + m68k_set_irq(2); // Set 68000 IPL 2 + GPUReleaseTimeslice(); + } + } + data &= ~0x02; + } + + // check for CPU -> GPU interrupt #0 + if (data & 0x04) + { +//WriteLog("CPU->GPU interrupt\n"); + GPUSetIRQLine(0, ASSERT_LINE); + m68k_end_timeslice(); + DSPReleaseTimeslice(); + data &= ~0x04; + } + + // single stepping + if (data & 0x10) + { + //WriteLog("asked to perform a single step (single step is %senabled)\n",(data&0x8)?"":"not "); + } + + gpu_control = (gpu_control & 0xF7C0) | (data & (~0xF7C0)); + + // if gpu wasn't running but is now running, execute a few cycles +#ifndef GPU_SINGLE_STEPPING +/* if (!gpu_was_running && GPU_RUNNING) +#ifdef GPU_DEBUG + { + WriteLog("GPU: Write32--About to do stupid braindead GPU execution for 200 cycles.\n"); +#endif // GPU_DEBUG + GPUExec(200); +#ifdef GPU_DEBUG + } +#endif // GPU_DEBUG//*/ +#else + if (gpu_control & 0x18) + GPUExec(1); +#endif // #ifndef GPU_SINGLE_STEPPING +#ifdef GPU_DEBUG +WriteLog("Write to GPU CTRL by %s: %08X ", whoName[who], data); +if (GPU_RUNNING) + WriteLog(" --> Starting to run at %08X by %s...", gpu_pc, whoName[who]); +else + WriteLog(" --> Stopped by %s! (GPU_PC: %08X)", whoName[who], gpu_pc); +WriteLog("\n"); +#endif // GPU_DEBUG +//if (GPU_RUNNING) +// GPUDumpDisassembly(); +/*if (GPU_RUNNING) +{ + if (gpu_pc == 0xF035D8) + { +// GPUDumpDisassembly(); +// log_done(); +// exit(1); + gpu_control &= 0xFFFFFFFE; // Don't run it and let's see what happens! +//Hmm. Seems to lock up when going into the demo... +//Try to disable the collision altogether! + } +}//*/ +extern int effect_start5; +static bool finished = false; +//if (GPU_RUNNING && effect_start5 && !finished) +if (GPU_RUNNING && effect_start5 && gpu_pc == 0xF035D8) +{ + // Let's do a dump of $6528! +/* uint32_t numItems = JaguarReadWord(0x6BD6); + WriteLog("\nDump of $6528: %u items.\n\n", numItems); + for(int i=0; i ", 0x6528+i, JaguarReadLong(0x6528+i), + JaguarReadLong(0x6528+i+4), JaguarReadLong(0x6528+i+8)); + uint16_t link = JaguarReadWord(0x6528+i+8+2); + for(int j=0; j<40; j+=4) + WriteLog("%08X ", JaguarReadLong(link + j)); + WriteLog("\n"); + } + WriteLog("\n");//*/ + // Let's try a manual blit here... +//This isn't working the way it should! !!! FIX !!! +//Err, actually, it is. +// NOW, it works right! Problem solved!!! It's a blitter bug! +/* uint32_t src = 0x4D54, dst = 0xF03000, width = 10 * 4; + for(int y=0; y<127; y++) + { + for(int x=0; x<2; x++) + { + JaguarWriteLong(dst, JaguarReadLong(src)); + + src += 4; + dst += 4; + } + src += width - (2 * 4); + }//*/ +/* finished = true; + doGPUDis = true; + WriteLog("\nGPU: About to execute collision detection code.\n\n");//*/ + +/* WriteLog("\nGPU: About to execute collision detection code. Data @ 4D54:\n\n"); + int count = 0; + for(int i=0x004D54; i<0x004D54+2048; i++) + { + WriteLog("%02X ", JaguarReadByte(i)); + count++; + if (count == 32) + { + count = 0; + WriteLog("\n"); + } + } + WriteLog("\n\nData @ F03000:\n\n"); + count = 0; + for(int i=0xF03000; i<0xF03200; i++) + { + WriteLog("%02X ", JaguarReadByte(i)); + count++; + if (count == 32) + { + count = 0; + WriteLog("\n"); + } + } + WriteLog("\n\n"); + log_done(); + exit(0);//*/ +} +//if (!GPU_RUNNING) +// doGPUDis = false; +/*if (!GPU_RUNNING && finished) +{ + WriteLog("\nGPU: Finished collision detection code. Exiting!\n\n"); + GPUDumpRegisters(); + log_done(); + exit(0); +}//*/ + // (?) If we're set running by the M68K (or DSP?) then end its timeslice to + // allow the GPU a chance to run... + // Yes! This partially fixed Trevor McFur... + if (GPU_RUNNING) + m68k_end_timeslice(); + break; + } + case 0x18: + gpu_hidata = data; + break; + case 0x1C: + gpu_div_control = data; + break; +// default: // unaligned long write + //exit(0); + //__asm int 3 + } + return; + } + +// JaguarWriteWord(offset, (data >> 16) & 0xFFFF, who); +// JaguarWriteWord(offset+2, data & 0xFFFF, who); +// We're a 32-bit processor, we can do a long write...! + JaguarWriteLong(offset, data, who); +} + +// +// Change register banks if necessary +// +void GPUUpdateRegisterBanks(void) +{ + int bank = (gpu_flags & REGPAGE); // REGPAGE bit + + if (gpu_flags & IMASK) // IMASK bit + bank = 0; // IMASK forces main bank to be bank 0 + + if (bank) + gpu_reg = gpu_reg_bank_1, gpu_alternate_reg = gpu_reg_bank_0; + else + gpu_reg = gpu_reg_bank_0, gpu_alternate_reg = gpu_reg_bank_1; +} + +void GPUHandleIRQs(void) +{ + // Bail out if we're already in an interrupt! + if (gpu_flags & IMASK) + return; + + // Get the interrupt latch & enable bits + uint32_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; + + // Bail out if latched interrupts aren't enabled + bits &= mask; + if (!bits) + return; + + // Determine which interrupt to service + uint32_t which = 0; //Isn't there a #pragma to disable this warning??? + if (bits & 0x01) + which = 0; + if (bits & 0x02) + which = 1; + if (bits & 0x04) + which = 2; + if (bits & 0x08) + which = 3; + if (bits & 0x10) + which = 4; + + if (start_logging) + WriteLog("GPU: Generating IRQ #%i\n", which); + + // set the interrupt flag + gpu_flags |= IMASK; + GPUUpdateRegisterBanks(); + + // subqt #4,r31 ; pre-decrement stack pointer + // move pc,r30 ; address of interrupted code + // store r30,(r31) ; store return address + gpu_reg[31] -= 4; + GPUWriteLong(gpu_reg[31], gpu_pc - 2, GPU); + + // movei #service_address,r30 ; pointer to ISR entry + // jump (r30) ; jump to ISR + // nop + gpu_pc = gpu_reg[30] = GPU_WORK_RAM_BASE + (which * 0x10); +} + +void GPUSetIRQLine(int irqline, int state) +{ + if (start_logging) + WriteLog("GPU: Setting GPU IRQ line #%i\n", irqline); + + uint32_t mask = 0x0040 << irqline; + gpu_control &= ~mask; // Clear the interrupt latch + + if (state) + { + gpu_control |= mask; // Assert the interrupt latch + GPUHandleIRQs(); // And handle the interrupt... + } +} + +//TEMPORARY: Testing only! +//#include "gpu2.h" +//#include "gpu3.h" + +void GPUInit(void) +{ +// memory_malloc_secure((void **)&gpu_ram_8, 0x1000, "GPU work RAM"); +// memory_malloc_secure((void **)&gpu_reg_bank_0, 32 * sizeof(int32_t), "GPU bank 0 regs"); +// memory_malloc_secure((void **)&gpu_reg_bank_1, 32 * sizeof(int32_t), "GPU bank 1 regs"); + + build_branch_condition_table(); + + GPUReset(); + +//TEMPORARY: Testing only! +// gpu2_init(); +// gpu3_init(); +} + +void GPUReset(void) +{ + // GPU registers (directly visible) + gpu_flags = 0x00000000; + gpu_matrix_control = 0x00000000; + gpu_pointer_to_matrix = 0x00000000; + gpu_data_organization = 0xFFFFFFFF; + gpu_pc = 0x00F03000; + gpu_control = 0x00002800; // Correctly sets this as TOM Rev. 2 + gpu_hidata = 0x00000000; + gpu_remain = 0x00000000; // These two registers are RO/WO + gpu_div_control = 0x00000000; + + // GPU internal register + gpu_acc = 0x00000000; + + gpu_reg = gpu_reg_bank_0; + gpu_alternate_reg = gpu_reg_bank_1; + + for(int i=0; i<32; i++) + gpu_reg[i] = gpu_alternate_reg[i] = 0x00000000; + + CLR_ZNC; + memset(gpu_ram_8, 0xFF, 0x1000); + gpu_in_exec = 0; +//not needed GPUInterruptPending = false; + GPUResetStats(); + + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32_t i=0; i<4096; i+=4) + *((uint32_t *)(&gpu_ram_8[i])) = rand(); +} + + +uint32_t GPUReadPC(void) +{ + return gpu_pc; +} + + +void GPUResetStats(void) +{ + for(uint32_t i=0; i<64; i++) + gpu_opcode_use[i] = 0; + WriteLog("--> GPU stats were reset!\n"); +} + + +void GPUDumpDisassembly(void) +{ + char buffer[512]; + + WriteLog("\n---[GPU code at 00F03000]---------------------------\n"); + uint32_t j = 0xF03000; + while (j <= 0xF03FFF) + { + uint32_t oldj = j; + j += dasmjag(JAGUAR_GPU, buffer, j); + WriteLog("\t%08X: %s\n", oldj, buffer); + } +} + + +void GPUDumpRegisters(void) +{ + WriteLog("\n---[GPU flags: NCZ %d%d%d]-----------------------\n", gpu_flag_n, gpu_flag_c, gpu_flag_z); + WriteLog("\nRegisters bank 0\n"); + for(int j=0; j<8; j++) + { + WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", + (j << 2) + 0, gpu_reg_bank_0[(j << 2) + 0], + (j << 2) + 1, gpu_reg_bank_0[(j << 2) + 1], + (j << 2) + 2, gpu_reg_bank_0[(j << 2) + 2], + (j << 2) + 3, gpu_reg_bank_0[(j << 2) + 3]); + } + WriteLog("Registers bank 1\n"); + for(int j=0; j<8; j++) + { + WriteLog("\tR%02i = %08X R%02i = %08X R%02i = %08X R%02i = %08X\n", + (j << 2) + 0, gpu_reg_bank_1[(j << 2) + 0], + (j << 2) + 1, gpu_reg_bank_1[(j << 2) + 1], + (j << 2) + 2, gpu_reg_bank_1[(j << 2) + 2], + (j << 2) + 3, gpu_reg_bank_1[(j << 2) + 3]); + } +} + + +void GPUDumpMemory(void) +{ + WriteLog("\n---[GPU data at 00F03000]---------------------------\n"); + for(int i=0; i<0xFFF; i+=4) + WriteLog("\t%08X: %02X %02X %02X %02X\n", 0xF03000+i, gpu_ram_8[i], + gpu_ram_8[i+1], gpu_ram_8[i+2], gpu_ram_8[i+3]); +} + + +void GPUDone(void) +{ + WriteLog("\n\n---------------------------------------------------------------------\n"); + WriteLog("GPU I/O Registers\n"); + WriteLog("---------------------------------------------------------------------\n"); + WriteLog("F0%04X (G_FLAGS): $%06X\n", 0x2100, (gpu_flags & 0xFFFFFFF8) | (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z); + WriteLog("F0%04X (G_MTXC): $%04X\n", 0x2104, gpu_matrix_control); + WriteLog("F0%04X (G_MTXA): $%04X\n", 0x2108, gpu_pointer_to_matrix); + WriteLog("F0%04X (G_END): $%02X\n", 0x210C, gpu_data_organization); + WriteLog("F0%04X (G_PC): $%06X\n", 0x2110, gpu_pc); + WriteLog("F0%04X (G_CTRL): $%06X\n", 0x2114, gpu_control); + WriteLog("F0%04X (G_HIDATA): $%08X\n", 0x2118, gpu_hidata); + WriteLog("F0%04X (G_REMAIN): $%08X\n", 0x211C, gpu_remain); + WriteLog("F0%04X (G_DIVCTRL): $%02X\n", 0x211C, gpu_div_control); + WriteLog("---------------------------------------------------------------------\n\n\n"); + + WriteLog("GPU: Stopped at PC=%08X (GPU %s running)\n", (unsigned int)gpu_pc, GPU_RUNNING ? "was" : "wasn't"); + + // Get the interrupt latch & enable bits + uint8_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F; + WriteLog("GPU: Latch bits = %02X, enable bits = %02X\n", bits, mask); + + GPUDumpRegisters(); + GPUDumpDisassembly(); + + WriteLog("\nGPU opcodes use:\n"); + for(int i=0; i<64; i++) + { + if (gpu_opcode_use[i]) + WriteLog("\t%17s %lu\n", gpu_opcode_str[i], gpu_opcode_use[i]); + } + WriteLog("\n"); +} + + +// +// Main GPU execution core +// +static int testCount = 1; +static int len = 0; +static bool tripwire = false; +void GPUExec(int32_t cycles) +{ + if (!GPU_RUNNING) + return; + +#ifdef GPU_SINGLE_STEPPING + if (gpu_control & 0x18) + { + cycles = 1; + gpu_control &= ~0x10; + } +#endif + GPUHandleIRQs(); + gpu_releaseTimeSlice_flag = 0; + gpu_in_exec++; + + while (cycles > 0 && GPU_RUNNING) + { +if (gpu_ram_8[0x054] == 0x98 && gpu_ram_8[0x055] == 0x0A && gpu_ram_8[0x056] == 0x03 + && gpu_ram_8[0x057] == 0x00 && gpu_ram_8[0x058] == 0x00 && gpu_ram_8[0x059] == 0x00) +{ + if (gpu_pc == 0xF03000) + { + extern uint32_t starCount; + starCount = 0; +/* WriteLog("GPU: Starting starfield generator... Dump of [R03=%08X]:\n", gpu_reg_bank_0[03]); + uint32_t base = gpu_reg_bank_0[3]; + for(uint32_t i=0; i<0x100; i+=16) + { + WriteLog("%02X: ", i); + for(uint32_t j=0; j<16; j++) + { + WriteLog("%02X ", JaguarReadByte(base + i + j)); + } + WriteLog("\n"); + }*/ + } +// if (gpu_pc == 0xF03) + { + } +}//*/ +/*if (gpu_pc == 0xF03B9E && gpu_reg_bank_0[01] == 0) +{ + GPUDumpRegisters(); + WriteLog("GPU: Starting disassembly log...\n"); + doGPUDis = true; +}//*/ +/*if (gpu_pc == 0xF0359A) +{ + doGPUDis = true; + GPUDumpRegisters(); +}*/ +/* gpu_flag_c = (gpu_flag_c ? 1 : 0); + gpu_flag_z = (gpu_flag_z ? 1 : 0); + gpu_flag_n = (gpu_flag_n ? 1 : 0);*/ +#if 0 +if (gpu_pc == 0xF03200) + doGPUDis = true; +#endif + + uint16_t opcode = GPUReadWord(gpu_pc, GPU); + uint32_t index = opcode >> 10; + gpu_instruction = opcode; // Added for GPU #3... + gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; + gpu_opcode_second_parameter = opcode & 0x1F; +/*if (gpu_pc == 0xF03BE8) +WriteLog("Start of OP frame write...\n"); +if (gpu_pc == 0xF03EEE) +WriteLog("--> Writing BRANCH object ---\n"); +if (gpu_pc == 0xF03F62) +WriteLog("--> Writing BITMAP object ***\n");//*/ +/*if (gpu_pc == 0xF03546) +{ + WriteLog("\n--> GPU PC: F03546\n"); + GPUDumpRegisters(); + GPUDumpDisassembly(); +}//*/ +/*if (gpu_pc == 0xF033F6) +{ + WriteLog("\n--> GPU PC: F033F6\n"); + GPUDumpRegisters(); + GPUDumpDisassembly(); +}//*/ +/*if (gpu_pc == 0xF033CC) +{ + WriteLog("\n--> GPU PC: F033CC\n"); + GPUDumpRegisters(); + GPUDumpDisassembly(); +}//*/ +/*if (gpu_pc == 0xF033D6) +{ + WriteLog("\n--> GPU PC: F033D6 (#%d)\n", testCount++); + GPUDumpRegisters(); + GPUDumpMemory(); +}//*/ +/*if (gpu_pc == 0xF033D8) +{ + WriteLog("\n--> GPU PC: F033D8 (#%d)\n", testCount++); + GPUDumpRegisters(); + GPUDumpMemory(); +}//*/ +/*if (gpu_pc == 0xF0358E) +{ + WriteLog("\n--> GPU PC: F0358E (#%d)\n", testCount++); + GPUDumpRegisters(); + GPUDumpMemory(); +}//*/ +/*if (gpu_pc == 0xF034CA) +{ + WriteLog("\n--> GPU PC: F034CA (#%d)\n", testCount++); + GPUDumpRegisters(); +}//*/ +/*if (gpu_pc == 0xF034CA) +{ + len = gpu_reg[1] + 4;//, r9save = gpu_reg[9]; + WriteLog("\nAbout to subtract [#%d] (R14=%08X, R15=%08X, R9=%08X):\n ", testCount++, gpu_reg[14], gpu_reg[15], gpu_reg[9]); + for(int i=0; i GPU PC: F035C8 (#%d)\n", testCount++); + GPUDumpRegisters(); + GPUDumpDisassembly(); +}//*/ + +if (gpu_start_log) +{ +// gpu_reset_stats(); +static char buffer[512]; +dasmjag(JAGUAR_GPU, buffer, gpu_pc); +WriteLog("GPU: [%08X] %s (RM=%08X, RN=%08X) -> ", gpu_pc, buffer, RM, RN); +}//*/ +//$E400 -> 1110 01 -> $39 -> 57 +//GPU #1 + gpu_pc += 2; + gpu_opcode[index](); +//GPU #2 +// gpu2_opcode[index](); +// gpu_pc += 2; +//GPU #3 (Doesn't show ATARI logo! #1 & #2 do...) +// gpu_pc += 2; +// gpu3_opcode[index](); + +// BIOS hacking +//GPU: [00F03548] jr nz,00F03560 (0xd561) (RM=00F03114, RN=00000004) -> --> JR: Branch taken. +/*static bool firstTime = true; +if (gpu_pc == 0xF03548 && firstTime) +{ + gpu_flag_z = 1; +// firstTime = false; + +//static char buffer[512]; +//int k=0xF03548; +//while (k<0xF0356C) +//{ +//int oldk = k; +//k += dasmjag(JAGUAR_GPU, buffer, k); +//WriteLog("GPU: [%08X] %s\n", oldk, buffer); +//} +// gpu_start_log = 1; +}//*/ +//GPU: [00F0354C] jump nz,(r29) (0xd3a1) (RM=00F03314, RN=00000004) -> (RM=00F03314, RN=00000004) +/*if (gpu_pc == 0xF0354C) + gpu_flag_z = 0;//, gpu_start_log = 1;//*/ + + cycles -= gpu_opcode_cycles[index]; + gpu_opcode_use[index]++; +if (gpu_start_log) + WriteLog("(RM=%08X, RN=%08X)\n", RM, RN);//*/ +if ((gpu_pc < 0xF03000 || gpu_pc > 0xF03FFF) && !tripwire) +{ + WriteLog("GPU: Executing outside local RAM! GPU_PC: %08X\n", gpu_pc); + tripwire = true; +} + } + + gpu_in_exec--; +} + +// +// GPU opcodes +// + +/* +GPU opcodes use (offset punch--vertically below bad guy): + add 18686 + addq 32621 + sub 7483 + subq 10252 + and 21229 + or 15003 + btst 1822 + bset 2072 + mult 141 + div 2392 + shlq 13449 + shrq 10297 + sharq 11104 + cmp 6775 + cmpq 5944 + move 31259 + moveq 4473 + movei 23277 + loadb 46 + loadw 4201 + load 28580 + load_r14_indexed 1183 + load_r15_indexed 1125 + storew 178 + store 10144 + store_r14_indexed 320 + store_r15_indexed 1 + move_pc 1742 + jump 24467 + jr 18090 + nop 41362 +*/ + + +static void gpu_opcode_jump(void) +{ +#ifdef GPU_DIS_JUMP +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doGPUDis) + WriteLog("%06X: JUMP %s, (R%02u) [NCZ:%u%u%u, R%02u=%08X] ", gpu_pc-2, condition[IMM_2], IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM); +#endif + // normalize flags +/* gpu_flag_c = (gpu_flag_c ? 1 : 0); + gpu_flag_z = (gpu_flag_z ? 1 : 0); + gpu_flag_n = (gpu_flag_n ? 1 : 0);*/ + // KLUDGE: Used by BRANCH_CONDITION + uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; + + if (BRANCH_CONDITION(IMM_2)) + { +#ifdef GPU_DIS_JUMP + if (doGPUDis) + WriteLog("Branched!\n"); +#endif +if (gpu_start_log) + WriteLog(" --> JUMP: Branch taken.\n"); + uint32_t delayed_pc = RM; + GPUExec(1); + gpu_pc = delayed_pc; +/* uint16_t opcode = GPUReadWord(gpu_pc, GPU); + gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; + gpu_opcode_second_parameter = opcode & 0x1F; + + gpu_pc = delayed_pc; + gpu_opcode[opcode>>10]();//*/ + } +#ifdef GPU_DIS_JUMP + else + if (doGPUDis) + WriteLog("Branch NOT taken.\n"); +#endif +} + + +static void gpu_opcode_jr(void) +{ +#ifdef GPU_DIS_JR +const char * condition[32] = +{ "T", "nz", "z", "???", "nc", "nc nz", "nc z", "???", "c", "c nz", + "c z", "???", "???", "???", "???", "???", "???", "???", "???", + "???", "nn", "nn nz", "nn z", "???", "n", "n nz", "n z", "???", + "???", "???", "???", "F" }; + if (doGPUDis) + WriteLog("%06X: JR %s, %06X [NCZ:%u%u%u] ", gpu_pc-2, condition[IMM_2], gpu_pc+((IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1) * 2), gpu_flag_n, gpu_flag_c, gpu_flag_z); +#endif +/* if (CONDITION(jaguar.op & 31)) + { + int32_t r1 = (INT8)((jaguar.op >> 2) & 0xF8) >> 2; + uint32_t newpc = jaguar.PC + r1; + CALL_MAME_DEBUG; + jaguar.op = ROPCODE(jaguar.PC); + jaguar.PC = newpc; + (*jaguar.table[jaguar.op >> 10])(); + + jaguar_icount -= 3; // 3 wait states guaranteed + }*/ + // normalize flags +/* gpu_flag_n = (gpu_flag_n ? 1 : 0); + gpu_flag_c = (gpu_flag_c ? 1 : 0); + gpu_flag_z = (gpu_flag_z ? 1 : 0);*/ + // KLUDGE: Used by BRANCH_CONDITION + uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z; + + if (BRANCH_CONDITION(IMM_2)) + { +#ifdef GPU_DIS_JR + if (doGPUDis) + WriteLog("Branched!\n"); +#endif +if (gpu_start_log) + WriteLog(" --> JR: Branch taken.\n"); + int32_t offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1 + int32_t delayed_pc = gpu_pc + (offset * 2); + GPUExec(1); + gpu_pc = delayed_pc; +/* uint16_t opcode = GPUReadWord(gpu_pc, GPU); + gpu_opcode_first_parameter = (opcode >> 5) & 0x1F; + gpu_opcode_second_parameter = opcode & 0x1F; + + gpu_pc = delayed_pc; + gpu_opcode[opcode>>10]();//*/ + } +#ifdef GPU_DIS_JR + else + if (doGPUDis) + WriteLog("Branch NOT taken.\n"); +#endif +} + + +static void gpu_opcode_add(void) +{ +#ifdef GPU_DIS_ADD + if (doGPUDis) + WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN + RM; + CLR_ZNC; SET_ZNC_ADD(RN, RM, res); + RN = res; +#ifdef GPU_DIS_ADD + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_addc(void) +{ +#ifdef GPU_DIS_ADDC + if (doGPUDis) + WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +/* int dreg = jaguar.op & 31; + uint32_t r1 = jaguar.r[(jaguar.op >> 5) & 31]; + uint32_t r2 = jaguar.r[dreg]; + uint32_t res = r2 + r1 + ((jaguar.FLAGS >> 1) & 1); + jaguar.r[dreg] = res; + CLR_ZNC; SET_ZNC_ADD(r2,r1,res);*/ + + uint32_t res = RN + RM + gpu_flag_c; + uint32_t carry = gpu_flag_c; +// SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes! + SET_ZNC_ADD(RN + carry, RM, res); +// SET_ZNC_ADD(RN, RM + carry, res); + RN = res; +#ifdef GPU_DIS_ADDC + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_addq(void) +{ +#ifdef GPU_DIS_ADDQ + if (doGPUDis) + WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN + r1; + CLR_ZNC; SET_ZNC_ADD(RN, r1, res); + RN = res; +#ifdef GPU_DIS_ADDQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_addqt(void) +{ +#ifdef GPU_DIS_ADDQT + if (doGPUDis) + WriteLog("%06X: ADDQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + RN += gpu_convert_zero[IMM_1]; +#ifdef GPU_DIS_ADDQT + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_sub(void) +{ +#ifdef GPU_DIS_SUB + if (doGPUDis) + WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN - RM; + SET_ZNC_SUB(RN, RM, res); + RN = res; +#ifdef GPU_DIS_SUB + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_subc(void) +{ +#ifdef GPU_DIS_SUBC + if (doGPUDis) + WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + // This is how the GPU ALU does it--Two's complement with inverted carry + uint64_t res = (uint64_t)RN + (uint64_t)(RM ^ 0xFFFFFFFF) + (gpu_flag_c ^ 1); + // Carry out of the result is inverted too + gpu_flag_c = ((res >> 32) & 0x01) ^ 1; + RN = (res & 0xFFFFFFFF); + SET_ZN(RN); +#ifdef GPU_DIS_SUBC + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_subq(void) +{ +#ifdef GPU_DIS_SUBQ + if (doGPUDis) + WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN - r1; + SET_ZNC_SUB(RN, r1, res); + RN = res; +#ifdef GPU_DIS_SUBQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_subqt(void) +{ +#ifdef GPU_DIS_SUBQT + if (doGPUDis) + WriteLog("%06X: SUBQT #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + RN -= gpu_convert_zero[IMM_1]; +#ifdef GPU_DIS_SUBQT + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_cmp(void) +{ +#ifdef GPU_DIS_CMP + if (doGPUDis) + WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res = RN - RM; + SET_ZNC_SUB(RN, RM, res); +#ifdef GPU_DIS_CMP + if (doGPUDis) + WriteLog("[NCZ:%u%u%u]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z); +#endif +} + + +static void gpu_opcode_cmpq(void) +{ + static int32_t sqtable[32] = + { 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 }; +#ifdef GPU_DIS_CMPQ + if (doGPUDis) + WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, sqtable[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3; + uint32_t res = RN - r1; + SET_ZNC_SUB(RN, r1, res); +#ifdef GPU_DIS_CMPQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z); +#endif +} + + +static void gpu_opcode_and(void) +{ +#ifdef GPU_DIS_AND + if (doGPUDis) + WriteLog("%06X: AND R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN & RM; + SET_ZN(RN); +#ifdef GPU_DIS_AND + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_or(void) +{ +#ifdef GPU_DIS_OR + if (doGPUDis) + WriteLog("%06X: OR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN | RM; + SET_ZN(RN); +#ifdef GPU_DIS_OR + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_xor(void) +{ +#ifdef GPU_DIS_XOR + if (doGPUDis) + WriteLog("%06X: XOR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RN ^ RM; + SET_ZN(RN); +#ifdef GPU_DIS_XOR + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_not(void) +{ +#ifdef GPU_DIS_NOT + if (doGPUDis) + WriteLog("%06X: NOT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = ~RN; + SET_ZN(RN); +#ifdef GPU_DIS_NOT + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_move_pc(void) +{ +#ifdef GPU_DIS_MOVEPC + if (doGPUDis) + WriteLog("%06X: MOVE PC, R%02u [NCZ:%u%u%u, PC=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_pc-2, IMM_2, RN); +#endif + // Should be previous PC--this might not always be previous instruction! + // Then again, this will point right at the *current* instruction, i.e., MOVE PC,R! + RN = gpu_pc - 2; +#ifdef GPU_DIS_MOVEPC + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_sat8(void) +{ +#ifdef GPU_DIS_SAT8 + if (doGPUDis) + WriteLog("%06X: SAT8 R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFF ? 0xFF : RN)); + SET_ZN(RN); +#ifdef GPU_DIS_SAT8 + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_sat16(void) +{ + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFF ? 0xFFFF : RN)); + SET_ZN(RN); +} + +static void gpu_opcode_sat24(void) +{ + RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFFFF ? 0xFFFFFF : RN)); + SET_ZN(RN); +} + + +static void gpu_opcode_store_r14_indexed(void) +{ +#ifdef GPU_DIS_STORE14I + if (doGPUDis) + WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2)); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); +#else + GPUWriteLong(gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2), RN, GPU); +#endif +} + + +static void gpu_opcode_store_r15_indexed(void) +{ +#ifdef GPU_DIS_STORE15I + if (doGPUDis) + WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2)); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); +#else + GPUWriteLong(gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2), RN, GPU); +#endif +} + + +static void gpu_opcode_load_r14_ri(void) +{ +#ifdef GPU_DIS_LOAD14R + if (doGPUDis) + WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[14], IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[14] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); +#else + RN = GPUReadLong(gpu_reg[14] + RM, GPU); +#endif +#ifdef GPU_DIS_LOAD14R + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_load_r15_ri(void) +{ +#ifdef GPU_DIS_LOAD15R + if (doGPUDis) + WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[15], IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[15] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); +#else + RN = GPUReadLong(gpu_reg[15] + RM, GPU); +#endif +#ifdef GPU_DIS_LOAD15R + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_store_r14_ri(void) +{ +#ifdef GPU_DIS_STORE14R + if (doGPUDis) + WriteLog("%06X: STORE R%02u, (R14+R%02u) [NCZ:%u%u%u, R%02u=%08X, R14+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[14]); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[14] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); +#else + GPUWriteLong(gpu_reg[14] + RM, RN, GPU); +#endif +} + + +static void gpu_opcode_store_r15_ri(void) +{ +#ifdef GPU_DIS_STORE15R + if (doGPUDis) + WriteLog("%06X: STORE R%02u, (R15+R%02u) [NCZ:%u%u%u, R%02u=%08X, R15+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[15]); +#endif +#ifdef GPU_CORRECT_ALIGNMENT_STORE + uint32_t address = gpu_reg[15] + RM; + + if (address >= 0xF03000 && address <= 0xF03FFF) + GPUWriteLong(address & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(address, RN, GPU); +#else + GPUWriteLong(gpu_reg[15] + RM, RN, GPU); +#endif +} + + +static void gpu_opcode_nop(void) +{ +#ifdef GPU_DIS_NOP + if (doGPUDis) + WriteLog("%06X: NOP [NCZ:%u%u%u]\n", gpu_pc-2, gpu_flag_n, gpu_flag_c, gpu_flag_z); +#endif +} + + +static void gpu_opcode_pack(void) +{ +#ifdef GPU_DIS_PACK + if (doGPUDis) + WriteLog("%06X: %s R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, (!IMM_1 ? "PACK " : "UNPACK"), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t val = RN; + +//BUG! if (RM == 0) // Pack + if (IMM_1 == 0) // Pack + RN = ((val >> 10) & 0x0000F000) | ((val >> 5) & 0x00000F00) | (val & 0x000000FF); + else // Unpack + RN = ((val & 0x0000F000) << 10) | ((val & 0x00000F00) << 5) | (val & 0x000000FF); +#ifdef GPU_DIS_PACK + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_storeb(void) +{ +#ifdef GPU_DIS_STOREB + if (doGPUDis) + WriteLog("%06X: STOREB R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM); +#endif +//Is this right??? +// Would appear to be so...! + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + GPUWriteLong(RM, RN & 0xFF, GPU); + else + JaguarWriteByte(RM, RN, GPU); +} + + +static void gpu_opcode_storew(void) +{ +#ifdef GPU_DIS_STOREW + if (doGPUDis) + WriteLog("%06X: STOREW R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + GPUWriteLong(RM & 0xFFFFFFFE, RN & 0xFFFF, GPU); + else + JaguarWriteWord(RM, RN, GPU); +#else + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + GPUWriteLong(RM, RN & 0xFFFF, GPU); + else + JaguarWriteWord(RM, RN, GPU); +#endif +} + + +static void gpu_opcode_store(void) +{ +#ifdef GPU_DIS_STORE + if (doGPUDis) + WriteLog("%06X: STORE R%02u, (R%02u) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + GPUWriteLong(RM & 0xFFFFFFFC, RN, GPU); + else + GPUWriteLong(RM, RN, GPU); +#else + GPUWriteLong(RM, RN, GPU); +#endif +} + + +static void gpu_opcode_storep(void) +{ +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + { + GPUWriteLong((RM & 0xFFFFFFF8) + 0, gpu_hidata, GPU); + GPUWriteLong((RM & 0xFFFFFFF8) + 4, RN, GPU); + } + else + { + GPUWriteLong(RM + 0, gpu_hidata, GPU); + GPUWriteLong(RM + 4, RN, GPU); + } +#else + GPUWriteLong(RM + 0, gpu_hidata, GPU); + GPUWriteLong(RM + 4, RN, GPU); +#endif +} + +static void gpu_opcode_loadb(void) +{ +#ifdef GPU_DIS_LOADB + if (doGPUDis) + WriteLog("%06X: LOADB (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(RM, GPU) & 0xFF; + else + RN = JaguarReadByte(RM, GPU); +#ifdef GPU_DIS_LOADB + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_loadw(void) +{ +#ifdef GPU_DIS_LOADW + if (doGPUDis) + WriteLog("%06X: LOADW (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(RM & 0xFFFFFFFE, GPU) & 0xFFFF; + else + RN = JaguarReadWord(RM, GPU); +#else + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(RM, GPU) & 0xFFFF; + else + RN = JaguarReadWord(RM, GPU); +#endif +#ifdef GPU_DIS_LOADW + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +// According to the docs, & "Do The Same", this address is long aligned... +// So let's try it: +// And it works!!! Need to fix all instances... +// Also, Power Drive Rally seems to contradict the idea that only LOADs in +// the $F03000-$F03FFF range are aligned... +#warning "!!! Alignment issues, need to find definitive final word on this !!!" +/* +Preliminary testing on real hardware seems to confirm that something strange goes on +with unaligned reads in main memory. When the address is off by 1, the result is the +same as the long address with the top byte replaced by something. So if the read is +from $401, and $400 has 12 34 56 78, the value read will be $nn345678, where nn is a currently unknown vlaue. +When the address is off by 2, the result would be $nnnn5678, where nnnn is unknown. +When the address is off by 3, the result would be $nnnnnn78, where nnnnnn is unknown. +It may be that the "unknown" values come from the prefetch queue, but not sure how +to test that. They seem to be stable, though, which would indicate such a mechanism. +Sometimes, however, the off by 2 case returns $12345678! +*/ +static void gpu_opcode_load(void) +{ +#ifdef GPU_DIS_LOAD + if (doGPUDis) + WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 }; +// if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(RM & 0xFFFFFFFC, GPU); +// RN = GPUReadLong(RM & 0x00FFFFFC, GPU); +// else +// RN = GPUReadLong(RM, GPU); + // Simulate garbage in unaligned reads... +//seems that this behavior is different in GPU mem vs. main mem... +// if ((RM < 0xF03000) || (RM > 0xF0BFFF)) +// RN |= mask[RM & 0x03]; +#else + RN = GPUReadLong(RM, GPU); +#endif +#ifdef GPU_DIS_LOAD + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_loadp(void) +{ +#ifdef GPU_CORRECT_ALIGNMENT + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + { + gpu_hidata = GPUReadLong((RM & 0xFFFFFFF8) + 0, GPU); + RN = GPUReadLong((RM & 0xFFFFFFF8) + 4, GPU); + } + else + { + gpu_hidata = GPUReadLong(RM + 0, GPU); + RN = GPUReadLong(RM + 4, GPU); + } +#else + gpu_hidata = GPUReadLong(RM + 0, GPU); + RN = GPUReadLong(RM + 4, GPU); +#endif +} + + +static void gpu_opcode_load_r14_indexed(void) +{ +#ifdef GPU_DIS_LOAD14I + if (doGPUDis) + WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2); + + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); +#else + RN = GPUReadLong(gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2), GPU); +#endif +#ifdef GPU_DIS_LOAD14I + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_load_r15_indexed(void) +{ +#ifdef GPU_DIS_LOAD15I + if (doGPUDis) + WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN); +#endif +#ifdef GPU_CORRECT_ALIGNMENT + uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2); + + if ((RM >= 0xF03000) && (RM <= 0xF03FFF)) + RN = GPUReadLong(address & 0xFFFFFFFC, GPU); + else + RN = GPUReadLong(address, GPU); +#else + RN = GPUReadLong(gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2), GPU); +#endif +#ifdef GPU_DIS_LOAD15I + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_movei(void) +{ +#ifdef GPU_DIS_MOVEI + if (doGPUDis) + WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, (uint32_t)GPUReadWord(gpu_pc) | ((uint32_t)GPUReadWord(gpu_pc + 2) << 16), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + // This instruction is followed by 32-bit value in LSW / MSW format... + RN = (uint32_t)GPUReadWord(gpu_pc, GPU) | ((uint32_t)GPUReadWord(gpu_pc + 2, GPU) << 16); + gpu_pc += 4; +#ifdef GPU_DIS_MOVEI + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_moveta(void) +{ +#ifdef GPU_DIS_MOVETA + if (doGPUDis) + WriteLog("%06X: MOVETA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, ALTERNATE_RN); +#endif + ALTERNATE_RN = RM; +#ifdef GPU_DIS_MOVETA + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u(alt)=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, ALTERNATE_RN); +#endif +} + + +static void gpu_opcode_movefa(void) +{ +#ifdef GPU_DIS_MOVEFA + if (doGPUDis) + WriteLog("%06X: MOVEFA R%02u, R%02u [NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, ALTERNATE_RM, IMM_2, RN); +#endif + RN = ALTERNATE_RM; +#ifdef GPU_DIS_MOVEFA + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u(alt)=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, ALTERNATE_RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_move(void) +{ +#ifdef GPU_DIS_MOVE + if (doGPUDis) + WriteLog("%06X: MOVE R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = RM; +#ifdef GPU_DIS_MOVE + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_moveq(void) +{ +#ifdef GPU_DIS_MOVEQ + if (doGPUDis) + WriteLog("%06X: MOVEQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + RN = IMM_1; +#ifdef GPU_DIS_MOVEQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_resmac(void) +{ + RN = gpu_acc; +} + + +static void gpu_opcode_imult(void) +{ +#ifdef GPU_DIS_IMULT + if (doGPUDis) + WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = (int16_t)RN * (int16_t)RM; + SET_ZN(RN); +#ifdef GPU_DIS_IMULT + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_mult(void) +{ +#ifdef GPU_DIS_MULT + if (doGPUDis) + WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + RN = (uint16_t)RM * (uint16_t)RN; +// RN = (RM & 0xFFFF) * (RN & 0xFFFF); + SET_ZN(RN); +#ifdef GPU_DIS_MULT + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_bclr(void) +{ +#ifdef GPU_DIS_BCLR + if (doGPUDis) + WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t res = RN & ~(1 << IMM_1); + RN = res; + SET_ZN(res); +#ifdef GPU_DIS_BCLR + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_btst(void) +{ +#ifdef GPU_DIS_BTST + if (doGPUDis) + WriteLog("%06X: BTST #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + gpu_flag_z = (~RN >> IMM_1) & 1; +#ifdef GPU_DIS_BTST + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_bset(void) +{ +#ifdef GPU_DIS_BSET + if (doGPUDis) + WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t res = RN | (1 << IMM_1); + RN = res; + SET_ZN(res); +#ifdef GPU_DIS_BSET + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_imacn(void) +{ + uint32_t res = (int16_t)RM * (int16_t)(RN); + gpu_acc += res; +} + + +static void gpu_opcode_mtoi(void) +{ + uint32_t _RM = RM; + uint32_t res = RN = (((int32_t)_RM >> 8) & 0xFF800000) | (_RM & 0x007FFFFF); + SET_ZN(res); +} + + +static void gpu_opcode_normi(void) +{ + uint32_t _RM = RM; + uint32_t res = 0; + + if (_RM) + { + while ((_RM & 0xFFC00000) == 0) + { + _RM <<= 1; + res--; + } + while ((_RM & 0xFF800000) != 0) + { + _RM >>= 1; + res++; + } + } + RN = res; + SET_ZN(res); +} + +static void gpu_opcode_mmult(void) +{ + int count = gpu_matrix_control & 0x0F; // Matrix width + uint32_t addr = gpu_pointer_to_matrix; // In the GPU's RAM + int64_t accum = 0; + uint32_t res; + + if (gpu_matrix_control & 0x10) // Column stepping + { + for(int i=0; i> 1)] >> 16) & 0xFFFF); + else + a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); + + int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU)); + accum += a * b; + addr += 4 * count; + } + } + else // Row stepping + { + for(int i=0; i> 1)] >> 16) & 0xFFFF); + else + a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF); + + int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU)); + accum += a * b; + addr += 4; + } + } + RN = res = (int32_t)accum; + // carry flag to do (out of the last add) + SET_ZN(res); +} + + +static void gpu_opcode_abs(void) +{ +#ifdef GPU_DIS_ABS + if (doGPUDis) + WriteLog("%06X: ABS R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + gpu_flag_c = RN >> 31; + if (RN == 0x80000000) + //Is 0x80000000 a positive number? If so, then we need to set C to 0 as well! + gpu_flag_n = 1, gpu_flag_z = 0; + else + { + if (gpu_flag_c) + RN = -RN; + gpu_flag_n = 0; SET_FLAG_Z(RN); + } +#ifdef GPU_DIS_ABS + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_div(void) // RN / RM +{ +#ifdef GPU_DIS_DIV + if (doGPUDis) + WriteLog("%06X: DIV R%02u, R%02u (%s) [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, (gpu_div_control & 0x01 ? "16.16" : "32"), gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +#if 0 + if (RM) + { + if (gpu_div_control & 0x01) // 16.16 division + { + gpu_remain = ((uint64_t)RN << 16) % RM; + RN = ((uint64_t)RN << 16) / RM; + } + else + { + // We calculate the remainder first because we destroy RN after + // this by assigning it to itself. + gpu_remain = RN % RM; + RN = RN / RM; + } + } + else + { + // This is what happens according to SCPCD. NYAN! + RN = 0xFFFFFFFF; + gpu_remain = 0; + } +#else + // Real algorithm, courtesy of SCPCD: NYAN! + uint32_t q = RN; + uint32_t r = 0; + + // If 16.16 division, stuff top 16 bits of RN into remainder and put the + // bottom 16 of RN in top 16 of quotient + if (gpu_div_control & 0x01) + q <<= 16, r = RN >> 16; + + for(int i=0; i<32; i++) + { +// uint32_t sign = (r >> 31) & 0x01; + uint32_t sign = r & 0x80000000; + r = (r << 1) | ((q >> 31) & 0x01); + r += (sign ? RM : -RM); + q = (q << 1) | (((~r) >> 31) & 0x01); + } + + RN = q; + gpu_remain = r; +#endif + +#ifdef GPU_DIS_DIV + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] Remainder: %08X\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN, gpu_remain); +#endif +} + + +static void gpu_opcode_imultn(void) +{ + uint32_t res = (int32_t)((int16_t)RN * (int16_t)RM); + gpu_acc = (int32_t)res; + SET_FLAG_Z(res); + SET_FLAG_N(res); +} + + +static void gpu_opcode_neg(void) +{ +#ifdef GPU_DIS_NEG + if (doGPUDis) + WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t res = -RN; + SET_ZNC_SUB(0, RN, res); + RN = res; +#ifdef GPU_DIS_NEG + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_shlq(void) +{ +#ifdef GPU_DIS_SHLQ + if (doGPUDis) + WriteLog("%06X: SHLQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, 32 - IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +// Was a bug here... +// (Look at Aaron's code: If r1 = 32, then 32 - 32 = 0 which is wrong!) + int32_t r1 = 32 - IMM_1; + uint32_t res = RN << r1; + SET_ZN(res); gpu_flag_c = (RN >> 31) & 1; + RN = res; +#ifdef GPU_DIS_SHLQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_shrq(void) +{ +#ifdef GPU_DIS_SHRQ + if (doGPUDis) + WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + int32_t r1 = gpu_convert_zero[IMM_1]; + uint32_t res = RN >> r1; + SET_ZN(res); gpu_flag_c = RN & 1; + RN = res; +#ifdef GPU_DIS_SHRQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_ror(void) +{ +#ifdef GPU_DIS_ROR + if (doGPUDis) + WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t r1 = RM & 0x1F; + uint32_t res = (RN >> r1) | (RN << (32 - r1)); + SET_ZN(res); gpu_flag_c = (RN >> 31) & 1; + RN = res; +#ifdef GPU_DIS_ROR + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +static void gpu_opcode_rorq(void) +{ +#ifdef GPU_DIS_RORQ + if (doGPUDis) + WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t r1 = gpu_convert_zero[IMM_1 & 0x1F]; + uint32_t r2 = RN; + uint32_t res = (r2 >> r1) | (r2 << (32 - r1)); + RN = res; + SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01; +#ifdef GPU_DIS_RORQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_sha(void) +{ +/* int dreg = jaguar.op & 31; + int32_t r1 = (int32_t)jaguar.r[(jaguar.op >> 5) & 31]; + uint32_t r2 = jaguar.r[dreg]; + uint32_t res; + + CLR_ZNC; + if (r1 < 0) + { + res = (r1 <= -32) ? 0 : (r2 << -r1); + jaguar.FLAGS |= (r2 >> 30) & 2; + } + else + { + res = (r1 >= 32) ? ((int32_t)r2 >> 31) : ((int32_t)r2 >> r1); + jaguar.FLAGS |= (r2 << 1) & 2; + } + jaguar.r[dreg] = res; + SET_ZN(res);*/ + +#ifdef GPU_DIS_SHA + if (doGPUDis) + WriteLog("%06X: SHA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + uint32_t res; + + if ((int32_t)RM < 0) + { + res = ((int32_t)RM <= -32) ? 0 : (RN << -(int32_t)RM); + gpu_flag_c = RN >> 31; + } + else + { + res = ((int32_t)RM >= 32) ? ((int32_t)RN >> 31) : ((int32_t)RN >> (int32_t)RM); + gpu_flag_c = RN & 0x01; + } + RN = res; + SET_ZN(res); +#ifdef GPU_DIS_SHA + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + +/* int32_t sRM=(int32_t)RM; + uint32_t _RN=RN; + + if (sRM<0) + { + uint32_t shift=-sRM; + if (shift>=32) shift=32; + gpu_flag_c=(_RN&0x80000000)>>31; + while (shift) + { + _RN<<=1; + shift--; + } + } + else + { + uint32_t shift=sRM; + if (shift>=32) shift=32; + gpu_flag_c=_RN&0x1; + while (shift) + { + _RN=((int32_t)_RN)>>1; + shift--; + } + } + RN=_RN; + SET_FLAG_Z(_RN); + SET_FLAG_N(_RN);*/ +} + + +static void gpu_opcode_sharq(void) +{ +#ifdef GPU_DIS_SHARQ + if (doGPUDis) + WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif + uint32_t res = (int32_t)RN >> gpu_convert_zero[IMM_1]; + SET_ZN(res); gpu_flag_c = RN & 0x01; + RN = res; +#ifdef GPU_DIS_SHARQ + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN); +#endif +} + + +static void gpu_opcode_sh(void) +{ +#ifdef GPU_DIS_SH + if (doGPUDis) + WriteLog("%06X: SH R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif + if (RM & 0x80000000) // Shift left + { + gpu_flag_c = RN >> 31; + RN = ((int32_t)RM <= -32 ? 0 : RN << -(int32_t)RM); + } + else // Shift right + { + gpu_flag_c = RN & 0x01; + RN = (RM >= 32 ? 0 : RN >> RM); + } + SET_ZN(RN); +#ifdef GPU_DIS_SH + if (doGPUDis) + WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN); +#endif +} + + +//Temporary: Testing only! +//#include "gpu2.cpp" +//#include "gpu3.cpp" + +#else + + +// New thread-safe GPU core + +int GPUCore(void * data) +{ +} + +#endif + diff --git a/waterbox/virtualjaguar/src/gpu.h b/waterbox/virtualjaguar/src/gpu.h new file mode 100644 index 0000000000..47ec01252a --- /dev/null +++ b/waterbox/virtualjaguar/src/gpu.h @@ -0,0 +1,42 @@ +// +// GPU.H: Header file +// + +#ifndef __GPU_H__ +#define __GPU_H__ + +//#include "types.h" +#include "memory.h" + +#define GPU_CONTROL_RAM_BASE 0x00F02100 +#define GPU_WORK_RAM_BASE 0x00F03000 + +void GPUInit(void); +void GPUReset(void); +void GPUExec(int32_t); +void GPUDone(void); +void GPUUpdateRegisterBanks(void); +void GPUHandleIRQs(void); +void GPUSetIRQLine(int irqline, int state); + +uint8_t GPUReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t GPUReadWord(uint32_t offset, uint32_t who = UNKNOWN); +uint32_t GPUReadLong(uint32_t offset, uint32_t who = UNKNOWN); +void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); +void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN); + +uint32_t GPUGetPC(void); +void GPUReleaseTimeslice(void); +void GPUResetStats(void); +uint32_t GPUReadPC(void); + +// GPU interrupt numbers (from $F00100, bits 4-8) + +enum { GPUIRQ_CPU = 0, GPUIRQ_DSP, GPUIRQ_TIMER, GPUIRQ_OBJECT, GPUIRQ_BLITTER }; + +// Exported vars + +extern uint32_t gpu_reg_bank_0[], gpu_reg_bank_1[]; + +#endif // __GPU_H__ diff --git a/waterbox/virtualjaguar/src/jagdasm.cpp b/waterbox/virtualjaguar/src/jagdasm.cpp new file mode 100644 index 0000000000..885e46a664 --- /dev/null +++ b/waterbox/virtualjaguar/src/jagdasm.cpp @@ -0,0 +1,196 @@ +// +// Jaguar RISC Disassembly +// +// Originally by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS) +// Minor cleanups by James Hammons +// (C) 2012 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 06/01/2012 Created this log (long overdue! ;-) +// JLH 01/23/2013 Beautifying of disassembly, including hex digits of opcodes +// and operands +// + +#include "jagdasm.h" + +#include +#include "jaguar.h" + +#define ROPCODE(a) JaguarReadWord(a) + +uint8_t convert_zero[32] = +{ 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; + +const char * condition[32] = +{ + "", + "nz,", + "z,", + "???,", + "nc,", + "nc nz,", + "nc z,", + "???,", + + "c,", + "c nz,", + "c z,", + "???,", + "???,", + "???,", + "???,", + "???,", + + "???,", + "???,", + "???,", + "???,", + "nn,", + "nn nz,", + "nn z,", + "???,", + + "n,", + "n nz,", + "n z,", + "???,", + "???,", + "???,", + "???,", + "never," +}; + + + +char * signed_16bit(int16_t val) +{ + static char temp[10]; + + if (val < 0) + sprintf(temp, "-$%X", -val); + else + sprintf(temp, "$%X", val); + + return temp; +} + + +unsigned dasmjag(int dsp_type, char * bufferOut, unsigned pc) +{ + char buffer[64]; + int op = ROPCODE(pc); + int reg1 = (op >> 5) & 31; + int reg2 = op & 31; + int size = 2; + pc += 2; + + switch (op >> 10) + { + case 0: sprintf(buffer, "ADD R%02d,R%02d", reg1, reg2); break; + case 1: sprintf(buffer, "ADDC R%02d,R%02d", reg1, reg2); break; + case 2: sprintf(buffer, "ADDQ $%X,R%02d", convert_zero[reg1], reg2); break; + case 3: sprintf(buffer, "ADDQT $%X,R%02d", convert_zero[reg1], reg2); break; + case 4: sprintf(buffer, "SUB R%02d,R%02d", reg1, reg2); break; + case 5: sprintf(buffer, "SUBC R%02d,R%02d", reg1, reg2); break; + case 6: sprintf(buffer, "SUBQ $%X,R%02d", convert_zero[reg1], reg2); break; + case 7: sprintf(buffer, "SUBQT $%X,R%02d", convert_zero[reg1], reg2); break; + case 8: sprintf(buffer, "NEG R%02d", reg2); break; + case 9: sprintf(buffer, "AND R%02d,R%02d", reg1, reg2); break; + case 10: sprintf(buffer, "OR R%02d,R%02d", reg1, reg2); break; + case 11: sprintf(buffer, "XOR R%02d,R%02d", reg1, reg2); break; + case 12: sprintf(buffer, "NOT R%02d", reg2); break; + case 13: sprintf(buffer, "BTST $%X,R%02d", reg1, reg2); break; + case 14: sprintf(buffer, "BSET $%X,R%02d", reg1, reg2); break; + case 15: sprintf(buffer, "BCLR $%X,R%02d", reg1, reg2); break; + case 16: sprintf(buffer, "MULT R%02d,R%02d", reg1, reg2); break; + case 17: sprintf(buffer, "IMULT R%02d,R%02d", reg1, reg2); break; + case 18: sprintf(buffer, "IMULTN R%02d,R%02d", reg1, reg2); break; + case 19: sprintf(buffer, "RESMAC R%02d", reg2); break; + case 20: sprintf(buffer, "IMACN R%02d,R%02d", reg1, reg2); break; + case 21: sprintf(buffer, "DIV R%02d,R%02d", reg1, reg2); break; + case 22: sprintf(buffer, "ABS R%02d", reg2); break; + case 23: sprintf(buffer, "SH R%02d,R%02d", reg1, reg2); break; + case 24: sprintf(buffer, "SHLQ $%X,R%02d", 32 - reg1, reg2); break; + case 25: sprintf(buffer, "SHRQ $%X,R%02d", convert_zero[reg1], reg2); break; + case 26: sprintf(buffer, "SHA R%02d,R%02d", reg1, reg2); break; + case 27: sprintf(buffer, "SHARQ $%X,R%02d", convert_zero[reg1], reg2); break; + case 28: sprintf(buffer, "ROR R%02d,R%02d", reg1, reg2); break; + case 29: sprintf(buffer, "RORQ $%X,R%02d", convert_zero[reg1], reg2); break; + case 30: sprintf(buffer, "CMP R%02d,R%02d", reg1, reg2); break; + case 31: sprintf(buffer, "CMPQ %s,R%02d", signed_16bit((int16_t)(reg1 << 11) >> 11), reg2);break; + case 32: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, "SAT8 R%02d", reg2); + else + sprintf(buffer, "SUBQMOD $%X,R%02d", convert_zero[reg1], reg2); + break; + case 33: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, "SAT16 R%02d", reg2); + else + sprintf(buffer, "SAT16S R%02d", reg2); + break; + case 34: sprintf(buffer, "MOVE R%02d,R%02d", reg1, reg2); break; + case 35: sprintf(buffer, "MOVEQ %d,R%02d", reg1, reg2); break; + case 36: sprintf(buffer, "MOVETA R%02d,R%02d", reg1, reg2); break; + case 37: sprintf(buffer, "MOVEFA R%02d,R%02d", reg1, reg2); break; + case 38: sprintf(buffer, "MOVEI #$%X,R%02d", ROPCODE(pc) | (ROPCODE(pc+2)<<16), reg2); size = 6; break; + case 39: sprintf(buffer, "LOADB (R%02d),R%02d", reg1, reg2); break; + case 40: sprintf(buffer, "LOADW (R%02d),R%02d", reg1, reg2); break; + case 41: sprintf(buffer, "LOAD (R%02d),R%02d", reg1, reg2); break; + case 42: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, "LOADP (R%02d),R%02d", reg1, reg2); + else + sprintf(buffer, "SAT32S R%02d", reg2); + break; + case 43: sprintf(buffer, "LOAD (R14+$%X),R%02d", convert_zero[reg1]*4, reg2);break; + case 44: sprintf(buffer, "LOAD (R15+$%X),R%02d", convert_zero[reg1]*4, reg2);break; + case 45: sprintf(buffer, "STOREB R%02d,(R%02d)", reg2, reg1); break; + case 46: sprintf(buffer, "STOREW R%02d,(R%02d)", reg2, reg1); break; + case 47: sprintf(buffer, "STORE R%02d,(R%02d)", reg2, reg1); break; + case 48: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, "STOREP R%02d,(R%02d)", reg2, reg1); + else + sprintf(buffer, "MIRROR R%02d", reg2); + break; + case 49: sprintf(buffer, "STORE R%02d,(R14+$%X)", reg2, convert_zero[reg1]*4);break; + case 50: sprintf(buffer, "STORE R%02d,(R15+$%X)", reg2, convert_zero[reg1]*4);break; + case 51: sprintf(buffer, "MOVE PC,R%02d", reg2); break; + case 52: sprintf(buffer, "JUMP %s(R%02d)", condition[reg2], reg1); break; + case 53: sprintf(buffer, "JR %s$%X", condition[reg2], pc + ((int8_t)(reg1 << 3) >> 2)); break; + case 54: sprintf(buffer, "MMULT R%02d,R%02d", reg1, reg2); break; + case 55: sprintf(buffer, "MTOI R%02d,R%02d", reg1, reg2); break; + case 56: sprintf(buffer, "NORMI R%02d,R%02d", reg1, reg2); break; + case 57: sprintf(buffer, "NOP"); break; + case 58: sprintf(buffer, "LOAD (R14+R%02d),R%02d", reg1, reg2); break; + case 59: sprintf(buffer, "LOAD (R15+R%02d),R%02d", reg1, reg2); break; + case 60: sprintf(buffer, "STORE R%02d,(R14+R%02d)", reg2, reg1); break; + case 61: sprintf(buffer, "STORE R%02d,(R15+R%02d)", reg2, reg1); break; + case 62: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, "SAT24 R%02d", reg2); + else + sprintf(buffer, "illegal [%d,%d]", reg1, reg2); + break; + case 63: if (dsp_type == JAGUAR_GPU) + sprintf(buffer, (reg1 ? "UNPACK R%02d" : "PACK R%02d"), reg2); + else + sprintf(buffer, "ADDQMOD $%X,R%02d", convert_zero[reg1], reg2); + break; + } + +#if 0 + sprintf(bufferOut,"%-24s (%04X)", buffer, op); +#else + if (size == 2) + sprintf(bufferOut, "%04X %-24s", op, buffer); + else + { + uint16_t word1 = ROPCODE(pc), word2 = ROPCODE(pc + 2); + sprintf(bufferOut, "%04X %04X %04X %-24s", op, word1, word2, buffer); + } +#endif + + return size; +} diff --git a/waterbox/virtualjaguar/src/jagdasm.h b/waterbox/virtualjaguar/src/jagdasm.h new file mode 100644 index 0000000000..0171f2bd51 --- /dev/null +++ b/waterbox/virtualjaguar/src/jagdasm.h @@ -0,0 +1,9 @@ +#ifndef __JAGDASM__ +#define __JAGDASM__ + +#define JAGUAR_GPU 0 +#define JAGUAR_DSP 1 + +unsigned dasmjag(int dsp_type, char * buffer, unsigned pc); + +#endif diff --git a/waterbox/virtualjaguar/src/jaguar.cpp b/waterbox/virtualjaguar/src/jaguar.cpp new file mode 100644 index 0000000000..bbbf0eb406 --- /dev/null +++ b/waterbox/virtualjaguar/src/jaguar.cpp @@ -0,0 +1,2245 @@ +// +// JAGUAR.CPP +// +// Originally by David Raingeard (Cal2) +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS) +// Cleanups and endian wrongness amelioration by James Hammons +// Note: Endian wrongness probably stems from the MAME origins of this emu and +// the braindead way in which MAME handled memory when this was written. :-) +// +// JLH = James Hammons +// +// WHO WHEN WHAT +// --- ---------- ----------------------------------------------------------- +// JLH 11/25/2009 Major rewrite of memory subsystem and handlers +// + +#include "jaguar.h" + +#include +#include +#include "blitter.h" +#include "cdrom.h" +#include "dac.h" +#include "dsp.h" +#include "eeprom.h" +#include "event.h" +#include "foooked.h" +#include "gpu.h" +#include "jerry.h" +#include "joystick.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" +#include "memtrack.h" +#include "mmu.h" +#include "settings.h" +#include "tom.h" + +#define CPU_DEBUG +//Do this in makefile??? Yes! Could, but it's easier to define here... +//#define LOG_UNMAPPED_MEMORY_ACCESSES +//#define ABORT_ON_UNMAPPED_MEMORY_ACCESS +//#define ABORT_ON_ILLEGAL_INSTRUCTIONS +//#define ABORT_ON_OFFICIAL_ILLEGAL_INSTRUCTION +//#define CPU_DEBUG_MEMORY +//#define LOG_CD_BIOS_CALLS +//#define CPU_DEBUG_TRACING +#define ALPINE_FUNCTIONS + +// Private function prototypes + +unsigned jaguar_unknown_readbyte(unsigned address, uint32_t who = UNKNOWN); +unsigned jaguar_unknown_readword(unsigned address, uint32_t who = UNKNOWN); +void jaguar_unknown_writebyte(unsigned address, unsigned data, uint32_t who = UNKNOWN); +void jaguar_unknown_writeword(unsigned address, unsigned data, uint32_t who = UNKNOWN); +void M68K_show_context(void); + +// External variables + +#ifdef CPU_DEBUG_MEMORY +extern bool startMemLog; // Set by "e" key +extern int effect_start; +extern int effect_start2, effect_start3, effect_start4, effect_start5, effect_start6; +#endif + +// Really, need to include memory.h for this, but it might interfere with some stuff... +extern uint8_t jagMemSpace[]; + +// Internal variables + +uint32_t jaguar_active_memory_dumps = 0; + +uint32_t jaguarMainROMCRC32, jaguarROMSize, jaguarRunAddress; +bool jaguarCartInserted = false; +bool lowerField = false; + +#ifdef CPU_DEBUG_MEMORY +uint8_t writeMemMax[0x400000], writeMemMin[0x400000]; +uint8_t readMem[0x400000]; +uint32_t returnAddr[4000], raPtr = 0xFFFFFFFF; +#endif + +uint32_t pcQueue[0x400]; +uint32_t a0Queue[0x400]; +uint32_t a1Queue[0x400]; +uint32_t a2Queue[0x400]; +uint32_t a3Queue[0x400]; +uint32_t a4Queue[0x400]; +uint32_t a5Queue[0x400]; +uint32_t a6Queue[0x400]; +uint32_t a7Queue[0x400]; +uint32_t d0Queue[0x400]; +uint32_t d1Queue[0x400]; +uint32_t d2Queue[0x400]; +uint32_t d3Queue[0x400]; +uint32_t d4Queue[0x400]; +uint32_t d5Queue[0x400]; +uint32_t d6Queue[0x400]; +uint32_t d7Queue[0x400]; +uint32_t srQueue[0x400]; +uint32_t pcQPtr = 0; +bool startM68KTracing = false; + +// Breakpoint on memory access vars (exported) +bool bpmActive = false; +uint32_t bpmAddress1; + + +// +// Callback function to detect illegal instructions +// +void GPUDumpDisassembly(void); +void GPUDumpRegisters(void); +static bool start = false; + +void M68KInstructionHook(void) +{ + uint32_t m68kPC = m68k_get_reg(NULL, M68K_REG_PC); +// Temp, for comparing... +{ +/* static char buffer[2048];//, mem[64]; + m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000); + printf("%08X: %s\n", m68kPC, buffer);//*/ +} +//JaguarDasm(m68kPC, 1); +//Testing Hover Strike... +#if 0 +//Dasm(regs.pc, 1); +static int hitCount = 0; +static int inRoutine = 0; +static int instSeen; + +//if (regs.pc == 0x80340A) +if (m68kPC == 0x803416) +{ + hitCount++; + inRoutine = 1; + instSeen = 0; + printf("%i: $80340A start. A0=%08X, A1=%08X ", hitCount, m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1)); +} +else if (m68kPC == 0x803422) +{ + inRoutine = 0; + printf("(%i instructions)\n", instSeen); +} + +if (inRoutine) + instSeen++; +#endif + +// For code tracing... +#ifdef CPU_DEBUG_TRACING + if (startM68KTracing) + { + static char buffer[2048]; + + m68k_disassemble(buffer, m68kPC, 0); + WriteLog("%06X: %s\n", m68kPC, buffer); + } +#endif + +// For tracebacks... +// Ideally, we'd save all the registers as well... + pcQueue[pcQPtr] = m68kPC; + a0Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A0); + a1Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A1); + a2Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A2); + a3Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A3); + a4Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A4); + a5Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A5); + a6Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A6); + a7Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_A7); + d0Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D0); + d1Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D1); + d2Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D2); + d3Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D3); + d4Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D4); + d5Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D5); + d6Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D6); + d7Queue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_D7); + srQueue[pcQPtr] = m68k_get_reg(NULL, M68K_REG_SR); + pcQPtr++; + pcQPtr &= 0x3FF; + + if (m68kPC & 0x01) // Oops! We're fetching an odd address! + { + /*WriteLog("M68K: Attempted to execute from an odd address!\n\nBacktrace:\n\n"); + + static char buffer[2048]; + for(int i=0; i<0x400; i++) + { +// WriteLog("[A2=%08X, D0=%08X]\n", a2Queue[(pcQPtr + i) & 0x3FF], d0Queue[(pcQPtr + i) & 0x3FF]); + WriteLog("[A0=%08X, A1=%08X, A2=%08X, A3=%08X, A4=%08X, A5=%08X, A6=%08X, A7=%08X, D0=%08X, D1=%08X, D2=%08X, D3=%08X, D4=%08X, D5=%08X, D6=%08X, D7=%08X, SR=%04X]\n", a0Queue[(pcQPtr + i) & 0x3FF], a1Queue[(pcQPtr + i) & 0x3FF], a2Queue[(pcQPtr + i) & 0x3FF], a3Queue[(pcQPtr + i) & 0x3FF], a4Queue[(pcQPtr + i) & 0x3FF], a5Queue[(pcQPtr + i) & 0x3FF], a6Queue[(pcQPtr + i) & 0x3FF], a7Queue[(pcQPtr + i) & 0x3FF], d0Queue[(pcQPtr + i) & 0x3FF], d1Queue[(pcQPtr + i) & 0x3FF], d2Queue[(pcQPtr + i) & 0x3FF], d3Queue[(pcQPtr + i) & 0x3FF], d4Queue[(pcQPtr + i) & 0x3FF], d5Queue[(pcQPtr + i) & 0x3FF], d6Queue[(pcQPtr + i) & 0x3FF], d7Queue[(pcQPtr + i) & 0x3FF], srQueue[(pcQPtr + i) & 0x3FF]); + m68k_disassemble(buffer, pcQueue[(pcQPtr + i) & 0x3FF], 0);//M68K_CPU_TYPE_68000); + WriteLog("\t%08X: %s\n", pcQueue[(pcQPtr + i) & 0x3FF], buffer); + } + WriteLog("\n"); + + uint32_t topOfStack = m68k_get_reg(NULL, M68K_REG_A7); + WriteLog("M68K: Top of stack: %08X. Stack trace:\n", JaguarReadLong(topOfStack)); + for(int i=0; i<10; i++) + WriteLog("%06X: %08X\n", topOfStack - (i * 4), JaguarReadLong(topOfStack - (i * 4))); + WriteLog("Jaguar: VBL interrupt is %s\n", ((TOMIRQEnabled(IRQ_VIDEO)) && (JaguarInterruptHandlerIsValid(64))) ? "enabled" : "disabled"); + M68K_show_context(); + LogDone(); + exit(0);*/ + } + + // Disassemble everything +/* { + static char buffer[2048]; + m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000); + WriteLog("%08X: %s", m68kPC, buffer); + WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1)); + }//*/ +/* if (m68kPC >= 0x807EC4 && m68kPC <= 0x807EDB) + { + static char buffer[2048]; + m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000); + WriteLog("%08X: %s", m68kPC, buffer); + WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1)); + }//*/ +/* if (m68kPC == 0x8D0E48 && effect_start5) + { + WriteLog("\nM68K: At collision detection code. Exiting!\n\n"); + GPUDumpRegisters(); + GPUDumpDisassembly(); + log_done(); + exit(0); + }//*/ +/* uint16_t opcode = JaguarReadWord(m68kPC); + if (opcode == 0x4E75) // RTS + { + if (startMemLog) +// WriteLog("Jaguar: Returning from subroutine to %08X\n", JaguarReadLong(m68k_get_reg(NULL, M68K_REG_A7))); + { + uint32_t addr = JaguarReadLong(m68k_get_reg(NULL, M68K_REG_A7)); + bool found = false; + if (raPtr != 0xFFFFFFFF) + { + for(uint32_t i=0; i<=raPtr; i++) + { + if (returnAddr[i] == addr) + { + found = true; + break; + } + } + } + + if (!found) + returnAddr[++raPtr] = addr; + } + }//*/ + +//Flip Out! debugging... +//805F46, 806486 +/* +00805FDC: movea.l #$9c6f8, A0 D0=00100010, A0=00100000 +00805FE2: move.w #$10, (A0)+ D0=00100010, A0=0009C6F8 +00805FE6: cmpa.l #$c96f8, A0 D0=00100010, A0=0009C6FA +00805FEC: bne 805fe2 D0=00100010, A0=0009C6FA + +0080603A: move.l #$11ed7c, $100.w D0=61700080, A0=000C96F8, D1=00000000, A1=000040D8 + +0012314C: move.l (A0)+, (A1)+ D0=61700080, A0=00124174, D1=00000000, A1=00F03FFC +0012314E: cmpa.l #$f04000, A1 D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +00123154: blt 12314c D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +00123156: move.l #$0, $f035d0.l D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +00123160: move.l #$f03000, $f02110.l D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +0012316A: move.l #$1, $f02114.l D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +00123174: rts D0=61700080, A0=00124178, D1=00000000, A1=00F04000 +*/ +/* static char buffer[2048]; +//if (m68kPC > 0x805F48) start = true; +//if (m68kPC > 0x806486) start = true; +//if (m68kPC == 0x805FEE) start = true; +//if (m68kPC == 0x80600C)// start = true; +if (m68kPC == 0x802058) start = true; +//{ +// GPUDumpRegisters(); +// GPUDumpDisassembly(); +// +// M68K_show_context(); +// log_done(); +// exit(0); +//} + if (start) + { + m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000); + WriteLog("%08X: %s \t\tD0=%08X, A0=%08X, D1=%08X, A1=%08X\n", m68kPC, buffer, m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_A1)); + }//*/ + +/* if (m68kPC == 0x803F16) + { + WriteLog("M68K: Registers found at $803F16:\n"); + WriteLog("\t68K PC=%06X\n", m68k_get_reg(NULL, M68K_REG_PC)); + for(int i=M68K_REG_D0; i<=M68K_REG_D7; i++) + WriteLog("\tD%i = %08X\n", i-M68K_REG_D0, m68k_get_reg(NULL, (m68k_register_t)i)); + WriteLog("\n"); + for(int i=M68K_REG_A0; i<=M68K_REG_A7; i++) + WriteLog("\tA%i = %08X\n", i-M68K_REG_A0, m68k_get_reg(NULL, (m68k_register_t)i)); + }*/ +//Looks like the DSP is supposed to return $12345678 when it finishes its validation routine... +// !!! Investigate !!! +/*extern bool doDSPDis; + static bool disgo = false; + if (m68kPC == 0x50222) + { + // CD BIOS hacking +// WriteLog("M68K: About to stuff $12345678 into $F1B000 (=%08X)...\n", DSPReadLong(0xF1B000, M68K)); +// DSPWriteLong(0xF1B000, 0x12345678, M68K); +// disgo = true; + } + if (m68kPC == 0x5000) +// doDSPDis = true; + disgo = true; + if (disgo) + { + static char buffer[2048]; + m68k_disassemble(buffer, m68kPC, M68K_CPU_TYPE_68000); + WriteLog("%08X: %s", m68kPC, buffer); + WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X, D2=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2)); + }//*/ +/* if (m68kPC == 0x82E1A) + { + static char buffer[2048]; + m68k_disassemble(buffer, m68kPC, 0);//M68K_CPU_TYPE_68000); + WriteLog("--> [Routine start] %08X: %s", m68kPC, buffer); + WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X(cmd), D1=%08X(# bytes), D2=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2)); + }//*/ +/* if (m68kPC == 0x82E58) + WriteLog("--> [Routine end]\n"); + if (m68kPC == 0x80004) + { + WriteLog("--> [Calling BusWrite2] D2: %08X\n", m68k_get_reg(NULL, M68K_REG_D2)); +// m68k_set_reg(M68K_REG_D2, 0x12345678); + }//*/ + +#ifdef LOG_CD_BIOS_CALLS +/* +CD_init:: -> $3000 +BIOS_VER:: -> $3004 +CD_mode:: -> $3006 +CD_ack:: -> $300C +CD_jeri:: -> $3012 +CD_spin:: -> $3018 +CD_stop:: -> $301E +CD_mute:: -> $3024 +CD_umute:: -> $302A +CD_paus:: -> $3030 +CD_upaus:: -> $3036 +CD_read:: -> $303C +CD_uread:: -> $3042 +CD_setup:: -> $3048 +CD_ptr:: -> $304E +CD_osamp:: -> $3054 +CD_getoc:: -> $305A +CD_initm:: -> $3060 +CD_initf:: -> $3066 +CD_switch:: -> $306C +*/ + if (m68kPC == 0x3000) + WriteLog("M68K: CD_init\n"); + else if (m68kPC == 0x3006 + (6 * 0)) + WriteLog("M68K: CD_mode\n"); + else if (m68kPC == 0x3006 + (6 * 1)) + WriteLog("M68K: CD_ack\n"); + else if (m68kPC == 0x3006 + (6 * 2)) + WriteLog("M68K: CD_jeri\n"); + else if (m68kPC == 0x3006 + (6 * 3)) + WriteLog("M68K: CD_spin\n"); + else if (m68kPC == 0x3006 + (6 * 4)) + WriteLog("M68K: CD_stop\n"); + else if (m68kPC == 0x3006 + (6 * 5)) + WriteLog("M68K: CD_mute\n"); + else if (m68kPC == 0x3006 + (6 * 6)) + WriteLog("M68K: CD_umute\n"); + else if (m68kPC == 0x3006 + (6 * 7)) + WriteLog("M68K: CD_paus\n"); + else if (m68kPC == 0x3006 + (6 * 8)) + WriteLog("M68K: CD_upaus\n"); + else if (m68kPC == 0x3006 + (6 * 9)) + WriteLog("M68K: CD_read\n"); + else if (m68kPC == 0x3006 + (6 * 10)) + WriteLog("M68K: CD_uread\n"); + else if (m68kPC == 0x3006 + (6 * 11)) + WriteLog("M68K: CD_setup\n"); + else if (m68kPC == 0x3006 + (6 * 12)) + WriteLog("M68K: CD_ptr\n"); + else if (m68kPC == 0x3006 + (6 * 13)) + WriteLog("M68K: CD_osamp\n"); + else if (m68kPC == 0x3006 + (6 * 14)) + WriteLog("M68K: CD_getoc\n"); + else if (m68kPC == 0x3006 + (6 * 15)) + WriteLog("M68K: CD_initm\n"); + else if (m68kPC == 0x3006 + (6 * 16)) + WriteLog("M68K: CD_initf\n"); + else if (m68kPC == 0x3006 + (6 * 17)) + WriteLog("M68K: CD_switch\n"); + + if (m68kPC >= 0x3000 && m68kPC <= 0x306C) + WriteLog("\t\tA0=%08X, A1=%08X, D0=%08X, D1=%08X, D2=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2)); +#endif + +#ifdef ABORT_ON_ILLEGAL_INSTRUCTIONS + if (!m68k_is_valid_instruction(m68k_read_memory_16(m68kPC), 0))//M68K_CPU_TYPE_68000)) + { +#ifndef ABORT_ON_OFFICIAL_ILLEGAL_INSTRUCTION + if (m68k_read_memory_16(m68kPC) == 0x4AFC) + { + // This is a kludge to let homebrew programs work properly (i.e., let the other processors + // keep going even when the 68K dumped back to the debugger or what have you). +//dis no wok right! +// m68k_set_reg(M68K_REG_PC, m68kPC - 2); +// Try setting the vector to the illegal instruction... +//This doesn't work right either! Do something else! Quick! +// SET32(jaguar_mainRam, 0x10, m68kPC); + + return; + } +#endif + + WriteLog("\nM68K encountered an illegal instruction at %08X!!!\n\nAborting!\n", m68kPC); + uint32_t topOfStack = m68k_get_reg(NULL, M68K_REG_A7); + WriteLog("M68K: Top of stack: %08X. Stack trace:\n", JaguarReadLong(topOfStack)); + uint32_t address = topOfStack - (4 * 4 * 3); + + for(int i=0; i<10; i++) + { + WriteLog("%06X:", address); + + for(int j=0; j<4; j++) + { + WriteLog(" %08X", JaguarReadLong(address)); + address += 4; + } + + WriteLog("\n"); + } + + WriteLog("Jaguar: VBL interrupt is %s\n", ((TOMIRQEnabled(IRQ_VIDEO)) && (JaguarInterruptHandlerIsValid(64))) ? "enabled" : "disabled"); + M68K_show_context(); + +//temp +// WriteLog("\n\n68K disasm\n\n"); +// jaguar_dasm(0x802000, 0x50C); +// WriteLog("\n\n"); +//endoftemp + + LogDone(); + exit(0); + }//*/ +#endif +} + +#if 0 +Now here be dragons... +Here is how memory ranges are defined in the CoJag driver. +Note that we only have to be concerned with 3 entities read/writing anything: +The main CPU, the GPU, and the DSP. Everything else is unnecessary. So we can keep our main memory +checking in jaguar.cpp, gpu.cpp and dsp.cpp. There should be NO checking in TOM, JERRY, etc. other than +things that are entirely internal to those modules. This way we should be able to get a handle on all +this crap which is currently scattered over Hells Half Acre(tm). + +Also: We need to distinguish whether or not we need .b, .w, and .dw versions of everything, or if there +is a good way to collapse that shit (look below for inspiration). Current method works, but is error prone. + +/************************************* + * + * Main CPU memory handlers + * + *************************************/ + +static ADDRESS_MAP_START( m68020_map, ADDRESS_SPACE_PROGRAM, 32 ) + AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_BASE(&jaguar_shared_ram) AM_SHARE(1) + AM_RANGE(0x800000, 0x9fffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_BASE(&rom_base) + AM_RANGE(0xa00000, 0xa1ffff) AM_RAM + AM_RANGE(0xa20000, 0xa21fff) AM_READWRITE(eeprom_data_r, eeprom_data_w) AM_BASE(&generic_nvram32) AM_SIZE(&generic_nvram_size) + AM_RANGE(0xa30000, 0xa30003) AM_WRITE(watchdog_reset32_w) + AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w) + AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w) + AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(2) + AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_controller32_r, ide_controller32_w) + AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE(jaguar_tom_regs32_r, jaguar_tom_regs32_w) + AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_BASE(&jaguar_gpu_clut) AM_SHARE(2) + AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w) + AM_RANGE(0xf02200, 0xf022ff) AM_READWRITE(jaguar_blitter_r, jaguar_blitter_w) + AM_RANGE(0xf03000, 0xf03fff) AM_MIRROR(0x008000) AM_RAM AM_BASE(&jaguar_gpu_ram) AM_SHARE(3) + AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w) + AM_RANGE(0xf16000, 0xf1600b) AM_READ(cojag_gun_input_r) // GPI02 + AM_RANGE(0xf17000, 0xf17003) AM_READ(status_r) // GPI03 +// AM_RANGE(0xf17800, 0xf17803) AM_WRITE(latch_w) // GPI04 + AM_RANGE(0xf17c00, 0xf17c03) AM_READ(jamma_r) // GPI05 + AM_RANGE(0xf1a100, 0xf1a13f) AM_READWRITE(dspctrl_r, dspctrl_w) + AM_RANGE(0xf1a140, 0xf1a17f) AM_READWRITE(jaguar_serial_r, jaguar_serial_w) + AM_RANGE(0xf1b000, 0xf1cfff) AM_RAM AM_BASE(&jaguar_dsp_ram) AM_SHARE(4) +ADDRESS_MAP_END + +/************************************* + * + * GPU memory handlers + * + *************************************/ + +static ADDRESS_MAP_START( gpu_map, ADDRESS_SPACE_PROGRAM, 32 ) + AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE(1) + AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK(8) + AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(9) + AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_controller32_r, ide_controller32_w) + AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE(jaguar_tom_regs32_r, jaguar_tom_regs32_w) + AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE(2) + AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w) + AM_RANGE(0xf02200, 0xf022ff) AM_READWRITE(jaguar_blitter_r, jaguar_blitter_w) + AM_RANGE(0xf03000, 0xf03fff) AM_RAM AM_SHARE(3) + AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w) +ADDRESS_MAP_END + +/************************************* + * + * DSP memory handlers + * + *************************************/ + +static ADDRESS_MAP_START( dsp_map, ADDRESS_SPACE_PROGRAM, 32 ) + AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE(1) + AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK(8) + AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK(9) + AM_RANGE(0xf10000, 0xf103ff) AM_READWRITE(jaguar_jerry_regs32_r, jaguar_jerry_regs32_w) + AM_RANGE(0xf1a100, 0xf1a13f) AM_READWRITE(dspctrl_r, dspctrl_w) + AM_RANGE(0xf1a140, 0xf1a17f) AM_READWRITE(jaguar_serial_r, jaguar_serial_w) + AM_RANGE(0xf1b000, 0xf1cfff) AM_RAM AM_SHARE(4) + AM_RANGE(0xf1d000, 0xf1dfff) AM_READ(jaguar_wave_rom_r) AM_BASE(&jaguar_wave_rom) +ADDRESS_MAP_END +*/ +#endif + +//#define EXPERIMENTAL_MEMORY_HANDLING +// Experimental memory mappage... +// Dunno if this is a good approach or not, but it seems to make better +// sense to have all this crap in one spot intstead of scattered all over +// the place the way it is now. +#ifdef EXPERIMENTAL_MEMORY_HANDLING +// Needed defines... +#define NEW_TIMER_SYSTEM + +/* +uint8_t jaguarMainRAM[0x400000]; // 68K CPU RAM +uint8_t jaguarMainROM[0x600000]; // 68K CPU ROM +uint8_t jaguarBootROM[0x040000]; // 68K CPU BIOS ROM--uses only half of this! +uint8_t jaguarCDBootROM[0x040000]; // 68K CPU CD BIOS ROM +bool BIOSLoaded = false; +bool CDBIOSLoaded = false; + +uint8_t cdRAM[0x100]; +uint8_t tomRAM[0x4000]; +uint8_t jerryRAM[0x10000]; +static uint16_t eeprom_ram[64]; + +// NOTE: CD BIOS ROM is read from cartridge space @ $802000 (it's a cartridge, after all) +*/ + +enum MemType { MM_NOP = 0, MM_RAM, MM_ROM, MM_IO }; + +// M68K Memory map/handlers +uint32_t { + { 0x000000, 0x3FFFFF, MM_RAM, jaguarMainRAM }, + { 0x800000, 0xDFFEFF, MM_ROM, jaguarMainROM }, +// Note that this is really memory mapped I/O region... +// { 0xDFFF00, 0xDFFFFF, MM_RAM, cdRAM }, + { 0xDFFF00, 0xDFFF03, MM_IO, cdBUTCH }, // base of Butch == interrupt control register, R/W + { 0xDFFF04, 0xDFFF07, MM_IO, cdDSCNTRL }, // DSA control register, R/W + { 0xDFFF0A, 0xDFFF0B, MM_IO, cdDS_DATA }, // DSA TX/RX data, R/W + { 0xDFFF10, 0xDFFF13, MM_IO, cdI2CNTRL }, // i2s bus control register, R/W + { 0xDFFF14, 0xDFFF17, MM_IO, cdSBCNTRL }, // CD subcode control register, R/W + { 0xDFFF18, 0xDFFF1B, MM_IO, cdSUBDATA }, // Subcode data register A + { 0xDFFF1C, 0xDFFF1F, MM_IO, cdSUBDATB }, // Subcode data register B + { 0xDFFF20, 0xDFFF23, MM_IO, cdSB_TIME }, // Subcode time and compare enable (D24) + { 0xDFFF24, 0xDFFF27, MM_IO, cdFIFO_DATA }, // i2s FIFO data + { 0xDFFF28, 0xDFFF2B, MM_IO, cdI2SDAT2 }, // i2s FIFO data (old) + { 0xDFFF2C, 0xDFFF2F, MM_IO, cdUNKNOWN }, // Seems to be some sort of I2S interface + + { 0xE00000, 0xE3FFFF, MM_ROM, jaguarBootROM }, + +// { 0xF00000, 0xF0FFFF, MM_IO, TOM_REGS_RW }, + { 0xF00050, 0xF00051, MM_IO, tomTimerPrescaler }, + { 0xF00052, 0xF00053, MM_IO, tomTimerDivider }, + { 0xF00400, 0xF005FF, MM_RAM, tomRAM }, // CLUT A&B: How to link these? Write to one writes to the other... + { 0xF00600, 0xF007FF, MM_RAM, tomRAM }, // Actually, this is a good approach--just make the reads the same as well + //What about LBUF writes??? + { 0xF02100, 0xF0211F, MM_IO, GPUWriteByte }, // GPU CONTROL + { 0xF02200, 0xF0229F, MM_IO, BlitterWriteByte }, // BLITTER + { 0xF03000, 0xF03FFF, MM_RAM, GPUWriteByte }, // GPU RAM + + { 0xF10000, 0xF1FFFF, MM_IO, JERRY_REGS_RW }, + +/* + EEPROM: + { 0xF14001, 0xF14001, MM_IO_RO, eepromFOO } + { 0xF14801, 0xF14801, MM_IO_WO, eepromBAR } + { 0xF15001, 0xF15001, MM_IO_RW, eepromBAZ } + + JOYSTICK: + { 0xF14000, 0xF14003, MM_IO, joystickFoo } + 0 = pad0/1 button values (4 bits each), RO(?) + 1 = pad0/1 index value (4 bits each), WO + 2 = unused, RO + 3 = NTSC/PAL, certain button states, RO + +JOYSTICK $F14000 Read/Write + 15.....8 7......0 +Read fedcba98 7654321q f-1 Signals J15 to J1 + q Cartridge EEPROM output data +Write exxxxxxm 76543210 e 1 = enable J7-J0 outputs + 0 = disable J7-J0 outputs + x don't care + m Audio mute + 0 = Audio muted (reset state) + 1 = Audio enabled + 7-4 J7-J4 outputs (port 2) + 3-0 J3-J0 outputs (port 1) +JOYBUTS $F14002 Read Only + 15.....8 7......0 +Read xxxxxxxx rrdv3210 x don't care + r Reserved + d Reserved + v 1 = NTSC Video hardware + 0 = PAL Video hardware + 3-2 Button inputs B3 & B2 (port 2) + 1-0 Button inputs B1 & B0 (port 1) + +J4 J5 J6 J7 Port 2 B2 B3 J12 J13 J14 J15 +J3 J2 J1 J0 Port 1 B0 B1 J8 J9 J10 J11 + 0 0 0 0 + 0 0 0 1 + 0 0 1 0 + 0 0 1 1 + 0 1 0 0 + 0 1 0 1 + 0 1 1 0 + 0 1 1 1 Row 3 C3 Option # 9 6 3 + 1 0 0 0 + 1 0 0 1 + 1 0 1 0 + 1 0 1 1 Row 2 C2 C 0 8 5 2 + 1 1 0 0 + 1 1 0 1 Row 1 C1 B * 7 4 1 + 1 1 1 0 Row 0 Pause A Up Down Left Right + 1 1 1 1 + +0 bit read in any position means that button is pressed. +C3 = C2 = 1 means std. Jag. cntrlr. or nothing attached. +*/ +}; + +void WriteByte(uint32_t address, uint8_t byte, uint32_t who/*=UNKNOWN*/) +{ + // Not sure, but I think the system only has 24 address bits... + address &= 0x00FFFFFF; + + // RAM ($000000 - $3FFFFF) 4M + if (address <= 0x3FFFFF) + jaguarMainRAM[address] = byte; + // hole ($400000 - $7FFFFF) 4M + else if (address <= 0x7FFFFF) + ; // Do nothing + // GAME ROM ($800000 - $DFFEFF) 6M - 256 bytes + else if (address <= 0xDFFEFF) + ; // Do nothing + // CDROM ($DFFF00 - $DFFFFF) 256 bytes + else if (address <= 0xDFFFFF) + { + cdRAM[address & 0xFF] = byte; +#ifdef CDROM_LOG + if ((address & 0xFF) < 12 * 4) + WriteLog("[%s] ", BReg[(address & 0xFF) / 4]); + WriteLog("CDROM: %s writing byte $%02X at $%08X [68K PC=$%08X]\n", whoName[who], data, offset, m68k_get_reg(NULL, M68K_REG_PC)); +#endif + } + // BIOS ROM ($E00000 - $E3FFFF) 256K + else if (address <= 0xE3FFFF) + ; // Do nothing + // hole ($E40000 - $EFFFFF) 768K + else if (address <= 0xEFFFFF) + ; // Do nothing + // TOM ($F00000 - $F0FFFF) 64K + else if (address <= 0xF0FFFF) +// ; // Do nothing + { + if (address == 0xF00050) + { + tomTimerPrescaler = (tomTimerPrescaler & 0x00FF) | ((uint16_t)byte << 8); + TOMResetPIT(); + return; + } + else if (address == 0xF00051) + { + tomTimerPrescaler = (tomTimerPrescaler & 0xFF00) | byte; + TOMResetPIT(); + return; + } + else if (address == 0xF00052) + { + tomTimerDivider = (tomTimerDivider & 0x00FF) | ((uint16_t)byte << 8); + TOMResetPIT(); + return; + } + else if (address == 0xF00053) + { + tomTimerDivider = (tomTimerDivider & 0xFF00) | byte; + TOMResetPIT(); + return; + } + else if (address >= 0xF00400 && address <= 0xF007FF) // CLUT (A & B) + { + // Writing to one CLUT writes to the other + address &= 0x5FF; // Mask out $F00600 (restrict to $F00400-5FF) + tomRAM[address] = tomRAM[address + 0x200] = byte; + return; + } + //What about LBUF writes??? + else if ((address >= 0xF02100) && (address <= 0xF0211F)) // GPU CONTROL + { + GPUWriteByte(address, byte, who); + return; + } + else if ((address >= 0xF02200) && (address <= 0xF0229F)) // BLITTER + { + BlitterWriteByte(address, byte, who); + return; + } + else if ((address >= 0xF03000) && (address <= 0xF03FFF)) // GPU RAM + { + GPUWriteByte(address, byte, who); + return; + } + + tomRAM[address & 0x3FFF] = byte; + } + // JERRY ($F10000 - $F1FFFF) 64K + else if (address <= 0xF1FFFF) +// ; // Do nothing + { +#ifdef JERRY_DEBUG + WriteLog("jerry: writing byte %.2x at 0x%.6x\n", byte, address); +#endif + if ((address >= DSP_CONTROL_RAM_BASE) && (address < DSP_CONTROL_RAM_BASE+0x20)) + { + DSPWriteByte(address, byte, who); + return; + } + else if ((address >= DSP_WORK_RAM_BASE) && (address < DSP_WORK_RAM_BASE+0x2000)) + { + DSPWriteByte(address, byte, who); + return; + } + // SCLK ($F1A150--8 bits wide) +//NOTE: This should be taken care of in DAC... + else if ((address >= 0xF1A152) && (address <= 0xF1A153)) + { +// WriteLog("JERRY: Writing %02X to SCLK...\n", data); + if ((address & 0x03) == 2) + JERRYI2SInterruptDivide = (JERRYI2SInterruptDivide & 0x00FF) | ((uint32_t)byte << 8); + else + JERRYI2SInterruptDivide = (JERRYI2SInterruptDivide & 0xFF00) | (uint32_t)byte; + + JERRYI2SInterruptTimer = -1; +#ifndef NEW_TIMER_SYSTEM + jerry_i2s_exec(0); +#else + RemoveCallback(JERRYI2SCallback); + JERRYI2SCallback(); +#endif +// return; + } + // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...) + else if (address >= 0xF1A148 && address <= 0xF1A157) + { + DACWriteByte(address, byte, who); + return; + } + else if (address >= 0xF10000 && address <= 0xF10007) + { +#ifndef NEW_TIMER_SYSTEM + switch (address & 0x07) + { + case 0: + JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0x00FF) | (byte << 8); + JERRYResetPIT1(); + break; + case 1: + JERRYPIT1Prescaler = (JERRYPIT1Prescaler & 0xFF00) | byte; + JERRYResetPIT1(); + break; + case 2: + JERRYPIT1Divider = (JERRYPIT1Divider & 0x00FF) | (byte << 8); + JERRYResetPIT1(); + break; + case 3: + JERRYPIT1Divider = (JERRYPIT1Divider & 0xFF00) | byte; + JERRYResetPIT1(); + break; + case 4: + JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0x00FF) | (byte << 8); + JERRYResetPIT2(); + break; + case 5: + JERRYPIT2Prescaler = (JERRYPIT2Prescaler & 0xFF00) | byte; + JERRYResetPIT2(); + break; + case 6: + JERRYPIT2Divider = (JERRYPIT2Divider & 0x00FF) | (byte << 8); + JERRYResetPIT2(); + break; + case 7: + JERRYPIT2Divider = (JERRYPIT2Divider & 0xFF00) | byte; + JERRYResetPIT2(); + } +#else +WriteLog("JERRY: Unhandled timer write (BYTE) at %08X...\n", address); +#endif + return; + } +/* else if ((offset >= 0xF10010) && (offset <= 0xF10015)) + { + clock_byte_write(offset, byte); + return; + }//*/ + // JERRY -> 68K interrupt enables/latches (need to be handled!) + else if (address >= 0xF10020 && address <= 0xF10023) + { +WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", byte, address); + } +/* else if ((offset >= 0xF17C00) && (offset <= 0xF17C01)) + { + anajoy_byte_write(offset, byte); + return; + }*/ + else if ((address >= 0xF14000) && (address <= 0xF14003)) + { + JoystickWriteByte(address, byte); + EepromWriteByte(address, byte); + return; + } + else if ((address >= 0xF14004) && (address <= 0xF1A0FF)) + { + EepromWriteByte(address, byte); + return; + } +//Need to protect write attempts to Wavetable ROM (F1D000-FFF) + else if (address >= 0xF1D000 && address <= 0xF1DFFF) + return; + + jerryRAM[address & 0xFFFF] = byte; + } + // hole ($F20000 - $FFFFFF) 1M - 128K + else + ; // Do nothing +} + + +void WriteWord(uint32_t adddress, uint16_t word) +{ +} + + +void WriteDWord(uint32_t adddress, uint32_t dword) +{ +} + + +uint8_t ReadByte(uint32_t adddress) +{ +} + + +uint16_t ReadWord(uint32_t adddress) +{ +} + + +uint32_t ReadDWord(uint32_t adddress) +{ +} +#endif + + +void ShowM68KContext(void) +{ + printf("\t68K PC=%06X\n", m68k_get_reg(NULL, M68K_REG_PC)); + + for(int i=M68K_REG_D0; i<=M68K_REG_D7; i++) + { + printf("D%i = %08X ", i-M68K_REG_D0, m68k_get_reg(NULL, (m68k_register_t)i)); + + if (i == M68K_REG_D3 || i == M68K_REG_D7) + printf("\n"); + } + + for(int i=M68K_REG_A0; i<=M68K_REG_A7; i++) + { + printf("A%i = %08X ", i-M68K_REG_A0, m68k_get_reg(NULL, (m68k_register_t)i)); + + if (i == M68K_REG_A3 || i == M68K_REG_A7) + printf("\n"); + } + + uint32_t currpc = m68k_get_reg(NULL, M68K_REG_PC); + uint32_t disPC = currpc - 30; + char buffer[128]; + + do + { + uint32_t oldpc = disPC; + disPC += m68k_disassemble(buffer, disPC, 0); + printf("%s%08X: %s\n", (oldpc == currpc ? ">" : " "), oldpc, buffer); + } + while (disPC < (currpc + 10)); +} + + +// +// Custom UAE 68000 read/write/IRQ functions +// + +#if 0 +IRQs: +=-=-= + + IPL Name Vector Control + ---------+---------------+---------------+--------------- + 2 VBLANK IRQ $100 INT1 bit #0 + 2 GPU IRQ $100 INT1 bit #1 + 2 HBLANK IRQ $100 INT1 bit #2 + 2 Timer IRQ $100 INT1 bit #3 + + Note: Both timer interrupts (JPIT && PIT) are on the same INT1 bit. + and are therefore indistinguishable. + + A typical way to install a LEVEL2 handler for the 68000 would be + something like this, you gotta supply "last_line" and "handler". + Note that the interrupt is auto vectored thru $100 (not $68) + + + V_AUTO = $100 + VI = $F004E + INT1 = $F00E0 + INT2 = $F00E2 + + IRQS_HANDLED=$909 ;; VBLANK and TIMER + + move.w #$2700,sr ;; no IRQs please + move.l #handler,V_AUTO ;; install our routine + + move.w #last_line,VI ;; scanline where IRQ should occur + ;; should be 'odd' BTW + move.w #IRQS_HANDLE&$FF,INT1 ;; enable VBLANK + TIMER + move.w #$2100,sr ;; enable IRQs on the 68K + ... + +handler: + move.w d0,-(a7) + move.w INT1,d0 + btst.b #0,d0 + bne.b .no_blank + + ... + +.no_blank: + btst.b #3,d0 + beq.b .no_timer + + ... + +.no_timer: + move.w #IRQS_HANDLED,INT1 ; clear latch, keep IRQ alive + move.w #0,INT2 ; let GPU run again + move.w (a7)+,d0 + rte + + As you can see, if you have multiple INT1 interrupts coming in, + you need to check the lower byte of INT1, to see which interrupt + happened. +#endif +int irq_ack_handler(int level) +{ +#ifdef CPU_DEBUG_TRACING + if (startM68KTracing) + { + WriteLog("irq_ack_handler: M68K PC=%06X\n", m68k_get_reg(NULL, M68K_REG_PC)); + } +#endif + + // Tracing the IPL lines on the Jaguar schematic yields the following: + // IPL1 is connected to INTL on TOM (OUT to 68K) + // IPL0-2 are also tied to Vcc via 4.7K resistors! + // (DINT on TOM goes into DINT on JERRY (IN Tom from Jerry)) + // There doesn't seem to be any other path to IPL0 or 2 on the schematic, + // which means that *all* IRQs to the 68K are routed thru TOM at level 2. + // Which means they're all maskable. + + // The GPU/DSP/etc are probably *not* issuing an NMI, but it seems to work + // OK... + // They aren't, and this causes problems with a, err, specific ROM. :-D + + if (level == 2) + { + m68k_set_irq(0); // Clear the IRQ (NOTE: Without this, the BIOS fails)... + return 64; // Set user interrupt #0 + } + + return M68K_INT_ACK_AUTOVECTOR; +} + + +//#define USE_NEW_MMU + +unsigned int m68k_read_memory_8(unsigned int address) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +#ifdef CPU_DEBUG_MEMORY + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFF)) + { + if (startMemLog) + readMem[address] = 1; + } +#endif +//WriteLog("[RM8] Addr: %08X\n", address); +//; So, it seems that it stores the returned DWORD at $51136 and $FB074. +/* if (address == 0x51136 || address == 0x51138 || address == 0xFB074 || address == 0xFB076 + || address == 0x1AF05E) + WriteLog("[RM8 PC=%08X] Addr: %08X, val: %02X\n", m68k_get_reg(NULL, M68K_REG_PC), address, jaguar_mainRam[address]);//*/ +#ifndef USE_NEW_MMU + unsigned int retVal = 0; + + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFF)) + retVal = jaguarMainRAM[address]; +// else if ((address >= 0x800000) && (address <= 0xDFFFFF)) + else if ((address >= 0x800000) && (address <= 0xDFFEFF)) + retVal = jaguarMainROM[address - 0x800000]; + else if ((address >= 0xE00000) && (address <= 0xE3FFFF)) +// retVal = jaguarBootROM[address - 0xE00000]; +// retVal = jaguarDevBootROM1[address - 0xE00000]; + retVal = jagMemSpace[address]; + else if ((address >= 0xDFFF00) && (address <= 0xDFFFFF)) + retVal = CDROMReadByte(address); + else if ((address >= 0xF00000) && (address <= 0xF0FFFF)) + retVal = TOMReadByte(address, M68K); + else if ((address >= 0xF10000) && (address <= 0xF1FFFF)) + retVal = JERRYReadByte(address, M68K); + else + retVal = jaguar_unknown_readbyte(address, M68K); + +//if (address >= 0x2800 && address <= 0x281F) +// WriteLog("M68K: Read byte $%02X at $%08X [PC=%08X]\n", retVal, address, m68k_get_reg(NULL, M68K_REG_PC)); +//if (address >= 0x8B5E4 && address <= 0x8B5E4 + 16) +// WriteLog("M68K: Read byte $%02X at $%08X [PC=%08X]\n", retVal, address, m68k_get_reg(NULL, M68K_REG_PC)); + return retVal; +#else + return MMURead8(address, M68K); +#endif +} + + +void gpu_dump_disassembly(void); +void gpu_dump_registers(void); + +unsigned int m68k_read_memory_16(unsigned int address) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +#ifdef CPU_DEBUG_MEMORY +/* if ((address >= 0x000000) && (address <= 0x3FFFFE)) + { + if (startMemLog) + readMem[address] = 1, readMem[address + 1] = 1; + }//*/ +/* if (effect_start && (address >= 0x8064FC && address <= 0x806501)) + { + return 0x4E71; // NOP + } + if (effect_start2 && (address >= 0x806502 && address <= 0x806507)) + { + return 0x4E71; // NOP + } + if (effect_start3 && (address >= 0x806512 && address <= 0x806517)) + { + return 0x4E71; // NOP + } + if (effect_start4 && (address >= 0x806524 && address <= 0x806527)) + { + return 0x4E71; // NOP + } + if (effect_start5 && (address >= 0x80653E && address <= 0x806543)) //Collision detection! + { + return 0x4E71; // NOP + } + if (effect_start6 && (address >= 0x806544 && address <= 0x806547)) + { + return 0x4E71; // NOP + }//*/ +#endif +//WriteLog("[RM16] Addr: %08X\n", address); +/*if (m68k_get_reg(NULL, M68K_REG_PC) == 0x00005FBA) +// for(int i=0; i<10000; i++) + WriteLog("[M68K] In routine #6!\n");//*/ +//if (m68k_get_reg(NULL, M68K_REG_PC) == 0x00006696) // GPU Program #4 +//if (m68k_get_reg(NULL, M68K_REG_PC) == 0x00005B3C) // GPU Program #2 +/*if (m68k_get_reg(NULL, M68K_REG_PC) == 0x00005BA8) // GPU Program #3 +{ + WriteLog("[M68K] About to run GPU! (Addr:%08X, data:%04X)\n", address, TOMReadWord(address)); + gpu_dump_registers(); + gpu_dump_disassembly(); +// for(int i=0; i<10000; i++) +// WriteLog("[M68K] About to run GPU!\n"); +}//*/ +//WriteLog("[WM8 PC=%08X] Addr: %08X, val: %02X\n", m68k_get_reg(NULL, M68K_REG_PC), address, value); +/*if (m68k_get_reg(NULL, M68K_REG_PC) >= 0x00006696 && m68k_get_reg(NULL, M68K_REG_PC) <= 0x000066A8) +{ + if (address == 0x000066A0) + { + gpu_dump_registers(); + gpu_dump_disassembly(); + } + for(int i=0; i<10000; i++) + WriteLog("[M68K] About to run GPU! (Addr:%08X, data:%04X)\n", address, TOMReadWord(address)); +}//*/ +//; So, it seems that it stores the returned DWORD at $51136 and $FB074. +/* if (address == 0x51136 || address == 0x51138 || address == 0xFB074 || address == 0xFB076 + || address == 0x1AF05E) + WriteLog("[RM16 PC=%08X] Addr: %08X, val: %04X\n", m68k_get_reg(NULL, M68K_REG_PC), address, GET16(jaguar_mainRam, address));//*/ +#ifndef USE_NEW_MMU + unsigned int retVal = 0; + + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFE)) +// retVal = (jaguar_mainRam[address] << 8) | jaguar_mainRam[address+1]; + retVal = GET16(jaguarMainRAM, address); +// else if ((address >= 0x800000) && (address <= 0xDFFFFE)) + else if ((address >= 0x800000) && (address <= 0xDFFEFE)) + { + // Memory Track reading... + if (((TOMGetMEMCON1() & 0x0006) == (2 << 1)) && (jaguarMainROMCRC32 == 0xFDF37F47)) + { + retVal = MTReadWord(address); + } + else + retVal = (jaguarMainROM[address - 0x800000] << 8) + | jaguarMainROM[address - 0x800000 + 1]; + } + else if ((address >= 0xE00000) && (address <= 0xE3FFFE)) +// retVal = (jaguarBootROM[address - 0xE00000] << 8) | jaguarBootROM[address - 0xE00000 + 1]; +// retVal = (jaguarDevBootROM1[address - 0xE00000] << 8) | jaguarDevBootROM1[address - 0xE00000 + 1]; + retVal = (jagMemSpace[address] << 8) | jagMemSpace[address + 1]; + else if ((address >= 0xDFFF00) && (address <= 0xDFFFFE)) + retVal = CDROMReadWord(address, M68K); + else if ((address >= 0xF00000) && (address <= 0xF0FFFE)) + retVal = TOMReadWord(address, M68K); + else if ((address >= 0xF10000) && (address <= 0xF1FFFE)) + retVal = JERRYReadWord(address, M68K); + else + retVal = jaguar_unknown_readword(address, M68K); + +//if (address >= 0xF1B000 && address <= 0xF1CFFF) +// WriteLog("M68K: Read word $%04X at $%08X [PC=%08X]\n", retVal, address, m68k_get_reg(NULL, M68K_REG_PC)); +//if (address >= 0x2800 && address <= 0x281F) +// WriteLog("M68K: Read word $%04X at $%08X [PC=%08X]\n", retVal, address, m68k_get_reg(NULL, M68K_REG_PC)); +//$8B3AE -> Transferred from $F1C010 +//$8B5E4 -> Only +1 read at $808AA +//if (address >= 0x8B5E4 && address <= 0x8B5E4 + 16) +// WriteLog("M68K: Read word $%04X at $%08X [PC=%08X]\n", retVal, address, m68k_get_reg(NULL, M68K_REG_PC)); + return retVal; +#else + return MMURead16(address, M68K); +#endif +} + + +unsigned int m68k_read_memory_32(unsigned int address) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +//; So, it seems that it stores the returned DWORD at $51136 and $FB074. +/* if (address == 0x51136 || address == 0xFB074 || address == 0x1AF05E) + WriteLog("[RM32 PC=%08X] Addr: %08X, val: %08X\n", m68k_get_reg(NULL, M68K_REG_PC), address, (m68k_read_memory_16(address) << 16) | m68k_read_memory_16(address + 2));//*/ + +//WriteLog("--> [RM32]\n"); +#ifndef USE_NEW_MMU + uint32_t retVal = 0; + + if ((address >= 0x800000) && (address <= 0xDFFEFE)) + { + // Memory Track reading... + if (((TOMGetMEMCON1() & 0x0006) == (2 << 1)) && (jaguarMainROMCRC32 == 0xFDF37F47)) + retVal = MTReadLong(address); + else + retVal = GET32(jaguarMainROM, address - 0x800000); + + return retVal; + } + + return (m68k_read_memory_16(address) << 16) | m68k_read_memory_16(address + 2); +#else + return MMURead32(address, M68K); +#endif +} + + +void m68k_write_memory_8(unsigned int address, unsigned int value) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +#ifdef CPU_DEBUG_MEMORY + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFF)) + { + if (startMemLog) + { + if (value > writeMemMax[address]) + writeMemMax[address] = value; + if (value < writeMemMin[address]) + writeMemMin[address] = value; + } + } +#endif +/*if (address == 0x4E00) + WriteLog("M68K: Writing %02X at %08X, PC=%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//if ((address >= 0x1FF020 && address <= 0x1FF03F) || (address >= 0x1FF820 && address <= 0x1FF83F)) +// WriteLog("M68K: Writing %02X at %08X\n", value, address); +//WriteLog("[WM8 PC=%08X] Addr: %08X, val: %02X\n", m68k_get_reg(NULL, M68K_REG_PC), address, value); +/*if (effect_start) + if (address >= 0x18FA70 && address < (0x18FA70 + 8000)) + WriteLog("M68K: Byte %02X written at %08X by 68K\n", value, address);//*/ +//$53D0 +/*if (address >= 0x53D0 && address <= 0x53FF) + printf("M68K: Writing byte $%02X at $%08X, PC=$%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//Testing AvP on UAE core... +//000075A0: FFFFF80E B6320220 (BITMAP) +/*if (address == 0x75A0 && value == 0xFF) + printf("M68K: (8) Tripwire hit...\n");//*/ + +#ifndef USE_NEW_MMU + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFF)) + jaguarMainRAM[address] = value; + else if ((address >= 0xDFFF00) && (address <= 0xDFFFFF)) + CDROMWriteByte(address, value, M68K); + else if ((address >= 0xF00000) && (address <= 0xF0FFFF)) + TOMWriteByte(address, value, M68K); + else if ((address >= 0xF10000) && (address <= 0xF1FFFF)) + JERRYWriteByte(address, value, M68K); + else + jaguar_unknown_writebyte(address, value, M68K); +#else + MMUWrite8(address, value, M68K); +#endif +} + + +void m68k_write_memory_16(unsigned int address, unsigned int value) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +#ifdef CPU_DEBUG_MEMORY + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFE)) + { + if (startMemLog) + { + uint8_t hi = value >> 8, lo = value & 0xFF; + + if (hi > writeMemMax[address]) + writeMemMax[address] = hi; + if (hi < writeMemMin[address]) + writeMemMin[address] = hi; + + if (lo > writeMemMax[address+1]) + writeMemMax[address+1] = lo; + if (lo < writeMemMin[address+1]) + writeMemMin[address+1] = lo; + } + } +#endif +/*if (address == 0x4E00) + WriteLog("M68K: Writing %02X at %08X, PC=%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//if ((address >= 0x1FF020 && address <= 0x1FF03F) || (address >= 0x1FF820 && address <= 0x1FF83F)) +// WriteLog("M68K: Writing %04X at %08X\n", value, address); +//WriteLog("[WM16 PC=%08X] Addr: %08X, val: %04X\n", m68k_get_reg(NULL, M68K_REG_PC), address, value); +//if (address >= 0xF02200 && address <= 0xF0229F) +// WriteLog("M68K: Writing to blitter --> %04X at %08X\n", value, address); +//if (address >= 0x0E75D0 && address <= 0x0E75E7) +// WriteLog("M68K: Writing %04X at %08X, M68K PC=%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC)); +/*extern uint32_t totalFrames; +if (address == 0xF02114) + WriteLog("M68K: Writing to GPU_CTRL (frame:%u)... [M68K PC:%08X]\n", totalFrames, m68k_get_reg(NULL, M68K_REG_PC)); +if (address == 0xF02110) + WriteLog("M68K: Writing to GPU_PC (frame:%u)... [M68K PC:%08X]\n", totalFrames, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//if (address >= 0xF03B00 && address <= 0xF03DFF) +// WriteLog("M68K: Writing %04X to %08X...\n", value, address); + +/*if (address == 0x0100)//64*4) + WriteLog("M68K: Wrote word to VI vector value %04X...\n", value);//*/ +/*if (effect_start) + if (address >= 0x18FA70 && address < (0x18FA70 + 8000)) + WriteLog("M68K: Word %04X written at %08X by 68K\n", value, address);//*/ +/* if (address == 0x51136 || address == 0x51138 || address == 0xFB074 || address == 0xFB076 + || address == 0x1AF05E) + WriteLog("[WM16 PC=%08X] Addr: %08X, val: %04X\n", m68k_get_reg(NULL, M68K_REG_PC), address, value);//*/ +//$53D0 +/*if (address >= 0x53D0 && address <= 0x53FF) + printf("M68K: Writing word $%04X at $%08X, PC=$%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//Testing AvP on UAE core... +//000075A0: FFFFF80E B6320220 (BITMAP) +/*if (address == 0x75A0 && value == 0xFFFF) +{ + printf("\nM68K: (16) Tripwire hit...\n"); + ShowM68KContext(); +}//*/ + +#ifndef USE_NEW_MMU + // Note that the Jaguar only has 2M of RAM, not 4! + if ((address >= 0x000000) && (address <= 0x1FFFFE)) + { +/* jaguar_mainRam[address] = value >> 8; + jaguar_mainRam[address + 1] = value & 0xFF;*/ + SET16(jaguarMainRAM, address, value); + } + // Memory Track device writes.... + else if ((address >= 0x800000) && (address <= 0x87FFFE)) + { + if (((TOMGetMEMCON1() & 0x0006) == (2 << 1)) && (jaguarMainROMCRC32 == 0xFDF37F47)) + MTWriteWord(address, value); + } + else if ((address >= 0xDFFF00) && (address <= 0xDFFFFE)) + CDROMWriteWord(address, value, M68K); + else if ((address >= 0xF00000) && (address <= 0xF0FFFE)) + TOMWriteWord(address, value, M68K); + else if ((address >= 0xF10000) && (address <= 0xF1FFFE)) + JERRYWriteWord(address, value, M68K); + else + { + jaguar_unknown_writeword(address, value, M68K); +#ifdef LOG_UNMAPPED_MEMORY_ACCESSES + WriteLog("\tA0=%08X, A1=%08X, D0=%08X, D1=%08X\n", + m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), + m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1)); +#endif + } +#else + MMUWrite16(address, value, M68K); +#endif +} + + +void m68k_write_memory_32(unsigned int address, unsigned int value) +{ +#ifdef ALPINE_FUNCTIONS + // Check if breakpoint on memory is active, and deal with it + if (bpmActive && address == bpmAddress1) + M68KDebugHalt(); +#endif + + // Musashi does this automagically for you, UAE core does not :-P + address &= 0x00FFFFFF; +/*if (address == 0x4E00) + WriteLog("M68K: Writing %02X at %08X, PC=%08X\n", value, address, m68k_get_reg(NULL, M68K_REG_PC));//*/ +//WriteLog("--> [WM32]\n"); +/*if (address == 0x0100)//64*4) + WriteLog("M68K: Wrote dword to VI vector value %08X...\n", value);//*/ +/*if (address >= 0xF03214 && address < 0xF0321F) + WriteLog("M68K: Writing DWORD (%08X) to GPU RAM (%08X)...\n", value, address);//*/ +//M68K: Writing DWORD (88E30047) to GPU RAM (00F03214)... +/*extern bool doGPUDis; +if (address == 0xF03214 && value == 0x88E30047) +// start = true; + doGPUDis = true;//*/ +/* if (address == 0x51136 || address == 0xFB074) + WriteLog("[WM32 PC=%08X] Addr: %08X, val: %02X\n", m68k_get_reg(NULL, M68K_REG_PC), address, value);//*/ +//Testing AvP on UAE core... +//000075A0: FFFFF80E B6320220 (BITMAP) +/*if (address == 0x75A0 && (value & 0xFFFF0000) == 0xFFFF0000) +{ + printf("\nM68K: (32) Tripwire hit...\n"); + ShowM68KContext(); +}//*/ + +#ifndef USE_NEW_MMU + m68k_write_memory_16(address, value >> 16); + m68k_write_memory_16(address + 2, value & 0xFFFF); +#else + MMUWrite32(address, value, M68K); +#endif +} + + +uint32_t JaguarGetHandler(uint32_t i) +{ + return JaguarReadLong(i * 4); +} + + +bool JaguarInterruptHandlerIsValid(uint32_t i) // Debug use only... +{ + uint32_t handler = JaguarGetHandler(i); + return (handler && (handler != 0xFFFFFFFF) ? true : false); +} + + +void M68K_show_context(void) +{ + WriteLog("68K PC=%06X\n", m68k_get_reg(NULL, M68K_REG_PC)); + + for(int i=M68K_REG_D0; i<=M68K_REG_D7; i++) + { + WriteLog("D%i = %08X ", i-M68K_REG_D0, m68k_get_reg(NULL, (m68k_register_t)i)); + + if (i == M68K_REG_D3 || i == M68K_REG_D7) + WriteLog("\n"); + } + + for(int i=M68K_REG_A0; i<=M68K_REG_A7; i++) + { + WriteLog("A%i = %08X ", i-M68K_REG_A0, m68k_get_reg(NULL, (m68k_register_t)i)); + + if (i == M68K_REG_A3 || i == M68K_REG_A7) + WriteLog("\n"); + } + + WriteLog("68K disasm\n"); +// jaguar_dasm(s68000readPC()-0x1000,0x20000); + JaguarDasm(m68k_get_reg(NULL, M68K_REG_PC) - 0x80, 0x200); +// jaguar_dasm(0x5000, 0x14414); + +// WriteLog("\n.......[Cart start]...........\n\n"); +// jaguar_dasm(0x192000, 0x1000);//0x200); + + WriteLog("..................\n"); + + if (TOMIRQEnabled(IRQ_VIDEO)) + { + WriteLog("video int: enabled\n"); + JaguarDasm(JaguarGetHandler(64), 0x200); + } + else + WriteLog("video int: disabled\n"); + + WriteLog("..................\n"); + + for(int i=0; i<256; i++) + { + WriteLog("handler %03i at ", i);//$%08X\n", i, (unsigned int)JaguarGetHandler(i)); + uint32_t address = (uint32_t)JaguarGetHandler(i); + + if (address == 0) + WriteLog(".........\n"); + else + WriteLog("$%08X\n", address); + } +} + + +// +// Unknown read/write byte/word routines +// + +// It's hard to believe that developers would be sloppy with their memory +// writes, yet in some cases the developers screwed up royal. E.g., Club Drive +// has the following code: +// +// 807EC4: movea.l #$f1b000, A1 +// 807ECA: movea.l #$8129e0, A0 +// 807ED0: move.l A0, D0 +// 807ED2: move.l #$f1bb94, D1 +// 807ED8: sub.l D0, D1 +// 807EDA: lsr.l #2, D1 +// 807EDC: move.l (A0)+, (A1)+ +// 807EDE: dbra D1, 807edc +// +// The problem is at $807ED0--instead of putting A0 into D0, they really meant +// to put A1 in. This mistake causes it to try and overwrite approximately +// $700000 worth of address space! (That is, unless the 68K causes a bus +// error...) + +void jaguar_unknown_writebyte(unsigned address, unsigned data, uint32_t who/*=UNKNOWN*/) +{ +#ifdef LOG_UNMAPPED_MEMORY_ACCESSES + WriteLog("Jaguar: Unknown byte %02X written at %08X by %s (M68K PC=%06X)\n", data, address, whoName[who], m68k_get_reg(NULL, M68K_REG_PC)); +#endif +#ifdef ABORT_ON_UNMAPPED_MEMORY_ACCESS +// extern bool finished; + finished = true; +// extern bool doDSPDis; + if (who == DSP) + doDSPDis = true; +#endif +} + + +void jaguar_unknown_writeword(unsigned address, unsigned data, uint32_t who/*=UNKNOWN*/) +{ +#ifdef LOG_UNMAPPED_MEMORY_ACCESSES + WriteLog("Jaguar: Unknown word %04X written at %08X by %s (M68K PC=%06X)\n", data, address, whoName[who], m68k_get_reg(NULL, M68K_REG_PC)); +#endif +#ifdef ABORT_ON_UNMAPPED_MEMORY_ACCESS +// extern bool finished; + finished = true; +// extern bool doDSPDis; + if (who == DSP) + doDSPDis = true; +#endif +} + + +unsigned jaguar_unknown_readbyte(unsigned address, uint32_t who/*=UNKNOWN*/) +{ +#ifdef LOG_UNMAPPED_MEMORY_ACCESSES + WriteLog("Jaguar: Unknown byte read at %08X by %s (M68K PC=%06X)\n", address, whoName[who], m68k_get_reg(NULL, M68K_REG_PC)); +#endif +#ifdef ABORT_ON_UNMAPPED_MEMORY_ACCESS +// extern bool finished; + finished = true; +// extern bool doDSPDis; + if (who == DSP) + doDSPDis = true; +#endif + return 0xFF; +} + + +unsigned jaguar_unknown_readword(unsigned address, uint32_t who/*=UNKNOWN*/) +{ +#ifdef LOG_UNMAPPED_MEMORY_ACCESSES + WriteLog("Jaguar: Unknown word read at %08X by %s (M68K PC=%06X)\n", address, whoName[who], m68k_get_reg(NULL, M68K_REG_PC)); +#endif +#ifdef ABORT_ON_UNMAPPED_MEMORY_ACCESS +// extern bool finished; + finished = true; +// extern bool doDSPDis; + if (who == DSP) + doDSPDis = true; +#endif + return 0xFFFF; +} + + +// +// Disassemble M68K instructions at the given offset +// + +unsigned int m68k_read_disassembler_8(unsigned int address) +{ + return m68k_read_memory_8(address); +} + + +unsigned int m68k_read_disassembler_16(unsigned int address) +{ + return m68k_read_memory_16(address); +} + + +unsigned int m68k_read_disassembler_32(unsigned int address) +{ + return m68k_read_memory_32(address); +} + + +void JaguarDasm(uint32_t offset, uint32_t qt) +{ +#ifdef CPU_DEBUG + static char buffer[2048];//, mem[64]; + int pc = offset, oldpc; + + for(uint32_t i=0; i= 0x800000) && (offset < 0xDFFF00)) + data = jaguarMainROM[offset - 0x800000]; + else if ((offset >= 0xDFFF00) && (offset <= 0xDFFFFF)) + data = CDROMReadByte(offset, who); + else if ((offset >= 0xE00000) && (offset < 0xE40000)) +// data = jaguarBootROM[offset & 0x3FFFF]; +// data = jaguarDevBootROM1[offset & 0x3FFFF]; + data = jagMemSpace[offset]; + else if ((offset >= 0xF00000) && (offset < 0xF10000)) + data = TOMReadByte(offset, who); + else if ((offset >= 0xF10000) && (offset < 0xF20000)) + data = JERRYReadByte(offset, who); + else + data = jaguar_unknown_readbyte(offset, who); + + return data; +} + + +uint16_t JaguarReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0xFFFFFF; + + // First 2M is mirrored in the $0 - $7FFFFF range + if (offset < 0x800000) + { + return (jaguarMainRAM[(offset+0) & 0x1FFFFF] << 8) | jaguarMainRAM[(offset+1) & 0x1FFFFF]; + } + else if ((offset >= 0x800000) && (offset < 0xDFFF00)) + { + offset -= 0x800000; + return (jaguarMainROM[offset+0] << 8) | jaguarMainROM[offset+1]; + } +// else if ((offset >= 0xDFFF00) && (offset < 0xDFFF00)) + else if ((offset >= 0xDFFF00) && (offset <= 0xDFFFFE)) + return CDROMReadWord(offset, who); + else if ((offset >= 0xE00000) && (offset <= 0xE3FFFE)) +// return (jaguarBootROM[(offset+0) & 0x3FFFF] << 8) | jaguarBootROM[(offset+1) & 0x3FFFF]; +// return (jaguarDevBootROM1[(offset+0) & 0x3FFFF] << 8) | jaguarDevBootROM1[(offset+1) & 0x3FFFF]; + return (jagMemSpace[offset + 0] << 8) | jagMemSpace[offset + 1]; + else if ((offset >= 0xF00000) && (offset <= 0xF0FFFE)) + return TOMReadWord(offset, who); + else if ((offset >= 0xF10000) && (offset <= 0xF1FFFE)) + return JERRYReadWord(offset, who); + + return jaguar_unknown_readword(offset, who); +} + + +void JaguarWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ +/* if ((offset & 0x1FFFFF) >= 0xE00 && (offset & 0x1FFFFF) < 0xE18) + { + WriteLog("JWB: Byte %02X written at %08X by %s\n", data, offset, whoName[who]); + }//*/ +/* if (offset >= 0x4E00 && offset < 0x4E04) + WriteLog("JWB: Byte %02X written at %08X by %s\n", data, offset, whoName[who]);//*/ +//Need to check for writes in the range of $18FA70 + 8000... +/*if (effect_start) + if (offset >= 0x18FA70 && offset < (0x18FA70 + 8000)) + WriteLog("JWB: Byte %02X written at %08X by %s\n", data, offset, whoName[who]);//*/ + + offset &= 0xFFFFFF; + + // First 2M is mirrored in the $0 - $7FFFFF range + if (offset < 0x800000) + { + jaguarMainRAM[offset & 0x1FFFFF] = data; + return; + } + else if ((offset >= 0xDFFF00) && (offset <= 0xDFFFFF)) + { + CDROMWriteByte(offset, data, who); + return; + } + else if ((offset >= 0xF00000) && (offset <= 0xF0FFFF)) + { + TOMWriteByte(offset, data, who); + return; + } + else if ((offset >= 0xF10000) && (offset <= 0xF1FFFF)) + { + JERRYWriteByte(offset, data, who); + return; + } + + jaguar_unknown_writebyte(offset, data, who); +} + + +uint32_t starCount; +void JaguarWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ +/* if ((offset & 0x1FFFFF) >= 0xE00 && (offset & 0x1FFFFF) < 0xE18) + { + WriteLog("JWW: Word %04X written at %08X by %s\n", data, offset, whoName[who]); + WriteLog(" GPU PC = $%06X\n", GPUReadLong(0xF02110, DEBUG)); + }//*/ +/* if (offset >= 0x4E00 && offset < 0x4E04) + WriteLog("JWW: Word %04X written at %08X by %s\n", data, offset, whoName[who]);//*/ +/*if (offset == 0x0100)//64*4) + WriteLog("M68K: %s wrote word to VI vector value %04X...\n", whoName[who], data); +if (offset == 0x0102)//64*4) + WriteLog("M68K: %s wrote word to VI vector+2 value %04X...\n", whoName[who], data);//*/ +//TEMP--Mirror of F03000? Yes, but only 32-bit CPUs can do it (i.e., NOT the 68K!) +// PLUS, you would handle this in the GPU/DSP WriteLong code! Not here! +//Need to check for writes in the range of $18FA70 + 8000... +/*if (effect_start) + if (offset >= 0x18FA70 && offset < (0x18FA70 + 8000)) + WriteLog("JWW: Word %04X written at %08X by %s\n", data, offset, whoName[who]);//*/ +/*if (offset >= 0x2C00 && offset <= 0x2CFF) + WriteLog("Jaguar: Word %04X written to TOC+%02X by %s\n", data, offset-0x2C00, whoName[who]);//*/ + + offset &= 0xFFFFFF; + + // First 2M is mirrored in the $0 - $7FFFFF range + if (offset <= 0x7FFFFE) + { +/* +GPU Table (CD BIOS) + +1A 69 F0 ($0000) -> Starfield +1A 73 C8 ($0001) -> Final clearing blit & bitmap blit? +1A 79 F0 ($0002) +1A 88 C0 ($0003) +1A 8F E8 ($0004) -> "Jaguar" small color logo? +1A 95 20 ($0005) +1A 9F 08 ($0006) +1A A1 38 ($0007) +1A AB 38 ($0008) +1A B3 C8 ($0009) +1A B9 C0 ($000A) +*/ + +//This MUST be done by the 68K! +/*if (offset == 0x670C) + WriteLog("Jaguar: %s writing to location $670C...\n", whoName[who]);*/ + +/*extern bool doGPUDis; +//if ((offset == 0x100000 + 75522) && who == GPU) // 76,226 -> 75522 +if ((offset == 0x100000 + 128470) && who == GPU) // 107,167 -> 128470 (384 x 250 screen size 16BPP) +//if ((offset >= 0x100000 && offset <= 0x12C087) && who == GPU) + doGPUDis = true;//*/ +/*if (offset == 0x100000 + 128470) // 107,167 -> 128470 (384 x 250 screen size 16BPP) + WriteLog("JWW: Writing value %04X at %08X by %s...\n", data, offset, whoName[who]); +if ((data & 0xFF00) != 0x7700) + WriteLog("JWW: Writing value %04X at %08X by %s...\n", data, offset, whoName[who]);//*/ +/*if ((offset >= 0x100000 && offset <= 0x147FFF) && who == GPU) + return;//*/ +/*if ((data & 0xFF00) != 0x7700 && who == GPU) + WriteLog("JWW: Writing value %04X at %08X by %s...\n", data, offset, whoName[who]);//*/ +/*if ((offset >= 0x100000 + 0x48000 && offset <= 0x12C087 + 0x48000) && who == GPU) + return;//*/ +/*extern bool doGPUDis; +if (offset == 0x120216 && who == GPU) + doGPUDis = true;//*/ +/*extern uint32_t gpu_pc; +if (who == GPU && (gpu_pc == 0xF03604 || gpu_pc == 0xF03638)) +{ + uint32_t base = offset - (offset > 0x148000 ? 0x148000 : 0x100000); + uint32_t y = base / 0x300; + uint32_t x = (base - (y * 0x300)) / 2; + WriteLog("JWW: Writing starfield star %04X at %08X (%u/%u) [%s]\n", data, offset, x, y, (gpu_pc == 0xF03604 ? "s" : "L")); +}//*/ +/* +JWW: Writing starfield star 775E at 0011F650 (555984/1447) +*/ +//if (offset == (0x001E17F8 + 0x34)) +/*if (who == GPU && offset == (0x001E17F8 + 0x34)) + data = 0xFE3C;//*/ +// WriteLog("JWW: Write at %08X written to by %s.\n", 0x001E17F8 + 0x34, whoName[who]);//*/ +/*extern uint32_t gpu_pc; +if (who == GPU && (gpu_pc == 0xF03604 || gpu_pc == 0xF03638)) +{ + extern int objectPtr; +// if (offset > 0x148000) +// return; + starCount++; + if (starCount > objectPtr) + return; + +// if (starCount == 1) +// WriteLog("--> Drawing 1st star...\n"); +// +// uint32_t base = offset - (offset > 0x148000 ? 0x148000 : 0x100000); +// uint32_t y = base / 0x300; +// uint32_t x = (base - (y * 0x300)) / 2; +// WriteLog("JWW: Writing starfield star %04X at %08X (%u/%u) [%s]\n", data, offset, x, y, (gpu_pc == 0xF03604 ? "s" : "L")); + +//A star of interest... +//-->JWW: Writing starfield star 77C9 at 0011D31A (269/155) [s] +//1st trail +3(x), -1(y) -> 272, 154 -> 0011D020 +//JWW: Blitter writing echo 77B3 at 0011D022... +}//*/ +//extern bool doGPUDis; +/*if (offset == 0x11D022 + 0x48000 || offset == 0x11D022)// && who == GPU) +{ +// doGPUDis = true; + WriteLog("JWW: %s writing echo %04X at %08X...\n", whoName[who], data, offset); +// LogBlit(); +} +if (offset == 0x11D31A + 0x48000 || offset == 0x11D31A) + WriteLog("JWW: %s writing star %04X at %08X...\n", whoName[who], data, offset);//*/ + + jaguarMainRAM[(offset+0) & 0x1FFFFF] = data >> 8; + jaguarMainRAM[(offset+1) & 0x1FFFFF] = data & 0xFF; + return; + } + else if (offset >= 0xDFFF00 && offset <= 0xDFFFFE) + { + CDROMWriteWord(offset, data, who); + return; + } + else if (offset >= 0xF00000 && offset <= 0xF0FFFE) + { + TOMWriteWord(offset, data, who); + return; + } + else if (offset >= 0xF10000 && offset <= 0xF1FFFE) + { + JERRYWriteWord(offset, data, who); + return; + } + // Don't bomb on attempts to write to ROM + else if (offset >= 0x800000 && offset <= 0xEFFFFF) + return; + + jaguar_unknown_writeword(offset, data, who); +} + + +// We really should re-do this so that it does *real* 32-bit access... !!! FIX !!! +uint32_t JaguarReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + return (JaguarReadWord(offset, who) << 16) | JaguarReadWord(offset+2, who); +} + + +// We really should re-do this so that it does *real* 32-bit access... !!! FIX !!! +void JaguarWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/) +{ +/* extern bool doDSPDis; + if (offset < 0x400 && !doDSPDis) + { + WriteLog("JLW: Write to %08X by %s... Starting DSP log!\n\n", offset, whoName[who]); + doDSPDis = true; + }//*/ +/*if (offset == 0x0100)//64*4) + WriteLog("M68K: %s wrote dword to VI vector value %08X...\n", whoName[who], data);//*/ + + JaguarWriteWord(offset, data >> 16, who); + JaguarWriteWord(offset+2, data & 0xFFFF, who); +} + + +void JaguarSetScreenBuffer(uint32_t * buffer) +{ + // This is in TOM, but we set it here... + screenBuffer = buffer; +} + + +void JaguarSetScreenPitch(uint32_t pitch) +{ + // This is in TOM, but we set it here... + screenPitch = pitch; +} + + +// +// Jaguar console initialization +// +void JaguarInit(void) +{ + // For randomizing RAM + srand(time(NULL)); + + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32_t i=0; i<0x200000; i+=4) + *((uint32_t *)(&jaguarMainRAM[i])) = rand(); + +#ifdef CPU_DEBUG_MEMORY + memset(readMem, 0x00, 0x400000); + memset(writeMemMin, 0xFF, 0x400000); + memset(writeMemMax, 0x00, 0x400000); +#endif +// memset(jaguarMainRAM, 0x00, 0x200000); +// memset(jaguar_mainRom, 0xFF, 0x200000); // & set it to all Fs... +// memset(jaguar_mainRom, 0x00, 0x200000); // & set it to all 0s... +//NOTE: This *doesn't* fix FlipOut... +//Or does it? Hmm... +//Seems to want $01010101... Dunno why. Investigate! +// memset(jaguarMainROM, 0x01, 0x600000); // & set it to all 01s... +// memset(jaguar_mainRom, 0xFF, 0x600000); // & set it to all Fs... + lowerField = false; // Reset the lower field flag +//temp, for crappy crap that sux +memset(jaguarMainRAM + 0x804, 0xFF, 4); + + m68k_pulse_reset(); // Need to do this so UAE disasm doesn't segfault on exit + GPUInit(); + DSPInit(); + TOMInit(); + JERRYInit(); + CDROMInit(); +} + + +//New timer based code stuffola... +void HalflineCallback(void); +void RenderCallback(void); +void JaguarReset(void) +{ + // Only problem with this approach: It wipes out RAM loaded files...! + // Contents of local RAM are quasi-stable; we simulate this by randomizing RAM contents + for(uint32_t i=8; i<0x200000; i+=4) + *((uint32_t *)(&jaguarMainRAM[i])) = rand(); + + // New timer base code stuffola... + InitializeEventList(); +//Need to change this so it uses the single RAM space and load the BIOS +//into it somewhere... +//Also, have to change this here and in JaguarReadXX() currently + // Only use the system BIOS if it's available...! (it's always available now!) + // AND only if a jaguar cartridge has been inserted. + if (vjs.useJaguarBIOS && jaguarCartInserted && !vjs.hardwareTypeAlpine) + memcpy(jaguarMainRAM, jagMemSpace + 0xE00000, 8); + else + SET32(jaguarMainRAM, 4, jaguarRunAddress); + +// WriteLog("jaguar_reset():\n"); + TOMReset(); + JERRYReset(); + GPUReset(); + DSPReset(); + CDROMReset(); + m68k_pulse_reset(); // Reset the 68000 + WriteLog("Jaguar: 68K reset. PC=%06X SP=%08X\n", m68k_get_reg(NULL, M68K_REG_PC), m68k_get_reg(NULL, M68K_REG_A7)); + + lowerField = false; // Reset the lower field flag +// SetCallbackTime(ScanlineCallback, 63.5555); +// SetCallbackTime(ScanlineCallback, 31.77775); + SetCallbackTime(HalflineCallback, (vjs.hardwareTypeNTSC ? 31.777777777 : 32.0)); +} + + +void JaguarDone(void) +{ +#ifdef CPU_DEBUG_MEMORY +/* WriteLog("\nJaguar: Memory Usage Stats (return addresses)\n\n"); + + for(uint32_t i=0; i<=raPtr; i++) + { + WriteLog("\t%08X\n", returnAddr[i]); + WriteLog("M68000 disassembly at $%08X...\n", returnAddr[i] - 16); + jaguar_dasm(returnAddr[i] - 16, 16); + WriteLog("\n"); + } + WriteLog("\n");//*/ + +/* int start = 0, end = 0; + bool endTriggered = false, startTriggered = false; + for(int i=0; i<0x400000; i++) + { + if (readMem[i] && writeMemMin[i] != 0xFF && writeMemMax != 0x00) + { + if (!startTriggered) + startTriggered = true, endTriggered = false, start = i; + + WriteLog("\t\tMin/Max @ %06X: %u/%u\n", i, writeMemMin[i], writeMemMax[i]); + } + else + { + if (!endTriggered) + { + end = i - 1, endTriggered = true, startTriggered = false; + WriteLog("\tMemory range accessed: %06X - %06X\n", start, end); + } + } + } + WriteLog("\n");//*/ +#endif +//#ifdef CPU_DEBUG +// for(int i=M68K_REG_A0; i<=M68K_REG_A7; i++) +// WriteLog("\tA%i = 0x%.8x\n", i-M68K_REG_A0, m68k_get_reg(NULL, (m68k_register_t)i)); + int32_t topOfStack = m68k_get_reg(NULL, M68K_REG_A7); + WriteLog("M68K: Top of stack: %08X -> (%08X). Stack trace:\n", topOfStack, JaguarReadLong(topOfStack)); +#if 0 + for(int i=-2; i<9; i++) + WriteLog("%06X: %08X\n", topOfStack + (i * 4), JaguarReadLong(topOfStack + (i * 4))); +#else + uint32_t address = topOfStack - (4 * 4 * 3); + + for(int i=0; i<10; i++) + { + WriteLog("%06X:", address); + + for(int j=0; j<4; j++) + { + WriteLog(" %08X", JaguarReadLong(address)); + address += 4; + } + + WriteLog("\n"); + } +#endif + +/* WriteLog("\nM68000 disassembly at $802288...\n"); + jaguar_dasm(0x802288, 3); + WriteLog("\nM68000 disassembly at $802200...\n"); + jaguar_dasm(0x802200, 500); + WriteLog("\nM68000 disassembly at $802518...\n"); + jaguar_dasm(0x802518, 100);//*/ + +/* WriteLog("\n\nM68000 disassembly at $803F00 (look @ $803F2A)...\n"); + jaguar_dasm(0x803F00, 500); + WriteLog("\n");//*/ + +/* WriteLog("\n\nM68000 disassembly at $802B00 (look @ $802B5E)...\n"); + jaguar_dasm(0x802B00, 500); + WriteLog("\n");//*/ + +/* WriteLog("\n\nM68000 disassembly at $809900 (look @ $8099F8)...\n"); + jaguar_dasm(0x809900, 500); + WriteLog("\n");//*/ +//8099F8 +/* WriteLog("\n\nDump of $8093C8:\n\n"); + for(int i=0x8093C8; i<0x809900; i+=4) + WriteLog("%06X: %08X\n", i, JaguarReadLong(i));//*/ +/* WriteLog("\n\nM68000 disassembly at $90006C...\n"); + jaguar_dasm(0x90006C, 500); + WriteLog("\n");//*/ +/* WriteLog("\n\nM68000 disassembly at $1AC000...\n"); + jaguar_dasm(0x1AC000, 6000); + WriteLog("\n");//*/ + +// WriteLog("Jaguar: CD BIOS version %04X\n", JaguarReadWord(0x3004)); + WriteLog("Jaguar: Interrupt enable = $%02X\n", TOMReadByte(0xF000E1, JAGUAR) & 0x1F); + WriteLog("Jaguar: Video interrupt is %s (line=%u)\n", ((TOMIRQEnabled(IRQ_VIDEO)) + && (JaguarInterruptHandlerIsValid(64))) ? "enabled" : "disabled", TOMReadWord(0xF0004E, JAGUAR)); + M68K_show_context(); +//#endif + + CDROMDone(); + GPUDone(); + DSPDone(); + TOMDone(); + JERRYDone(); + + // temp, until debugger is in place +//00802016: jsr $836F1A.l +//0080201C: jsr $836B30.l +//00802022: jsr $836B18.l +//00802028: jsr $8135F0.l +//00813C1E: jsr $813F76.l +//00802038: jsr $836D00.l +//00802098: jsr $8373A4.l +//008020A2: jsr $83E24A.l +//008020BA: jsr $83E156.l +//008020C6: jsr $83E19C.l +//008020E6: jsr $8445E8.l +//008020EC: jsr $838C20.l +//0080211A: jsr $838ED6.l +//00802124: jsr $89CA56.l +//0080212A: jsr $802B48.l +#if 0 + WriteLog("-------------------------------------------\n"); + JaguarDasm(0x8445E8, 0x200); + WriteLog("-------------------------------------------\n"); + JaguarDasm(0x838C20, 0x200); + WriteLog("-------------------------------------------\n"); + JaguarDasm(0x838ED6, 0x200); + WriteLog("-------------------------------------------\n"); + JaguarDasm(0x89CA56, 0x200); + WriteLog("-------------------------------------------\n"); + JaguarDasm(0x802B48, 0x200); + WriteLog("\n\nM68000 disassembly at $802000...\n"); + JaguarDasm(0x802000, 6000); + WriteLog("\n");//*/ +#endif +/* WriteLog("\n\nM68000 disassembly at $6004...\n"); + JaguarDasm(0x6004, 10000); + WriteLog("\n");//*/ +// WriteLog("\n\nM68000 disassembly at $802000...\n"); +// JaguarDasm(0x802000, 0x1000); +// WriteLog("\n\nM68000 disassembly at $4100...\n"); +// JaguarDasm(0x4100, 200); +// WriteLog("\n\nM68000 disassembly at $800800...\n"); +// JaguarDasm(0x800800, 0x1000); +} + + +// Temp debugging stuff + +void DumpMainMemory(void) +{ + FILE * fp = fopen("./memdump.bin", "wb"); + + if (fp == NULL) + return; + + fwrite(jaguarMainRAM, 1, 0x200000, fp); + fclose(fp); +} + + +uint8_t * GetRamPtr(void) +{ + return jaguarMainRAM; +} + + +// +// New Jaguar execution stack +// This executes 1 frame's worth of code. +// +bool frameDone; +void JaguarExecuteNew(void) +{ + frameDone = false; + + do + { + double timeToNextEvent = GetTimeToNextEvent(); +//WriteLog("JEN: Time to next event (%u) is %f usec (%u RISC cycles)...\n", nextEvent, timeToNextEvent, USEC_TO_RISC_CYCLES(timeToNextEvent)); + + m68k_execute(USEC_TO_M68K_CYCLES(timeToNextEvent)); + + if (vjs.GPUEnabled) + GPUExec(USEC_TO_RISC_CYCLES(timeToNextEvent)); + + HandleNextEvent(); + } + while (!frameDone); +} + + +// +// The thing to keep in mind is that the VC is advanced every HALF line, +// regardless of whether the display is interlaced or not. The only difference +// with an interlaced display is that the high bit of VC will be set when the +// lower field is being rendered. (NB: The high bit of VC is ALWAYS set on the +// lower field, regardless of whether it's in interlace mode or not. +// NB2: Seems it doesn't always, not sure what the constraint is...) +// +// Normally, TVs will render a full frame in 1/30s (NTSC) or 1/25s (PAL) by +// rendering two fields that are slighty vertically offset from each other. +// Each field is created in 1/60s (NTSC) or 1/50s (PAL), and every other line +// is rendered in this mode so that each field, when overlaid on each other, +// will yield the final picture at the full resolution for the full frame. +// +// We execute a half frame in each timeslice (1/60s NTSC, 1/50s PAL). +// Since the number of lines in a FULL frame is 525 for NTSC, 625 for PAL, +// it will be half this number for a half frame. BUT, since we're counting +// HALF lines, we double this number and we're back at 525 for NTSC, 625 for +// PAL. +// +// Scanline times are 63.5555... μs in NTSC and 64 μs in PAL +// Half line times are, naturally, half of this. :-P +// +void HalflineCallback(void) +{ + uint16_t vc = TOMReadWord(0xF00006, JAGUAR); + uint16_t vp = TOMReadWord(0xF0003E, JAGUAR) + 1; + uint16_t vi = TOMReadWord(0xF0004E, JAGUAR); +// uint16_t vbb = TOMReadWord(0xF00040, JAGUAR); + vc++; + + // Each # of lines is for a full frame == 1/30s (NTSC), 1/25s (PAL). + // So we cut the number of half-lines in a frame in half. :-P + uint16_t numHalfLines = ((vjs.hardwareTypeNTSC ? 525 : 625) * 2) / 2; + + if ((vc & 0x7FF) >= numHalfLines) + { + lowerField = !lowerField; + // If we're rendering the lower field, set the high bit (#11, counting + // from 0) of VC + vc = (lowerField ? 0x0800 : 0x0000); + } + +//WriteLog("HLC: Currently on line %u (VP=%u)...\n", vc, vp); + TOMWriteWord(0xF00006, vc, JAGUAR); + + // Time for Vertical Interrupt? + if ((vc & 0x7FF) == vi && (vc & 0x7FF) > 0 && TOMIRQEnabled(IRQ_VIDEO)) + { + // We don't have to worry about autovectors & whatnot because the Jaguar + // tells you through its HW registers who sent the interrupt... + TOMSetPendingVideoInt(); + m68k_set_irq(2); + } + + TOMExecHalfline(vc, true); + +//Change this to VBB??? +//Doesn't seem to matter (at least for Flip Out & I-War) + if ((vc & 0x7FF) == 0) +// if (vc == vbb) + { + JoystickExec(); + frameDone = true; + }//*/ + + SetCallbackTime(HalflineCallback, (vjs.hardwareTypeNTSC ? 31.777777777 : 32.0)); +} + diff --git a/waterbox/virtualjaguar/src/jaguar.h b/waterbox/virtualjaguar/src/jaguar.h new file mode 100644 index 0000000000..63e6de6238 --- /dev/null +++ b/waterbox/virtualjaguar/src/jaguar.h @@ -0,0 +1,51 @@ +#ifndef __JAGUAR_H__ +#define __JAGUAR_H__ + +#include +#include "memory.h" // For "UNKNOWN" enum + +void JaguarSetScreenBuffer(uint32_t * buffer); +void JaguarSetScreenPitch(uint32_t pitch); +void JaguarInit(void); +void JaguarReset(void); +void JaguarDone(void); + +uint8_t JaguarReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t JaguarReadWord(uint32_t offset, uint32_t who = UNKNOWN); +uint32_t JaguarReadLong(uint32_t offset, uint32_t who = UNKNOWN); +void JaguarWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void JaguarWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); +void JaguarWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN); + +bool JaguarInterruptHandlerIsValid(uint32_t i); +void JaguarDasm(uint32_t offset, uint32_t qt); + +void JaguarExecuteNew(void); + +// Exports from JAGUAR.CPP + +extern int32_t jaguarCPUInExec; +extern uint32_t jaguarMainROMCRC32, jaguarROMSize, jaguarRunAddress; +extern char * jaguarEepromsPath; +extern bool jaguarCartInserted; +extern bool bpmActive; +extern uint32_t bpmAddress1; + +// Various clock rates + +#define M68K_CLOCK_RATE_PAL 13296950 +#define M68K_CLOCK_RATE_NTSC 13295453 +#define RISC_CLOCK_RATE_PAL 26593900 +#define RISC_CLOCK_RATE_NTSC 26590906 + +// Stuff for IRQ handling + +#define ASSERT_LINE 1 +#define CLEAR_LINE 0 + +//Temp debug stuff (will go away soon, so don't depend on these) + +void DumpMainMemory(void); +uint8_t * GetRamPtr(void); + +#endif // __JAGUAR_H__ diff --git a/waterbox/virtualjaguar/src/jerry.cpp b/waterbox/virtualjaguar/src/jerry.cpp new file mode 100644 index 0000000000..1e2478fbbd --- /dev/null +++ b/waterbox/virtualjaguar/src/jerry.cpp @@ -0,0 +1,791 @@ +// +// JERRY Core +// +// Originally by David Raingeard +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Carwin Jones (BeOS) +// Cleanups/rewrites/fixes by James Hammons +// +// JLH = James Hammons +// +// WHO WHEN WHAT +// --- ---------- ----------------------------------------------------------- +// JLH 11/25/2009 Major rewrite of memory subsystem and handlers +// + +// ------------------------------------------------------------ +// JERRY REGISTERS (Mapped by Aaron Giles) +// ------------------------------------------------------------ +// F10000-F13FFF R/W xxxxxxxx xxxxxxxx Jerry +// F10000 W xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler +// F10002 W xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider +// F10004 W xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler +// F10008 W xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider +// F10010 W ------xx xxxxxxxx CLK1 - processor clock divider +// F10012 W ------xx xxxxxxxx CLK2 - video clock divider +// F10014 W -------- --xxxxxx CLK3 - chroma clock divider +// F10020 R/W ---xxxxx ---xxxxx JINTCTRL - interrupt control register +// W ---x---- -------- (J_SYNCLR - clear synchronous serial intf ints) +// W ----x--- -------- (J_ASYNCLR - clear asynchronous serial intf ints) +// W -----x-- -------- (J_TIM2CLR - clear timer 2 [tempo] interrupts) +// W ------x- -------- (J_TIM1CLR - clear timer 1 [sample] interrupts) +// W -------x -------- (J_EXTCLR - clear external interrupts) +// R/W -------- ---x---- (J_SYNENA - enable synchronous serial intf ints) +// R/W -------- ----x--- (J_ASYNENA - enable asynchronous serial intf ints) +// R/W -------- -----x-- (J_TIM2ENA - enable timer 2 [tempo] interrupts) +// R/W -------- ------x- (J_TIM1ENA - enable timer 1 [sample] interrupts) +// R/W -------- -------x (J_EXTENA - enable external interrupts) +// F10030 R/W -------- xxxxxxxx ASIDATA - asynchronous serial data +// F10032 W -x------ -xxxxxxx ASICTRL - asynchronous serial control +// W -x------ -------- (TXBRK - transmit break) +// W -------- -x------ (CLRERR - clear error) +// W -------- --x----- (RINTEN - enable receiver interrupts) +// W -------- ---x---- (TINTEN - enable transmitter interrupts) +// W -------- ----x--- (RXIPOL - receiver input polarity) +// W -------- -----x-- (TXOPOL - transmitter output polarity) +// W -------- ------x- (PAREN - parity enable) +// W -------- -------x (ODD - odd parity select) +// F10032 R xxx-xxxx x-xxxxxx ASISTAT - asynchronous serial status +// R x------- -------- (ERROR - OR of PE,FE,OE) +// R -x------ -------- (TXBRK - transmit break) +// R --x----- -------- (SERIN - serial input) +// R ----x--- -------- (OE - overrun error) +// R -----x-- -------- (FE - framing error) +// R ------x- -------- (PE - parity error) +// R -------x -------- (TBE - transmit buffer empty) +// R -------- x------- (RBF - receive buffer full) +// R -------- ---x---- (TINTEN - enable transmitter interrupts) +// R -------- ----x--- (RXIPOL - receiver input polarity) +// R -------- -----x-- (TXOPOL - transmitter output polarity) +// R -------- ------x- (PAREN - parity enable) +// R -------- -------x (ODD - odd parity) +// F10034 R/W xxxxxxxx xxxxxxxx ASICLK - asynchronous serial interface clock +// F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler +// F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider +// F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler +// F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider +// ------------------------------------------------------------ +// F14000-F17FFF R/W xxxxxxxx xxxxxxxx Joysticks and GPIO0-5 +// F14000 R xxxxxxxx xxxxxxxx JOYSTICK - read joystick state +// F14000 W x------- xxxxxxxx JOYSTICK - latch joystick output +// W x------- -------- (enable joystick outputs) +// W -------- xxxxxxxx (joystick output data) +// F14002 R xxxxxxxx xxxxxxxx JOYBUTS - button register +// F14800-F14FFF R/W xxxxxxxx xxxxxxxx GPI00 - reserved (CD-ROM? no.) +// F15000-F15FFF R/W xxxxxxxx xxxxxxxx GPI01 - reserved +// F16000-F16FFF R/W xxxxxxxx xxxxxxxx GPI02 - reserved +// F17000-F177FF R/W xxxxxxxx xxxxxxxx GPI03 - reserved +// F17800-F17BFF R/W xxxxxxxx xxxxxxxx GPI04 - reserved +// F17C00-F17FFF R/W xxxxxxxx xxxxxxxx GPI05 - reserved +// ------------------------------------------------------------ +// F18000-F1FFFF R/W xxxxxxxx xxxxxxxx Jerry DSP +// F1A100 R/W xxxxxxxx xxxxxxxx D_FLAGS - DSP flags register +// R/W x------- -------- (DMAEN - DMA enable) +// R/W -x------ -------- (REGPAGE - register page) +// W --x----- -------- (D_EXT0CLR - clear external interrupt 0) +// W ---x---- -------- (D_TIM2CLR - clear timer 2 interrupt) +// W ----x--- -------- (D_TIM1CLR - clear timer 1 interrupt) +// W -----x-- -------- (D_I2SCLR - clear I2S interrupt) +// W ------x- -------- (D_CPUCLR - clear CPU interrupt) +// R/W -------x -------- (D_EXT0ENA - enable external interrupt 0) +// R/W -------- x------- (D_TIM2ENA - enable timer 2 interrupt) +// R/W -------- -x------ (D_TIM1ENA - enable timer 1 interrupt) +// R/W -------- --x----- (D_I2SENA - enable I2S interrupt) +// R/W -------- ---x---- (D_CPUENA - enable CPU interrupt) +// R/W -------- ----x--- (IMASK - interrupt mask) +// R/W -------- -----x-- (NEGA_FLAG - ALU negative) +// R/W -------- ------x- (CARRY_FLAG - ALU carry) +// R/W -------- -------x (ZERO_FLAG - ALU zero) +// F1A102 R/W -------- ------xx D_FLAGS - upper DSP flags +// R/W -------- ------x- (D_EXT1ENA - enable external interrupt 1) +// R/W -------- -------x (D_EXT1CLR - clear external interrupt 1) +// F1A104 W -------- ----xxxx D_MTXC - matrix control register +// W -------- ----x--- (MATCOL - column/row major) +// W -------- -----xxx (MATRIX3-15 - matrix width) +// F1A108 W ----xxxx xxxxxx-- D_MTXA - matrix address register +// F1A10C W -------- -----x-x D_END - data organization register +// W -------- -----x-- (BIG_INST - big endian instruction fetch) +// W -------- -------x (BIG_IO - big endian I/O) +// F1A110 R/W xxxxxxxx xxxxxxxx D_PC - DSP program counter +// F1A114 R/W xxxxxxxx xx-xxxxx D_CTRL - DSP control/status register +// R xxxx---- -------- (VERSION - DSP version code) +// R/W ----x--- -------- (BUS_HOG - hog the bus!) +// R/W -----x-- -------- (D_EXT0LAT - external interrupt 0 latch) +// R/W ------x- -------- (D_TIM2LAT - timer 2 interrupt latch) +// R/W -------x -------- (D_TIM1LAT - timer 1 interrupt latch) +// R/W -------- x------- (D_I2SLAT - I2S interrupt latch) +// R/W -------- -x------ (D_CPULAT - CPU interrupt latch) +// R/W -------- ---x---- (SINGLE_GO - single step one instruction) +// R/W -------- ----x--- (SINGLE_STEP - single step mode) +// R/W -------- -----x-- (FORCEINT0 - cause interrupt 0 on GPU) +// R/W -------- ------x- (CPUINT - send GPU interrupt to CPU) +// R/W -------- -------x (DSPGO - enable DSP execution) +// F1A116 R/W -------- -------x D_CTRL - upper DSP control/status register +// R/W -------- -------x (D_EXT1LAT - external interrupt 1 latch) +// F1A118-F1A11B W xxxxxxxx xxxxxxxx D_MOD - modulo instruction mask +// F1A11C-F1A11F R xxxxxxxx xxxxxxxx D_REMAIN - divide unit remainder +// F1A11C W -------- -------x D_DIVCTRL - divide unit control +// W -------- -------x (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide) +// F1A120-F1A123 R xxxxxxxx xxxxxxxx D_MACHI - multiply & accumulate high bits +// F1A148 W xxxxxxxx xxxxxxxx R_DAC - right transmit data +// F1A14C W xxxxxxxx xxxxxxxx L_DAC - left transmit data +// F1A150 W -------- xxxxxxxx SCLK - serial clock frequency +// F1A150 R -------- ------xx SSTAT +// R -------- ------x- (left - no description) +// R -------- -------x (WS - word strobe status) +// F1A154 W -------- --xxxx-x SMODE - serial mode +// W -------- --x----- (EVERYWORD - interrupt on MSB of every word) +// W -------- ---x---- (FALLING - interrupt on falling edge) +// W -------- ----x--- (RISING - interrupt of rising edge) +// W -------- -----x-- (WSEN - enable word strobes) +// W -------- -------x (INTERNAL - enables serial clock) +// ------------------------------------------------------------ +// F1B000-F1CFFF R/W xxxxxxxx xxxxxxxx Local DSP RAM +// ------------------------------------------------------------ +// F1D000 R xxxxxxxx xxxxxxxx ROM_TRI - triangle wave +// F1D200 R xxxxxxxx xxxxxxxx ROM_SINE - full sine wave +// F1D400 R xxxxxxxx xxxxxxxx ROM_AMSINE - amplitude modulated sine wave +// F1D600 R xxxxxxxx xxxxxxxx ROM_12W - sine wave and second order harmonic +// F1D800 R xxxxxxxx xxxxxxxx ROM_CHIRP16 - chirp +// F1DA00 R xxxxxxxx xxxxxxxx ROM_NTRI - traingle wave with noise +// F1DC00 R xxxxxxxx xxxxxxxx ROM_DELTA - spike +// F1DE00 R xxxxxxxx xxxxxxxx ROM_NOISE - white noise +// ------------------------------------------------------------ + +#include "jerry.h" + +#include // For memcpy +//#include +#include "cdrom.h" +#include "dac.h" +#include "dsp.h" +#include "eeprom.h" +#include "event.h" +#include "jaguar.h" +#include "joystick.h" +#include "log.h" +#include "m68000/m68kinterface.h" +#include "memtrack.h" +#include "settings.h" +#include "tom.h" +//#include "memory.h" +#include "wavetable.h" + +//Note that 44100 Hz requires samples every 22.675737 usec. +//#define JERRY_DEBUG + +/*static*/ uint8_t jerry_ram_8[0x10000]; + +//#define JERRY_CONFIG 0x4002 // ??? What's this ??? + +// JERRY Registers (write, offset from $F10000) +#define JPIT1 0x00 +#define JPIT2 0x02 +#define JPIT3 0x04 +#define JPIT4 0x08 +#define CLK1 0x10 +#define CLK2 0x12 +#define CLK3 0x14 +#define JINTCTRL 0x20 +#define ASIDATA 0x30 +#define ASICTRL 0x32 +#define ASICLK 0x34 +#define SCLK 0xA150 +#define SMODE 0xA154 + + +uint8_t analog_x, analog_y; + +static uint32_t JERRYPIT1Prescaler; +static uint32_t JERRYPIT1Divider; +static uint32_t JERRYPIT2Prescaler; +static uint32_t JERRYPIT2Divider; +static int32_t jerry_timer_1_counter; +static int32_t jerry_timer_2_counter; + +//uint32_t JERRYI2SInterruptDivide = 8; +int32_t JERRYI2SInterruptTimer = -1; +uint32_t jerryI2SCycles; +uint32_t jerryIntPending; + +static uint16_t jerryInterruptMask = 0; +static uint16_t jerryPendingInterrupt = 0; + +// Private function prototypes + +void JERRYResetPIT1(void); +void JERRYResetPIT2(void); +void JERRYResetI2S(void); + +void JERRYPIT1Callback(void); +void JERRYPIT2Callback(void); +void JERRYI2SCallback(void); + + +void JERRYResetI2S(void) +{ + //WriteLog("i2s: reseting\n"); +//This is really SCLK... !!! FIX !!! + sclk = 8; + JERRYI2SInterruptTimer = -1; +} + + +void JERRYResetPIT1(void) +{ + RemoveCallback(JERRYPIT1Callback); + + if (JERRYPIT1Prescaler | JERRYPIT1Divider) + { + double usecs = (float)(JERRYPIT1Prescaler + 1) * (float)(JERRYPIT1Divider + 1) * RISC_CYCLE_IN_USEC; + SetCallbackTime(JERRYPIT1Callback, usecs, EVENT_JERRY); + } +} + + +void JERRYResetPIT2(void) +{ + RemoveCallback(JERRYPIT2Callback); + + if (JERRYPIT1Prescaler | JERRYPIT1Divider) + { + double usecs = (float)(JERRYPIT2Prescaler + 1) * (float)(JERRYPIT2Divider + 1) * RISC_CYCLE_IN_USEC; + SetCallbackTime(JERRYPIT2Callback, usecs, EVENT_JERRY); + } +} + + +// This is the cause of the regressions in Cybermorph and Missile Command 3D... +// Solution: Probably have to check the DSP enable bit before sending these thru. +//#define JERRY_NO_IRQS +void JERRYPIT1Callback(void) +{ +#ifndef JERRY_NO_IRQS +//WriteLog("JERRY: In PIT1 callback, IRQM=$%04X\n", jerryInterruptMask); + if (TOMIRQEnabled(IRQ_DSP)) + { + if (jerryInterruptMask & IRQ2_TIMER1) // CPU Timer 1 IRQ + { +// Not sure, but I think we don't generate another IRQ if one's already going... +// But this seems to work... :-/ + jerryPendingInterrupt |= IRQ2_TIMER1; + m68k_set_irq(2); // Generate 68K IPL 2 + } + } +#endif + + DSPSetIRQLine(DSPIRQ_TIMER0, ASSERT_LINE); // This does the 'IRQ enabled' checking... + JERRYResetPIT1(); +} + + +void JERRYPIT2Callback(void) +{ +#ifndef JERRY_NO_IRQS + if (TOMIRQEnabled(IRQ_DSP)) + { +//WriteLog("JERRY: In PIT2 callback, IRQM=$%04X\n", jerryInterruptMask); + if (jerryInterruptMask & IRQ2_TIMER2) // CPU Timer 2 IRQ + { + jerryPendingInterrupt |= IRQ2_TIMER2; + m68k_set_irq(2); // Generate 68K IPL 2 + } + } +#endif + + DSPSetIRQLine(DSPIRQ_TIMER1, ASSERT_LINE); // This does the 'IRQ enabled' checking... + JERRYResetPIT2(); +} + + +void JERRYI2SCallback(void) +{ + // We don't have to divide the RISC clock rate by this--the reason is a bit + // convoluted. Will put explanation here later... +// What's needed here is to find the ratio of the frequency to the number of clock cycles +// in one second. For example, if the sample rate is 44100, we divide the clock rate by +// this: 26590906 / 44100 = 602 cycles. +// Which means, every 602 cycles that go by we have to generate an interrupt. + jerryI2SCycles = 32 * (2 * (sclk + 1)); +//This makes audio faster, but not enough and the pitch is wrong besides +// jerryI2SCycles = 32 * (2 * (sclk - 1)); + + // If INTERNAL flag is set, then JERRY's SCLK is master + if (smode & SMODE_INTERNAL) + { + // This does the 'IRQ enabled' checking... + DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE); +// double usecs = (float)jerryI2SCycles * RISC_CYCLE_IN_USEC; +//this fix is almost enough to fix timings in tripper, but not quite enough... + double usecs = (float)jerryI2SCycles * (vjs.hardwareTypeNTSC ? RISC_CYCLE_IN_USEC : RISC_CYCLE_PAL_IN_USEC); + SetCallbackTime(JERRYI2SCallback, usecs, EVENT_JERRY); + } + else + { + // JERRY is slave to external word clock + +//Note that 44100 Hz requires samples every 22.675737 usec. +//When JERRY is slave to the word clock, we need to do interrupts either at 44.1K +//sample rate or at a 88.2K sample rate (11.332... usec). +/* // This is just a temporary kludge to see if the CD bus mastering works + // I.e., this is totally faked...! +// The whole interrupt system is pretty much borked and is need of an overhaul. +// What we need is a way of handling these interrupts when they happen instead of +// scanline boundaries the way it is now. + jerry_i2s_interrupt_timer -= cycles; + if (jerry_i2s_interrupt_timer <= 0) + { +//This is probably wrong as well (i.e., need to check enable lines)... !!! FIX !!! [DONE] + if (ButchIsReadyToSend())//Not sure this is right spot to check... + { +// return GetWordFromButchSSI(offset, who); + SetSSIWordsXmittedFromButch(); + DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE); + } + jerry_i2s_interrupt_timer += 602; + }*/ + + if (ButchIsReadyToSend())//Not sure this is right spot to check... + { +// return GetWordFromButchSSI(offset, who); + SetSSIWordsXmittedFromButch(); + DSPSetIRQLine(DSPIRQ_SSI, ASSERT_LINE); + } + + SetCallbackTime(JERRYI2SCallback, 22.675737, EVENT_JERRY); + } +} + + +void JERRYInit(void) +{ + JoystickInit(); + MTInit(); + memcpy(&jerry_ram_8[0xD000], waveTableROM, 0x1000); + + JERRYPIT1Prescaler = 0xFFFF; + JERRYPIT2Prescaler = 0xFFFF; + JERRYPIT1Divider = 0xFFFF; + JERRYPIT2Divider = 0xFFFF; + jerryInterruptMask = 0x0000; + jerryPendingInterrupt = 0x0000; + + DACInit(); +} + + +void JERRYReset(void) +{ + JoystickReset(); + EepromReset(); + MTReset(); + JERRYResetI2S(); + + memset(jerry_ram_8, 0x00, 0xD000); // Don't clear out the Wavetable ROM...! + JERRYPIT1Prescaler = 0xFFFF; + JERRYPIT2Prescaler = 0xFFFF; + JERRYPIT1Divider = 0xFFFF; + JERRYPIT2Divider = 0xFFFF; + jerry_timer_1_counter = 0; + jerry_timer_2_counter = 0; + jerryInterruptMask = 0x0000; + jerryPendingInterrupt = 0x0000; + + DACReset(); +} + + +void JERRYDone(void) +{ + JERRYDumpIORegistersToLog(); + WriteLog("JERRY: M68K Interrupt control ($F10020) = %04X\n", GET16(jerry_ram_8, 0x20)); + JoystickDone(); + DACDone(); + EepromDone(); + MTDone(); +} + + +bool JERRYIRQEnabled(int irq) +{ + // Read the word @ $F10020 +// return jerry_ram_8[0x21] & (1 << irq); + return jerryInterruptMask & irq; +} + + +void JERRYSetPendingIRQ(int irq) +{ + // This is the shadow of INT (it's a split RO/WO register) +// jerryIntPending |= (1 << irq); + jerryPendingInterrupt |= irq; +} + +// +// Dump all JERRY register values to the log +// +void JERRYDumpIORegistersToLog(void) +{ + WriteLog("\n\n---------------------------------------------------------------------\n"); + WriteLog("JERRY I/O Registers\n"); + WriteLog("---------------------------------------------------------------------\n"); + WriteLog("F1%04X (JPIT1): $%04X\n", JPIT1, GET16(jerry_ram_8, JPIT1)); + WriteLog("F1%04X (JPIT2): $%04X\n", JPIT2, GET16(jerry_ram_8, JPIT2)); + WriteLog("F1%04X (JPIT3): $%04X\n", JPIT3, GET16(jerry_ram_8, JPIT3)); + WriteLog("F1%04X (JPIT4): $%04X\n", JPIT4, GET16(jerry_ram_8, JPIT4)); + WriteLog("F1%04X (CLK1): $%04X\n", CLK1, GET16(jerry_ram_8, CLK1)); + WriteLog("F1%04X (CLK2): $%04X\n", CLK2, GET16(jerry_ram_8, CLK2)); + WriteLog("F1%04X (CLK3): $%04X\n", CLK3, GET16(jerry_ram_8, CLK3)); + WriteLog("F1%04X (JINTCTRL): $%04X\n", JINTCTRL, GET16(jerry_ram_8, JINTCTRL)); + WriteLog("F1%04X (ASIDATA): $%04X\n", ASIDATA, GET16(jerry_ram_8, ASIDATA)); + WriteLog("F1%04X (ASICTRL): $%04X\n", ASICTRL, GET16(jerry_ram_8, ASICTRL)); + WriteLog("F1%04X (ASICLK): $%04X\n", ASICLK, GET16(jerry_ram_8, ASICLK)); + WriteLog("F1%04X (SCLK): $%04X\n", SCLK, GET16(jerry_ram_8, SCLK)); + WriteLog("F1%04X (SMODE): $%04X\n", SMODE, GET16(jerry_ram_8, SMODE)); + WriteLog("---------------------------------------------------------------------\n\n\n"); +} + + +// +// JERRY byte access (read) +// +uint8_t JERRYReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ +#ifdef JERRY_DEBUG + WriteLog("JERRY: Reading byte at %06X\n", offset); +#endif + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20)) + return DSPReadByte(offset, who); + else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE+0x2000)) + return DSPReadByte(offset, who); + // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...) + else if (offset >= 0xF1A148 && offset <= 0xF1A153) + return DACReadByte(offset, who); +// F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler +// F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider +// F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler +// F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider +//This is WRONG! +// else if (offset >= 0xF10000 && offset <= 0xF10007) +//This is still wrong. What needs to be returned here are the values being counted down +//in the jerry_timer_n_counter variables... !!! FIX !!! [DONE] + +//This is probably the problem with the new timer code... This is invalid +//under the new system... !!! FIX !!! + else if ((offset >= 0xF10036) && (offset <= 0xF1003D)) + { +WriteLog("JERRY: Unhandled timer read (BYTE) at %08X...\n", offset); + } +// else if (offset >= 0xF10010 && offset <= 0xF10015) +// return clock_byte_read(offset); +// else if (offset >= 0xF17C00 && offset <= 0xF17C01) +// return anajoy_byte_read(offset); + else if (offset >= 0xF14000 && offset <= 0xF14003) +// return JoystickReadByte(offset) | EepromReadByte(offset); + { + uint16_t value = JoystickReadWord(offset & 0xFE); + + if (offset & 0x01) + value &= 0xFF; + else + value >>= 8; + + // This is wrong, should only have the lowest bit from $F14001 + return value | EepromReadByte(offset); + } + else if (offset >= 0xF14000 && offset <= 0xF1A0FF) + return EepromReadByte(offset); + + return jerry_ram_8[offset & 0xFFFF]; +} + + +// +// JERRY word access (read) +// +uint16_t JERRYReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ +#ifdef JERRY_DEBUG + WriteLog("JERRY: Reading word at %06X\n", offset); +#endif + + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE+0x20)) + return DSPReadWord(offset, who); + else if (offset >= DSP_WORK_RAM_BASE && offset <= DSP_WORK_RAM_BASE + 0x1FFF) + return DSPReadWord(offset, who); + // LRXD/RRXD/SSTAT $F1A148/4C/50 (really 16-bit registers...) + else if (offset >= 0xF1A148 && offset <= 0xF1A153) + return DACReadWord(offset, who); +// F10036 R xxxxxxxx xxxxxxxx JPIT1 - timer 1 pre-scaler +// F10038 R xxxxxxxx xxxxxxxx JPIT2 - timer 1 divider +// F1003A R xxxxxxxx xxxxxxxx JPIT3 - timer 2 pre-scaler +// F1003C R xxxxxxxx xxxxxxxx JPIT4 - timer 2 divider +//This is WRONG! +// else if ((offset >= 0xF10000) && (offset <= 0xF10007)) +//This is still wrong. What needs to be returned here are the values being counted down +//in the jerry_timer_n_counter variables... !!! FIX !!! [DONE] + else if ((offset >= 0xF10036) && (offset <= 0xF1003D)) + { +WriteLog("JERRY: Unhandled timer read (WORD) at %08X...\n", offset); + } +// else if ((offset >= 0xF10010) && (offset <= 0xF10015)) +// return clock_word_read(offset); + else if (offset == 0xF10020) +// return jerryIntPending; + return jerryPendingInterrupt; +// else if ((offset >= 0xF17C00) && (offset <= 0xF17C01)) +// return anajoy_word_read(offset); + else if (offset == 0xF14000) + return (JoystickReadWord(offset) & 0xFFFE) | EepromReadWord(offset); + else if ((offset >= 0xF14002) && (offset < 0xF14003)) + return JoystickReadWord(offset); + else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF)) + return EepromReadWord(offset); + +/*if (offset >= 0xF1D000) + WriteLog("JERRY: Reading word at %08X [%04X]...\n", offset, ((uint16_t)jerry_ram_8[(offset+0)&0xFFFF] << 8) | jerry_ram_8[(offset+1)&0xFFFF]);//*/ + + offset &= 0xFFFF; // Prevent crashing...! + return ((uint16_t)jerry_ram_8[offset+0] << 8) | jerry_ram_8[offset+1]; +} + + +// +// JERRY byte access (write) +// +void JERRYWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + // Moved here tentatively, so we can see everything written to JERRY. + jerry_ram_8[offset & 0xFFFF] = data; + +#ifdef JERRY_DEBUG + WriteLog("jerry: writing byte %.2x at 0x%.6x\n",data,offset); +#endif + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE + 0x20)) + { + DSPWriteByte(offset, data, who); + return; + } + else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE + 0x2000)) + { + DSPWriteByte(offset, data, who); + return; + } + // SCLK ($F1A150--8 bits wide) +//NOTE: This should be taken care of in DAC... +#if 0 + else if ((offset >= 0xF1A152) && (offset <= 0xF1A153)) + { +#if 0 +// WriteLog("JERRY: Writing %02X to SCLK...\n", data); + if ((offset & 0x03) == 2) + sclk = (sclk & 0x00FF) | ((uint32_t)data << 8); + else + sclk = (sclk & 0xFF00) | (uint32_t)data; +#else + sclk = data; +#endif +#warning "!!! SCLK should be handled in dac.cpp !!!" + JERRYI2SInterruptTimer = -1; + RemoveCallback(JERRYI2SCallback); + JERRYI2SCallback(); +// return; + } +#endif + // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...) + else if (offset >= 0xF1A148 && offset <= 0xF1A157) + { + DACWriteByte(offset, data, who); + return; + } + else if (offset >= 0xF10000 && offset <= 0xF10007) + { +WriteLog("JERRY: Unhandled timer write (BYTE) at %08X...\n", offset); + return; + } +/* else if ((offset >= 0xF10010) && (offset <= 0xF10015)) + { + clock_byte_write(offset, data); + return; + }//*/ + // JERRY -> 68K interrupt enables/latches (need to be handled!) + else if (offset >= 0xF10020 && offset <= 0xF10021)//WAS:23) + { + if (offset == 0xF10020) + { + // Clear pending interrupts... + jerryPendingInterrupt &= ~data; + } + else if (offset == 0xF10021) + jerryInterruptMask = data; +//WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%02X to $%08X!\n", data, offset); +//WriteLog("JERRY: (Previous is partially handled... IRQMask=$%04X)\n", jerryInterruptMask); + } +/* else if ((offset >= 0xF17C00) && (offset <= 0xF17C01)) + { + anajoy_byte_write(offset, data); + return; + }*/ + else if ((offset >= 0xF14000) && (offset <= 0xF14003)) + { +WriteLog("JERRYWriteByte: Unhandled byte write to JOYSTICK by %s.\n", whoName[who]); +// JoystickWriteByte(offset, data); + JoystickWriteWord(offset & 0xFE, (uint16_t)data); +// This is wrong, EEPROM is never written here + EepromWriteByte(offset, data); + return; + } + else if ((offset >= 0xF14000) && (offset <= 0xF1A0FF)) + { + EepromWriteByte(offset, data); + return; + } + +//Need to protect write attempts to Wavetable ROM (F1D000-FFF) + if (offset >= 0xF1D000 && offset <= 0xF1DFFF) + return; + +// jerry_ram_8[offset & 0xFFFF] = data; +} + + +// +// JERRY word access (write) +// +void JERRYWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + // Moved here tentatively, so we can see everything written to JERRY. + jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF; + jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF; + +#ifdef JERRY_DEBUG + WriteLog( "JERRY: Writing word %04X at %06X\n", data, offset); +#endif +#if 1 +if (offset == 0xF10000) + WriteLog("JERRY: JPIT1 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10002) + WriteLog("JERRY: JPIT2 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10004) + WriteLog("JERRY: JPIT3 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10006) + WriteLog("JERRY: JPIT4 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10010) + WriteLog("JERRY: CLK1 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10012) + WriteLog("JERRY: CLK2 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10014) + WriteLog("JERRY: CLK3 word written by %s: %u\n", whoName[who], data); +//else if (offset == 0xF1A100) +// WriteLog("JERRY: D_FLAGS word written by %s: %u\n", whoName[who], data); +//else if (offset == 0xF1A102) +// WriteLog("JERRY: D_FLAGS+2 word written by %s: %u\n", whoName[who], data); +else if (offset == 0xF10020) + WriteLog("JERRY: JINTCTRL word written by %s: $%04X (%s%s%s%s%s%s)\n", whoName[who], data, + (data & 0x01 ? "Extrnl " : ""), (data & 0x02 ? "DSP " : ""), + (data & 0x04 ? "Timer0 " : ""), (data & 0x08 ? "Timer1 " : ""), + (data & 0x10 ? "ASI " : ""), (data & 0x20 ? "I2S " : "")); +#endif + + if ((offset >= DSP_CONTROL_RAM_BASE) && (offset < DSP_CONTROL_RAM_BASE + 0x20)) + { + DSPWriteWord(offset, data, who); + return; + } + else if ((offset >= DSP_WORK_RAM_BASE) && (offset < DSP_WORK_RAM_BASE + 0x2000)) + { + DSPWriteWord(offset, data, who); + return; + } +//NOTE: This should be taken care of in DAC... +#if 0 + else if (offset == 0xF1A152) // Bottom half of SCLK ($F1A150) + { +#warning "!!! SCLK should be handled in dac.cpp !!!" + WriteLog("JERRY: Writing $%X to SCLK (by %s)...\n", data, whoName[who]); +//This should *only* be enabled when SMODE has its INTERNAL bit set! !!! FIX !!! +#if 0 + sclk = (uint8_t)data; +#else + sclk = data & 0xFF; +#endif + JERRYI2SInterruptTimer = -1; + RemoveCallback(JERRYI2SCallback); + JERRYI2SCallback(); + + DACWriteWord(offset, data, who); + return; + } +#endif + // LTXD/RTXD/SCLK/SMODE $F1A148/4C/50/54 (really 16-bit registers...) + else if (offset >= 0xF1A148 && offset <= 0xF1A156) + { + DACWriteWord(offset, data, who); + return; + } + else if (offset >= 0xF10000 && offset <= 0xF10007) + { + switch(offset & 0x07) + { + case 0: + JERRYPIT1Prescaler = data; + JERRYResetPIT1(); + break; + case 2: + JERRYPIT1Divider = data; + JERRYResetPIT1(); + break; + case 4: + JERRYPIT2Prescaler = data; + JERRYResetPIT2(); + break; + case 6: + JERRYPIT2Divider = data; + JERRYResetPIT2(); + } + // Need to handle (unaligned) cases??? + + return; + } + // JERRY -> 68K interrupt enables/latches (need to be handled!) + else if (offset >= 0xF10020 && offset <= 0xF10022) + { + jerryInterruptMask = data & 0xFF; + jerryPendingInterrupt &= ~(data >> 8); +//WriteLog("JERRY: (68K int en/lat - Unhandled!) Tried to write $%04X to $%08X!\n", data, offset); +//WriteLog("JERRY: (Previous is partially handled... IRQMask=$%04X)\n", jerryInterruptMask); + return; + } + else if (offset >= 0xF14000 && offset < 0xF14003) + { + JoystickWriteWord(offset, data); + EepromWriteWord(offset, data); + return; + } + else if (offset >= 0xF14000 && offset <= 0xF1A0FF) + { + EepromWriteWord(offset, data); + return; + } + +//Need to protect write attempts to Wavetable ROM (F1D000-FFF) + if (offset >= 0xF1D000 && offset <= 0xF1DFFF) + return; + +// jerry_ram_8[(offset+0) & 0xFFFF] = (data >> 8) & 0xFF; +// jerry_ram_8[(offset+1) & 0xFFFF] = data & 0xFF; +} + + +int JERRYGetPIT1Frequency(void) +{ + int systemClockFrequency = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL); + return systemClockFrequency / ((JERRYPIT1Prescaler + 1) * (JERRYPIT1Divider + 1)); +} + + +int JERRYGetPIT2Frequency(void) +{ + int systemClockFrequency = (vjs.hardwareTypeNTSC ? RISC_CLOCK_RATE_NTSC : RISC_CLOCK_RATE_PAL); + return systemClockFrequency / ((JERRYPIT2Prescaler + 1) * (JERRYPIT2Divider + 1)); +} + diff --git a/waterbox/virtualjaguar/src/jerry.h b/waterbox/virtualjaguar/src/jerry.h new file mode 100644 index 0000000000..868c5a0efc --- /dev/null +++ b/waterbox/virtualjaguar/src/jerry.h @@ -0,0 +1,44 @@ +// +// JERRY.H: Header file +// + +#ifndef __JERRY_H__ +#define __JERRY_H__ + +//#include "types.h" +#include "memory.h" + +void JERRYInit(void); +void JERRYReset(void); +void JERRYDone(void); +void JERRYDumpIORegistersToLog(void); + +uint8_t JERRYReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t JERRYReadWord(uint32_t offset, uint32_t who = UNKNOWN); +void JERRYWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void JERRYWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); + +void JERRYExecPIT(uint32_t cycles); +void JERRYI2SExec(uint32_t cycles); + +int JERRYGetPIT1Frequency(void); +int JERRYGetPIT2Frequency(void); + +// 68000 Interrupt bit positions (enabled at $F10020) + +//enum { IRQ2_EXTERNAL = 0, IRQ2_DSP, IRQ2_TIMER1, IRQ2_TIMER2, IRQ2_ASI, IRQ2_SSI }; +enum { IRQ2_EXTERNAL=0x01, IRQ2_DSP=0x02, IRQ2_TIMER1=0x04, IRQ2_TIMER2=0x08, IRQ2_ASI=0x10, IRQ2_SSI=0x20 }; + +bool JERRYIRQEnabled(int irq); +void JERRYSetPendingIRQ(int irq); + +// This should stay inside this file, but it's here for now... +// Need to set up an interface function so that this can go back +void JERRYI2SCallback(void); + +// External variables + +//extern uint32_t JERRYI2SInterruptDivide; +extern int32_t JERRYI2SInterruptTimer; + +#endif diff --git a/waterbox/virtualjaguar/src/joystick.cpp b/waterbox/virtualjaguar/src/joystick.cpp new file mode 100644 index 0000000000..69d75771cd --- /dev/null +++ b/waterbox/virtualjaguar/src/joystick.cpp @@ -0,0 +1,189 @@ +// +// Joystick handler +// +// by cal2 +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Extensive rewrite by James Hammons +// (C) 2013 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +#include "joystick.h" +#include // For memset() +#include "gpu.h" +#include "jaguar.h" +#include "log.h" +#include "settings.h" + +// Global vars + +static uint8_t joystick_ram[4]; +uint8_t joypad0Buttons[21]; +uint8_t joypad1Buttons[21]; +bool audioEnabled = false; +bool joysticksEnabled = false; + + +bool GUIKeyHeld = false; +extern int start_logging; +int gpu_start_log = 0; +int op_start_log = 0; +int blit_start_log = 0; +int effect_start = 0; +int effect_start2 = 0, effect_start3 = 0, effect_start4 = 0, effect_start5 = 0, effect_start6 = 0; +bool interactiveMode = false; +bool iLeft, iRight, iToggle = false; +bool keyHeld1 = false, keyHeld2 = false, keyHeld3 = false; +int objectPtr = 0; +bool startMemLog = false; +extern bool doDSPDis, doGPUDis; + +bool blitterSingleStep = false; +bool bssGo = false; +bool bssHeld = false; + +extern bool lagged; +extern void (*inputcb)(); + + +void JoystickInit(void) +{ + JoystickReset(); +} + + +void JoystickExec(void) +{ + gpu_start_log = 0; // Only log while key down! + effect_start = 0; + effect_start2 = effect_start3 = effect_start4 = effect_start5 = effect_start6 = 0; + blit_start_log = 0; + iLeft = iRight = false; +} + + +void JoystickReset(void) +{ + memset(joystick_ram, 0x00, 4); + memset(joypad0Buttons, 0, 21); + memset(joypad1Buttons, 0, 21); +} + + +void JoystickDone(void) +{ +} + + +uint16_t JoystickReadWord(uint32_t offset) +{ + lagged = false; + if (__builtin_expect(!!inputcb, false)) + inputcb(); + + // E, D, B, 7 + uint8_t joypad0Offset[16] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0C, 0xFF, 0xFF, 0xFF, 0x08, 0xFF, 0x04, 0x00, 0xFF + }; + uint8_t joypad1Offset[16] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x04, 0xFF, 0x08, 0x0C, 0xFF + }; + +#warning "No bounds checking done in JoystickReadByte!" + offset &= 0x03; + + if (offset == 0) + { + if (!joysticksEnabled) + return 0xFFFF; + + // Joystick data returns active low for buttons pressed, high for non- + // pressed. + uint16_t data = 0xFFFF; + uint8_t offset0 = joypad0Offset[joystick_ram[1] & 0x0F]; + uint8_t offset1 = joypad1Offset[(joystick_ram[1] >> 4) & 0x0F]; + + if (offset0 != 0xFF) + { + uint16_t mask[4] = { 0xFEFF, 0xFDFF, 0xFBFF, 0xF7FF }; + uint16_t msk2[4] = { 0xFFFF, 0xFFFD, 0xFFFB, 0xFFF7 }; + + for(uint8_t i=0; i<4; i++) + data &= (joypad0Buttons[offset0 + i] ? mask[i] : 0xFFFF); + + data &= msk2[offset0 / 4]; + } + + if (offset1 != 0xFF) + { + uint16_t mask[4] = { 0xEFFF, 0xDFFF, 0xBFFF, 0x7FFF }; + uint16_t msk2[4] = { 0xFF7F, 0xFFBF, 0xFFDF, 0xFFEF }; + + for(uint8_t i=0; i<4; i++) + data &= (joypad1Buttons[offset1 + i] ? mask[i] : 0xFFFF); + + data &= msk2[offset1 / 4]; + } + + return data; + } + else if (offset == 2) + { + // Hardware ID returns NTSC/PAL identification bit here + // N.B.: On real H/W, bit 7 is *always* zero...! + uint16_t data = 0xFF6F | (vjs.hardwareTypeNTSC ? 0x10 : 0x00); + + if (!joysticksEnabled) + return data; + + // Joystick data returns active low for buttons pressed, high for non- + // pressed. + uint8_t offset0 = joypad0Offset[joystick_ram[1] & 0x0F]; + uint8_t offset1 = joypad1Offset[(joystick_ram[1] >> 4) & 0x0F]; + + if (offset0 != 0xFF) + { + offset0 /= 4; // Make index 0, 1, 2, 3 instead of 0, 4, 8, 12 + uint8_t mask[4][2] = { { BUTTON_A, BUTTON_PAUSE }, { BUTTON_B, 0xFF }, { BUTTON_C, 0xFF }, { BUTTON_OPTION, 0xFF } }; + data &= (joypad0Buttons[mask[offset0][0]] ? 0xFFFD : 0xFFFF); + + if (mask[offset0][1] != 0xFF) + data &= (joypad0Buttons[mask[offset0][1]] ? 0xFFFE : 0xFFFF); + } + + if (offset1 != 0xFF) + { + offset1 /= 4; // Make index 0, 1, 2, 3 instead of 0, 4, 8, 12 + uint8_t mask[4][2] = { { BUTTON_A, BUTTON_PAUSE }, { BUTTON_B, 0xFF }, { BUTTON_C, 0xFF }, { BUTTON_OPTION, 0xFF } }; + data &= (joypad1Buttons[mask[offset1][0]] ? 0xFFF7 : 0xFFFF); + + if (mask[offset1][1] != 0xFF) + data &= (joypad1Buttons[mask[offset1][1]] ? 0xFFFB : 0xFFFF); + } + + return data; + } + + return 0xFFFF; +} + + +void JoystickWriteWord(uint32_t offset, uint16_t data) +{ +#warning "No bounds checking done for JoystickWriteWord!" + offset &= 0x03; + joystick_ram[offset + 0] = (data >> 8) & 0xFF; + joystick_ram[offset + 1] = data & 0xFF; + + if (offset == 0) + { + audioEnabled = (data & 0x0100 ? true : false); + joysticksEnabled = (data & 0x8000 ? true : false); + } +} + diff --git a/waterbox/virtualjaguar/src/joystick.h b/waterbox/virtualjaguar/src/joystick.h new file mode 100644 index 0000000000..09e2378ce5 --- /dev/null +++ b/waterbox/virtualjaguar/src/joystick.h @@ -0,0 +1,49 @@ +// +// Jaguar joystick handler +// + +#ifndef __JOYSTICK_H__ +#define __JOYSTICK_H__ + +#include + +enum { BUTTON_FIRST = 0, BUTTON_U = 0, +BUTTON_D = 1, +BUTTON_L = 2, +BUTTON_R = 3, + +BUTTON_s = 4, +BUTTON_7 = 5, +BUTTON_4 = 6, +BUTTON_1 = 7, +BUTTON_0 = 8, +BUTTON_8 = 9, +BUTTON_5 = 10, +BUTTON_2 = 11, +BUTTON_d = 12, +BUTTON_9 = 13, +BUTTON_6 = 14, +BUTTON_3 = 15, + +BUTTON_A = 16, +BUTTON_B = 17, +BUTTON_C = 18, +BUTTON_OPTION = 19, +BUTTON_PAUSE = 20, BUTTON_LAST = 20 }; + +void JoystickInit(void); +void JoystickReset(void); +void JoystickDone(void); +//void JoystickWriteByte(uint32_t, uint8_t); +void JoystickWriteWord(uint32_t, uint16_t); +//uint8_t JoystickReadByte(uint32_t); +uint16_t JoystickReadWord(uint32_t); +void JoystickExec(void); + +extern uint8_t joypad0Buttons[]; +extern uint8_t joypad1Buttons[]; +extern bool audioEnabled; +extern bool joysticksEnabled; + +#endif // __JOYSTICK_H__ + diff --git a/waterbox/virtualjaguar/src/log.cpp b/waterbox/virtualjaguar/src/log.cpp new file mode 100644 index 0000000000..23fc806fa3 --- /dev/null +++ b/waterbox/virtualjaguar/src/log.cpp @@ -0,0 +1,80 @@ +// +// Log handler +// +// Originally by David Raingeard (Cal2) +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Cleanups/new stuff by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 07/11/2011 Instead of dumping out on max log file size being reached, we +// now just silently ignore any more output. 10 megs ought to be +// enough for anybody. ;-) Except when it isn't. :-P +// + +#include "log.h" + +#include +#include +#include + + +//#define MAX_LOG_SIZE 10000000 // Maximum size of log file (10 MB) +#define MAX_LOG_SIZE 100000000 // Maximum size of log file (100 MB) + +static FILE * log_stream = NULL; +static uint32_t logSize = 0; + +int LogInit(const char * path) +{ + log_stream = fopen(path, "w"); + + if (log_stream == NULL) + return 0; + + return 1; +} + +FILE * LogGet(void) +{ + return log_stream; +} + +void LogDone(void) +{ + if (log_stream != NULL) + fclose(log_stream); +} + +// +// This logger is used mainly to ensure that text gets written to the log file +// even if the program crashes. The performance hit is acceptable in this case! +// +void WriteLog(const char * text, ...) +{ + va_list arg; + va_start(arg, text); + + if (log_stream == NULL) + { + va_end(arg); + return; + } + + logSize += vfprintf(log_stream, text, arg); + + if (logSize > MAX_LOG_SIZE) + { + // Instead of dumping out, we just close the file and ignore any more output. + fflush(log_stream); + fclose(log_stream); + log_stream = NULL; + } + + va_end(arg); + fflush(log_stream); // Make sure that text is written! +} diff --git a/waterbox/virtualjaguar/src/log.h b/waterbox/virtualjaguar/src/log.h new file mode 100644 index 0000000000..c406bf8154 --- /dev/null +++ b/waterbox/virtualjaguar/src/log.h @@ -0,0 +1,27 @@ +// +// log.h: Logfile support +// + +#ifndef __LOG_H__ +#define __LOG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int LogInit(const char *); +FILE * LogGet(void); +void LogDone(void); +void WriteLog(const char * text, ...); + +#ifdef __cplusplus +} +#endif + +// Some useful defines... :-) +//#define GPU_DEBUG +//#define LOG_BLITS + +#endif // __LOG_H__ diff --git a/waterbox/virtualjaguar/src/m68000/cpudefs.c b/waterbox/virtualjaguar/src/m68000/cpudefs.c new file mode 100644 index 0000000000..33e0fb06d8 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpudefs.c @@ -0,0 +1,183 @@ +#include "sysdeps.h" +#include "readcpu.h" +const struct instr_def defs68k[] = { +{ 60, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "ORSR.B #1"}, +{ 124, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "ORSR.W #1"}, +{ 192, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 63936, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd]"}, +{ 0, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "OR.z #z,d[!Areg]"}, +{ 572, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "ANDSR.B #1"}, +{ 636, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "ANDSR.W #1"}, +{ 512, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "AND.z #z,d[!Areg]"}, +{ 1024, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUB.z #z,d[!Areg]"}, +{ 1536, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADD.z #z,d[!Areg]"}, +{ 1728, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "CALLM s[!Dreg,Areg,Aipi,Apdi,Immd]"}, +{ 1728, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "RTM s[Dreg,Areg]"}, +{ 2048, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 17, "BTST #1,s[!Areg]"}, +{ 2112, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCHG #1,s[!Areg,Immd]"}, +{ 2176, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCLR #1,s[!Areg,Immd]"}, +{ 2240, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BSET #1,s[!Areg,Immd]"}, +{ 2620, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "EORSR.B #1"}, +{ 2684, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "EORSR.W #1"}, +{ 2560, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 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17, "BFEXTS #1,s[!Areg,Apdi,Aipi,Immd]"}, +{ 60608, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"}, +{ 60864, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "BFFFO #1,s[!Areg,Apdi,Aipi,Immd]"}, +{ 61120, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"}, +{ 61376, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"}, +{ 61952, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FPP #1,s"}, +{ 62016, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FDBcc #1,s[Areg-Dreg]"}, +{ 62016, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FScc #1,s[!Areg,Immd,PC8r,PC16]"}, +{ 62074, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FTRAPcc #1"}, +{ 62075, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FTRAPcc #2"}, +{ 62076, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 0, "FTRAPcc"}, +{ 62080, 6, {10,10,10,10,10,10,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FBcc #K,#1"}, +{ 62144, 6, {10,10,10,10,10,10,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FBcc #K,#2"}, +{ 62208, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 32, "FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]"}, +{ 62272, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FRESTORE s[!Dreg,Areg,Apdi,Immd]"}, +{ 62720, 8, {5,5,5,5,5,12,12,12,0,0,0,0,0,0,0,0}, 65280, 4, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "MMUOP #i,s"}, +{ 62472, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CINVL #p,Ar"}, +{ 62480, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CINVP #p,Ar"}, +{ 62488, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "CINVA #p"}, +{ 62504, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CPUSHL #p,Ar"}, +{ 62512, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CPUSHP #p,Ar"}, +{ 62520, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "CPUSHA #p"}, +{ 63008, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 ArP,AxP"}, +{ 62976, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 s[Dreg-Aipi],L"}, +{ 62976, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 L,d[Areg-Aipi]"}, +{ 62976, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 s[Aind],L"}, +{ 62976, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 L,d[Aipi-Aind]"}}; +int n_defs68k = 179; diff --git a/waterbox/virtualjaguar/src/m68000/cpudefs.h b/waterbox/virtualjaguar/src/m68000/cpudefs.h new file mode 100644 index 0000000000..191057f1f7 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpudefs.h @@ -0,0 +1,97 @@ +// +// Common definitions for the UAE 68000 core +// +// by James Hammons +// (C) 2011 Underground Software +// +// This file is distributed under the GNU Public License, version 3 or at your +// option any later version. Read the file GPLv3 for details. +// + +#ifndef __CPUDEFS_H__ +#define __CPUDEFS_H__ + +#include "sysdeps.h" + +/* Special flags */ +#define SPCFLAG_DEBUGGER 0x001 +#define SPCFLAG_STOP 0x002 +#define SPCFLAG_BUSERROR 0x004 +#define SPCFLAG_INT 0x008 +#define SPCFLAG_BRK 0x010 +#define SPCFLAG_EXTRA_CYCLES 0x020 +#define SPCFLAG_TRACE 0x040 +#define SPCFLAG_DOTRACE 0x080 +#define SPCFLAG_DOINT 0x100 +#define SPCFLAG_MFP 0x200 +#define SPCFLAG_EXEC 0x400 +#define SPCFLAG_MODE_CHANGE 0x800 + +struct regstruct +{ + uint32_t regs[16]; + uint32_t usp, isp; + uint16_t sr; + uint8_t s; + uint8_t stopped; + int intmask; + int intLevel; + + unsigned int c; + unsigned int z; + unsigned int n; + unsigned int v; + unsigned int x; + + uint32_t pc; + uint8_t * pc_p; + uint8_t * pc_oldp; + + uint32_t spcflags; + + uint32_t prefetch_pc; + uint32_t prefetch; + + int32_t remainingCycles; + uint32_t interruptCycles; +}; + +extern struct regstruct regs, lastint_regs; + +#define m68k_dreg(r, num) ((r).regs[(num)]) +#define m68k_areg(r, num) (((r).regs + 8)[(num)]) + +#define ZFLG (regs.z) +#define NFLG (regs.n) +#define CFLG (regs.c) +#define VFLG (regs.v) +#define XFLG (regs.x) + +/* Possible exceptions sources for M68000_Exception() and Exception() */ +#define M68000_EXC_SRC_CPU 1 /* Direct CPU exception */ +#define M68000_EXC_SRC_AUTOVEC 2 /* Auto-vector exception (e.g. VBL) */ +//#define M68000_EXC_SRC_INT_MFP 3 /* MFP interrupt exception */ +//#define M68000_EXC_SRC_INT_DSP 4 /* DSP interrupt exception */ + +#define SET_CFLG(x) (CFLG = (x)) +#define SET_NFLG(x) (NFLG = (x)) +#define SET_VFLG(x) (VFLG = (x)) +#define SET_ZFLG(x) (ZFLG = (x)) +#define SET_XFLG(x) (XFLG = (x)) + +#define GET_CFLG CFLG +#define GET_NFLG NFLG +#define GET_VFLG VFLG +#define GET_ZFLG ZFLG +#define GET_XFLG XFLG + +#define CLEAR_CZNV do { \ + SET_CFLG(0); \ + SET_ZFLG(0); \ + SET_NFLG(0); \ + SET_VFLG(0); \ +} while (0) + +#define COPY_CARRY (SET_XFLG(GET_CFLG)) + +#endif // __CPUDEFS_H__ diff --git a/waterbox/virtualjaguar/src/m68000/cpuemu.c b/waterbox/virtualjaguar/src/m68000/cpuemu.c new file mode 100644 index 0000000000..a97db34be9 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpuemu.c @@ -0,0 +1,60608 @@ +#include "cpudefs.h" +#include "cpuextra.h" +#include "inlines.h" +#include "cputbl.h" +#define CPUFUNC(x) x##_ff +#ifdef NOFLAGS +#include "noflags.h" +#endif + +const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 }; +const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 }; + +const int movem_index1[256] = { +0x08, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x06, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x07, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x06, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, +}; + +const int movem_index2[256] = { +0xFFFFFFFF, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x01, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x00, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x01, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, +}; + +const int movem_next[256] = { +0x00, 0x00, 0x00, 0x02, 0x00, 0x04, 0x04, 0x06, 0x00, 0x08, 0x08, 0x0A, 0x08, 0x0C, 0x0C, 0x0E, +0x00, 0x10, 0x10, 0x12, 0x10, 0x14, 0x14, 0x16, 0x10, 0x18, 0x18, 0x1A, 0x18, 0x1C, 0x1C, 0x1E, +0x00, 0x20, 0x20, 0x22, 0x20, 0x24, 0x24, 0x26, 0x20, 0x28, 0x28, 0x2A, 0x28, 0x2C, 0x2C, 0x2E, +0x20, 0x30, 0x30, 0x32, 0x30, 0x34, 0x34, 0x36, 0x30, 0x38, 0x38, 0x3A, 0x38, 0x3C, 0x3C, 0x3E, +0x00, 0x40, 0x40, 0x42, 0x40, 0x44, 0x44, 0x46, 0x40, 0x48, 0x48, 0x4A, 0x48, 0x4C, 0x4C, 0x4E, +0x40, 0x50, 0x50, 0x52, 0x50, 0x54, 0x54, 0x56, 0x50, 0x58, 0x58, 0x5A, 0x58, 0x5C, 0x5C, 0x5E, +0x40, 0x60, 0x60, 0x62, 0x60, 0x64, 0x64, 0x66, 0x60, 0x68, 0x68, 0x6A, 0x68, 0x6C, 0x6C, 0x6E, +0x60, 0x70, 0x70, 0x72, 0x70, 0x74, 0x74, 0x76, 0x70, 0x78, 0x78, 0x7A, 0x78, 0x7C, 0x7C, 0x7E, +0x00, 0x80, 0x80, 0x82, 0x80, 0x84, 0x84, 0x86, 0x80, 0x88, 0x88, 0x8A, 0x88, 0x8C, 0x8C, 0x8E, +0x80, 0x90, 0x90, 0x92, 0x90, 0x94, 0x94, 0x96, 0x90, 0x98, 0x98, 0x9A, 0x98, 0x9C, 0x9C, 0x9E, +0x80, 0xA0, 0xA0, 0xA2, 0xA0, 0xA4, 0xA4, 0xA6, 0xA0, 0xA8, 0xA8, 0xAA, 0xA8, 0xAC, 0xAC, 0xAE, +0xA0, 0xB0, 0xB0, 0xB2, 0xB0, 0xB4, 0xB4, 0xB6, 0xB0, 0xB8, 0xB8, 0xBA, 0xB8, 0xBC, 0xBC, 0xBE, +0x80, 0xC0, 0xC0, 0xC2, 0xC0, 0xC4, 0xC4, 0xC6, 0xC0, 0xC8, 0xC8, 0xCA, 0xC8, 0xCC, 0xCC, 0xCE, +0xC0, 0xD0, 0xD0, 0xD2, 0xD0, 0xD4, 0xD4, 0xD6, 0xD0, 0xD8, 0xD8, 0xDA, 0xD8, 0xDC, 0xDC, 0xDE, +0xC0, 0xE0, 0xE0, 0xE2, 0xE0, 0xE4, 0xE4, 0xE6, 0xE0, 0xE8, 0xE8, 0xEA, 0xE8, 0xEC, 0xEC, 0xEE, +0xE0, 0xF0, 0xF0, 0xF2, 0xF0, 0xF4, 0xF4, 0xF6, 0xF0, 0xF8, 0xF8, 0xFA, 0xF8, 0xFC, 0xFC, 0xFE, +}; + + +#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8) +#define PART_1 1 +#define PART_2 1 +#define PART_3 1 +#define PART_4 1 +#define PART_5 1 +#define PART_6 1 +#define PART_7 1 +#define PART_8 1 +#endif + +#ifdef PART_1 +unsigned long CPUFUNC(op_0_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_10_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_18_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_20_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_28_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_30_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_38_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_39_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_3c_4)(uint32_t opcode) /* ORSR */ +{ + OpcodeFamily = 4; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword(2); + src &= 0xFF; + regs.sr |= src; + MakeFromSR(); +}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_40_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_50_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_58_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_60_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_68_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_70_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_78_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_79_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_7c_4)(uint32_t opcode) /* ORSR */ +{ + OpcodeFamily = 4; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel18; } +{ MakeSR(); +{ int16_t src = get_iword(2); + regs.sr |= src; + MakeFromSR(); +}}}m68k_incpc(4); +endlabel18: ; +return 20; +} +unsigned long CPUFUNC(op_80_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_90_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_98_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_a0_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_a8_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_b0_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_b8_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_b9_4)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_100_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_108_4)(uint32_t opcode) /* MVPMR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 29; CurrentInstrCycles = 16; +{ uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ uint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_110_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_118_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_120_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 10; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_128_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_130_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_138_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_139_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_13a_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_13b_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_13c_4)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = get_ibyte(2); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_140_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_148_4)(uint32_t opcode) /* MVPMR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 29; CurrentInstrCycles = 24; +{ uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ uint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16) + + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6); + m68k_dreg(regs, dstreg) = (val); +}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_150_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_158_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_160_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_168_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_170_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_178_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_179_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_17a_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_17b_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_180_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 10; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_dreg(regs, dstreg) = (dst); + if ( src < 16 ) { m68k_incpc(2); return 8; } +}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_188_4)(uint32_t opcode) /* MVPRM */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 28; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); + uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + m68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_190_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_198_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1a0_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_1a8_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1b0_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1b8_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1b9_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_1ba_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1bb_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1c0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1c8_4)(uint32_t opcode) /* MVPRM */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 28; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); + uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + m68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16); + m68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src); +}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_1d0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1d8_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1e0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_1e8_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1f0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1f8_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1f9_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_1fa_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1fb_4)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_200_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_210_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_218_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_220_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_228_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_230_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_238_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_239_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_23c_4)(uint32_t opcode) /* ANDSR */ +{ + OpcodeFamily = 5; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword(2); + src |= 0xFF00; + regs.sr &= src; + MakeFromSR(); +}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_240_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_250_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_258_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_260_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_268_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_270_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_278_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_279_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_27c_4)(uint32_t opcode) /* ANDSR */ +{ + OpcodeFamily = 5; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel89; } +{ MakeSR(); +{ int16_t src = get_iword(2); + regs.sr &= src; + MakeFromSR(); +}}}m68k_incpc(4); +endlabel89: ; +return 20; +} +unsigned long CPUFUNC(op_280_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_290_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_298_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_2a0_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_2a8_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_2b0_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_2b8_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_2b9_4)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_400_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_410_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_418_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_420_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_428_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_430_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_438_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_439_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_440_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_450_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_458_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_460_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_468_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_470_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_478_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_479_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_480_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_490_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_498_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_4a0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_4a8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_4b0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_4b8_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_4b9_4)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_600_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_610_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_618_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_620_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_628_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_630_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_638_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_639_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_640_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_650_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_658_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_660_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_668_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_670_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_678_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_679_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_680_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_690_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_698_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_6a0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_6a8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_6b0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_6b8_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_6b9_4)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_800_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 10; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(4); +return 10; +} +unsigned long CPUFUNC(op_810_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_818_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_820_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_828_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_830_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_838_4)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_839_4)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(8); +return 20; +} +unsigned long CPUFUNC(op_83a_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_83b_4)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 21; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_83c_4)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ int8_t dst = get_ibyte(4); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(6); +return 12; +} +unsigned long CPUFUNC(op_840_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_850_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_858_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_860_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_868_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_870_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_878_4)(uint32_t opcode) /* BCHG */ +{ + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_879_4)(uint32_t opcode) /* BCHG */ +{ + OpcodeFamily = 22; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_87a_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_87b_4)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 22; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_880_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 14; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_dreg(regs, dstreg) = (dst); + if ( src < 16 ) { m68k_incpc(4); return 12; } +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_890_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_898_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8a0_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_8a8_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8b0_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_8b8_4)(uint32_t opcode) /* BCLR */ +{ + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8b9_4)(uint32_t opcode) /* BCLR */ +{ + OpcodeFamily = 23; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_8ba_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8bb_4)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 23; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_8c0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_8d0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8d8_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8e0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_8e8_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8f0_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_8f8_4)(uint32_t opcode) /* BSET */ +{ + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8f9_4)(uint32_t opcode) /* BSET */ +{ + OpcodeFamily = 24; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_8fa_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8fb_4)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 24; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_write_memory_8(dsta,dst); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_a00_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_a10_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_a18_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_a20_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_a28_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_a30_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_a38_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_a39_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_a3c_4)(uint32_t opcode) /* EORSR */ +{ + OpcodeFamily = 6; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword(2); + src &= 0xFF; + regs.sr ^= src; + MakeFromSR(); +}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_a40_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_a50_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_a58_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_a60_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_a68_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_a70_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_a78_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_a79_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_a7c_4)(uint32_t opcode) /* EORSR */ +{ + OpcodeFamily = 6; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel204; } +{ MakeSR(); +{ int16_t src = get_iword(2); + regs.sr ^= src; + MakeFromSR(); +}}}m68k_incpc(4); +endlabel204: ; +return 20; +} +#endif + +#ifdef PART_2 +unsigned long CPUFUNC(op_a80_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_a90_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_a98_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_aa0_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_aa8_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_ab0_4)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_ab8_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_ab9_4)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_c00_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_c10_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c18_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c20_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c28_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c30_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_c38_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c39_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 20; +} +unsigned long CPUFUNC(op_c3a_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c3b_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_c40_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_c50_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c58_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c60_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c68_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c70_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_c78_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c79_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 20; +} +unsigned long CPUFUNC(op_c7a_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword(4); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c7b_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_c80_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +return 14; +} +unsigned long CPUFUNC(op_c90_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_c98_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_ca0_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 22; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_ca8_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_cb0_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_cb8_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_cb9_4)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(10); +return 28; +} +unsigned long CPUFUNC(op_cba_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_getpc () + 6; + dsta += (int32_t)(int16_t)get_iword(6); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_cbb_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong(2); +{ uint32_t tmppc = m68k_getpc() + 6; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword(6)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_1000_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_1008_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int8_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_1010_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1018_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1020_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_1028_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1030_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_1038_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1039_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_103a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_103b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_103c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_1080_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1088_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1090_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1098_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_10a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_10a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_10b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_10ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_10bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_10c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_10c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_10d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_10d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_10e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_10e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_10f8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10f9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_10fa_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_10fb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_10fc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1100_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1108_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_1110_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1118_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_1120_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_1128_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1130_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1138_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1139_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_113a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_113b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_113c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1140_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1148_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_1150_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1158_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_1160_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1168_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_1170_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_1178_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_1179_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_117a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_117b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_117c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_1180_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_1188_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_1190_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_1198_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_11a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_11a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_11b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 24; +} +unsigned long CPUFUNC(op_11b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_11b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_11ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_11bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 24; +} +unsigned long CPUFUNC(op_11bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_11c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_11c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_11d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_11d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_11e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_11e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_11f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_11f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_11f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_11fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_11fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_11fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_13c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_13c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_13d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_13d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_13e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_13e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_13f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_13f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_13f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(10); +return 28; +} +unsigned long CPUFUNC(op_13fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_13fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_13fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte(2); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}m68k_incpc(8); +return 20; +} +unsigned long CPUFUNC(op_2000_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_2008_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_2010_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2018_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2020_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_2028_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2030_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_2038_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2039_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_203a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_203b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_203c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong(2); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 12; +} +unsigned long CPUFUNC(op_2040_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_2048_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_2050_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2058_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2060_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_2068_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2070_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_2078_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2079_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_207a_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_207b_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_207c_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong(2); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(6); +return 12; +} +unsigned long CPUFUNC(op_2080_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2088_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2090_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_2098_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_20a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_20a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_20b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_20ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_20bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_20c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_20c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_20d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_20d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_20e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_20e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_20f8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20f9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_20fa_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_20fb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_20fc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_2100_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2108_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_2110_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_2118_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_2120_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_2128_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_2130_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_2138_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +#endif + +#ifdef PART_3 +unsigned long CPUFUNC(op_2139_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_213a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_213b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_213c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_2140_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2148_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_2150_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_2158_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_2160_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_2168_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_2170_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_2178_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_2179_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_217a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_217b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_217c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_2180_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_2188_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_2190_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_2198_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_21a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 28; +} +unsigned long CPUFUNC(op_21a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_21b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 32; +} +unsigned long CPUFUNC(op_21b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_21b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_21ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_21bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 32; +} +unsigned long CPUFUNC(op_21bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_21c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_21c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_21d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_21d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_21e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_21e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_21f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_21f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_21f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_21fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_21fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_21fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_23c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_23c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_23d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_23d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_23e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 30; +} +unsigned long CPUFUNC(op_23e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_23f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_23f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_23f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 36; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(10); +return 36; +} +unsigned long CPUFUNC(op_23fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 32; +} +unsigned long CPUFUNC(op_23fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(8); +return 34; +} +unsigned long CPUFUNC(op_23fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong(2); +{ uint32_t dsta = get_ilong(6); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}m68k_incpc(10); +return 28; +} +unsigned long CPUFUNC(op_3000_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_3008_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_3010_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3018_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3020_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_3028_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3030_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_3038_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3039_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_303a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_303b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_303c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_3040_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_3048_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_3050_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3058_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3060_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_3068_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3070_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_3078_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3079_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_307a_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_307b_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_307c_4)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_3080_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3088_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3090_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_3098_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_30a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_30a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_30b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_30ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_30bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_30c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_30c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_30d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_30d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_30e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_30e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_30f8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30f9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_30fa_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_30fb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_30fc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3100_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3108_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_3110_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_3118_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_3120_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_3128_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_3130_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_3138_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_3139_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_313a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_313b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_313c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3140_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3148_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_3150_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_3158_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_3160_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_3168_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_3170_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_3178_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_3179_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_317a_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_317b_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_317c_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_3180_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_3188_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_3190_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_3198_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_31a0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_31a8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_31b0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 24; +} +unsigned long CPUFUNC(op_31b8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_31b9_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_31ba_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_31bb_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 24; +} +unsigned long CPUFUNC(op_31bc_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_31c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_31c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_31d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_31d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_31e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_31e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_31f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_31f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_31f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(6); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_31fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_31fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_31fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_33c0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_33c8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_33d0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_33d8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_33e0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_33e8_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_33f0_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_33f8_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_33f9_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(6); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(10); +return 28; +} +unsigned long CPUFUNC(op_33fa_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 24; +} +unsigned long CPUFUNC(op_33fb_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(8); +return 26; +} +unsigned long CPUFUNC(op_33fc_4)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int16_t src = get_iword(2); +{ uint32_t dsta = get_ilong(4); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}m68k_incpc(8); +return 20; +} +unsigned long CPUFUNC(op_4000_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4010_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4018_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4020_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4028_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4030_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4038_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4039_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4040_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff); +}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4050_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4058_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4060_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4068_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4070_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4078_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4079_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(srca,newv); +}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4080_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (newv); +}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_4090_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_4098_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_40a0_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_40a8_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_40b0_4)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_40b8_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_40b9_4)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(srca,newv); +}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_40c0_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 6; +{{ MakeSR(); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff); +}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_40d0_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_40d8_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += 2; + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_40e0_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + m68k_areg (regs, srcreg) = srca; + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_40e8_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_40f0_4)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_40f8_4)(uint32_t opcode) /* MVSR2 */ +{ + OpcodeFamily = 32; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_40f9_4)(uint32_t opcode) /* MVSR2 */ +{ + OpcodeFamily = 32; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); + MakeSR(); + m68k_write_memory_16(srca,regs.sr); +}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4180_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; } +}}}endlabel587: ; +return 10; +} +unsigned long CPUFUNC(op_4190_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; } +}}}}endlabel588: ; +return 14; +} +unsigned long CPUFUNC(op_4198_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; } +}}}}endlabel589: ; +return 14; +} +unsigned long CPUFUNC(op_41a0_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; } +}}}}endlabel590: ; +return 16; +} +unsigned long CPUFUNC(op_41a8_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; } +}}}}endlabel591: ; +return 18; +} +unsigned long CPUFUNC(op_41b0_4)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 20; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; } +}}}}endlabel592: ; +return 20; +} +unsigned long CPUFUNC(op_41b8_4)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; } +}}}}endlabel593: ; +return 18; +} +unsigned long CPUFUNC(op_41b9_4)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 22; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; } +}}}}endlabel594: ; +return 22; +} +unsigned long CPUFUNC(op_41ba_4)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; } +}}}}endlabel595: ; +return 18; +} +unsigned long CPUFUNC(op_41bb_4)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 20; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; } +}}}}endlabel596: ; +return 20; +} +unsigned long CPUFUNC(op_41bc_4)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; } +}}}endlabel597: ; +return 14; +} +unsigned long CPUFUNC(op_41d0_4)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 4; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_41e8_4)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_41f0_4)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_41f8_4)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_41f9_4)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 12; +{{ uint32_t srca = get_ilong(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(6); +return 12; +} +unsigned long CPUFUNC(op_41fa_4)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_41fb_4)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_4200_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 4; +{{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4210_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4218_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4220_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4228_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4230_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4238_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4239_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_write_memory_8(srca,0); +}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4240_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 4; +{{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4250_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4258_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += 2; + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4260_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + m68k_areg (regs, srcreg) = srca; + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4268_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(4); +return 16; +} +#endif + +#ifdef PART_4 +unsigned long CPUFUNC(op_4270_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4278_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4279_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_write_memory_16(srca,0); +}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4280_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 6; +{{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (0); +}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_4290_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_4298_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += 4; + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_42a0_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + m68k_areg (regs, srcreg) = srca; + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_42a8_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_42b0_4)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_42b8_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_42b9_4)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_write_memory_32(srca,0); +}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_4400_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4410_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4418_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4420_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4428_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4430_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4438_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4439_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(srca,dst); +}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4440_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4450_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4458_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4460_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4468_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4470_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4478_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4479_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(srca,dst); +}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4480_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (dst); +}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_4490_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_4498_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_44a0_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_44a8_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_44b0_4)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_44b8_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_44b9_4)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(srca,dst); +}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_44c0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_44d0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_44d8_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_44e0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_44e8_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_44f0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(4); +return 22; +} +unsigned long CPUFUNC(op_44f8_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_44f9_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(6); +return 24; +} +unsigned long CPUFUNC(op_44fa_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_44fb_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}m68k_incpc(4); +return 22; +} +unsigned long CPUFUNC(op_44fc_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ int16_t src = get_iword(2); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4600_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4610_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4618_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4620_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4628_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4630_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4638_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4639_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_write_memory_8(srca,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4640_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4650_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4658_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4660_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4668_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4670_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4678_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4679_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_write_memory_16(srca,dst); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4680_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_4690_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_4698_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_46a0_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_46a8_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_46b0_4)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_46b8_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_46b9_4)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_write_memory_32(srca,dst); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_46c0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 12; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel688; } +{{ int16_t src = m68k_dreg(regs, srcreg); + regs.sr = src; + MakeFromSR(); +}}}m68k_incpc(2); +endlabel688: ; +return 12; +} +unsigned long CPUFUNC(op_46d0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel689; } +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(2); +endlabel689: ; +return 16; +} +unsigned long CPUFUNC(op_46d8_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel690; } +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(2); +endlabel690: ; +return 16; +} +unsigned long CPUFUNC(op_46e0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 18; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel691; } +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(2); +endlabel691: ; +return 18; +} +unsigned long CPUFUNC(op_46e8_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel692; } +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(4); +endlabel692: ; +return 20; +} +unsigned long CPUFUNC(op_46f0_4)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 22; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel693; } +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(4); +endlabel693: ; +return 22; +} +unsigned long CPUFUNC(op_46f8_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel694; } +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(4); +endlabel694: ; +return 20; +} +unsigned long CPUFUNC(op_46f9_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 24; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel695; } +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(6); +endlabel695: ; +return 24; +} +unsigned long CPUFUNC(op_46fa_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel696; } +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(4); +endlabel696: ; +return 20; +} +unsigned long CPUFUNC(op_46fb_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 22; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel697; } +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}m68k_incpc(4); +endlabel697: ; +return 22; +} +unsigned long CPUFUNC(op_46fc_4)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel698; } +{{ int16_t src = get_iword(2); + regs.sr = src; + MakeFromSR(); +}}}m68k_incpc(4); +endlabel698: ; +return 16; +} +unsigned long CPUFUNC(op_4800_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_4810_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4818_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4820_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4828_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4830_4)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4838_4)(uint32_t opcode) /* NBCD */ +{ + OpcodeFamily = 17; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4839_4)(uint32_t opcode) /* NBCD */ +{ + OpcodeFamily = 17; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(srca,newv); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4840_4)(uint32_t opcode) /* SWAP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 34; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4850_4)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4868_4)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4870_4)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(4); +return 22; +} +unsigned long CPUFUNC(op_4878_4)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4879_4)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_487a_4)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_487b_4)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = dsta; + m68k_write_memory_32(dsta,srca); +}}}m68k_incpc(4); +return 22; +} +unsigned long CPUFUNC(op_4880_4)(uint32_t opcode) /* EXT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 36; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint16_t dst = (int16_t)(int8_t)src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4890_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(4); + return (8+retcycles); +} +unsigned long CPUFUNC(op_48a0_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) - 0; +{ uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; + while (amask) { srca -= 2; m68k_write_memory_16(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; } + while (dmask) { srca -= 2; m68k_write_memory_16(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; } + m68k_areg(regs, dstreg) = srca; +}}}m68k_incpc(4); + return (8+retcycles); +} +unsigned long CPUFUNC(op_48a8_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (12+retcycles); +} +unsigned long CPUFUNC(op_48b0_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 14; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (14+retcycles); +} +unsigned long CPUFUNC(op_48b8_4)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (12+retcycles); +} +unsigned long CPUFUNC(op_48b9_4)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = get_ilong(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(8); + return (16+retcycles); +} +unsigned long CPUFUNC(op_48c0_4)(uint32_t opcode) /* EXT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 36; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = (int32_t)(int16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_48d0_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(4); + return (8+retcycles); +} +unsigned long CPUFUNC(op_48e0_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) - 0; +{ uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; + while (amask) { srca -= 4; m68k_write_memory_32(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; } + while (dmask) { srca -= 4; m68k_write_memory_32(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; } + m68k_areg(regs, dstreg) = srca; +}}}m68k_incpc(4); + return (8+retcycles); +} +unsigned long CPUFUNC(op_48e8_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (12+retcycles); +} +unsigned long CPUFUNC(op_48f0_4)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 14; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (14+retcycles); +} +unsigned long CPUFUNC(op_48f8_4)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (12+retcycles); +} +unsigned long CPUFUNC(op_48f9_4)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + retcycles = 0; +{ uint32_t srca = get_ilong(4); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(8); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4a00_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4a10_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_4a18_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_4a20_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_4a28_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a30_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_4a38_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a39_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_4a3a_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a3b_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_4a3c_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_4a40_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4a48_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4a50_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_4a58_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_4a60_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_4a68_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a70_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_4a78_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a79_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_4a7a_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_4a7b_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_4a7c_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_4a80_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4a88_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4a90_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4a98_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4aa0_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4aa8_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4ab0_4)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4ab8_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4ab9_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_4aba_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_4abb_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4abc_4)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(6); +return 12; +} +unsigned long CPUFUNC(op_4ac0_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff); +}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4ad0_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4ad8_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_4ae0_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_4ae8_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4af0_4)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_4af8_4)(uint32_t opcode) /* TAS */ +{ + OpcodeFamily = 98; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4af9_4)(uint32_t opcode) /* TAS */ +{ + OpcodeFamily = 98; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_write_memory_8(srca,src); +}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_4c90_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(4); + return (12+retcycles); +} +unsigned long CPUFUNC(op_4c98_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } + m68k_areg(regs, dstreg) = srca; +}}}m68k_incpc(4); + return (12+retcycles); +} +unsigned long CPUFUNC(op_4ca8_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cb0_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cb8_4)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cb9_4)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 20; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_ilong(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(8); + return (20+retcycles); +} +unsigned long CPUFUNC(op_4cba_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 2; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_getpc () + 4; + srca += (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cbb_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 3; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}m68k_incpc(6); + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cd0_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(4); + return (12+retcycles); +} +unsigned long CPUFUNC(op_4cd8_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } + m68k_areg(regs, dstreg) = srca; +}}}m68k_incpc(4); + return (12+retcycles); +} +unsigned long CPUFUNC(op_4ce8_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cf0_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); + BusCyclePenalty += 2; +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cf8_4)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cf9_4)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 20; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_ilong(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(8); + return (20+retcycles); +} +unsigned long CPUFUNC(op_4cfa_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 2; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_getpc () + 4; + srca += (int32_t)(int16_t)get_iword(4); +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cfb_4)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 3; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(4)); + BusCyclePenalty += 2; +{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}m68k_incpc(6); + return (18+retcycles); +} +unsigned long CPUFUNC(op_4e40_4)(uint32_t opcode) /* TRAP */ +{ + uint32_t srcreg = (opcode & 15); + OpcodeFamily = 39; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +m68k_incpc(2); + Exception(src+32,0,M68000_EXC_SRC_CPU); +}}return 4; +} +unsigned long CPUFUNC(op_4e50_4)(uint32_t opcode) /* LINK */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 47; CurrentInstrCycles = 18; +{{ uint32_t olda = m68k_areg(regs, 7) - 4; + m68k_areg (regs, 7) = olda; +{ int32_t src = m68k_areg(regs, srcreg); + m68k_write_memory_32(olda,src); + m68k_areg(regs, srcreg) = (m68k_areg(regs, 7)); +{ int16_t offs = get_iword(2); + m68k_areg(regs, 7) += offs; +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_4e58_4)(uint32_t opcode) /* UNLK */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 48; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); + m68k_areg(regs, 7) = src; +{ uint32_t olda = m68k_areg(regs, 7); +{ int32_t old = m68k_read_memory_32(olda); + m68k_areg(regs, 7) += 4; + m68k_areg(regs, srcreg) = (old); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_4e60_4)(uint32_t opcode) /* MVR2USP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 40; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel791; } +{{ int32_t src = m68k_areg(regs, srcreg); + regs.usp = src; +}}}m68k_incpc(2); +endlabel791: ; +return 4; +} +unsigned long CPUFUNC(op_4e68_4)(uint32_t opcode) /* MVUSP2R */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 41; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel792; } +{{ m68k_areg(regs, srcreg) = (regs.usp); +}}}m68k_incpc(2); +endlabel792: ; +return 4; +} +unsigned long CPUFUNC(op_4e70_4)(uint32_t opcode) /* RESET */ +{ + OpcodeFamily = 42; CurrentInstrCycles = 132; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel793; } +{}}m68k_incpc(2); +endlabel793: ; +return 132; +} +unsigned long CPUFUNC(op_4e71_4)(uint32_t opcode) /* NOP */ +{ + OpcodeFamily = 43; CurrentInstrCycles = 4; +{}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_4e72_4)(uint32_t opcode) /* STOP */ +{ + OpcodeFamily = 44; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel795; } +{{ int16_t src = get_iword(2); + regs.sr = src; + MakeFromSR(); + m68k_setstopped(1); +}}}m68k_incpc(4); +endlabel795: ; +return 4; +} +unsigned long CPUFUNC(op_4e73_4)(uint32_t opcode) /* RTE */ +{ + OpcodeFamily = 45; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel796; } +{{ uint32_t sra = m68k_areg(regs, 7); +{ int16_t sr = m68k_read_memory_16(sra); + m68k_areg(regs, 7) += 2; +{ uint32_t pca = m68k_areg(regs, 7); +{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; + regs.sr = sr; m68k_setpc_rte(pc); + MakeFromSR(); +}}}}}}endlabel796: ; +return 20; +} +unsigned long CPUFUNC(op_4e74_4)(uint32_t opcode) /* RTD */ +{ + OpcodeFamily = 46; CurrentInstrCycles = 16; +{{ uint32_t pca = m68k_areg(regs, 7); +{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; +{ int16_t offs = get_iword(2); + m68k_areg(regs, 7) += offs; + m68k_setpc_rte(pc); +}}}}return 16; +} +unsigned long CPUFUNC(op_4e75_4)(uint32_t opcode) /* RTS */ +{ + OpcodeFamily = 49; CurrentInstrCycles = 16; +{ m68k_do_rts(); +}return 16; +} +unsigned long CPUFUNC(op_4e76_4)(uint32_t opcode) /* TRAPV */ +{ + OpcodeFamily = 50; CurrentInstrCycles = 4; +{m68k_incpc(2); + if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel799; } +}endlabel799: ; +return 4; +} +unsigned long CPUFUNC(op_4e77_4)(uint32_t opcode) /* RTR */ +{ + OpcodeFamily = 51; CurrentInstrCycles = 20; +{ MakeSR(); +{ uint32_t sra = m68k_areg(regs, 7); +{ int16_t sr = m68k_read_memory_16(sra); + m68k_areg(regs, 7) += 2; +{ uint32_t pca = m68k_areg(regs, 7); +{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; + regs.sr &= 0xFF00; sr &= 0xFF; + regs.sr |= sr; m68k_setpc(pc); + MakeFromSR(); +}}}}}return 20; +} +unsigned long CPUFUNC(op_4e90_4)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + uint32_t oldpc = m68k_getpc () + 2; + m68k_do_jsr(m68k_getpc() + 2, srca); +}}return 16; +} +unsigned long CPUFUNC(op_4ea8_4)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + uint32_t oldpc = m68k_getpc () + 4; + m68k_do_jsr(m68k_getpc() + 4, srca); +}}return 18; +} +unsigned long CPUFUNC(op_4eb0_4)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + uint32_t oldpc = m68k_getpc () + 4; + m68k_do_jsr(m68k_getpc() + 4, srca); +}}return 22; +} +unsigned long CPUFUNC(op_4eb8_4)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + uint32_t oldpc = m68k_getpc () + 4; + m68k_do_jsr(m68k_getpc() + 4, srca); +}}return 18; +} +unsigned long CPUFUNC(op_4eb9_4)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); + uint32_t oldpc = m68k_getpc () + 6; + m68k_do_jsr(m68k_getpc() + 6, srca); +}}return 20; +} +unsigned long CPUFUNC(op_4eba_4)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); + uint32_t oldpc = m68k_getpc () + 4; + m68k_do_jsr(m68k_getpc() + 4, srca); +}}return 18; +} +unsigned long CPUFUNC(op_4ebb_4)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; + uint32_t oldpc = m68k_getpc () + 4; + m68k_do_jsr(m68k_getpc() + 4, srca); +}}return 22; +} +unsigned long CPUFUNC(op_4ed0_4)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_setpc(srca); +}}return 8; +} +unsigned long CPUFUNC(op_4ee8_4)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); + m68k_setpc(srca); +}}return 10; +} +unsigned long CPUFUNC(op_4ef0_4)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; + m68k_setpc(srca); +}}return 14; +} +unsigned long CPUFUNC(op_4ef8_4)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); + m68k_setpc(srca); +}}return 10; +} +unsigned long CPUFUNC(op_4ef9_4)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 12; +{{ uint32_t srca = get_ilong(2); + m68k_setpc(srca); +}}return 12; +} +unsigned long CPUFUNC(op_4efa_4)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); + m68k_setpc(srca); +}}return 10; +} +unsigned long CPUFUNC(op_4efb_4)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; + m68k_setpc(srca); +}}return 14; +} +unsigned long CPUFUNC(op_5000_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5010_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5018_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +#endif + +#ifdef PART_5 +unsigned long CPUFUNC(op_5020_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5028_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5030_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5038_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5039_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5040_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5048_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5050_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5058_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5060_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5068_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5070_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5078_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5079_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5080_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5088_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5090_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_5098_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_50a0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_50a8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_50b0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 26; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_50b8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_50b9_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_50c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(0) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_50c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(0)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel842: ; +return 12; +} +unsigned long CPUFUNC(op_50d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_50d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_50e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_50e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_50f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_50f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_50f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(0) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5100_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5110_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5118_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5120_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5128_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5130_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5138_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5139_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5140_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5148_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5150_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5158_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5160_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5168_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5170_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5178_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5179_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5180_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5188_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_5190_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_5198_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_51a0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_51a8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_51b0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 26; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_51b8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_51b9_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_51c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(1) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_51c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(1)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel877: ; +return 12; +} +unsigned long CPUFUNC(op_51d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_51d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_51e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_51e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_51f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_51f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_51f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(1) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_52c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(2) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_52c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(2)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel886: ; +return 12; +} +unsigned long CPUFUNC(op_52d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_52d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_52e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_52e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_52f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_52f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_52f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(2) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_53c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(3) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_53c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(3)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel895: ; +return 12; +} +unsigned long CPUFUNC(op_53d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_53d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_53e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_53e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_53f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_53f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_53f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(3) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_54c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(4) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_54c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(4)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel904: ; +return 12; +} +unsigned long CPUFUNC(op_54d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_54d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_54e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_54e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_54f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_54f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_54f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(4) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_55c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(5) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_55c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(5)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel913: ; +return 12; +} +unsigned long CPUFUNC(op_55d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_55d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_55e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_55e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_55f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_55f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_55f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(5) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_56c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(6) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_56c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(6)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel922: ; +return 12; +} +unsigned long CPUFUNC(op_56d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_56d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_56e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_56e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_56f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_56f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_56f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(6) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_57c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(7) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_57c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(7)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel931: ; +return 12; +} +unsigned long CPUFUNC(op_57d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_57d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_57e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_57e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_57f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_57f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_57f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(7) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_58c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(8) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_58c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(8)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel940: ; +return 12; +} +unsigned long CPUFUNC(op_58d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_58d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_58e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_58e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_58f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_58f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_58f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(8) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_59c0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(9) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_59c8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(9)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel949: ; +return 12; +} +unsigned long CPUFUNC(op_59d0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_59d8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_59e0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_59e8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_59f0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_59f8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_59f9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(9) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5ac0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(10) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5ac8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(10)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel958: ; +return 12; +} +unsigned long CPUFUNC(op_5ad0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5ad8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5ae0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5ae8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5af0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5af8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5af9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(10) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5bc0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(11) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5bc8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(11)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel967: ; +return 12; +} +unsigned long CPUFUNC(op_5bd0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5bd8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5be0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5be8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5bf0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5bf8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5bf9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(11) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5cc0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(12) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5cc8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(12)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel976: ; +return 12; +} +unsigned long CPUFUNC(op_5cd0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5cd8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5ce0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5ce8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5cf0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5cf8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5cf9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(12) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5dc0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(13) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5dc8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(13)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel985: ; +return 12; +} +unsigned long CPUFUNC(op_5dd0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5dd8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5de0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5de8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5df0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5df8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5df9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(13) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5ec0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(14) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5ec8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(14)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel994: ; +return 12; +} +unsigned long CPUFUNC(op_5ed0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5ed8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5ee0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_5ee8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5ef0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5ef8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5ef9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(14) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_5fc0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(15) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_5fc8_4)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword(2); + if (!cctrue(15)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + m68k_incpc((int32_t)offs + 2); + return 10; + } else { + m68k_incpc(4); + return 14; + } + } +}}}m68k_incpc(4); +endlabel1003: ; +return 12; +} +unsigned long CPUFUNC(op_5fd0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5fd8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_5fe0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(2); +return 14; +} +#endif + +#ifdef PART_6 +unsigned long CPUFUNC(op_5fe8_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5ff0_4)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_5ff8_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_5ff9_4)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int val = cctrue(15) ? 0xff : 0; + m68k_write_memory_8(srca,val); +}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_6000_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(0)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1011: ; +return 12; +} +unsigned long CPUFUNC(op_6001_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(0)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1012: ; +return 8; +} +unsigned long CPUFUNC(op_60ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(0)) goto endlabel1013; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1013; +{ int32_t src = get_ilong(2); + if (!cctrue(0)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1013: ; +return 12; +} +unsigned long CPUFUNC(op_6100_4)(uint32_t opcode) /* BSR */ +{ + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ int16_t src = get_iword(2); + int32_t s = (int32_t)src + 2; + m68k_do_bsr(m68k_getpc() + 4, s); +}}return 18; +} +unsigned long CPUFUNC(op_6101_4)(uint32_t opcode) /* BSR */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; + int32_t s = (int32_t)src + 2; + m68k_do_bsr(m68k_getpc() + 2, s); +}}return 18; +} +unsigned long CPUFUNC(op_61ff_4)(uint32_t opcode) /* BSR */ +{ + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ int32_t src = get_ilong(2); + int32_t s = (int32_t)src + 2; + m68k_do_bsr(m68k_getpc() + 6, s); +}}return 18; +} +unsigned long CPUFUNC(op_6200_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(2)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1017: ; +return 12; +} +unsigned long CPUFUNC(op_6201_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(2)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1018: ; +return 8; +} +unsigned long CPUFUNC(op_62ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(2)) goto endlabel1019; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1019; +{ int32_t src = get_ilong(2); + if (!cctrue(2)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1019: ; +return 12; +} +unsigned long CPUFUNC(op_6300_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(3)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1020: ; +return 12; +} +unsigned long CPUFUNC(op_6301_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(3)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1021: ; +return 8; +} +unsigned long CPUFUNC(op_63ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(3)) goto endlabel1022; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1022; +{ int32_t src = get_ilong(2); + if (!cctrue(3)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1022: ; +return 12; +} +unsigned long CPUFUNC(op_6400_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(4)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1023: ; +return 12; +} +unsigned long CPUFUNC(op_6401_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(4)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1024: ; +return 8; +} +unsigned long CPUFUNC(op_64ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(4)) goto endlabel1025; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1025; +{ int32_t src = get_ilong(2); + if (!cctrue(4)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1025: ; +return 12; +} +unsigned long CPUFUNC(op_6500_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(5)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1026: ; +return 12; +} +unsigned long CPUFUNC(op_6501_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(5)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1027: ; +return 8; +} +unsigned long CPUFUNC(op_65ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(5)) goto endlabel1028; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1028; +{ int32_t src = get_ilong(2); + if (!cctrue(5)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1028: ; +return 12; +} +unsigned long CPUFUNC(op_6600_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(6)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1029: ; +return 12; +} +unsigned long CPUFUNC(op_6601_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(6)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1030: ; +return 8; +} +unsigned long CPUFUNC(op_66ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(6)) goto endlabel1031; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1031; +{ int32_t src = get_ilong(2); + if (!cctrue(6)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1031: ; +return 12; +} +unsigned long CPUFUNC(op_6700_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(7)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1032: ; +return 12; +} +unsigned long CPUFUNC(op_6701_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(7)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1033: ; +return 8; +} +unsigned long CPUFUNC(op_67ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(7)) goto endlabel1034; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1034; +{ int32_t src = get_ilong(2); + if (!cctrue(7)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1034: ; +return 12; +} +unsigned long CPUFUNC(op_6800_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(8)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1035: ; +return 12; +} +unsigned long CPUFUNC(op_6801_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(8)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1036: ; +return 8; +} +unsigned long CPUFUNC(op_68ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(8)) goto endlabel1037; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1037; +{ int32_t src = get_ilong(2); + if (!cctrue(8)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1037: ; +return 12; +} +unsigned long CPUFUNC(op_6900_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(9)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1038: ; +return 12; +} +unsigned long CPUFUNC(op_6901_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(9)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1039: ; +return 8; +} +unsigned long CPUFUNC(op_69ff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(9)) goto endlabel1040; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1040; +{ int32_t src = get_ilong(2); + if (!cctrue(9)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1040: ; +return 12; +} +unsigned long CPUFUNC(op_6a00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(10)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1041: ; +return 12; +} +unsigned long CPUFUNC(op_6a01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(10)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1042: ; +return 8; +} +unsigned long CPUFUNC(op_6aff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(10)) goto endlabel1043; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1043; +{ int32_t src = get_ilong(2); + if (!cctrue(10)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1043: ; +return 12; +} +unsigned long CPUFUNC(op_6b00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(11)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1044: ; +return 12; +} +unsigned long CPUFUNC(op_6b01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(11)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1045: ; +return 8; +} +unsigned long CPUFUNC(op_6bff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(11)) goto endlabel1046; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1046; +{ int32_t src = get_ilong(2); + if (!cctrue(11)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1046: ; +return 12; +} +unsigned long CPUFUNC(op_6c00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(12)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1047: ; +return 12; +} +unsigned long CPUFUNC(op_6c01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(12)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1048: ; +return 8; +} +unsigned long CPUFUNC(op_6cff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(12)) goto endlabel1049; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1049; +{ int32_t src = get_ilong(2); + if (!cctrue(12)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1049: ; +return 12; +} +unsigned long CPUFUNC(op_6d00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(13)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1050: ; +return 12; +} +unsigned long CPUFUNC(op_6d01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(13)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1051: ; +return 8; +} +unsigned long CPUFUNC(op_6dff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(13)) goto endlabel1052; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1052; +{ int32_t src = get_ilong(2); + if (!cctrue(13)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1052: ; +return 12; +} +unsigned long CPUFUNC(op_6e00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(14)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1053: ; +return 12; +} +unsigned long CPUFUNC(op_6e01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(14)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1054: ; +return 8; +} +unsigned long CPUFUNC(op_6eff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(14)) goto endlabel1055; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1055; +{ int32_t src = get_ilong(2); + if (!cctrue(14)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1055: ; +return 12; +} +unsigned long CPUFUNC(op_6f00_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); + if (!cctrue(15)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(4); +endlabel1056: ; +return 12; +} +unsigned long CPUFUNC(op_6f01_4)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(15)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(2); +endlabel1057: ; +return 8; +} +unsigned long CPUFUNC(op_6fff_4)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(15)) goto endlabel1058; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1058; +{ int32_t src = get_ilong(2); + if (!cctrue(15)) goto didnt_jump; + m68k_incpc ((int32_t)src + 2); + return 10; +didnt_jump:; +}}m68k_incpc(6); +endlabel1058: ; +return 12; +} +unsigned long CPUFUNC(op_7000_4)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_8000_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_8010_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_8018_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_8020_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_8028_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_8030_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_8038_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_8039_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_803a_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_803b_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_803c_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_8040_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_8050_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_8058_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_8060_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_8068_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_8070_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_8078_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_8079_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_807a_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_807b_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_807c_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_8080_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_8090_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_8098_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_80a0_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_80a8_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_80b0_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_80b8_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_80b9_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_80ba_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_80bb_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_80bc_4)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_80c0_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 4; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1093; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}endlabel1093: ; + return (4+retcycles); +} +unsigned long CPUFUNC(op_80d0_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1094; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1094: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_80d8_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1095; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1095: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_80e0_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1096; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1096: ; + return (10+retcycles); +} +unsigned long CPUFUNC(op_80e8_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1097; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1097: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80f0_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1098; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1098: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_80f8_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1099; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1099: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80f9_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1100; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1100: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_80fa_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1101; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1101: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80fb_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1102; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}endlabel1102: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_80fc_4)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1103; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}endlabel1103: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_8100_4)(uint32_t opcode) /* SBCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 10; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); + uint16_t newv, tmp_newv; + int bcd = 0; + newv = tmp_newv = newv_hi + newv_lo; + if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; + if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } + SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_8108_4)(uint32_t opcode) /* SBCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 10; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); + uint16_t newv, tmp_newv; + int bcd = 0; + newv = tmp_newv = newv_hi + newv_lo; + if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; + if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } + SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); + m68k_write_memory_8(dsta,newv); +}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_8110_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_8118_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_8120_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_8128_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8130_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_8138_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8139_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8150_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_8158_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_8160_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_8168_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8170_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_8178_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_8179_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_8190_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_8198_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_81a0_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_81a8_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_81b0_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_81b8_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_81b9_4)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_81c0_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 4; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1127; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}endlabel1127: ; + return (4+retcycles); +} +unsigned long CPUFUNC(op_81d0_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1128; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1128: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_81d8_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1129; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1129: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_81e0_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1130; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1130: ; + return (10+retcycles); +} +unsigned long CPUFUNC(op_81e8_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1131; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1131: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81f0_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1132; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1132: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_81f8_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1133; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1133: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81f9_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1134; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1134: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_81fa_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1135; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1135: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81fb_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1136; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}endlabel1136: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_81fc_4)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1137; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}endlabel1137: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_9000_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_9010_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9018_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9020_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_9028_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_9030_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_9038_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_9039_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_903a_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_903b_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_903c_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_9040_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_9048_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_9050_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9058_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9060_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_9068_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_9070_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_9078_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_9079_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_907a_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_907b_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_907c_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_9080_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9088_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9090_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_9098_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_90a0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_90a8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_90b0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_90b8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_90b9_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_90ba_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_90bb_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_90bc_4)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_90c0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_90c8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_90d0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_90d8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_90e0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_90e8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_90f0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_90f8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_90f9_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_90fa_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_90fb_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_90fc_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_9100_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_9108_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_9110_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_9118_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_9120_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_9128_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_9130_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_9138_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_9139_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_9140_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_9148_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_9150_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_9158_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_9160_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_9168_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_9170_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_9178_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_9179_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_9180_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_9188_4)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 30; +} +unsigned long CPUFUNC(op_9190_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_9198_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_91a0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_91a8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_91b0_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_91b8_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_91b9_4)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_91c0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_91c8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_91d0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_91d8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_91e0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_91e8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_91f0_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_91f8_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_91f9_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_91fa_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_91fb_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_91fc_4)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_b000_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_b010_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_b018_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_b020_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_b028_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b030_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b038_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b039_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_b03a_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b03b_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +#endif + +#ifdef PART_7 +unsigned long CPUFUNC(op_b03c_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_b040_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_b048_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_b050_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_b058_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_b060_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_b068_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b070_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b078_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b079_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_b07a_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_b07b_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b07c_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_b080_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b088_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b090_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b098_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b0a0_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_b0a8_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b0b0_4)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_b0b8_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b0b9_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_b0ba_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b0bb_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_b0bc_4)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +return 14; +} +unsigned long CPUFUNC(op_b0c0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b0c8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b0d0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_b0d8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_b0e0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b0e8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b0f0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b0f8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b0f9_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 18; +} +unsigned long CPUFUNC(op_b0fa_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_b0fb_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b0fc_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +return 10; +} +unsigned long CPUFUNC(op_b100_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_b108_4)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b110_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b118_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b120_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b128_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b130_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b138_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b139_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_b140_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_b148_4)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b150_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b158_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_b160_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b168_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b170_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b178_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_b179_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_b180_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_b188_4)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_b190_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_b198_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_b1a0_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_b1a8_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_b1b0_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_b1b8_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_b1b9_4)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_b1c0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b1c8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_b1d0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b1d8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_b1e0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_b1e8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b1f0_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_b1f8_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b1f9_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_b1fa_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_b1fb_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_b1fc_4)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +return 14; +} +unsigned long CPUFUNC(op_c000_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_c010_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_c018_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_c020_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_c028_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c030_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c038_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c039_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c03a_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c03b_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c03c_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_c040_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_c050_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_c058_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_c060_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_c068_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c070_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c078_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c079_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c07a_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_c07b_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_c07c_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_c080_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_c090_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_c098_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_c0a0_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_c0a8_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_c0b0_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_c0b8_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_c0b9_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_c0ba_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_c0bb_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_c0bc_4)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_c0c0_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 38; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}m68k_incpc(2); + return (38+retcycles*2); +} +unsigned long CPUFUNC(op_c0d0_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(2); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c0d8_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(2); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c0e0_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 44; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(2); + return (44+retcycles*2); +} +unsigned long CPUFUNC(op_c0e8_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0f0_4)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 48; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(4); + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c0f8_4)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0f9_4)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 50; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(6); + return (50+retcycles*2); +} +unsigned long CPUFUNC(op_c0fa_4)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0fb_4)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 48; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}m68k_incpc(4); + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c0fc_4)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}m68k_incpc(4); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c100_4)(uint32_t opcode) /* ABCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 14; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); + uint16_t newv, tmp_newv; + int cflg; + newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } + cflg = (newv & 0x3F0) > 0x90; + if (cflg) newv += 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_c108_4)(uint32_t opcode) /* ABCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 14; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); + uint16_t newv, tmp_newv; + int cflg; + newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } + cflg = (newv & 0x3F0) > 0x90; + if (cflg) newv += 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_c110_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_c118_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_c120_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_c128_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_c130_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_c138_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_c139_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_write_memory_8(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_c140_4)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + m68k_dreg(regs, srcreg) = (dst); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_c148_4)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); + m68k_areg(regs, srcreg) = (dst); + m68k_areg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_c150_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_c158_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_c160_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_c168_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_c170_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_c178_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_c179_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_write_memory_16(dsta,src); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_c188_4)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); + m68k_dreg(regs, srcreg) = (dst); + m68k_areg(regs, dstreg) = (src); +}}}m68k_incpc(2); +return 6; +} +unsigned long CPUFUNC(op_c190_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_c198_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_c1a0_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_c1a8_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_c1b0_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_c1b8_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_c1b9_4)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_write_memory_32(dsta,src); +}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_c1c0_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 38; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}m68k_incpc(2); + return (38+retcycles*2); +} +unsigned long CPUFUNC(op_c1d0_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(2); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c1d8_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(2); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c1e0_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 44; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(2); + return (44+retcycles*2); +} +unsigned long CPUFUNC(op_c1e8_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1f0_4)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 48; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(4); + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c1f8_4)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1f9_4)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 50; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(6); + return (50+retcycles*2); +} +unsigned long CPUFUNC(op_c1fa_4)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(4); + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1fb_4)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 48; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}m68k_incpc(4); + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c1fc_4)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}m68k_incpc(4); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_d000_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_d010_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d018_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d020_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_d028_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d030_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_d038_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d039_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_d03a_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d03b_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_d03c_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_d040_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_d048_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_d050_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d058_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d060_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(2); +return 10; +} +unsigned long CPUFUNC(op_d068_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d070_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_d078_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d079_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_d07a_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d07b_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}m68k_incpc(4); +return 14; +} +unsigned long CPUFUNC(op_d07c_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int16_t src = get_iword(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +return 8; +} +unsigned long CPUFUNC(op_d080_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d088_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d090_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d098_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d0a0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_d0a8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d0b0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_d0b8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d0b9_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_d0ba_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d0bb_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_d0bc_4)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_d0c0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d0c8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d0d0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d0d8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d0e0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d0e8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d0f0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d0f8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d0f9_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_d0fa_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d0fb_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d0fc_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ int16_t src = get_iword(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(4); +return 12; +} +unsigned long CPUFUNC(op_d100_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_d108_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_d110_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d118_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d120_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d128_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d130_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d138_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d139_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_8(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_d140_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}m68k_incpc(2); +return 4; +} +unsigned long CPUFUNC(op_d148_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; +{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 18; +} +unsigned long CPUFUNC(op_d150_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d158_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_d160_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; +{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d168_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d170_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d178_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_d179_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_16(dsta,newv); +}}}}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_d180_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d188_4)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 30; +} +unsigned long CPUFUNC(op_d190_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_d198_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 20; +} +unsigned long CPUFUNC(op_d1a0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; +{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(2); +return 22; +} +unsigned long CPUFUNC(op_d1a8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_d1b0_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 26; +} +unsigned long CPUFUNC(op_d1b8_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(4); +return 24; +} +unsigned long CPUFUNC(op_d1b9_4)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong(2); +{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_write_memory_32(dsta,newv); +}}}}}}}m68k_incpc(6); +return 28; +} +unsigned long CPUFUNC(op_d1c0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d1c8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +return 8; +} +unsigned long CPUFUNC(op_d1d0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +#endif + +#ifdef PART_8 +unsigned long CPUFUNC(op_d1d8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_d1e0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; +{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +return 16; +} +unsigned long CPUFUNC(op_d1e8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d1f0_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_d1f8_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d1f9_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(6); +return 22; +} +unsigned long CPUFUNC(op_d1fa_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword(2); +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_d1fb_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); + BusCyclePenalty += 2; +{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}m68k_incpc(4); +return 20; +} +unsigned long CPUFUNC(op_d1fc_4)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(6); +return 16; +} +unsigned long CPUFUNC(op_e000_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + uint32_t sign = (0x80 & val) >> 7; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + val = 0xff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xff << (8 - cnt)) & (uint32_t)-sign; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e008_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG ((cnt == 8) & (val >> 7)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e010_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (7 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e018_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 7; + hival = val << (8 - cnt); + val >>= cnt; + val |= hival; + val &= 0xff; + SET_CFLG ((val & 0x80) >> 7); + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e020_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + uint32_t sign = (0x80 & val) >> 7; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + val = 0xff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xff << (8 - cnt)) & (uint32_t)-sign; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e028_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG ((cnt == 8) & (val >> 7)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e030_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 36) cnt -= 36; + if (cnt >= 18) cnt -= 18; + if (cnt >= 9) cnt -= 9; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (7 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e038_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 7; + hival = val << (8 - cnt); + val >>= cnt; + val |= hival; + val &= 0xff; + SET_CFLG ((val & 0x80) >> 7); + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e040_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + uint32_t sign = (0x8000 & val) >> 15; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + val = 0xffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e048_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG ((cnt == 16) & (val >> 15)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e050_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (15 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e058_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 15; + hival = val << (16 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffff; + SET_CFLG ((val & 0x8000) >> 15); + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e060_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + uint32_t sign = (0x8000 & val) >> 15; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + val = 0xffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e068_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG ((cnt == 16) & (val >> 15)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e070_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 34) cnt -= 34; + if (cnt >= 17) cnt -= 17; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (15 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e078_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 15; + hival = val << (16 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffff; + SET_CFLG ((val & 0x8000) >> 15); + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e080_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + uint32_t sign = (0x80000000 & val) >> 31; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + val = 0xffffffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e088_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG ((cnt == 32) & (val >> 31)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e090_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (31 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e098_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 31; + hival = val << (32 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffffffff; + SET_CFLG ((val & 0x80000000) >> 31); + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0a0_4)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + uint32_t sign = (0x80000000 & val) >> 31; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + val = 0xffffffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0a8_4)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG ((cnt == 32) & (val >> 31)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0b0_4)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 33) cnt -= 33; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (31 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0b8_4)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 31; + hival = val << (32 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffffffff; + SET_CFLG ((val & 0x80000000) >> 31); + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0d0_4)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e0d8_4)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e0e0_4)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e0e8_4)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e0f0_4)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e0f8_4)(uint32_t opcode) /* ASRW */ +{ + OpcodeFamily = 72; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e0f9_4)(uint32_t opcode) /* ASRW */ +{ + OpcodeFamily = 72; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e100_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xff << (7 - cnt)) & 0xff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e108_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e110_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (7 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e118_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 7; + loval = val >> (8 - cnt); + val <<= cnt; + val |= loval; + val &= 0xff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e120_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xff << (7 - cnt)) & 0xff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e128_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e130_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 36) cnt -= 36; + if (cnt >= 18) cnt -= 18; + if (cnt >= 9) cnt -= 9; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (7 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e138_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 7; + loval = val >> (8 - cnt); + val <<= cnt; + val |= loval; + val &= 0xff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e140_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e148_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e150_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (15 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e158_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 15; + loval = val >> (16 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e160_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e168_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e170_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 34) cnt -= 34; + if (cnt >= 17) cnt -= 17; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (15 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e178_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 15; + loval = val >> (16 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e180_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e188_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e190_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (31 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e198_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 31; + loval = val >> (32 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffffffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1a0_4)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1a8_4)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1b0_4)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 33) cnt -= 33; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (31 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1b8_4)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 31; + loval = val >> (32 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffffffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1d0_4)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e1d8_4)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e1e0_4)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e1e8_4)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e1f0_4)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e1f8_4)(uint32_t opcode) /* ASLW */ +{ + OpcodeFamily = 73; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e1f9_4)(uint32_t opcode) /* ASLW */ +{ + OpcodeFamily = 73; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e2d0_4)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e2d8_4)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e2e0_4)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e2e8_4)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e2f0_4)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e2f8_4)(uint32_t opcode) /* LSRW */ +{ + OpcodeFamily = 74; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e2f9_4)(uint32_t opcode) /* LSRW */ +{ + OpcodeFamily = 74; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e3d0_4)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e3d8_4)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e3e0_4)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e3e8_4)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e3f0_4)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e3f8_4)(uint32_t opcode) /* LSLW */ +{ + OpcodeFamily = 75; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e3f9_4)(uint32_t opcode) /* LSLW */ +{ + OpcodeFamily = 75; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e4d0_4)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e4d8_4)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e4e0_4)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e4e8_4)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e4f0_4)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e4f8_4)(uint32_t opcode) /* ROXRW */ +{ + OpcodeFamily = 79; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e4f9_4)(uint32_t opcode) /* ROXRW */ +{ + OpcodeFamily = 79; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e5d0_4)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e5d8_4)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e5e0_4)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e5e8_4)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e5f0_4)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e5f8_4)(uint32_t opcode) /* ROXLW */ +{ + OpcodeFamily = 78; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e5f9_4)(uint32_t opcode) /* ROXLW */ +{ + OpcodeFamily = 78; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e6d0_4)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e6d8_4)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e6e0_4)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e6e8_4)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e6f0_4)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e6f8_4)(uint32_t opcode) /* RORW */ +{ + OpcodeFamily = 77; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e6f9_4)(uint32_t opcode) /* RORW */ +{ + OpcodeFamily = 77; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +unsigned long CPUFUNC(op_e7d0_4)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e7d8_4)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 12; +} +unsigned long CPUFUNC(op_e7e0_4)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; +{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(2); +return 14; +} +unsigned long CPUFUNC(op_e7e8_4)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e7f0_4)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); + BusCyclePenalty += 2; +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 18; +} +unsigned long CPUFUNC(op_e7f8_4)(uint32_t opcode) /* ROLW */ +{ + OpcodeFamily = 76; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(4); +return 16; +} +unsigned long CPUFUNC(op_e7f9_4)(uint32_t opcode) /* ROLW */ +{ + OpcodeFamily = 76; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong(2); +{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + m68k_write_memory_16(dataa,val); +}}}}m68k_incpc(6); +return 20; +} +#endif + + +#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8) +#define PART_1 1 +#define PART_2 1 +#define PART_3 1 +#define PART_4 1 +#define PART_5 1 +#define PART_6 1 +#define PART_7 1 +#define PART_8 1 +#endif + +#ifdef PART_1 +unsigned long CPUFUNC(op_0_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_10_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_18_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_20_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_28_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_30_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_38_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_39_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_3c_5)(uint32_t opcode) /* ORSR */ +{ + OpcodeFamily = 4; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + src &= 0xFF; + regs.sr |= src; + MakeFromSR(); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 20; +} +unsigned long CPUFUNC(op_40_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_50_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1591; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1591: ; +return 16; +} +unsigned long CPUFUNC(op_58_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1592; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1592: ; +return 16; +} +unsigned long CPUFUNC(op_60_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1593; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1593: ; +return 18; +} +unsigned long CPUFUNC(op_68_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1594; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1594: ; +return 20; +} +unsigned long CPUFUNC(op_70_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1595; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1595: ; +return 22; +} +unsigned long CPUFUNC(op_78_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1596; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1596: ; +return 20; +} +unsigned long CPUFUNC(op_79_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1597; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1597: ; +return 24; +} +unsigned long CPUFUNC(op_7c_5)(uint32_t opcode) /* ORSR */ +{ + OpcodeFamily = 4; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1598; } +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + regs.sr |= src; + MakeFromSR(); +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1598: ; +return 20; +} +unsigned long CPUFUNC(op_80_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_90_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1600; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1600: ; +return 28; +} +unsigned long CPUFUNC(op_98_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1601; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1601: ; +return 28; +} +unsigned long CPUFUNC(op_a0_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1602; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1602: ; +return 30; +} +unsigned long CPUFUNC(op_a8_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1603; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1603: ; +return 32; +} +unsigned long CPUFUNC(op_b0_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1604; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1604: ; +return 34; +} +unsigned long CPUFUNC(op_b8_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1605; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1605: ; +return 32; +} +unsigned long CPUFUNC(op_b9_5)(uint32_t opcode) /* OR */ +{ + OpcodeFamily = 1; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1606; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1606: ; +return 36; +} +unsigned long CPUFUNC(op_100_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_108_5)(uint32_t opcode) /* MVPMR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 29; CurrentInstrCycles = 16; +{ uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ uint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_110_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_118_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_120_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 10; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_128_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_130_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_138_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_139_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_13a_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_13b_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_13c_5)(uint32_t opcode) /* BTST */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 21; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = get_ibyte_prefetch(2); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_140_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_148_5)(uint32_t opcode) /* MVPMR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 29; CurrentInstrCycles = 24; +{ uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ uint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16) + + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6); + m68k_dreg(regs, dstreg) = (val); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 24; +} +unsigned long CPUFUNC(op_150_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_158_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_160_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 14; +} +unsigned long CPUFUNC(op_168_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_170_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_178_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_179_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_17a_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_17b_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_180_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 10; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_dreg(regs, dstreg) = (dst); + if ( src < 16 ) { m68k_incpc(2); return 8; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_188_5)(uint32_t opcode) /* MVPRM */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 28; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); + uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + m68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_190_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_198_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_1a0_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 14; +} +unsigned long CPUFUNC(op_1a8_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1b0_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_1b8_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1b9_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_1ba_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1bb_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_1c0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_1c8_5)(uint32_t opcode) /* MVPRM */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 28; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); + uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + m68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16); + m68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 24; +} +unsigned long CPUFUNC(op_1d0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_1d8_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_1e0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,dst); +}}}}return 14; +} +unsigned long CPUFUNC(op_1e8_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1f0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_1f8_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1f9_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_1fa_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 2; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_getpc () + 2; + dsta += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_1fb_5)(uint32_t opcode) /* BSET */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = 3; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_200_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_210_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_218_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_220_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_228_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_230_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_238_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_239_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_23c_5)(uint32_t opcode) /* ANDSR */ +{ + OpcodeFamily = 5; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + src |= 0xFF00; + regs.sr &= src; + MakeFromSR(); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 20; +} +unsigned long CPUFUNC(op_240_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_250_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1662; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1662: ; +return 16; +} +unsigned long CPUFUNC(op_258_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1663; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1663: ; +return 16; +} +unsigned long CPUFUNC(op_260_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1664; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1664: ; +return 18; +} +unsigned long CPUFUNC(op_268_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1665; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1665: ; +return 20; +} +unsigned long CPUFUNC(op_270_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1666; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1666: ; +return 22; +} +unsigned long CPUFUNC(op_278_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1667; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1667: ; +return 20; +} +unsigned long CPUFUNC(op_279_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1668; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1668: ; +return 24; +} +unsigned long CPUFUNC(op_27c_5)(uint32_t opcode) /* ANDSR */ +{ + OpcodeFamily = 5; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1669; } +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + regs.sr &= src; + MakeFromSR(); +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1669: ; +return 20; +} +unsigned long CPUFUNC(op_280_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_290_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1671; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1671: ; +return 28; +} +unsigned long CPUFUNC(op_298_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1672; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1672: ; +return 28; +} +unsigned long CPUFUNC(op_2a0_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1673; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1673: ; +return 30; +} +unsigned long CPUFUNC(op_2a8_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1674; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1674: ; +return 32; +} +unsigned long CPUFUNC(op_2b0_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1675; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1675: ; +return 34; +} +unsigned long CPUFUNC(op_2b8_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1676; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1676: ; +return 32; +} +unsigned long CPUFUNC(op_2b9_5)(uint32_t opcode) /* AND */ +{ + OpcodeFamily = 2; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1677; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1677: ; +return 36; +} +unsigned long CPUFUNC(op_400_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_410_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_418_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_420_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_428_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_430_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 22; +} +unsigned long CPUFUNC(op_438_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_439_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 24; +} +unsigned long CPUFUNC(op_440_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_450_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1687; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1687: ; +return 16; +} +unsigned long CPUFUNC(op_458_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1688; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1688: ; +return 16; +} +unsigned long CPUFUNC(op_460_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1689; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1689: ; +return 18; +} +unsigned long CPUFUNC(op_468_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1690; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1690: ; +return 20; +} +unsigned long CPUFUNC(op_470_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1691; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1691: ; +return 22; +} +unsigned long CPUFUNC(op_478_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1692; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1692: ; +return 20; +} +unsigned long CPUFUNC(op_479_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1693; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1693: ; +return 24; +} +unsigned long CPUFUNC(op_480_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_490_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1695; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1695: ; +return 28; +} +unsigned long CPUFUNC(op_498_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1696; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1696: ; +return 28; +} +unsigned long CPUFUNC(op_4a0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1697; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1697: ; +return 30; +} +unsigned long CPUFUNC(op_4a8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1698; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1698: ; +return 32; +} +unsigned long CPUFUNC(op_4b0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1699; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1699: ; +return 34; +} +unsigned long CPUFUNC(op_4b8_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1700; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1700: ; +return 32; +} +unsigned long CPUFUNC(op_4b9_5)(uint32_t opcode) /* SUB */ +{ + OpcodeFamily = 7; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1701; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1701: ; +return 36; +} +unsigned long CPUFUNC(op_600_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_610_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_618_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_620_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_628_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_630_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 22; +} +unsigned long CPUFUNC(op_638_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_639_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 24; +} +unsigned long CPUFUNC(op_640_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_650_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1711; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1711: ; +return 16; +} +unsigned long CPUFUNC(op_658_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1712; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1712: ; +return 16; +} +unsigned long CPUFUNC(op_660_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1713; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1713: ; +return 18; +} +unsigned long CPUFUNC(op_668_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1714; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1714: ; +return 20; +} +unsigned long CPUFUNC(op_670_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1715; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1715: ; +return 22; +} +unsigned long CPUFUNC(op_678_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1716; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1716: ; +return 20; +} +unsigned long CPUFUNC(op_679_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1717; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel1717: ; +return 24; +} +unsigned long CPUFUNC(op_680_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_690_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1719; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1719: ; +return 28; +} +unsigned long CPUFUNC(op_698_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1720; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1720: ; +return 28; +} +unsigned long CPUFUNC(op_6a0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1721; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1721: ; +return 30; +} +unsigned long CPUFUNC(op_6a8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1722; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1722: ; +return 32; +} +unsigned long CPUFUNC(op_6b0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1723; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1723: ; +return 34; +} +unsigned long CPUFUNC(op_6b8_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1724; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1724: ; +return 32; +} +unsigned long CPUFUNC(op_6b9_5)(uint32_t opcode) /* ADD */ +{ + OpcodeFamily = 11; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1725; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel1725: ; +return 36; +} +unsigned long CPUFUNC(op_800_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 10; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 10; +} +unsigned long CPUFUNC(op_810_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_818_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_820_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 14; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_828_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_830_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 21; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 18; +} +unsigned long CPUFUNC(op_838_5)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_839_5)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(8); +fill_prefetch_0 (); +return 20; +} +unsigned long CPUFUNC(op_83a_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 21; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_83b_5)(uint32_t opcode) /* BTST */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 21; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 18; +} +unsigned long CPUFUNC(op_83c_5)(uint32_t opcode) /* BTST */ +{ + OpcodeFamily = 21; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ int8_t dst = get_ibyte_prefetch(4); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_840_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_850_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_858_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_860_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_868_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_870_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 22; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_878_5)(uint32_t opcode) /* BCHG */ +{ + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_879_5)(uint32_t opcode) /* BCHG */ +{ + OpcodeFamily = 22; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 24; +} +unsigned long CPUFUNC(op_87a_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 22; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_87b_5)(uint32_t opcode) /* BCHG */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 22; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + dst ^= (1 << src); + SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_880_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 14; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); + m68k_dreg(regs, dstreg) = (dst); + if ( src < 16 ) { m68k_incpc(4); return 12; } +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_890_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_898_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_8a0_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_8a8_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8b0_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 23; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_8b8_5)(uint32_t opcode) /* BCLR */ +{ + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8b9_5)(uint32_t opcode) /* BCLR */ +{ + OpcodeFamily = 23; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 24; +} +unsigned long CPUFUNC(op_8ba_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 23; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8bb_5)(uint32_t opcode) /* BCLR */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 23; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst &= ~(1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_8c0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= 31; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); + m68k_dreg(regs, dstreg) = (dst); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_8d0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_8d8_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_8e0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_8e8_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8f0_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 24; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_8f8_5)(uint32_t opcode) /* BSET */ +{ + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8f9_5)(uint32_t opcode) /* BSET */ +{ + OpcodeFamily = 24; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 24; +} +unsigned long CPUFUNC(op_8fa_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 24; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_8fb_5)(uint32_t opcode) /* BSET */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 24; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= 7; + SET_ZFLG (1 ^ ((dst >> src) & 1)); + dst |= (1 << src); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,dst); +}}}}return 22; +} +unsigned long CPUFUNC(op_a00_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_a10_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_a18_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_a20_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_a28_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_a30_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_a38_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_a39_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_a3c_5)(uint32_t opcode) /* EORSR */ +{ + OpcodeFamily = 6; CurrentInstrCycles = 20; +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + src &= 0xFF; + regs.sr ^= src; + MakeFromSR(); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 20; +} +unsigned long CPUFUNC(op_a40_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_a50_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1777; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1777: ; +return 16; +} +unsigned long CPUFUNC(op_a58_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1778; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1778: ; +return 16; +} +unsigned long CPUFUNC(op_a60_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1779; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1779: ; +return 18; +} +unsigned long CPUFUNC(op_a68_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1780; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1780: ; +return 20; +} +unsigned long CPUFUNC(op_a70_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1781; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1781: ; +return 22; +} +unsigned long CPUFUNC(op_a78_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1782; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1782: ; +return 20; +} +unsigned long CPUFUNC(op_a79_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1783; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel1783: ; +return 24; +} +unsigned long CPUFUNC(op_a7c_5)(uint32_t opcode) /* EORSR */ +{ + OpcodeFamily = 6; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1784; } +{ MakeSR(); +{ int16_t src = get_iword_prefetch(2); + regs.sr ^= src; + MakeFromSR(); +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1784: ; +return 20; +} +#endif + +#ifdef PART_2 +unsigned long CPUFUNC(op_a80_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_a90_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1786; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1786: ; +return 28; +} +unsigned long CPUFUNC(op_a98_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1787; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1787: ; +return 28; +} +unsigned long CPUFUNC(op_aa0_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 30; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1788; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1788: ; +return 30; +} +unsigned long CPUFUNC(op_aa8_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1789; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1789: ; +return 32; +} +unsigned long CPUFUNC(op_ab0_5)(uint32_t opcode) /* EOR */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 34; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1790; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1790: ; +return 34; +} +unsigned long CPUFUNC(op_ab8_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 32; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1791; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1791: ; +return 32; +} +unsigned long CPUFUNC(op_ab9_5)(uint32_t opcode) /* EOR */ +{ + OpcodeFamily = 3; CurrentInstrCycles = 36; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1792; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel1792: ; +return 36; +} +unsigned long CPUFUNC(op_c00_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_c10_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_c18_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_c20_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_c28_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_c30_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 18; +} +unsigned long CPUFUNC(op_c38_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_c39_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +return 20; +} +unsigned long CPUFUNC(op_c3a_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_c3b_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 18; +} +unsigned long CPUFUNC(op_c40_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_c50_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1804; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1804: ; +return 12; +} +unsigned long CPUFUNC(op_c58_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1805; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1805: ; +return 12; +} +unsigned long CPUFUNC(op_c60_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1806; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1806: ; +return 14; +} +unsigned long CPUFUNC(op_c68_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1807; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1807: ; +return 16; +} +unsigned long CPUFUNC(op_c70_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1808; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1808: ; +return 18; +} +unsigned long CPUFUNC(op_c78_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1809; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1809: ; +return 16; +} +unsigned long CPUFUNC(op_c79_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1810; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1810: ; +return 20; +} +unsigned long CPUFUNC(op_c7a_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 4; + dsta += (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1811; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1811: ; +return 16; +} +unsigned long CPUFUNC(op_c7b_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1812; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1812: ; +return 18; +} +unsigned long CPUFUNC(op_c80_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_c90_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1814; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1814: ; +return 20; +} +unsigned long CPUFUNC(op_c98_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1815; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1815: ; +return 20; +} +unsigned long CPUFUNC(op_ca0_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 22; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1816; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1816: ; +return 22; +} +unsigned long CPUFUNC(op_ca8_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1817; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1817: ; +return 24; +} +unsigned long CPUFUNC(op_cb0_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = opcode & 7; + OpcodeFamily = 25; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1818; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1818: ; +return 26; +} +unsigned long CPUFUNC(op_cb8_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1819; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1819: ; +return 24; +} +unsigned long CPUFUNC(op_cb9_5)(uint32_t opcode) /* CMP */ +{ + OpcodeFamily = 25; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1820; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(10); +fill_prefetch_0 (); +endlabel1820: ; +return 28; +} +unsigned long CPUFUNC(op_cba_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 2; + OpcodeFamily = 25; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_getpc () + 6; + dsta += (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1821; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1821: ; +return 24; +} +unsigned long CPUFUNC(op_cbb_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = 3; + OpcodeFamily = 25; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t tmppc = m68k_getpc() + 6; + uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1822; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel1822: ; +return 26; +} +unsigned long CPUFUNC(op_1000_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_1008_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int8_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_1010_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_1018_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_1020_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_1028_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_1030_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_1038_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_1039_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_103a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_103b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_103c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_1080_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_1088_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_1090_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_1098_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_10a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_10a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_10b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_10ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_10bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_10c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_10c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_10d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_10d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_10e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_10e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_10f8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10f9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_10fa_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_10fb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_10fc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_1100_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_1108_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}return 8; +} +unsigned long CPUFUNC(op_1110_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_1118_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_1120_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_1128_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_1130_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_1138_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_1139_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_113a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_113b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_113c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; + m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_1140_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_1148_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_1150_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_1158_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_1160_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_1168_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_1170_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_1178_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_1179_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_117a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_117b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_117c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 16; +} +unsigned long CPUFUNC(op_1180_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 14; +} +unsigned long CPUFUNC(op_1188_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 14; +} +unsigned long CPUFUNC(op_1190_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_1198_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_11a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_11a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_11b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_11b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_11b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 26; +} +unsigned long CPUFUNC(op_11ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_11bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_11bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 18; +} +unsigned long CPUFUNC(op_11c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_11c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 12; +} +unsigned long CPUFUNC(op_11d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_11d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_11e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_11e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_11f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_11f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_11f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_11fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_11fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_11fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 16; +} +unsigned long CPUFUNC(op_13c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 16; +} +unsigned long CPUFUNC(op_13c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int8_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 16; +} +unsigned long CPUFUNC(op_13d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_13d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_13e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 22; +} +unsigned long CPUFUNC(op_13e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_13f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 26; +} +unsigned long CPUFUNC(op_13f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_13f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(6); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 28; +} +unsigned long CPUFUNC(op_13fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 24; +} +unsigned long CPUFUNC(op_13fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 26; +} +unsigned long CPUFUNC(op_13fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int8_t src = get_ibyte_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}return 20; +} +unsigned long CPUFUNC(op_2000_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_2008_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_2010_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1921; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1921: ; +return 12; +} +unsigned long CPUFUNC(op_2018_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1922; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1922: ; +return 12; +} +unsigned long CPUFUNC(op_2020_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1923; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1923: ; +return 14; +} +unsigned long CPUFUNC(op_2028_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1924; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1924: ; +return 16; +} +unsigned long CPUFUNC(op_2030_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1925; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1925: ; +return 18; +} +unsigned long CPUFUNC(op_2038_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1926; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1926: ; +return 16; +} +unsigned long CPUFUNC(op_2039_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1927; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1927: ; +return 20; +} +unsigned long CPUFUNC(op_203a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1928; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1928: ; +return 16; +} +unsigned long CPUFUNC(op_203b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1929; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1929: ; +return 18; +} +unsigned long CPUFUNC(op_203c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong_prefetch(2); +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_2040_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_2048_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_2050_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1933; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1933: ; +return 12; +} +unsigned long CPUFUNC(op_2058_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1934; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1934: ; +return 12; +} +unsigned long CPUFUNC(op_2060_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1935; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel1935: ; +return 14; +} +unsigned long CPUFUNC(op_2068_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1936; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1936: ; +return 16; +} +unsigned long CPUFUNC(op_2070_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1937; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1937: ; +return 18; +} +unsigned long CPUFUNC(op_2078_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1938; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1938: ; +return 16; +} +unsigned long CPUFUNC(op_2079_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1939; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel1939: ; +return 20; +} +unsigned long CPUFUNC(op_207a_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1940; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1940: ; +return 16; +} +unsigned long CPUFUNC(op_207b_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1941; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel1941: ; +return 18; +} +unsigned long CPUFUNC(op_207c_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t val = src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_2080_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1943; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1943: ; +return 12; +} +unsigned long CPUFUNC(op_2088_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1944; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1944: ; +return 12; +} +unsigned long CPUFUNC(op_2090_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1945; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1945; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1945: ; +return 20; +} +unsigned long CPUFUNC(op_2098_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1946; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1946; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1946: ; +return 20; +} +unsigned long CPUFUNC(op_20a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1947; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1947; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1947: ; +return 22; +} +unsigned long CPUFUNC(op_20a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1948; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1948; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1948: ; +return 24; +} +unsigned long CPUFUNC(op_20b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1949; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1949; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1949: ; +return 26; +} +unsigned long CPUFUNC(op_20b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1950; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1950; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1950: ; +return 24; +} +unsigned long CPUFUNC(op_20b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1951; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1951; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1951: ; +return 28; +} +unsigned long CPUFUNC(op_20ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1952; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1952; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1952: ; +return 24; +} +unsigned long CPUFUNC(op_20bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1953; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1953; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1953: ; +return 26; +} +unsigned long CPUFUNC(op_20bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1954; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1954: ; +return 20; +} +unsigned long CPUFUNC(op_20c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1955; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1955: ; +return 12; +} +unsigned long CPUFUNC(op_20c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1956; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1956: ; +return 12; +} +unsigned long CPUFUNC(op_20d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1957; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1957; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1957: ; +return 20; +} +unsigned long CPUFUNC(op_20d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1958; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1958; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1958: ; +return 20; +} +unsigned long CPUFUNC(op_20e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1959; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1959; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1959: ; +return 22; +} +unsigned long CPUFUNC(op_20e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1960; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1960; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1960: ; +return 24; +} +unsigned long CPUFUNC(op_20f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1961; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1961; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1961: ; +return 26; +} +unsigned long CPUFUNC(op_20f8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1962; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1962; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1962: ; +return 24; +} +unsigned long CPUFUNC(op_20f9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1963; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1963; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1963: ; +return 28; +} +unsigned long CPUFUNC(op_20fa_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1964; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1964; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1964: ; +return 24; +} +unsigned long CPUFUNC(op_20fb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1965; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1965; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1965: ; +return 26; +} +unsigned long CPUFUNC(op_20fc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1966; + } +{ m68k_areg(regs, dstreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1966: ; +return 20; +} +unsigned long CPUFUNC(op_2100_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1967; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1967: ; +return 12; +} +unsigned long CPUFUNC(op_2108_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1968; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1968: ; +return 12; +} +unsigned long CPUFUNC(op_2110_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1969; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1969; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1969: ; +return 20; +} +unsigned long CPUFUNC(op_2118_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1970; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1970; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1970: ; +return 20; +} +unsigned long CPUFUNC(op_2120_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1971; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1971; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1971: ; +return 22; +} +unsigned long CPUFUNC(op_2128_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1972; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1972; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1972: ; +return 24; +} +unsigned long CPUFUNC(op_2130_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1973; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1973; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1973: ; +return 26; +} +unsigned long CPUFUNC(op_2138_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1974; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1974; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1974: ; +return 24; +} +#endif + +#ifdef PART_3 +unsigned long CPUFUNC(op_2139_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1975; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1975; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1975: ; +return 28; +} +unsigned long CPUFUNC(op_213a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1976; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1976; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1976: ; +return 24; +} +unsigned long CPUFUNC(op_213b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1977; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1977; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1977: ; +return 26; +} +unsigned long CPUFUNC(op_213c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1978; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1978: ; +return 20; +} +unsigned long CPUFUNC(op_2140_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1979; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1979: ; +return 16; +} +unsigned long CPUFUNC(op_2148_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1980; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1980: ; +return 16; +} +unsigned long CPUFUNC(op_2150_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1981; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1981; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1981: ; +return 24; +} +unsigned long CPUFUNC(op_2158_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1982; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1982; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1982: ; +return 24; +} +unsigned long CPUFUNC(op_2160_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1983; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1983; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1983: ; +return 26; +} +unsigned long CPUFUNC(op_2168_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1984; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1984; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1984: ; +return 28; +} +unsigned long CPUFUNC(op_2170_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1985; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1985; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1985: ; +return 30; +} +unsigned long CPUFUNC(op_2178_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1986; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1986; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1986: ; +return 28; +} +unsigned long CPUFUNC(op_2179_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1987; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1987; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1987: ; +return 32; +} +unsigned long CPUFUNC(op_217a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1988; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1988; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1988: ; +return 28; +} +unsigned long CPUFUNC(op_217b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1989; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1989; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1989: ; +return 30; +} +unsigned long CPUFUNC(op_217c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1990; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1990: ; +return 24; +} +unsigned long CPUFUNC(op_2180_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1991; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1991: ; +return 18; +} +unsigned long CPUFUNC(op_2188_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1992; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel1992: ; +return 18; +} +unsigned long CPUFUNC(op_2190_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1993; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1993; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1993: ; +return 26; +} +unsigned long CPUFUNC(op_2198_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1994; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1994; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1994: ; +return 26; +} +unsigned long CPUFUNC(op_21a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1995; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1995; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1995: ; +return 28; +} +unsigned long CPUFUNC(op_21a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1996; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1996; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1996: ; +return 30; +} +unsigned long CPUFUNC(op_21b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1997; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1997; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1997: ; +return 32; +} +unsigned long CPUFUNC(op_21b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1998; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1998; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1998: ; +return 30; +} +unsigned long CPUFUNC(op_21b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1999; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel1999; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel1999: ; +return 34; +} +unsigned long CPUFUNC(op_21ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2000; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2000; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2000: ; +return 30; +} +unsigned long CPUFUNC(op_21bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2001; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2001; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2001: ; +return 32; +} +unsigned long CPUFUNC(op_21bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2002; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2002: ; +return 26; +} +unsigned long CPUFUNC(op_21c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2003; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2003: ; +return 16; +} +unsigned long CPUFUNC(op_21c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2004; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2004: ; +return 16; +} +unsigned long CPUFUNC(op_21d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2005; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2005; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2005: ; +return 24; +} +unsigned long CPUFUNC(op_21d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2006; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2006; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2006: ; +return 24; +} +unsigned long CPUFUNC(op_21e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2007; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2007; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2007: ; +return 26; +} +unsigned long CPUFUNC(op_21e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2008; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2008; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2008: ; +return 28; +} +unsigned long CPUFUNC(op_21f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2009; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2009; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2009: ; +return 30; +} +unsigned long CPUFUNC(op_21f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2010; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2010; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2010: ; +return 28; +} +unsigned long CPUFUNC(op_21f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2011; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2011; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2011: ; +return 32; +} +unsigned long CPUFUNC(op_21fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2012; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2012; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2012: ; +return 28; +} +unsigned long CPUFUNC(op_21fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2013; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2013; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2013: ; +return 30; +} +unsigned long CPUFUNC(op_21fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2014; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2014: ; +return 24; +} +unsigned long CPUFUNC(op_23c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2015; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2015: ; +return 20; +} +unsigned long CPUFUNC(op_23c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int32_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2016; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2016: ; +return 20; +} +unsigned long CPUFUNC(op_23d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2017; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2017; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2017: ; +return 28; +} +unsigned long CPUFUNC(op_23d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2018; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2018; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2018: ; +return 28; +} +unsigned long CPUFUNC(op_23e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2019; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2019; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2019: ; +return 30; +} +unsigned long CPUFUNC(op_23e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2020; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2020; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2020: ; +return 32; +} +unsigned long CPUFUNC(op_23f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2021; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2021; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2021: ; +return 34; +} +unsigned long CPUFUNC(op_23f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2022; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2022; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2022: ; +return 32; +} +unsigned long CPUFUNC(op_23f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 36; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2023; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2023; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2023: ; +return 36; +} +unsigned long CPUFUNC(op_23fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 32; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2024; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2024; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2024: ; +return 32; +} +unsigned long CPUFUNC(op_23fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 34; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2025; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2025; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}}endlabel2025: ; +return 34; +} +unsigned long CPUFUNC(op_23fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ int32_t src = get_ilong_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2026; + } +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}endlabel2026: ; +return 28; +} +unsigned long CPUFUNC(op_3000_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_3008_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_3010_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2029; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2029: ; +return 8; +} +unsigned long CPUFUNC(op_3018_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2030; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2030: ; +return 8; +} +unsigned long CPUFUNC(op_3020_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2031; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2031: ; +return 10; +} +unsigned long CPUFUNC(op_3028_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2032; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2032: ; +return 12; +} +unsigned long CPUFUNC(op_3030_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2033; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2033: ; +return 14; +} +unsigned long CPUFUNC(op_3038_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2034; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2034: ; +return 12; +} +unsigned long CPUFUNC(op_3039_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2035; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2035: ; +return 16; +} +unsigned long CPUFUNC(op_303a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2036; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2036: ; +return 12; +} +unsigned long CPUFUNC(op_303b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2037; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2037: ; +return 14; +} +unsigned long CPUFUNC(op_303c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_3040_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_3048_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_3050_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2041; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2041: ; +return 8; +} +unsigned long CPUFUNC(op_3058_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2042; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2042: ; +return 8; +} +unsigned long CPUFUNC(op_3060_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2043; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2043: ; +return 10; +} +unsigned long CPUFUNC(op_3068_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2044; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2044: ; +return 12; +} +unsigned long CPUFUNC(op_3070_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2045; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2045: ; +return 14; +} +unsigned long CPUFUNC(op_3078_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2046; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2046: ; +return 12; +} +unsigned long CPUFUNC(op_3079_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2047; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2047: ; +return 16; +} +unsigned long CPUFUNC(op_307a_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2048; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2048: ; +return 12; +} +unsigned long CPUFUNC(op_307b_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2049; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2049: ; +return 14; +} +unsigned long CPUFUNC(op_307c_5)(uint32_t opcode) /* MOVEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 31; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t val = (int32_t)(int16_t)src; + m68k_areg(regs, dstreg) = (val); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_3080_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2051; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2051: ; +return 8; +} +unsigned long CPUFUNC(op_3088_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2052; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2052: ; +return 8; +} +unsigned long CPUFUNC(op_3090_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2053; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2053; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2053: ; +return 12; +} +unsigned long CPUFUNC(op_3098_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2054; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2054; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2054: ; +return 12; +} +unsigned long CPUFUNC(op_30a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2055; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2055; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2055: ; +return 14; +} +unsigned long CPUFUNC(op_30a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2056; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2056; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2056: ; +return 16; +} +unsigned long CPUFUNC(op_30b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2057; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2057; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2057: ; +return 18; +} +unsigned long CPUFUNC(op_30b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2058; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2058; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2058: ; +return 16; +} +unsigned long CPUFUNC(op_30b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2059; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2059; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2059: ; +return 20; +} +unsigned long CPUFUNC(op_30ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2060; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2060; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2060: ; +return 16; +} +unsigned long CPUFUNC(op_30bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2061; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2061; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2061: ; +return 18; +} +unsigned long CPUFUNC(op_30bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2062; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2062: ; +return 12; +} +unsigned long CPUFUNC(op_30c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2063; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2063: ; +return 8; +} +unsigned long CPUFUNC(op_30c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2064; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2064: ; +return 8; +} +unsigned long CPUFUNC(op_30d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2065; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2065; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2065: ; +return 12; +} +unsigned long CPUFUNC(op_30d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2066; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2066; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2066: ; +return 12; +} +unsigned long CPUFUNC(op_30e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2067; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2067; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2067: ; +return 14; +} +unsigned long CPUFUNC(op_30e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2068; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2068; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2068: ; +return 16; +} +unsigned long CPUFUNC(op_30f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2069; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2069; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2069: ; +return 18; +} +unsigned long CPUFUNC(op_30f8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2070; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2070; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2070: ; +return 16; +} +unsigned long CPUFUNC(op_30f9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2071; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2071; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2071: ; +return 20; +} +unsigned long CPUFUNC(op_30fa_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2072; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2072; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2072: ; +return 16; +} +unsigned long CPUFUNC(op_30fb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2073; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2073; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2073: ; +return 18; +} +unsigned long CPUFUNC(op_30fc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2074; + } +{ m68k_areg(regs, dstreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2074: ; +return 12; +} +unsigned long CPUFUNC(op_3100_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2075; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2075: ; +return 8; +} +unsigned long CPUFUNC(op_3108_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2076; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2076: ; +return 8; +} +unsigned long CPUFUNC(op_3110_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2077; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2077; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2077: ; +return 12; +} +unsigned long CPUFUNC(op_3118_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2078; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2078; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2078: ; +return 12; +} +unsigned long CPUFUNC(op_3120_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2079; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2079; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2079: ; +return 14; +} +unsigned long CPUFUNC(op_3128_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2080; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2080; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2080: ; +return 16; +} +unsigned long CPUFUNC(op_3130_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2081; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2081; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2081: ; +return 18; +} +unsigned long CPUFUNC(op_3138_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2082; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2082; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2082: ; +return 16; +} +unsigned long CPUFUNC(op_3139_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2083; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2083; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2083: ; +return 20; +} +unsigned long CPUFUNC(op_313a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2084; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2084; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2084: ; +return 16; +} +unsigned long CPUFUNC(op_313b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2085; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2085; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2085: ; +return 18; +} +unsigned long CPUFUNC(op_313c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2086; + } +{ m68k_areg (regs, dstreg) = dsta; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2086: ; +return 12; +} +unsigned long CPUFUNC(op_3140_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2087; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2087: ; +return 12; +} +unsigned long CPUFUNC(op_3148_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2088; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2088: ; +return 12; +} +unsigned long CPUFUNC(op_3150_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2089; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2089; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2089: ; +return 16; +} +unsigned long CPUFUNC(op_3158_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2090; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2090; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2090: ; +return 16; +} +unsigned long CPUFUNC(op_3160_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2091; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2091; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2091: ; +return 18; +} +unsigned long CPUFUNC(op_3168_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2092; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2092; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2092: ; +return 20; +} +unsigned long CPUFUNC(op_3170_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2093; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2093; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2093: ; +return 22; +} +unsigned long CPUFUNC(op_3178_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2094; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2094; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2094: ; +return 20; +} +unsigned long CPUFUNC(op_3179_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2095; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2095; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2095: ; +return 24; +} +unsigned long CPUFUNC(op_317a_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2096; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2096; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2096: ; +return 20; +} +unsigned long CPUFUNC(op_317b_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2097; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2097; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2097: ; +return 22; +} +unsigned long CPUFUNC(op_317c_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2098; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2098: ; +return 16; +} +unsigned long CPUFUNC(op_3180_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2099; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2099: ; +return 14; +} +unsigned long CPUFUNC(op_3188_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 14; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2100; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2100: ; +return 14; +} +unsigned long CPUFUNC(op_3190_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2101; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2101; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2101: ; +return 18; +} +unsigned long CPUFUNC(op_3198_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2102; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2102; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2102: ; +return 18; +} +unsigned long CPUFUNC(op_31a0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2103; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2103; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2103: ; +return 20; +} +unsigned long CPUFUNC(op_31a8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2104; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2104; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2104: ; +return 22; +} +unsigned long CPUFUNC(op_31b0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2105; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2105; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2105: ; +return 24; +} +unsigned long CPUFUNC(op_31b8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2106; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2106; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2106: ; +return 22; +} +unsigned long CPUFUNC(op_31b9_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2107; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2107; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2107: ; +return 26; +} +unsigned long CPUFUNC(op_31ba_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2108; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2108; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2108: ; +return 22; +} +unsigned long CPUFUNC(op_31bb_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2109; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2109; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2109: ; +return 24; +} +unsigned long CPUFUNC(op_31bc_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2110; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2110: ; +return 18; +} +unsigned long CPUFUNC(op_31c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2111; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2111: ; +return 12; +} +unsigned long CPUFUNC(op_31c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 12; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2112; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2112: ; +return 12; +} +unsigned long CPUFUNC(op_31d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2113; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2113; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2113: ; +return 16; +} +unsigned long CPUFUNC(op_31d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2114; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2114; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2114: ; +return 16; +} +unsigned long CPUFUNC(op_31e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2115; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2115; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2115: ; +return 18; +} +unsigned long CPUFUNC(op_31e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2116; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2116; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2116: ; +return 20; +} +unsigned long CPUFUNC(op_31f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2117; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2117; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2117: ; +return 22; +} +unsigned long CPUFUNC(op_31f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2118; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2118; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2118: ; +return 20; +} +unsigned long CPUFUNC(op_31f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2119; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2119; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2119: ; +return 24; +} +unsigned long CPUFUNC(op_31fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2120; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2120; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2120: ; +return 20; +} +unsigned long CPUFUNC(op_31fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2121; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2121; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2121: ; +return 22; +} +unsigned long CPUFUNC(op_31fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2122; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2122: ; +return 16; +} +unsigned long CPUFUNC(op_33c0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2123; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2123: ; +return 16; +} +unsigned long CPUFUNC(op_33c8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 16; +{{ int16_t src = m68k_areg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2124; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2124: ; +return 16; +} +unsigned long CPUFUNC(op_33d0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2125; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2125; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2125: ; +return 20; +} +unsigned long CPUFUNC(op_33d8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2126; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2126; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2126: ; +return 20; +} +unsigned long CPUFUNC(op_33e0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2127; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2127; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2127: ; +return 22; +} +unsigned long CPUFUNC(op_33e8_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2128; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2128; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2128: ; +return 24; +} +unsigned long CPUFUNC(op_33f0_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2129; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2129; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2129: ; +return 26; +} +unsigned long CPUFUNC(op_33f8_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2130; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2130; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2130: ; +return 24; +} +unsigned long CPUFUNC(op_33f9_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2131; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(6); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 10; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2131; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(10); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2131: ; +return 28; +} +unsigned long CPUFUNC(op_33fa_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2132; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2132; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2132: ; +return 24; +} +unsigned long CPUFUNC(op_33fb_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 26; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2133; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2133; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}}endlabel2133: ; +return 26; +} +unsigned long CPUFUNC(op_33fc_5)(uint32_t opcode) /* MOVE */ +{ + OpcodeFamily = 30; CurrentInstrCycles = 20; +{{ int16_t src = get_iword_prefetch(2); +{ uint32_t dsta = get_ilong_prefetch(4); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2134; + } +{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(8); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}endlabel2134: ; +return 20; +} +unsigned long CPUFUNC(op_4000_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4010_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}}return 12; +} +unsigned long CPUFUNC(op_4018_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}}return 12; +} +unsigned long CPUFUNC(op_4020_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}}return 14; +} +unsigned long CPUFUNC(op_4028_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}}return 16; +} +unsigned long CPUFUNC(op_4030_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}}return 18; +} +unsigned long CPUFUNC(op_4038_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}}return 16; +} +unsigned long CPUFUNC(op_4039_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}}return 20; +} +unsigned long CPUFUNC(op_4040_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4050_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2144; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2144: ; +return 12; +} +unsigned long CPUFUNC(op_4058_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2145; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2145: ; +return 12; +} +unsigned long CPUFUNC(op_4060_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2146; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2146: ; +return 14; +} +unsigned long CPUFUNC(op_4068_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2147; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2147: ; +return 16; +} +unsigned long CPUFUNC(op_4070_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2148; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2148: ; +return 18; +} +unsigned long CPUFUNC(op_4078_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2149; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2149: ; +return 16; +} +unsigned long CPUFUNC(op_4079_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2150; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(srca,newv); +}}}}}}endlabel2150: ; +return 20; +} +unsigned long CPUFUNC(op_4080_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_4090_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2152; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2152: ; +return 20; +} +unsigned long CPUFUNC(op_4098_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2153; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2153: ; +return 20; +} +unsigned long CPUFUNC(op_40a0_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2154; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2154: ; +return 22; +} +unsigned long CPUFUNC(op_40a8_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2155; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2155: ; +return 24; +} +unsigned long CPUFUNC(op_40b0_5)(uint32_t opcode) /* NEGX */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 16; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2156; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2156: ; +return 26; +} +unsigned long CPUFUNC(op_40b8_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2157; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2157: ; +return 24; +} +unsigned long CPUFUNC(op_40b9_5)(uint32_t opcode) /* NEGX */ +{ + OpcodeFamily = 16; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2158; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(srca,newv); +}}}}}}endlabel2158: ; +return 28; +} +unsigned long CPUFUNC(op_40c0_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 6; +{{ MakeSR(); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_40d0_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2160; + } +{ MakeSR(); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2160: ; +return 12; +} +unsigned long CPUFUNC(op_40d8_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2161; + } +{ m68k_areg(regs, srcreg) += 2; + MakeSR(); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2161: ; +return 12; +} +unsigned long CPUFUNC(op_40e0_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2162; + } +{ m68k_areg (regs, srcreg) = srca; + MakeSR(); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2162: ; +return 14; +} +unsigned long CPUFUNC(op_40e8_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2163; + } +{ MakeSR(); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2163: ; +return 16; +} +unsigned long CPUFUNC(op_40f0_5)(uint32_t opcode) /* MVSR2 */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 32; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2164; + } +{ MakeSR(); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2164: ; +return 18; +} +unsigned long CPUFUNC(op_40f8_5)(uint32_t opcode) /* MVSR2 */ +{ + OpcodeFamily = 32; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2165; + } +{ MakeSR(); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2165: ; +return 16; +} +unsigned long CPUFUNC(op_40f9_5)(uint32_t opcode) /* MVSR2 */ +{ + OpcodeFamily = 32; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2166; + } +{ MakeSR(); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(srca,regs.sr); +}}}endlabel2166: ; +return 20; +} +unsigned long CPUFUNC(op_4180_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2167; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2167; } +}}}endlabel2167: ; +return 10; +} +unsigned long CPUFUNC(op_4190_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2168; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2168; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2168; } +}}}}}endlabel2168: ; +return 14; +} +unsigned long CPUFUNC(op_4198_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2169; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2169; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2169; } +}}}}}endlabel2169: ; +return 14; +} +unsigned long CPUFUNC(op_41a0_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2170; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2170; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2170; } +}}}}}endlabel2170: ; +return 16; +} +unsigned long CPUFUNC(op_41a8_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2171; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2171; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2171; } +}}}}}endlabel2171: ; +return 18; +} +unsigned long CPUFUNC(op_41b0_5)(uint32_t opcode) /* CHK */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 20; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2172; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2172; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2172; } +}}}}}endlabel2172: ; +return 20; +} +unsigned long CPUFUNC(op_41b8_5)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2173; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2173; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2173; } +}}}}}endlabel2173: ; +return 18; +} +unsigned long CPUFUNC(op_41b9_5)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 22; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2174; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2174; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2174; } +}}}}}endlabel2174: ; +return 22; +} +unsigned long CPUFUNC(op_41ba_5)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 18; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2175; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2175; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2175; } +}}}}}endlabel2175: ; +return 18; +} +unsigned long CPUFUNC(op_41bb_5)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 20; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2176; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2176; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2176; } +}}}}}endlabel2176: ; +return 20; +} +unsigned long CPUFUNC(op_41bc_5)(uint32_t opcode) /* CHK */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 80; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2177; } + else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2177; } +}}}endlabel2177: ; +return 14; +} +unsigned long CPUFUNC(op_41d0_5)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 4; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_41e8_5)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_41f0_5)(uint32_t opcode) /* LEA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_41f8_5)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_41f9_5)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 12; +{{ uint32_t srca = get_ilong_prefetch(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_41fa_5)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_41fb_5)(uint32_t opcode) /* LEA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 56; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ m68k_areg(regs, dstreg) = (srca); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_4200_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 4; +{{ CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4210_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,0); +}}return 12; +} +unsigned long CPUFUNC(op_4218_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,0); +}}return 12; +} +unsigned long CPUFUNC(op_4220_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,0); +}}return 14; +} +unsigned long CPUFUNC(op_4228_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,0); +}}return 16; +} +unsigned long CPUFUNC(op_4230_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,0); +}}return 18; +} +unsigned long CPUFUNC(op_4238_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,0); +}}return 16; +} +unsigned long CPUFUNC(op_4239_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(0)) == 0); + SET_NFLG (((int8_t)(0)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,0); +}}return 20; +} +unsigned long CPUFUNC(op_4240_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 4; +{{ CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4250_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2194; + } +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,0); +}}}endlabel2194: ; +return 12; +} +unsigned long CPUFUNC(op_4258_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2195; + } +{ m68k_areg(regs, srcreg) += 2; + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,0); +}}}endlabel2195: ; +return 12; +} +unsigned long CPUFUNC(op_4260_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2196; + } +{ m68k_areg (regs, srcreg) = srca; + int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,0); +}}}endlabel2196: ; +return 14; +} +unsigned long CPUFUNC(op_4268_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2197; + } +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,0); +}}}endlabel2197: ; +return 16; +} +#endif + +#ifdef PART_4 +unsigned long CPUFUNC(op_4270_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2198; + } +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,0); +}}}endlabel2198: ; +return 18; +} +unsigned long CPUFUNC(op_4278_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2199; + } +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,0); +}}}endlabel2199: ; +return 16; +} +unsigned long CPUFUNC(op_4279_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2200; + } +{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(0)) == 0); + SET_NFLG (((int16_t)(0)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(srca,0); +}}}endlabel2200: ; +return 20; +} +unsigned long CPUFUNC(op_4280_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 6; +{{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); + m68k_dreg(regs, srcreg) = (0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_4290_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2202; + } +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,0); +}}}endlabel2202: ; +return 20; +} +unsigned long CPUFUNC(op_4298_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2203; + } +{ m68k_areg(regs, srcreg) += 4; + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,0); +}}}endlabel2203: ; +return 20; +} +unsigned long CPUFUNC(op_42a0_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2204; + } +{ m68k_areg (regs, srcreg) = srca; + int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,0); +}}}endlabel2204: ; +return 22; +} +unsigned long CPUFUNC(op_42a8_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2205; + } +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,0); +}}}endlabel2205: ; +return 24; +} +unsigned long CPUFUNC(op_42b0_5)(uint32_t opcode) /* CLR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 18; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2206; + } +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,0); +}}}endlabel2206: ; +return 26; +} +unsigned long CPUFUNC(op_42b8_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2207; + } +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,0); +}}}endlabel2207: ; +return 24; +} +unsigned long CPUFUNC(op_42b9_5)(uint32_t opcode) /* CLR */ +{ + OpcodeFamily = 18; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2208; + } +{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(0)) == 0); + SET_NFLG (((int32_t)(0)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(srca,0); +}}}endlabel2208: ; +return 28; +} +unsigned long CPUFUNC(op_4400_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4410_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 12; +} +unsigned long CPUFUNC(op_4418_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 12; +} +unsigned long CPUFUNC(op_4420_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 14; +} +unsigned long CPUFUNC(op_4428_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 16; +} +unsigned long CPUFUNC(op_4430_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 18; +} +unsigned long CPUFUNC(op_4438_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 16; +} +unsigned long CPUFUNC(op_4439_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(0)) < 0; + int flgn = ((int8_t)(dst)) < 0; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}}}return 20; +} +unsigned long CPUFUNC(op_4440_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4450_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2218; + } +{{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2218: ; +return 12; +} +unsigned long CPUFUNC(op_4458_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2219; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2219: ; +return 12; +} +unsigned long CPUFUNC(op_4460_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2220; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2220: ; +return 14; +} +unsigned long CPUFUNC(op_4468_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2221; + } +{{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2221: ; +return 16; +} +unsigned long CPUFUNC(op_4470_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2222; + } +{{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2222: ; +return 18; +} +unsigned long CPUFUNC(op_4478_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2223; + } +{{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2223: ; +return 16; +} +unsigned long CPUFUNC(op_4479_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2224; + } +{{ int16_t src = m68k_read_memory_16(srca); +{{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(0)) < 0; + int flgn = ((int16_t)(dst)) < 0; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}}}endlabel2224: ; +return 20; +} +unsigned long CPUFUNC(op_4480_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, srcreg) = (dst); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_4490_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2226; + } +{{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2226: ; +return 20; +} +unsigned long CPUFUNC(op_4498_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2227; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2227: ; +return 20; +} +unsigned long CPUFUNC(op_44a0_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2228; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2228: ; +return 22; +} +unsigned long CPUFUNC(op_44a8_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2229; + } +{{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2229: ; +return 24; +} +unsigned long CPUFUNC(op_44b0_5)(uint32_t opcode) /* NEG */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 15; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2230; + } +{{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2230: ; +return 26; +} +unsigned long CPUFUNC(op_44b8_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2231; + } +{{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2231: ; +return 24; +} +unsigned long CPUFUNC(op_44b9_5)(uint32_t opcode) /* NEG */ +{ + OpcodeFamily = 15; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2232; + } +{{ int32_t src = m68k_read_memory_32(srca); +{{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(0)) < 0; + int flgn = ((int32_t)(dst)) < 0; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}}}endlabel2232: ; +return 28; +} +unsigned long CPUFUNC(op_44c0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 12; +} +unsigned long CPUFUNC(op_44d0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2234; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2234: ; +return 16; +} +unsigned long CPUFUNC(op_44d8_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2235; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2235: ; +return 16; +} +unsigned long CPUFUNC(op_44e0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2236; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2236: ; +return 18; +} +unsigned long CPUFUNC(op_44e8_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2237; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2237: ; +return 20; +} +unsigned long CPUFUNC(op_44f0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2238; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2238: ; +return 22; +} +unsigned long CPUFUNC(op_44f8_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2239; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2239: ; +return 20; +} +unsigned long CPUFUNC(op_44f9_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 24; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2240; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2240: ; +return 24; +} +unsigned long CPUFUNC(op_44fa_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2241; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2241: ; +return 20; +} +unsigned long CPUFUNC(op_44fb_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2242; + } +{{ int16_t src = m68k_read_memory_16(srca); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2242: ; +return 22; +} +unsigned long CPUFUNC(op_44fc_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 16; +{{ int16_t src = get_iword_prefetch(2); + MakeSR(); + regs.sr &= 0xFF00; + regs.sr |= src & 0xFF; + MakeFromSR(); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_4600_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4610_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_4618_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}return 12; +} +unsigned long CPUFUNC(op_4620_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,dst); +}}}}return 14; +} +unsigned long CPUFUNC(op_4628_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_4630_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}return 18; +} +unsigned long CPUFUNC(op_4638_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}return 16; +} +unsigned long CPUFUNC(op_4639_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(dst)) == 0); + SET_NFLG (((int8_t)(dst)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,dst); +}}}}return 20; +} +unsigned long CPUFUNC(op_4640_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4650_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2253; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2253: ; +return 12; +} +unsigned long CPUFUNC(op_4658_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2254; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2254: ; +return 12; +} +unsigned long CPUFUNC(op_4660_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2255; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2255: ; +return 14; +} +unsigned long CPUFUNC(op_4668_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2256; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2256: ; +return 16; +} +unsigned long CPUFUNC(op_4670_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2257; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2257: ; +return 18; +} +unsigned long CPUFUNC(op_4678_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2258; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2258: ; +return 16; +} +unsigned long CPUFUNC(op_4679_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2259; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(srca,dst); +}}}}}endlabel2259: ; +return 20; +} +unsigned long CPUFUNC(op_4680_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_4690_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2261; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2261: ; +return 20; +} +unsigned long CPUFUNC(op_4698_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2262; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2262: ; +return 20; +} +unsigned long CPUFUNC(op_46a0_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 22; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2263; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2263: ; +return 22; +} +unsigned long CPUFUNC(op_46a8_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 24; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2264; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2264: ; +return 24; +} +unsigned long CPUFUNC(op_46b0_5)(uint32_t opcode) /* NOT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 19; CurrentInstrCycles = 26; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2265; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2265: ; +return 26; +} +unsigned long CPUFUNC(op_46b8_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 24; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2266; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2266: ; +return 24; +} +unsigned long CPUFUNC(op_46b9_5)(uint32_t opcode) /* NOT */ +{ + OpcodeFamily = 19; CurrentInstrCycles = 28; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2267; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ uint32_t dst = ~src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(srca,dst); +}}}}}endlabel2267: ; +return 28; +} +unsigned long CPUFUNC(op_46c0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 12; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2268; } +{{ int16_t src = m68k_dreg(regs, srcreg); + regs.sr = src; + MakeFromSR(); +}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2268: ; +return 12; +} +unsigned long CPUFUNC(op_46d0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2269; } +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2269; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2269: ; +return 16; +} +unsigned long CPUFUNC(op_46d8_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2270; } +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2270; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2270: ; +return 16; +} +unsigned long CPUFUNC(op_46e0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 18; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2271; } +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2271; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2271: ; +return 18; +} +unsigned long CPUFUNC(op_46e8_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2272; } +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2272; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2272: ; +return 20; +} +unsigned long CPUFUNC(op_46f0_5)(uint32_t opcode) /* MV2SR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 33; CurrentInstrCycles = 22; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2273; } +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2273; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2273: ; +return 22; +} +unsigned long CPUFUNC(op_46f8_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2274; } +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2274; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2274: ; +return 20; +} +unsigned long CPUFUNC(op_46f9_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 24; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2275; } +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2275; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2275: ; +return 24; +} +unsigned long CPUFUNC(op_46fa_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2276; } +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2276; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2276: ; +return 20; +} +unsigned long CPUFUNC(op_46fb_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 22; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2277; } +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2277; + } +{{ int16_t src = m68k_read_memory_16(srca); + regs.sr = src; + MakeFromSR(); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2277: ; +return 22; +} +unsigned long CPUFUNC(op_46fc_5)(uint32_t opcode) /* MV2SR */ +{ + OpcodeFamily = 33; CurrentInstrCycles = 16; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2278; } +{{ int16_t src = get_iword_prefetch(2); + regs.sr = src; + MakeFromSR(); +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2278: ; +return 16; +} +unsigned long CPUFUNC(op_4800_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_4810_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}return 12; +} +unsigned long CPUFUNC(op_4818_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}return 12; +} +unsigned long CPUFUNC(op_4820_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,newv); +}}}}return 14; +} +unsigned long CPUFUNC(op_4828_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}return 16; +} +unsigned long CPUFUNC(op_4830_5)(uint32_t opcode) /* NBCD */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 17; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}return 18; +} +unsigned long CPUFUNC(op_4838_5)(uint32_t opcode) /* NBCD */ +{ + OpcodeFamily = 17; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}return 16; +} +unsigned long CPUFUNC(op_4839_5)(uint32_t opcode) /* NBCD */ +{ + OpcodeFamily = 17; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = - (src & 0xF0); + uint16_t newv; + int cflg; + if (newv_lo > 9) { newv_lo -= 6; } + newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; + if (cflg) newv -= 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,newv); +}}}}return 20; +} +unsigned long CPUFUNC(op_4840_5)(uint32_t opcode) /* SWAP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 34; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4850_5)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2288; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2288: ; +return 12; +} +unsigned long CPUFUNC(op_4868_5)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2289; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2289: ; +return 16; +} +unsigned long CPUFUNC(op_4870_5)(uint32_t opcode) /* PEA */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 57; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2290; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2290: ; +return 22; +} +unsigned long CPUFUNC(op_4878_5)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2291; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2291: ; +return 16; +} +unsigned long CPUFUNC(op_4879_5)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2292; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2292: ; +return 20; +} +unsigned long CPUFUNC(op_487a_5)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2293; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2293: ; +return 16; +} +unsigned long CPUFUNC(op_487b_5)(uint32_t opcode) /* PEA */ +{ + OpcodeFamily = 57; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ uint32_t dsta = m68k_areg(regs, 7) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2294; + } +{ m68k_areg (regs, 7) = dsta; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,srca); +}}}}endlabel2294: ; +return 22; +} +unsigned long CPUFUNC(op_4880_5)(uint32_t opcode) /* EXT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 36; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint16_t dst = (int16_t)(int8_t)src; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(dst)) == 0); + SET_NFLG (((int16_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4890_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2296; + } +{m68k_incpc(4); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}endlabel2296: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_48a0_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) - 0; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2297; + } +{m68k_incpc(4); +fill_prefetch_0 (); +{ uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; + while (amask) { srca -= 2; m68k_write_memory_16(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; } + while (dmask) { srca -= 2; m68k_write_memory_16(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; } + m68k_areg(regs, dstreg) = srca; +}}}}endlabel2297: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_48a8_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2298; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}endlabel2298: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_48b0_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 14; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2299; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}endlabel2299: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_48b8_5)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2300; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}endlabel2300: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_48b9_5)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = get_ilong_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2301; + } +{m68k_incpc(8); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}endlabel2301: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_48c0_5)(uint32_t opcode) /* EXT */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 36; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dst = (int32_t)(int16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(dst)) == 0); + SET_NFLG (((int32_t)(dst)) < 0); + m68k_dreg(regs, srcreg) = (dst); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_48d0_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2303; + } +{m68k_incpc(4); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}endlabel2303: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_48e0_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 8; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) - 0; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2304; + } +{m68k_incpc(4); +fill_prefetch_0 (); +{ uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; + while (amask) { srca -= 4; m68k_write_memory_32(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; } + while (dmask) { srca -= 4; m68k_write_memory_32(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; } + m68k_areg(regs, dstreg) = srca; +}}}}endlabel2304: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_48e8_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2305; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}endlabel2305: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_48f0_5)(uint32_t opcode) /* MVMLE */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 14; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2306; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}endlabel2306: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_48f8_5)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2307; + } +{m68k_incpc(6); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}endlabel2307: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_48f9_5)(uint32_t opcode) /* MVMLE */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 38; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + retcycles = 0; +{ uint32_t srca = get_ilong_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2308; + } +{m68k_incpc(8); +fill_prefetch_0 (); +{ uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}endlabel2308: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4a00_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4a10_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_4a18_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_4a20_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_4a28_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_4a30_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_4a38_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_4a39_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_4a3a_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_4a3b_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_4a3c_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_4a40_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4a48_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4a50_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2322; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2322: ; +return 8; +} +unsigned long CPUFUNC(op_4a58_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2323; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2323: ; +return 8; +} +unsigned long CPUFUNC(op_4a60_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2324; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2324: ; +return 10; +} +unsigned long CPUFUNC(op_4a68_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2325; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2325: ; +return 12; +} +unsigned long CPUFUNC(op_4a70_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2326; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2326: ; +return 14; +} +unsigned long CPUFUNC(op_4a78_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2327; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2327: ; +return 12; +} +unsigned long CPUFUNC(op_4a79_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2328; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2328: ; +return 16; +} +unsigned long CPUFUNC(op_4a7a_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2329; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2329: ; +return 12; +} +unsigned long CPUFUNC(op_4a7b_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2330; + } +{{ int16_t src = m68k_read_memory_16(srca); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2330: ; +return 14; +} +unsigned long CPUFUNC(op_4a7c_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_4a80_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int32_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4a88_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 4; +{{ int32_t src = m68k_areg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4a90_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2334; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2334: ; +return 12; +} +unsigned long CPUFUNC(op_4a98_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2335; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2335: ; +return 12; +} +unsigned long CPUFUNC(op_4aa0_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2336; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2336: ; +return 14; +} +unsigned long CPUFUNC(op_4aa8_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2337; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2337: ; +return 16; +} +unsigned long CPUFUNC(op_4ab0_5)(uint32_t opcode) /* TST */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 20; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2338; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2338: ; +return 18; +} +unsigned long CPUFUNC(op_4ab8_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2339; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2339: ; +return 16; +} +unsigned long CPUFUNC(op_4ab9_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2340; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2340: ; +return 20; +} +unsigned long CPUFUNC(op_4aba_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2341; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2341: ; +return 16; +} +unsigned long CPUFUNC(op_4abb_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2342; + } +{{ int32_t src = m68k_read_memory_32(srca); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2342: ; +return 18; +} +unsigned long CPUFUNC(op_4abc_5)(uint32_t opcode) /* TST */ +{ + OpcodeFamily = 20; CurrentInstrCycles = 12; +{{ int32_t src = get_ilong_prefetch(2); + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +}}m68k_incpc(6); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_4ac0_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff); +}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4ad0_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,src); +}}}return 14; +} +unsigned long CPUFUNC(op_4ad8_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,src); +}}}return 14; +} +unsigned long CPUFUNC(op_4ae0_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,src); +}}}return 16; +} +unsigned long CPUFUNC(op_4ae8_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,src); +}}}return 18; +} +unsigned long CPUFUNC(op_4af0_5)(uint32_t opcode) /* TAS */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 98; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,src); +}}}return 20; +} +unsigned long CPUFUNC(op_4af8_5)(uint32_t opcode) /* TAS */ +{ + OpcodeFamily = 98; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,src); +}}}return 18; +} +unsigned long CPUFUNC(op_4af9_5)(uint32_t opcode) /* TAS */ +{ + OpcodeFamily = 98; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + src |= 0x80; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,src); +}}}return 22; +} +unsigned long CPUFUNC(op_4c90_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2352; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2352: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_4c98_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2353; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } + m68k_areg(regs, dstreg) = srca; +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2353: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_4ca8_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2354; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2354: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cb0_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2355; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2355: ; + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cb8_5)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2356; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2356: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cb9_5)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 20; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_ilong_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2357; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel2357: ; + return (20+retcycles); +} +unsigned long CPUFUNC(op_4cba_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 2; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_getpc () + 4; + srca += (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2358; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2358: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cbb_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 3; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2359; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2359: ; + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cd0_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2360; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2360: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_4cd8_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 12; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2361; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } + m68k_areg(regs, dstreg) = srca; +}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2361: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_4ce8_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2362; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2362: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cf0_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2363; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2363: ; + return (18+retcycles); +} +unsigned long CPUFUNC(op_4cf8_5)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2364; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2364: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cf9_5)(uint32_t opcode) /* MVMEL */ +{ + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 20; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = get_ilong_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 8; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2365; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(8); +fill_prefetch_0 (); +endlabel2365: ; + return (20+retcycles); +} +unsigned long CPUFUNC(op_4cfa_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 2; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 16; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t srca = m68k_getpc () + 4; + srca += (int32_t)(int16_t)get_iword_prefetch(4); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2366; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2366: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_4cfb_5)(uint32_t opcode) /* MVMEL */ +{ + uint32_t dstreg = 3; + unsigned int retcycles = 0; + OpcodeFamily = 37; CurrentInstrCycles = 18; +{ uint16_t mask = get_iword_prefetch(2); + unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; + retcycles = 0; +{ uint32_t tmppc = m68k_getpc() + 4; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(4)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2367; + } +{{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } + while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } +}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2367: ; + return (18+retcycles); +} +unsigned long CPUFUNC(op_4e40_5)(uint32_t opcode) /* TRAP */ +{ + uint32_t srcreg = (opcode & 15); + OpcodeFamily = 39; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +m68k_incpc(2); +fill_prefetch_2 (); + Exception(src+32,0,M68000_EXC_SRC_CPU); +}}return 4; +} +unsigned long CPUFUNC(op_4e50_5)(uint32_t opcode) /* LINK */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 47; CurrentInstrCycles = 18; +{{ uint32_t olda = m68k_areg(regs, 7) - 4; + if ((olda & 1) != 0) { + last_fault_for_exception_3 = olda; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2369; + } +{ m68k_areg (regs, 7) = olda; +{ int32_t src = m68k_areg(regs, srcreg); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(olda,src); + m68k_areg(regs, srcreg) = (m68k_areg(regs, 7)); +{ int16_t offs = get_iword_prefetch(0); + m68k_areg(regs, 7) += offs; +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2369: ; +return 18; +} +unsigned long CPUFUNC(op_4e58_5)(uint32_t opcode) /* UNLK */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 48; CurrentInstrCycles = 12; +{{ int32_t src = m68k_areg(regs, srcreg); + m68k_areg(regs, 7) = src; +{ uint32_t olda = m68k_areg(regs, 7); + if ((olda & 1) != 0) { + last_fault_for_exception_3 = olda; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2370; + } +{{ int32_t old = m68k_read_memory_32(olda); + m68k_areg(regs, 7) += 4; + m68k_areg(regs, srcreg) = (old); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2370: ; +return 12; +} +unsigned long CPUFUNC(op_4e60_5)(uint32_t opcode) /* MVR2USP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 40; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2371; } +{{ int32_t src = m68k_areg(regs, srcreg); + regs.usp = src; +}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2371: ; +return 4; +} +unsigned long CPUFUNC(op_4e68_5)(uint32_t opcode) /* MVUSP2R */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 41; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2372; } +{{ m68k_areg(regs, srcreg) = (regs.usp); +}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2372: ; +return 4; +} +unsigned long CPUFUNC(op_4e70_5)(uint32_t opcode) /* RESET */ +{ + OpcodeFamily = 42; CurrentInstrCycles = 132; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2373; } +{}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2373: ; +return 132; +} +unsigned long CPUFUNC(op_4e71_5)(uint32_t opcode) /* NOP */ +{ + OpcodeFamily = 43; CurrentInstrCycles = 4; +{}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_4e72_5)(uint32_t opcode) /* STOP */ +{ + OpcodeFamily = 44; CurrentInstrCycles = 4; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2375; } +{{ int16_t src = get_iword_prefetch(2); + regs.sr = src; + MakeFromSR(); + m68k_setstopped(1); +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2375: ; +return 4; +} +unsigned long CPUFUNC(op_4e73_5)(uint32_t opcode) /* RTE */ +{ + OpcodeFamily = 45; CurrentInstrCycles = 20; +{if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2376; } +{{ uint32_t sra = m68k_areg(regs, 7); + if ((sra & 1) != 0) { + last_fault_for_exception_3 = sra; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2376; + } +{{ int16_t sr = m68k_read_memory_16(sra); + m68k_areg(regs, 7) += 2; +{ uint32_t pca = m68k_areg(regs, 7); + if ((pca & 1) != 0) { + last_fault_for_exception_3 = pca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2376; + } +{{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; + regs.sr = sr; m68k_setpc_rte(pc); +fill_prefetch_0 (); + MakeFromSR(); +}}}}}}}}endlabel2376: ; +return 20; +} +unsigned long CPUFUNC(op_4e74_5)(uint32_t opcode) /* RTD */ +{ + OpcodeFamily = 46; CurrentInstrCycles = 16; +{{ uint32_t pca = m68k_areg(regs, 7); + if ((pca & 1) != 0) { + last_fault_for_exception_3 = pca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2377; + } +{{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; +{ int16_t offs = get_iword_prefetch(2); + m68k_areg(regs, 7) += offs; + m68k_setpc_rte(pc); +fill_prefetch_0 (); +}}}}}endlabel2377: ; +return 16; +} +unsigned long CPUFUNC(op_4e75_5)(uint32_t opcode) /* RTS */ +{ + OpcodeFamily = 49; CurrentInstrCycles = 16; +{ m68k_do_rts(); +fill_prefetch_0 (); +}return 16; +} +unsigned long CPUFUNC(op_4e76_5)(uint32_t opcode) /* TRAPV */ +{ + OpcodeFamily = 50; CurrentInstrCycles = 4; +{m68k_incpc(2); +fill_prefetch_2 (); + if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel2379; } +}endlabel2379: ; +return 4; +} +unsigned long CPUFUNC(op_4e77_5)(uint32_t opcode) /* RTR */ +{ + OpcodeFamily = 51; CurrentInstrCycles = 20; +{ MakeSR(); +{ uint32_t sra = m68k_areg(regs, 7); + if ((sra & 1) != 0) { + last_fault_for_exception_3 = sra; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2380; + } +{{ int16_t sr = m68k_read_memory_16(sra); + m68k_areg(regs, 7) += 2; +{ uint32_t pca = m68k_areg(regs, 7); + if ((pca & 1) != 0) { + last_fault_for_exception_3 = pca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2380; + } +{{ int32_t pc = m68k_read_memory_32(pca); + m68k_areg(regs, 7) += 4; + regs.sr &= 0xFF00; sr &= 0xFF; + regs.sr |= sr; m68k_setpc(pc); +fill_prefetch_0 (); + MakeFromSR(); +}}}}}}}endlabel2380: ; +return 20; +} +unsigned long CPUFUNC(op_4e90_5)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg); + uint32_t oldpc = m68k_getpc () + 2; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2381; + } + m68k_do_jsr(m68k_getpc() + 2, srca); +fill_prefetch_0 (); +}}endlabel2381: ; +return 16; +} +unsigned long CPUFUNC(op_4ea8_5)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + uint32_t oldpc = m68k_getpc () + 4; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2382; + } + m68k_do_jsr(m68k_getpc() + 4, srca); +fill_prefetch_0 (); +}}endlabel2382: ; +return 18; +} +unsigned long CPUFUNC(op_4eb0_5)(uint32_t opcode) /* JSR */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 52; CurrentInstrCycles = 22; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + uint32_t oldpc = m68k_getpc () + 4; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2383; + } + m68k_do_jsr(m68k_getpc() + 4, srca); +fill_prefetch_0 (); +}}endlabel2383: ; +return 22; +} +unsigned long CPUFUNC(op_4eb8_5)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + uint32_t oldpc = m68k_getpc () + 4; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2384; + } + m68k_do_jsr(m68k_getpc() + 4, srca); +fill_prefetch_0 (); +}}endlabel2384: ; +return 18; +} +unsigned long CPUFUNC(op_4eb9_5)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + uint32_t oldpc = m68k_getpc () + 6; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2385; + } + m68k_do_jsr(m68k_getpc() + 6, srca); +fill_prefetch_0 (); +}}endlabel2385: ; +return 20; +} +unsigned long CPUFUNC(op_4eba_5)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + uint32_t oldpc = m68k_getpc () + 4; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2386; + } + m68k_do_jsr(m68k_getpc() + 4, srca); +fill_prefetch_0 (); +}}endlabel2386: ; +return 18; +} +unsigned long CPUFUNC(op_4ebb_5)(uint32_t opcode) /* JSR */ +{ + OpcodeFamily = 52; CurrentInstrCycles = 22; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + uint32_t oldpc = m68k_getpc () + 4; + if (srca & 1) { + last_addr_for_exception_3 = oldpc; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2387; + } + m68k_do_jsr(m68k_getpc() + 4, srca); +fill_prefetch_0 (); +}}endlabel2387: ; +return 22; +} +unsigned long CPUFUNC(op_4ed0_5)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2388; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2388: ; +return 8; +} +unsigned long CPUFUNC(op_4ee8_5)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2389; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2389: ; +return 10; +} +unsigned long CPUFUNC(op_4ef0_5)(uint32_t opcode) /* JMP */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 53; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2390; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2390: ; +return 14; +} +unsigned long CPUFUNC(op_4ef8_5)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2391; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2391: ; +return 10; +} +unsigned long CPUFUNC(op_4ef9_5)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 12; +{{ uint32_t srca = get_ilong_prefetch(2); + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2392; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2392: ; +return 12; +} +unsigned long CPUFUNC(op_4efa_5)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2393; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2393: ; +return 10; +} +unsigned long CPUFUNC(op_4efb_5)(uint32_t opcode) /* JMP */ +{ + OpcodeFamily = 53; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if (srca & 1) { + last_addr_for_exception_3 = m68k_getpc() + 6; + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2394; + } + m68k_setpc(srca); +fill_prefetch_0 (); +}}endlabel2394: ; +return 14; +} +unsigned long CPUFUNC(op_5000_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5010_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_5018_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +#endif + +#ifdef PART_5 +unsigned long CPUFUNC(op_5020_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 14; +} +unsigned long CPUFUNC(op_5028_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_5030_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_5038_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_5039_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_5040_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5048_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5050_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2405; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2405: ; +return 12; +} +unsigned long CPUFUNC(op_5058_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2406; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2406: ; +return 12; +} +unsigned long CPUFUNC(op_5060_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2407; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2407: ; +return 14; +} +unsigned long CPUFUNC(op_5068_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2408; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2408: ; +return 16; +} +unsigned long CPUFUNC(op_5070_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2409; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2409: ; +return 18; +} +unsigned long CPUFUNC(op_5078_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2410; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2410: ; +return 16; +} +unsigned long CPUFUNC(op_5079_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2411; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2411: ; +return 20; +} +unsigned long CPUFUNC(op_5080_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5088_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5090_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2414; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2414: ; +return 20; +} +unsigned long CPUFUNC(op_5098_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2415; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2415: ; +return 20; +} +unsigned long CPUFUNC(op_50a0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2416; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2416: ; +return 22; +} +unsigned long CPUFUNC(op_50a8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2417; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2417: ; +return 24; +} +unsigned long CPUFUNC(op_50b0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 26; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2418; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2418: ; +return 26; +} +unsigned long CPUFUNC(op_50b8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2419; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2419: ; +return 24; +} +unsigned long CPUFUNC(op_50b9_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2420; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2420: ; +return 28; +} +unsigned long CPUFUNC(op_50c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(0) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_50c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(0)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2422; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2422: ; +return 12; +} +unsigned long CPUFUNC(op_50d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_50d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_50e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_50e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_50f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_50f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_50f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(0) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5100_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5110_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_5118_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_5120_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 14; +} +unsigned long CPUFUNC(op_5128_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_5130_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_5138_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_5139_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_5140_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5148_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5150_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2440; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2440: ; +return 12; +} +unsigned long CPUFUNC(op_5158_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2441; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2441: ; +return 12; +} +unsigned long CPUFUNC(op_5160_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2442; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2442: ; +return 14; +} +unsigned long CPUFUNC(op_5168_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2443; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2443: ; +return 16; +} +unsigned long CPUFUNC(op_5170_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2444; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2444: ; +return 18; +} +unsigned long CPUFUNC(op_5178_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2445; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2445: ; +return 16; +} +unsigned long CPUFUNC(op_5179_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2446; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2446: ; +return 20; +} +unsigned long CPUFUNC(op_5180_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5188_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_5190_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2449; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2449: ; +return 20; +} +unsigned long CPUFUNC(op_5198_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2450; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2450: ; +return 20; +} +unsigned long CPUFUNC(op_51a0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2451; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2451: ; +return 22; +} +unsigned long CPUFUNC(op_51a8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2452; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2452: ; +return 24; +} +unsigned long CPUFUNC(op_51b0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 26; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2453; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2453: ; +return 26; +} +unsigned long CPUFUNC(op_51b8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ uint32_t src = srcreg; +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2454; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2454: ; +return 24; +} +unsigned long CPUFUNC(op_51b9_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ uint32_t src = srcreg; +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2455; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2455: ; +return 28; +} +unsigned long CPUFUNC(op_51c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(1) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_51c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(1)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2457; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2457: ; +return 12; +} +unsigned long CPUFUNC(op_51d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_51d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_51e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_51e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_51f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_51f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_51f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(1) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_52c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(2) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_52c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(2)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2466; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2466: ; +return 12; +} +unsigned long CPUFUNC(op_52d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_52d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_52e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_52e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_52f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_52f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_52f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(2) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_53c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(3) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_53c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(3)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2475; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2475: ; +return 12; +} +unsigned long CPUFUNC(op_53d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_53d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_53e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_53e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_53f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_53f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_53f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(3) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_54c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(4) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_54c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(4)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2484; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2484: ; +return 12; +} +unsigned long CPUFUNC(op_54d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_54d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_54e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_54e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_54f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_54f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_54f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(4) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_55c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(5) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_55c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(5)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2493; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2493: ; +return 12; +} +unsigned long CPUFUNC(op_55d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_55d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_55e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_55e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_55f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_55f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_55f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(5) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_56c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(6) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_56c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(6)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2502; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2502: ; +return 12; +} +unsigned long CPUFUNC(op_56d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_56d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_56e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_56e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_56f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_56f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_56f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(6) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_57c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(7) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_57c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(7)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2511; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2511: ; +return 12; +} +unsigned long CPUFUNC(op_57d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_57d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_57e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_57e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_57f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_57f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_57f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(7) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_58c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(8) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_58c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(8)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2520; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2520: ; +return 12; +} +unsigned long CPUFUNC(op_58d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_58d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_58e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_58e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_58f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_58f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_58f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(8) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_59c0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(9) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_59c8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(9)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2529; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2529: ; +return 12; +} +unsigned long CPUFUNC(op_59d0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_59d8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_59e0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_59e8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_59f0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_59f8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_59f9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(9) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5ac0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(10) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5ac8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(10)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2538; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2538: ; +return 12; +} +unsigned long CPUFUNC(op_5ad0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5ad8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5ae0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_5ae8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5af0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5af8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5af9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(10) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5bc0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(11) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5bc8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(11)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2547; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2547: ; +return 12; +} +unsigned long CPUFUNC(op_5bd0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5bd8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5be0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_5be8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5bf0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5bf8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5bf9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(11) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5cc0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(12) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5cc8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(12)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2556; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2556: ; +return 12; +} +unsigned long CPUFUNC(op_5cd0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5cd8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5ce0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_5ce8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5cf0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5cf8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5cf9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(12) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5dc0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(13) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5dc8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(13)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2565; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2565: ; +return 12; +} +unsigned long CPUFUNC(op_5dd0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5dd8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5de0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_5de8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5df0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5df8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5df9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(13) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5ec0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(14) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5ec8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(14)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2574; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2574: ; +return 12; +} +unsigned long CPUFUNC(op_5ed0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5ed8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5ee0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +unsigned long CPUFUNC(op_5ee8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5ef0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5ef8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5ef9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(14) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_5fc0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 4; +{{{ int val = cctrue(15) ? 0xff : 0; + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); + if (val) { m68k_incpc(2) ; return 4+2; } +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_5fc8_5)(uint32_t opcode) /* DBcc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 58; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t offs = get_iword_prefetch(2); + if (!cctrue(15)) { + m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); + if (src) { + if (offs & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2 + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2583; + } + m68k_incpc((int32_t)offs + 2); +fill_prefetch_0 (); + return 10; + } else { + m68k_incpc(4); +fill_prefetch_0 (); + return 14; + } + } +}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2583: ; +return 12; +} +unsigned long CPUFUNC(op_5fd0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5fd8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 12; +} +unsigned long CPUFUNC(op_5fe0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; + m68k_areg (regs, srcreg) = srca; +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(srca,val); +}}}return 14; +} +#endif + +#ifdef PART_6 +unsigned long CPUFUNC(op_5fe8_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5ff0_5)(uint32_t opcode) /* Scc */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 59; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 18; +} +unsigned long CPUFUNC(op_5ff8_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 16; +} +unsigned long CPUFUNC(op_5ff9_5)(uint32_t opcode) /* Scc */ +{ + OpcodeFamily = 59; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int val = cctrue(15) ? 0xff : 0; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(srca,val); +}}}return 20; +} +unsigned long CPUFUNC(op_6000_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(0)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2591; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2591: ; +return 12; +} +unsigned long CPUFUNC(op_6001_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(0)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2592; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2592: ; +return 8; +} +unsigned long CPUFUNC(op_60ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(0)) goto endlabel2593; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2593; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(0)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2593; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2593: ; +return 12; +} +unsigned long CPUFUNC(op_6100_5)(uint32_t opcode) /* BSR */ +{ + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ int16_t src = get_iword_prefetch(2); + int32_t s = (int32_t)src + 2; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + s; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2594; + } + m68k_do_bsr(m68k_getpc() + 4, s); +fill_prefetch_0 (); +}}endlabel2594: ; +return 18; +} +unsigned long CPUFUNC(op_6101_5)(uint32_t opcode) /* BSR */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ uint32_t src = srcreg; + int32_t s = (int32_t)src + 2; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + s; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2595; + } + m68k_do_bsr(m68k_getpc() + 2, s); +fill_prefetch_0 (); +}}endlabel2595: ; +return 18; +} +unsigned long CPUFUNC(op_61ff_5)(uint32_t opcode) /* BSR */ +{ + OpcodeFamily = 54; CurrentInstrCycles = 18; +{{ int32_t src = get_ilong_prefetch(2); + int32_t s = (int32_t)src + 2; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + s; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2596; + } + m68k_do_bsr(m68k_getpc() + 6, s); +fill_prefetch_0 (); +}}endlabel2596: ; +return 18; +} +unsigned long CPUFUNC(op_6200_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(2)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2597; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2597: ; +return 12; +} +unsigned long CPUFUNC(op_6201_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(2)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2598; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2598: ; +return 8; +} +unsigned long CPUFUNC(op_62ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(2)) goto endlabel2599; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2599; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(2)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2599; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2599: ; +return 12; +} +unsigned long CPUFUNC(op_6300_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(3)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2600; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2600: ; +return 12; +} +unsigned long CPUFUNC(op_6301_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(3)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2601; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2601: ; +return 8; +} +unsigned long CPUFUNC(op_63ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(3)) goto endlabel2602; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2602; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(3)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2602; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2602: ; +return 12; +} +unsigned long CPUFUNC(op_6400_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(4)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2603; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2603: ; +return 12; +} +unsigned long CPUFUNC(op_6401_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(4)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2604; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2604: ; +return 8; +} +unsigned long CPUFUNC(op_64ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(4)) goto endlabel2605; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2605; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(4)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2605; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2605: ; +return 12; +} +unsigned long CPUFUNC(op_6500_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(5)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2606; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2606: ; +return 12; +} +unsigned long CPUFUNC(op_6501_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(5)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2607; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2607: ; +return 8; +} +unsigned long CPUFUNC(op_65ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(5)) goto endlabel2608; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2608; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(5)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2608; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2608: ; +return 12; +} +unsigned long CPUFUNC(op_6600_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(6)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2609; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2609: ; +return 12; +} +unsigned long CPUFUNC(op_6601_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(6)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2610; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2610: ; +return 8; +} +unsigned long CPUFUNC(op_66ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(6)) goto endlabel2611; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2611; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(6)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2611; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2611: ; +return 12; +} +unsigned long CPUFUNC(op_6700_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(7)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2612; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2612: ; +return 12; +} +unsigned long CPUFUNC(op_6701_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(7)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2613; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2613: ; +return 8; +} +unsigned long CPUFUNC(op_67ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(7)) goto endlabel2614; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2614; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(7)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2614; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2614: ; +return 12; +} +unsigned long CPUFUNC(op_6800_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(8)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2615; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2615: ; +return 12; +} +unsigned long CPUFUNC(op_6801_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(8)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2616; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2616: ; +return 8; +} +unsigned long CPUFUNC(op_68ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(8)) goto endlabel2617; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2617; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(8)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2617; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2617: ; +return 12; +} +unsigned long CPUFUNC(op_6900_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(9)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2618; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2618: ; +return 12; +} +unsigned long CPUFUNC(op_6901_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(9)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2619; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2619: ; +return 8; +} +unsigned long CPUFUNC(op_69ff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(9)) goto endlabel2620; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2620; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(9)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2620; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2620: ; +return 12; +} +unsigned long CPUFUNC(op_6a00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(10)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2621; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2621: ; +return 12; +} +unsigned long CPUFUNC(op_6a01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(10)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2622; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2622: ; +return 8; +} +unsigned long CPUFUNC(op_6aff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(10)) goto endlabel2623; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2623; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(10)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2623; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2623: ; +return 12; +} +unsigned long CPUFUNC(op_6b00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(11)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2624; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2624: ; +return 12; +} +unsigned long CPUFUNC(op_6b01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(11)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2625; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2625: ; +return 8; +} +unsigned long CPUFUNC(op_6bff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(11)) goto endlabel2626; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2626; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(11)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2626; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2626: ; +return 12; +} +unsigned long CPUFUNC(op_6c00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(12)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2627; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2627: ; +return 12; +} +unsigned long CPUFUNC(op_6c01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(12)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2628; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2628: ; +return 8; +} +unsigned long CPUFUNC(op_6cff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(12)) goto endlabel2629; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2629; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(12)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2629; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2629: ; +return 12; +} +unsigned long CPUFUNC(op_6d00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(13)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2630; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2630: ; +return 12; +} +unsigned long CPUFUNC(op_6d01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(13)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2631; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2631: ; +return 8; +} +unsigned long CPUFUNC(op_6dff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(13)) goto endlabel2632; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2632; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(13)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2632; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2632: ; +return 12; +} +unsigned long CPUFUNC(op_6e00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(14)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2633; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2633: ; +return 12; +} +unsigned long CPUFUNC(op_6e01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(14)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2634; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2634: ; +return 8; +} +unsigned long CPUFUNC(op_6eff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(14)) goto endlabel2635; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2635; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(14)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2635; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2635: ; +return 12; +} +unsigned long CPUFUNC(op_6f00_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); + if (!cctrue(15)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2636; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2636: ; +return 12; +} +unsigned long CPUFUNC(op_6f01_5)(uint32_t opcode) /* Bcc */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + OpcodeFamily = 55; CurrentInstrCycles = 8; +{{ uint32_t src = srcreg; + if (!cctrue(15)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2637; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2637: ; +return 8; +} +unsigned long CPUFUNC(op_6fff_5)(uint32_t opcode) /* Bcc */ +{ + OpcodeFamily = 55; CurrentInstrCycles = 12; +{ m68k_incpc(2); + if (!cctrue(15)) goto endlabel2638; + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 1; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2638; +{ int32_t src = get_ilong_prefetch(2); + if (!cctrue(15)) goto didnt_jump; + if (src & 1) { + last_addr_for_exception_3 = m68k_getpc() + 2; + last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; + last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2638; + } + m68k_incpc ((int32_t)src + 2); +fill_prefetch_0 (); + return 10; +didnt_jump:; +}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2638: ; +return 12; +} +unsigned long CPUFUNC(op_7000_5)(uint32_t opcode) /* MOVE */ +{ + uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 30; CurrentInstrCycles = 4; +{{ uint32_t src = srcreg; +{ CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_8000_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_8010_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_8018_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_8020_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_8028_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_8030_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_8038_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_8039_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_803a_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_803b_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_803c_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_8040_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_8050_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2652; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2652: ; +return 8; +} +unsigned long CPUFUNC(op_8058_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2653; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2653: ; +return 8; +} +unsigned long CPUFUNC(op_8060_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2654; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2654: ; +return 10; +} +unsigned long CPUFUNC(op_8068_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2655; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2655: ; +return 12; +} +unsigned long CPUFUNC(op_8070_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2656; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2656: ; +return 14; +} +unsigned long CPUFUNC(op_8078_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2657; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2657: ; +return 12; +} +unsigned long CPUFUNC(op_8079_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2658; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2658: ; +return 16; +} +unsigned long CPUFUNC(op_807a_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2659; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2659: ; +return 12; +} +unsigned long CPUFUNC(op_807b_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2660; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2660: ; +return 14; +} +unsigned long CPUFUNC(op_807c_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_8080_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_8090_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2663; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2663: ; +return 14; +} +unsigned long CPUFUNC(op_8098_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2664; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2664: ; +return 14; +} +unsigned long CPUFUNC(op_80a0_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2665; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2665: ; +return 16; +} +unsigned long CPUFUNC(op_80a8_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2666; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2666: ; +return 18; +} +unsigned long CPUFUNC(op_80b0_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2667; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2667: ; +return 20; +} +unsigned long CPUFUNC(op_80b8_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2668; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2668: ; +return 18; +} +unsigned long CPUFUNC(op_80b9_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2669; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2669: ; +return 22; +} +unsigned long CPUFUNC(op_80ba_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2670; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2670: ; +return 18; +} +unsigned long CPUFUNC(op_80bb_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2671; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2671: ; +return 20; +} +unsigned long CPUFUNC(op_80bc_5)(uint32_t opcode) /* OR */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_80c0_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 4; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2673; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}endlabel2673: ; + return (4+retcycles); +} +unsigned long CPUFUNC(op_80d0_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2674; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2674; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2674: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_80d8_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2675; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2675; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2675: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_80e0_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2676; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2676; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2676: ; + return (10+retcycles); +} +unsigned long CPUFUNC(op_80e8_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2677; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2677; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2677: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80f0_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2678; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2678; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2678: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_80f8_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2679; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2679; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2679: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80f9_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2680; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2680; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2680: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_80fa_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2681; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2681; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2681: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_80fb_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2682; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2682; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}}}endlabel2682: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_80fc_5)(uint32_t opcode) /* DIVU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 60; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2683; } else { + uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; + uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; + if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); +}}}endlabel2683: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_8100_5)(uint32_t opcode) /* SBCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 10; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); + uint16_t newv, tmp_newv; + int bcd = 0; + newv = tmp_newv = newv_hi + newv_lo; + if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; + if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } + SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_8108_5)(uint32_t opcode) /* SBCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 10; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); + uint16_t newv, tmp_newv; + int bcd = 0; + newv = tmp_newv = newv_hi + newv_lo; + if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; + if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } + SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}return 18; +} +unsigned long CPUFUNC(op_8110_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_8118_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_8120_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_8128_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_8130_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_8138_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_8139_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_8150_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2693; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2693: ; +return 12; +} +unsigned long CPUFUNC(op_8158_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2694; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2694: ; +return 12; +} +unsigned long CPUFUNC(op_8160_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2695; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2695: ; +return 14; +} +unsigned long CPUFUNC(op_8168_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2696; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2696: ; +return 16; +} +unsigned long CPUFUNC(op_8170_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2697; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2697: ; +return 18; +} +unsigned long CPUFUNC(op_8178_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2698; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2698: ; +return 16; +} +unsigned long CPUFUNC(op_8179_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2699; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2699: ; +return 20; +} +unsigned long CPUFUNC(op_8190_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2700; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2700: ; +return 20; +} +unsigned long CPUFUNC(op_8198_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2701; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2701: ; +return 20; +} +unsigned long CPUFUNC(op_81a0_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2702; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2702: ; +return 22; +} +unsigned long CPUFUNC(op_81a8_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2703; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2703: ; +return 24; +} +unsigned long CPUFUNC(op_81b0_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 1; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2704; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2704: ; +return 26; +} +unsigned long CPUFUNC(op_81b8_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2705; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2705: ; +return 24; +} +unsigned long CPUFUNC(op_81b9_5)(uint32_t opcode) /* OR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 1; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2706; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src |= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2706: ; +return 28; +} +unsigned long CPUFUNC(op_81c0_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 4; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2707; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}endlabel2707: ; + return (4+retcycles); +} +unsigned long CPUFUNC(op_81d0_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2708; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2708; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2708: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_81d8_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2709; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2709; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2709: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_81e0_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 10; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2710; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(2); +fill_prefetch_2 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2710; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2710: ; + return (10+retcycles); +} +unsigned long CPUFUNC(op_81e8_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2711; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2711; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2711: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81f0_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2712; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2712; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2712: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_81f8_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2713; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2713; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2713: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81f9_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 16; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2714; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(6); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2714; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2714: ; + return (16+retcycles); +} +unsigned long CPUFUNC(op_81fa_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 12; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2715; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2715; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2715: ; + return (12+retcycles); +} +unsigned long CPUFUNC(op_81fb_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 14; +{ uint32_t oldpc = m68k_getpc(); +{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2716; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2716; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}}}endlabel2716: ; + return (14+retcycles); +} +unsigned long CPUFUNC(op_81fc_5)(uint32_t opcode) /* DIVS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 61; CurrentInstrCycles = 8; +{ uint32_t oldpc = m68k_getpc(); +{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +m68k_incpc(4); +fill_prefetch_0 (); + if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2717; } else { + int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; + uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; + if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else + { + if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_NFLG (((int16_t)(newv)) < 0); + newv = (newv & 0xffff) | ((uint32_t)rem << 16); + m68k_dreg(regs, dstreg) = (newv); + } + } + retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); +}}}endlabel2717: ; + return (8+retcycles); +} +unsigned long CPUFUNC(op_9000_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_9010_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_9018_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_9020_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_9028_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_9030_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_9038_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_9039_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_903a_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_903b_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_903c_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_9040_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_9048_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_9050_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2731; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2731: ; +return 8; +} +unsigned long CPUFUNC(op_9058_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2732; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2732: ; +return 8; +} +unsigned long CPUFUNC(op_9060_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2733; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2733: ; +return 10; +} +unsigned long CPUFUNC(op_9068_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2734; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2734: ; +return 12; +} +unsigned long CPUFUNC(op_9070_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2735; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2735: ; +return 14; +} +unsigned long CPUFUNC(op_9078_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2736; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2736: ; +return 12; +} +unsigned long CPUFUNC(op_9079_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2737; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2737: ; +return 16; +} +unsigned long CPUFUNC(op_907a_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2738; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2738: ; +return 12; +} +unsigned long CPUFUNC(op_907b_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2739; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2739: ; +return 14; +} +unsigned long CPUFUNC(op_907c_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_9080_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_9088_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_9090_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2743; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2743: ; +return 14; +} +unsigned long CPUFUNC(op_9098_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2744; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2744: ; +return 14; +} +unsigned long CPUFUNC(op_90a0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2745; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2745: ; +return 16; +} +unsigned long CPUFUNC(op_90a8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2746; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2746: ; +return 18; +} +unsigned long CPUFUNC(op_90b0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2747; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2747: ; +return 20; +} +unsigned long CPUFUNC(op_90b8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2748; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2748: ; +return 18; +} +unsigned long CPUFUNC(op_90b9_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2749; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2749: ; +return 22; +} +unsigned long CPUFUNC(op_90ba_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2750; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2750: ; +return 18; +} +unsigned long CPUFUNC(op_90bb_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2751; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2751: ; +return 20; +} +unsigned long CPUFUNC(op_90bc_5)(uint32_t opcode) /* SUB */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_90c0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_90c8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_90d0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2755; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2755: ; +return 12; +} +unsigned long CPUFUNC(op_90d8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2756; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2756: ; +return 12; +} +unsigned long CPUFUNC(op_90e0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2757; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2757: ; +return 14; +} +unsigned long CPUFUNC(op_90e8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2758; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2758: ; +return 16; +} +unsigned long CPUFUNC(op_90f0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2759; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2759: ; +return 18; +} +unsigned long CPUFUNC(op_90f8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2760; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2760: ; +return 16; +} +unsigned long CPUFUNC(op_90f9_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2761; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2761: ; +return 20; +} +unsigned long CPUFUNC(op_90fa_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2762; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2762: ; +return 16; +} +unsigned long CPUFUNC(op_90fb_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2763; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2763: ; +return 18; +} +unsigned long CPUFUNC(op_90fc_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_9100_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_9108_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_9110_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_9118_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_9120_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 14; +} +unsigned long CPUFUNC(op_9128_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_9130_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_9138_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_9139_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_9140_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_9148_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2775; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2775; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}}endlabel2775: ; +return 18; +} +unsigned long CPUFUNC(op_9150_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2776; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2776: ; +return 12; +} +unsigned long CPUFUNC(op_9158_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2777; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2777: ; +return 12; +} +unsigned long CPUFUNC(op_9160_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2778; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2778: ; +return 14; +} +unsigned long CPUFUNC(op_9168_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2779; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2779: ; +return 16; +} +unsigned long CPUFUNC(op_9170_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2780; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2780: ; +return 18; +} +unsigned long CPUFUNC(op_9178_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2781; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2781: ; +return 16; +} +unsigned long CPUFUNC(op_9179_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2782; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel2782: ; +return 20; +} +unsigned long CPUFUNC(op_9180_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_9188_5)(uint32_t opcode) /* SUBX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 9; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2784; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2784; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}}endlabel2784: ; +return 30; +} +unsigned long CPUFUNC(op_9190_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2785; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2785: ; +return 20; +} +unsigned long CPUFUNC(op_9198_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2786; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2786: ; +return 20; +} +unsigned long CPUFUNC(op_91a0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2787; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2787: ; +return 22; +} +unsigned long CPUFUNC(op_91a8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2788; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2788: ; +return 24; +} +unsigned long CPUFUNC(op_91b0_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 7; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2789; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2789: ; +return 26; +} +unsigned long CPUFUNC(op_91b8_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2790; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2790: ; +return 24; +} +unsigned long CPUFUNC(op_91b9_5)(uint32_t opcode) /* SUB */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 7; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2791; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel2791: ; +return 28; +} +unsigned long CPUFUNC(op_91c0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_91c8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_91d0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2794; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2794: ; +return 14; +} +unsigned long CPUFUNC(op_91d8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2795; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2795: ; +return 14; +} +unsigned long CPUFUNC(op_91e0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2796; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2796: ; +return 16; +} +unsigned long CPUFUNC(op_91e8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2797; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2797: ; +return 18; +} +unsigned long CPUFUNC(op_91f0_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2798; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2798: ; +return 20; +} +unsigned long CPUFUNC(op_91f8_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2799; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2799: ; +return 18; +} +unsigned long CPUFUNC(op_91f9_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2800; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2800: ; +return 22; +} +unsigned long CPUFUNC(op_91fa_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2801; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2801: ; +return 18; +} +unsigned long CPUFUNC(op_91fb_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2802; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2802: ; +return 20; +} +unsigned long CPUFUNC(op_91fc_5)(uint32_t opcode) /* SUBA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 8; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst - src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_b000_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_b010_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_b018_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_b020_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_b028_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_b030_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_b038_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_b039_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_b03a_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_b03b_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +#endif + +#ifdef PART_7 +unsigned long CPUFUNC(op_b03c_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_b040_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_b048_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_b050_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2817; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2817: ; +return 8; +} +unsigned long CPUFUNC(op_b058_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2818; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2818: ; +return 8; +} +unsigned long CPUFUNC(op_b060_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2819; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2819: ; +return 10; +} +unsigned long CPUFUNC(op_b068_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2820; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2820: ; +return 12; +} +unsigned long CPUFUNC(op_b070_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2821; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2821: ; +return 14; +} +unsigned long CPUFUNC(op_b078_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2822; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2822: ; +return 12; +} +unsigned long CPUFUNC(op_b079_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2823; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2823: ; +return 16; +} +unsigned long CPUFUNC(op_b07a_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2824; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2824: ; +return 12; +} +unsigned long CPUFUNC(op_b07b_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2825; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2825: ; +return 14; +} +unsigned long CPUFUNC(op_b07c_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_b080_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b088_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b090_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2829; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2829: ; +return 14; +} +unsigned long CPUFUNC(op_b098_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2830; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2830: ; +return 14; +} +unsigned long CPUFUNC(op_b0a0_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2831; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2831: ; +return 16; +} +unsigned long CPUFUNC(op_b0a8_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2832; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2832: ; +return 18; +} +unsigned long CPUFUNC(op_b0b0_5)(uint32_t opcode) /* CMP */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2833; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2833: ; +return 20; +} +unsigned long CPUFUNC(op_b0b8_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2834; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2834: ; +return 18; +} +unsigned long CPUFUNC(op_b0b9_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2835; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2835: ; +return 22; +} +unsigned long CPUFUNC(op_b0ba_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2836; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2836: ; +return 18; +} +unsigned long CPUFUNC(op_b0bb_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2837; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2837: ; +return 20; +} +unsigned long CPUFUNC(op_b0bc_5)(uint32_t opcode) /* CMP */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 25; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_b0c0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b0c8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b0d0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2841; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2841: ; +return 10; +} +unsigned long CPUFUNC(op_b0d8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2842; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2842: ; +return 10; +} +unsigned long CPUFUNC(op_b0e0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2843; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2843: ; +return 12; +} +unsigned long CPUFUNC(op_b0e8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2844; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2844: ; +return 14; +} +unsigned long CPUFUNC(op_b0f0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2845; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2845: ; +return 16; +} +unsigned long CPUFUNC(op_b0f8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2846; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2846: ; +return 14; +} +unsigned long CPUFUNC(op_b0f9_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2847; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2847: ; +return 18; +} +unsigned long CPUFUNC(op_b0fa_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2848; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2848: ; +return 14; +} +unsigned long CPUFUNC(op_b0fb_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2849; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2849: ; +return 16; +} +unsigned long CPUFUNC(op_b0fc_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 10; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 10; +} +unsigned long CPUFUNC(op_b100_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_b108_5)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 12; +} +unsigned long CPUFUNC(op_b110_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_b118_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_b120_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_b128_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_b130_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_b138_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_b139_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_b140_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_b148_5)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2861; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2861; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2861: ; +return 12; +} +unsigned long CPUFUNC(op_b150_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2862; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2862: ; +return 12; +} +unsigned long CPUFUNC(op_b158_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2863; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2863: ; +return 12; +} +unsigned long CPUFUNC(op_b160_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2864; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2864: ; +return 14; +} +unsigned long CPUFUNC(op_b168_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2865; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2865: ; +return 16; +} +unsigned long CPUFUNC(op_b170_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2866; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2866: ; +return 18; +} +unsigned long CPUFUNC(op_b178_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2867; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2867: ; +return 16; +} +unsigned long CPUFUNC(op_b179_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2868; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2868: ; +return 20; +} +unsigned long CPUFUNC(op_b180_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_b188_5)(uint32_t opcode) /* CMPM */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 26; CurrentInstrCycles = 20; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2870; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2870; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2870: ; +return 20; +} +unsigned long CPUFUNC(op_b190_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2871; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2871: ; +return 20; +} +unsigned long CPUFUNC(op_b198_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2872; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2872: ; +return 20; +} +unsigned long CPUFUNC(op_b1a0_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2873; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2873: ; +return 22; +} +unsigned long CPUFUNC(op_b1a8_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2874; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2874: ; +return 24; +} +unsigned long CPUFUNC(op_b1b0_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 3; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2875; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2875: ; +return 26; +} +unsigned long CPUFUNC(op_b1b8_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2876; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2876: ; +return 24; +} +unsigned long CPUFUNC(op_b1b9_5)(uint32_t opcode) /* EOR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 3; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2877; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src ^= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2877: ; +return 28; +} +unsigned long CPUFUNC(op_b1c0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b1c8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_b1d0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2880; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2880: ; +return 14; +} +unsigned long CPUFUNC(op_b1d8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2881; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2881: ; +return 14; +} +unsigned long CPUFUNC(op_b1e0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2882; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2882: ; +return 16; +} +unsigned long CPUFUNC(op_b1e8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2883; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2883: ; +return 18; +} +unsigned long CPUFUNC(op_b1f0_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2884; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2884: ; +return 20; +} +unsigned long CPUFUNC(op_b1f8_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2885; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2885: ; +return 18; +} +unsigned long CPUFUNC(op_b1f9_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2886; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2886: ; +return 22; +} +unsigned long CPUFUNC(op_b1fa_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2887; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2887: ; +return 18; +} +unsigned long CPUFUNC(op_b1fb_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2888; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2888: ; +return 20; +} +unsigned long CPUFUNC(op_b1fc_5)(uint32_t opcode) /* CMPA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 27; CurrentInstrCycles = 14; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs != flgo) && (flgn != flgo)); + SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); + SET_NFLG (flgn != 0); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_c000_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_c010_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_c018_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_c020_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_c028_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_c030_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_c038_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_c039_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_c03a_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_c03b_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_c03c_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_c040_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_c050_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2902; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2902: ; +return 8; +} +unsigned long CPUFUNC(op_c058_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2903; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2903: ; +return 8; +} +unsigned long CPUFUNC(op_c060_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2904; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2904: ; +return 10; +} +unsigned long CPUFUNC(op_c068_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2905; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2905: ; +return 12; +} +unsigned long CPUFUNC(op_c070_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2906; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2906: ; +return 14; +} +unsigned long CPUFUNC(op_c078_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2907; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2907: ; +return 12; +} +unsigned long CPUFUNC(op_c079_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2908; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2908: ; +return 16; +} +unsigned long CPUFUNC(op_c07a_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2909; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2909: ; +return 12; +} +unsigned long CPUFUNC(op_c07b_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2910; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2910: ; +return 14; +} +unsigned long CPUFUNC(op_c07c_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); +}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_c080_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_c090_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2913; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2913: ; +return 14; +} +unsigned long CPUFUNC(op_c098_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2914; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2914: ; +return 14; +} +unsigned long CPUFUNC(op_c0a0_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2915; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2915: ; +return 16; +} +unsigned long CPUFUNC(op_c0a8_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2916; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2916: ; +return 18; +} +unsigned long CPUFUNC(op_c0b0_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2917; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2917: ; +return 20; +} +unsigned long CPUFUNC(op_c0b8_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2918; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2918: ; +return 18; +} +unsigned long CPUFUNC(op_c0b9_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2919; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2919: ; +return 22; +} +unsigned long CPUFUNC(op_c0ba_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2920; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2920: ; +return 18; +} +unsigned long CPUFUNC(op_c0bb_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2921; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2921: ; +return 20; +} +unsigned long CPUFUNC(op_c0bc_5)(uint32_t opcode) /* AND */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_c0c0_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 38; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (38+retcycles*2); +} +unsigned long CPUFUNC(op_c0d0_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2924; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2924: ; + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c0d8_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2925; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2925: ; + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c0e0_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 44; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2926; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2926: ; + return (44+retcycles*2); +} +unsigned long CPUFUNC(op_c0e8_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2927; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2927: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0f0_5)(uint32_t opcode) /* MULU */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 48; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2928; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2928: ; + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c0f8_5)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2929; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2929: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0f9_5)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 50; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2930; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2930: ; + return (50+retcycles*2); +} +unsigned long CPUFUNC(op_c0fa_5)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2931; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2931: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c0fb_5)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 48; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2932; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2932: ; + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c0fc_5)(uint32_t opcode) /* MULU */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 62; CurrentInstrCycles = 42; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } +}}}}m68k_incpc(4); +fill_prefetch_0 (); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c100_5)(uint32_t opcode) /* ABCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 14; CurrentInstrCycles = 6; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); + uint16_t newv, tmp_newv; + int cflg; + newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } + cflg = (newv & 0x3F0) > 0x90; + if (cflg) newv += 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_c108_5)(uint32_t opcode) /* ABCD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 14; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); + uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); + uint16_t newv, tmp_newv; + int cflg; + newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } + cflg = (newv & 0x3F0) > 0x90; + if (cflg) newv += 0x60; + SET_CFLG (cflg); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}return 18; +} +unsigned long CPUFUNC(op_c110_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_c118_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 12; +} +unsigned long CPUFUNC(op_c120_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,src); +}}}}return 14; +} +unsigned long CPUFUNC(op_c128_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_c130_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 18; +} +unsigned long CPUFUNC(op_c138_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 16; +} +unsigned long CPUFUNC(op_c139_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int8_t)(src)) == 0); + SET_NFLG (((int8_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,src); +}}}}return 20; +} +unsigned long CPUFUNC(op_c140_5)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); + m68k_dreg(regs, srcreg) = (dst); + m68k_dreg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_c148_5)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); + m68k_areg(regs, srcreg) = (dst); + m68k_areg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_c150_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2945; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2945: ; +return 12; +} +unsigned long CPUFUNC(op_c158_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2946; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2946: ; +return 12; +} +unsigned long CPUFUNC(op_c160_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2947; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2947: ; +return 14; +} +unsigned long CPUFUNC(op_c168_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2948; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2948: ; +return 16; +} +unsigned long CPUFUNC(op_c170_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2949; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2949: ; +return 18; +} +unsigned long CPUFUNC(op_c178_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2950; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2950: ; +return 16; +} +unsigned long CPUFUNC(op_c179_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2951; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(src)) == 0); + SET_NFLG (((int16_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,src); +}}}}}endlabel2951: ; +return 20; +} +unsigned long CPUFUNC(op_c188_5)(uint32_t opcode) /* EXG */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 35; CurrentInstrCycles = 6; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); + m68k_dreg(regs, srcreg) = (dst); + m68k_areg(regs, dstreg) = (src); +}}}m68k_incpc(2); +fill_prefetch_2 (); +return 6; +} +unsigned long CPUFUNC(op_c190_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2953; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2953: ; +return 20; +} +unsigned long CPUFUNC(op_c198_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2954; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2954: ; +return 20; +} +unsigned long CPUFUNC(op_c1a0_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2955; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2955: ; +return 22; +} +unsigned long CPUFUNC(op_c1a8_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2956; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2956: ; +return 24; +} +unsigned long CPUFUNC(op_c1b0_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 2; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2957; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2957: ; +return 26; +} +unsigned long CPUFUNC(op_c1b8_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2958; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2958: ; +return 24; +} +unsigned long CPUFUNC(op_c1b9_5)(uint32_t opcode) /* AND */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 2; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2959; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + src &= dst; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(src)) == 0); + SET_NFLG (((int32_t)(src)) < 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,src); +}}}}}endlabel2959: ; +return 28; +} +unsigned long CPUFUNC(op_c1c0_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 38; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (38+retcycles*2); +} +unsigned long CPUFUNC(op_c1d0_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2961; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2961: ; + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c1d8_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2962; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2962: ; + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_c1e0_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 44; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2963; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2963: ; + return (44+retcycles*2); +} +unsigned long CPUFUNC(op_c1e8_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2964; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2964: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1f0_5)(uint32_t opcode) /* MULS */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 48; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2965; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2965: ; + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c1f8_5)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2966; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2966: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1f9_5)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 50; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2967; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2967: ; + return (50+retcycles*2); +} +unsigned long CPUFUNC(op_c1fa_5)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 46; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2968; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2968: ; + return (46+retcycles*2); +} +unsigned long CPUFUNC(op_c1fb_5)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 48; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2969; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2969: ; + return (48+retcycles*2); +} +unsigned long CPUFUNC(op_c1fc_5)(uint32_t opcode) /* MULS */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + unsigned int retcycles = 0; + OpcodeFamily = 63; CurrentInstrCycles = 42; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; + uint32_t src2; + CLEAR_CZNV; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); + src2 = ((uint32_t)src) << 1; + while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } +}}}}m68k_incpc(4); +fill_prefetch_0 (); + return (42+retcycles*2); +} +unsigned long CPUFUNC(op_d000_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_d010_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d018_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d020_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 10; +} +unsigned long CPUFUNC(op_d028_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_d030_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_d038_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_d039_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_d03a_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_d03b_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t src = m68k_read_memory_8(srca); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 14; +} +unsigned long CPUFUNC(op_d03c_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int8_t src = get_ibyte_prefetch(2); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_d040_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_d048_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 4; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_d050_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2984; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2984: ; +return 8; +} +unsigned long CPUFUNC(op_d058_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2985; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2985: ; +return 8; +} +unsigned long CPUFUNC(op_d060_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 10; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2986; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2986: ; +return 10; +} +unsigned long CPUFUNC(op_d068_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2987; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2987: ; +return 12; +} +unsigned long CPUFUNC(op_d070_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2988; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2988: ; +return 14; +} +unsigned long CPUFUNC(op_d078_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2989; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2989: ; +return 12; +} +unsigned long CPUFUNC(op_d079_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2990; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel2990: ; +return 16; +} +unsigned long CPUFUNC(op_d07a_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2991; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2991: ; +return 12; +} +unsigned long CPUFUNC(op_d07b_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2992; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2992: ; +return 14; +} +unsigned long CPUFUNC(op_d07c_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int16_t src = get_iword_prefetch(2); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 8; +} +unsigned long CPUFUNC(op_d080_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d088_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d090_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2996; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2996: ; +return 14; +} +unsigned long CPUFUNC(op_d098_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2997; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2997: ; +return 14; +} +unsigned long CPUFUNC(op_d0a0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2998; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel2998: ; +return 16; +} +unsigned long CPUFUNC(op_d0a8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel2999; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel2999: ; +return 18; +} +unsigned long CPUFUNC(op_d0b0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3000; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3000: ; +return 20; +} +unsigned long CPUFUNC(op_d0b8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3001; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3001: ; +return 18; +} +unsigned long CPUFUNC(op_d0b9_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3002; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel3002: ; +return 22; +} +unsigned long CPUFUNC(op_d0ba_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3003; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3003: ; +return 18; +} +unsigned long CPUFUNC(op_d0bb_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3004; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3004: ; +return 20; +} +unsigned long CPUFUNC(op_d0bc_5)(uint32_t opcode) /* ADD */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_d0c0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d0c8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int16_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d0d0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3008; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3008: ; +return 12; +} +unsigned long CPUFUNC(op_d0d8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3009; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg(regs, srcreg) += 2; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3009: ; +return 12; +} +unsigned long CPUFUNC(op_d0e0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3010; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3010: ; +return 14; +} +unsigned long CPUFUNC(op_d0e8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3011; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3011: ; +return 16; +} +unsigned long CPUFUNC(op_d0f0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3012; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3012: ; +return 18; +} +unsigned long CPUFUNC(op_d0f8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3013; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3013: ; +return 16; +} +unsigned long CPUFUNC(op_d0f9_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3014; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel3014: ; +return 20; +} +unsigned long CPUFUNC(op_d0fa_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3015; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3015: ; +return 16; +} +unsigned long CPUFUNC(op_d0fb_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3016; + } +{{ int16_t src = m68k_read_memory_16(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3016: ; +return 18; +} +unsigned long CPUFUNC(op_d0fc_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 12; +{{ int16_t src = get_iword_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(4); +fill_prefetch_0 (); +return 12; +} +unsigned long CPUFUNC(op_d100_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 4; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ int8_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_d108_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; +{ int8_t src = m68k_read_memory_8(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); + SET_NFLG (((int8_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_d110_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_d118_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 12; +} +unsigned long CPUFUNC(op_d120_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; +{ int8_t dst = m68k_read_memory_8(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 14; +} +unsigned long CPUFUNC(op_d128_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_d130_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 18; +} +unsigned long CPUFUNC(op_d138_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 16; +} +unsigned long CPUFUNC(op_d139_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int8_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); +{ int8_t dst = m68k_read_memory_8(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); +{ int flgs = ((int8_t)(src)) < 0; + int flgo = ((int8_t)(dst)) < 0; + int flgn = ((int8_t)(newv)) < 0; + SET_ZFLG (((int8_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_8(dsta,newv); +}}}}}}}return 20; +} +unsigned long CPUFUNC(op_d140_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 4; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ int16_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 4; +} +unsigned long CPUFUNC(op_d148_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3028; + } +{{ int16_t src = m68k_read_memory_16(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3028; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); + SET_NFLG (((int16_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}}endlabel3028: ; +return 18; +} +unsigned long CPUFUNC(op_d150_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3029; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3029: ; +return 12; +} +unsigned long CPUFUNC(op_d158_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 12; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3030; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg(regs, dstreg) += 2; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3030: ; +return 12; +} +unsigned long CPUFUNC(op_d160_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 14; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3031; + } +{{ int16_t dst = m68k_read_memory_16(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3031: ; +return 14; +} +unsigned long CPUFUNC(op_d168_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3032; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3032: ; +return 16; +} +unsigned long CPUFUNC(op_d170_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 18; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3033; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3033: ; +return 18; +} +unsigned long CPUFUNC(op_d178_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 16; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3034; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3034: ; +return 16; +} +unsigned long CPUFUNC(op_d179_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int16_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3035; + } +{{ int16_t dst = m68k_read_memory_16(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); +{ int flgs = ((int16_t)(src)) < 0; + int flgo = ((int16_t)(dst)) < 0; + int flgn = ((int16_t)(newv)) < 0; + SET_ZFLG (((int16_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dsta,newv); +}}}}}}}}endlabel3035: ; +return 20; +} +unsigned long CPUFUNC(op_d180_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_dreg(regs, dstreg); +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); + m68k_dreg(regs, dstreg) = (newv); +}}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d188_5)(uint32_t opcode) /* ADDX */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 13; CurrentInstrCycles = 30; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3037; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3037; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); + COPY_CARRY; + SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); + SET_NFLG (((int32_t)(newv)) < 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}}endlabel3037: ; +return 30; +} +unsigned long CPUFUNC(op_d190_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3038; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3038: ; +return 20; +} +unsigned long CPUFUNC(op_d198_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 20; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3039; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg(regs, dstreg) += 4; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3039: ; +return 20; +} +unsigned long CPUFUNC(op_d1a0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 22; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) - 4; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3040; + } +{{ int32_t dst = m68k_read_memory_32(dsta); + m68k_areg (regs, dstreg) = dsta; +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3040: ; +return 22; +} +unsigned long CPUFUNC(op_d1a8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3041; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3041: ; +return 24; +} +unsigned long CPUFUNC(op_d1b0_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + OpcodeFamily = 11; CurrentInstrCycles = 26; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3042; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3042: ; +return 26; +} +unsigned long CPUFUNC(op_d1b8_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 24; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3043; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3043: ; +return 24; +} +unsigned long CPUFUNC(op_d1b9_5)(uint32_t opcode) /* ADD */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + OpcodeFamily = 11; CurrentInstrCycles = 28; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ uint32_t dsta = get_ilong_prefetch(2); + if ((dsta & 1) != 0) { + last_fault_for_exception_3 = dsta; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3044; + } +{{ int32_t dst = m68k_read_memory_32(dsta); +{ refill_prefetch (m68k_getpc(), 2); +{uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); +{ int flgs = ((int32_t)(src)) < 0; + int flgo = ((int32_t)(dst)) < 0; + int flgn = ((int32_t)(newv)) < 0; + SET_ZFLG (((int32_t)(newv)) == 0); + SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); + SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); + COPY_CARRY; + SET_NFLG (flgn != 0); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_32(dsta,newv); +}}}}}}}}endlabel3044: ; +return 28; +} +unsigned long CPUFUNC(op_d1c0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int32_t src = m68k_dreg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d1c8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 8; +{{ int32_t src = m68k_areg(regs, srcreg); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(2); +fill_prefetch_2 (); +return 8; +} +unsigned long CPUFUNC(op_d1d0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3047; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3047: ; +return 14; +} +#endif + +#ifdef PART_8 +unsigned long CPUFUNC(op_d1d8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 14; +{{ uint32_t srca = m68k_areg(regs, srcreg); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3048; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg(regs, srcreg) += 4; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3048: ; +return 14; +} +unsigned long CPUFUNC(op_d1e0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ uint32_t srca = m68k_areg(regs, srcreg) - 4; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3049; + } +{{ int32_t src = m68k_read_memory_32(srca); + m68k_areg (regs, srcreg) = srca; +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(2); +fill_prefetch_2 (); +endlabel3049: ; +return 16; +} +unsigned long CPUFUNC(op_d1e8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3050; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3050: ; +return 18; +} +unsigned long CPUFUNC(op_d1f0_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t srcreg = (opcode & 7); + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3051; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3051: ; +return 20; +} +unsigned long CPUFUNC(op_d1f8_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3052; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3052: ; +return 18; +} +unsigned long CPUFUNC(op_d1f9_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 22; +{{ uint32_t srca = get_ilong_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3053; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(6); +fill_prefetch_0 (); +endlabel3053: ; +return 22; +} +unsigned long CPUFUNC(op_d1fa_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 18; +{{ uint32_t srca = m68k_getpc () + 2; + srca += (int32_t)(int16_t)get_iword_prefetch(2); + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3054; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3054: ; +return 18; +} +unsigned long CPUFUNC(op_d1fb_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 20; +{{ uint32_t tmppc = m68k_getpc() + 2; + uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((srca & 1) != 0) { + last_fault_for_exception_3 = srca; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3055; + } +{{ int32_t src = m68k_read_memory_32(srca); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}}}m68k_incpc(4); +fill_prefetch_0 (); +endlabel3055: ; +return 20; +} +unsigned long CPUFUNC(op_d1fc_5)(uint32_t opcode) /* ADDA */ +{ + uint32_t dstreg = (opcode >> 9) & 7; + OpcodeFamily = 12; CurrentInstrCycles = 16; +{{ int32_t src = get_ilong_prefetch(2); +{ int32_t dst = m68k_areg(regs, dstreg); +{ uint32_t newv = dst + src; + m68k_areg(regs, dstreg) = (newv); +}}}}m68k_incpc(6); +fill_prefetch_0 (); +return 16; +} +unsigned long CPUFUNC(op_e000_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + uint32_t sign = (0x80 & val) >> 7; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + val = 0xff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xff << (8 - cnt)) & (uint32_t)-sign; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e008_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG ((cnt == 8) & (val >> 7)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e010_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (7 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e018_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 7; + hival = val << (8 - cnt); + val >>= cnt; + val |= hival; + val &= 0xff; + SET_CFLG ((val & 0x80) >> 7); + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e020_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + uint32_t sign = (0x80 & val) >> 7; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + val = 0xff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xff << (8 - cnt)) & (uint32_t)-sign; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e028_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG ((cnt == 8) & (val >> 7)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e030_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 36) cnt -= 36; + if (cnt >= 18) cnt -= 18; + if (cnt >= 9) cnt -= 9; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (7 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e038_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 7; + hival = val << (8 - cnt); + val >>= cnt; + val |= hival; + val &= 0xff; + SET_CFLG ((val & 0x80) >> 7); + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e040_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + uint32_t sign = (0x8000 & val) >> 15; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + val = 0xffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e048_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG ((cnt == 16) & (val >> 15)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e050_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (15 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e058_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 15; + hival = val << (16 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffff; + SET_CFLG ((val & 0x8000) >> 15); + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e060_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + uint32_t sign = (0x8000 & val) >> 15; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + val = 0xffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e068_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG ((cnt == 16) & (val >> 15)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e070_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 34) cnt -= 34; + if (cnt >= 17) cnt -= 17; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (15 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e078_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 15; + hival = val << (16 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffff; + SET_CFLG ((val & 0x8000) >> 15); + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e080_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + uint32_t sign = (0x80000000 & val) >> 31; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + val = 0xffffffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e088_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG ((cnt == 32) & (val >> 31)); + COPY_CARRY; + val = 0; + } else { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e090_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (31 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e098_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t hival; + cnt &= 31; + hival = val << (32 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffffffff; + SET_CFLG ((val & 0x80000000) >> 31); + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0a0_5)(uint32_t opcode) /* ASR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 64; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + uint32_t sign = (0x80000000 & val) >> 31; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + val = 0xffffffff & (uint32_t)-sign; + SET_CFLG (sign); + COPY_CARRY; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0a8_5)(uint32_t opcode) /* LSR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 66; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG ((cnt == 32) & (val >> 31)); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val >>= cnt - 1; + SET_CFLG (val & 1); + COPY_CARRY; + val >>= 1; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0b0_5)(uint32_t opcode) /* ROXR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 71; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 33) cnt -= 33; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t hival = (val << 1) | GET_XFLG; + hival <<= (31 - cnt); + val >>= cnt; + carry = val & 1; + val >>= 1; + val |= hival; + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0b8_5)(uint32_t opcode) /* ROR */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 69; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { uint32_t hival; + cnt &= 31; + hival = val << (32 - cnt); + val >>= cnt; + val |= hival; + val &= 0xffffffff; + SET_CFLG ((val & 0x80000000) >> 31); + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e0d0_5)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3081; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3081: ; +return 12; +} +unsigned long CPUFUNC(op_e0d8_5)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3082; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3082: ; +return 12; +} +unsigned long CPUFUNC(op_e0e0_5)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3083; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3083: ; +return 14; +} +unsigned long CPUFUNC(op_e0e8_5)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3084; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3084: ; +return 16; +} +unsigned long CPUFUNC(op_e0f0_5)(uint32_t opcode) /* ASRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 72; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3085; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3085: ; +return 18; +} +unsigned long CPUFUNC(op_e0f8_5)(uint32_t opcode) /* ASRW */ +{ + OpcodeFamily = 72; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3086; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3086: ; +return 16; +} +unsigned long CPUFUNC(op_e0f9_5)(uint32_t opcode) /* ASRW */ +{ + OpcodeFamily = 72; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3087; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t cflg = val & 1; + val = (val >> 1) | sign; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + SET_CFLG (cflg); + COPY_CARRY; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3087: ; +return 20; +} +unsigned long CPUFUNC(op_e100_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xff << (7 - cnt)) & 0xff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e108_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e110_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (7 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e118_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 7; + loval = val >> (8 - cnt); + val <<= cnt; + val |= loval; + val &= 0xff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e120_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xff << (7 - cnt)) & 0xff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e128_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 8) { + SET_CFLG (cnt == 8 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80) >> 7); + COPY_CARRY; + val <<= 1; + val &= 0xff; + } + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e130_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 36) cnt -= 36; + if (cnt >= 18) cnt -= 18; + if (cnt >= 9) cnt -= 9; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (7 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e138_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int8_t cnt = m68k_dreg(regs, srcreg); +{ int8_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint8_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 7; + loval = val >> (8 - cnt); + val <<= cnt; + val |= loval; + val &= 0xff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int8_t)(val)) == 0); + SET_NFLG (((int8_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e140_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e148_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e150_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (15 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e158_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 15; + loval = val >> (16 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e160_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e168_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 16) { + SET_CFLG (cnt == 16 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x8000) >> 15); + COPY_CARRY; + val <<= 1; + val &= 0xffff; + } + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e170_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 34) cnt -= 34; + if (cnt >= 17) cnt -= 17; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (15 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e178_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int16_t cnt = m68k_dreg(regs, srcreg); +{ int16_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = (uint16_t)data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 15; + loval = val >> (16 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (6+retcycles*2); +} +unsigned long CPUFUNC(op_e180_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e188_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e190_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ cnt--; + { + uint32_t carry; + uint32_t loval = val >> (31 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e198_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ uint32_t cnt = srcreg; +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; +{ uint32_t loval; + cnt &= 31; + loval = val >> (32 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffffffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1a0_5)(uint32_t opcode) /* ASL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 65; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_VFLG (val != 0); + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; + SET_VFLG ((val & mask) != mask && (val & mask) != 0); + val <<= cnt - 1; + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1a8_5)(uint32_t opcode) /* LSL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 67; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 32) { + SET_CFLG (cnt == 32 ? val & 1 : 0); + COPY_CARRY; + val = 0; + } else if (cnt > 0) { + val <<= (cnt - 1); + SET_CFLG ((val & 0x80000000) >> 31); + COPY_CARRY; + val <<= 1; + val &= 0xffffffff; + } + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1b0_5)(uint32_t opcode) /* ROXL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 70; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt >= 33) cnt -= 33; + if (cnt > 0) { + cnt--; + { + uint32_t carry; + uint32_t loval = val >> (31 - cnt); + carry = loval & 1; + val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); + SET_XFLG (carry); + val &= 0xffffffff; + } } + SET_CFLG (GET_XFLG); + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1b8_5)(uint32_t opcode) /* ROL */ +{ + uint32_t srcreg = ((opcode >> 9) & 7); + uint32_t dstreg = opcode & 7; + unsigned int retcycles = 0; + OpcodeFamily = 68; CurrentInstrCycles = 4; +{{ int32_t cnt = m68k_dreg(regs, srcreg); +{ int32_t data = m68k_dreg(regs, dstreg); +{ uint32_t val = data; + cnt &= 63; + retcycles = cnt; + CLEAR_CZNV; + if (cnt > 0) { + uint32_t loval; + cnt &= 31; + loval = val >> (32 - cnt); + val <<= cnt; + val |= loval; + val &= 0xffffffff; + SET_CFLG (val & 1); +} + SET_ZFLG (((int32_t)(val)) == 0); + SET_NFLG (((int32_t)(val)) < 0); + m68k_dreg(regs, dstreg) = (val); +}}}}m68k_incpc(2); +fill_prefetch_2 (); + return (8+retcycles*2); +} +unsigned long CPUFUNC(op_e1d0_5)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3112; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3112: ; +return 12; +} +unsigned long CPUFUNC(op_e1d8_5)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3113; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3113: ; +return 12; +} +unsigned long CPUFUNC(op_e1e0_5)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3114; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3114: ; +return 14; +} +unsigned long CPUFUNC(op_e1e8_5)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3115; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3115: ; +return 16; +} +unsigned long CPUFUNC(op_e1f0_5)(uint32_t opcode) /* ASLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 73; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3116; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3116: ; +return 18; +} +unsigned long CPUFUNC(op_e1f8_5)(uint32_t opcode) /* ASLW */ +{ + OpcodeFamily = 73; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3117; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3117: ; +return 16; +} +unsigned long CPUFUNC(op_e1f9_5)(uint32_t opcode) /* ASLW */ +{ + OpcodeFamily = 73; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3118; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t sign = 0x8000 & val; + uint32_t sign2; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); + sign2 = 0x8000 & val; + SET_CFLG (sign != 0); + COPY_CARRY; + SET_VFLG (GET_VFLG | (sign2 != sign)); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3118: ; +return 20; +} +unsigned long CPUFUNC(op_e2d0_5)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3119; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3119: ; +return 12; +} +unsigned long CPUFUNC(op_e2d8_5)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3120; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3120: ; +return 12; +} +unsigned long CPUFUNC(op_e2e0_5)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3121; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3121: ; +return 14; +} +unsigned long CPUFUNC(op_e2e8_5)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3122; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3122: ; +return 16; +} +unsigned long CPUFUNC(op_e2f0_5)(uint32_t opcode) /* LSRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 74; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3123; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3123: ; +return 18; +} +unsigned long CPUFUNC(op_e2f8_5)(uint32_t opcode) /* LSRW */ +{ + OpcodeFamily = 74; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3124; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3124: ; +return 16; +} +unsigned long CPUFUNC(op_e2f9_5)(uint32_t opcode) /* LSRW */ +{ + OpcodeFamily = 74; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3125; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint32_t val = (uint16_t)data; + uint32_t carry = val & 1; + val >>= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3125: ; +return 20; +} +unsigned long CPUFUNC(op_e3d0_5)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3126; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3126: ; +return 12; +} +unsigned long CPUFUNC(op_e3d8_5)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3127; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3127: ; +return 12; +} +unsigned long CPUFUNC(op_e3e0_5)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3128; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3128: ; +return 14; +} +unsigned long CPUFUNC(op_e3e8_5)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3129; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3129: ; +return 16; +} +unsigned long CPUFUNC(op_e3f0_5)(uint32_t opcode) /* LSLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 75; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3130; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3130: ; +return 18; +} +unsigned long CPUFUNC(op_e3f8_5)(uint32_t opcode) /* LSLW */ +{ + OpcodeFamily = 75; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3131; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3131: ; +return 16; +} +unsigned long CPUFUNC(op_e3f9_5)(uint32_t opcode) /* LSLW */ +{ + OpcodeFamily = 75; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3132; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3132: ; +return 20; +} +unsigned long CPUFUNC(op_e4d0_5)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3133; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3133: ; +return 12; +} +unsigned long CPUFUNC(op_e4d8_5)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3134; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3134: ; +return 12; +} +unsigned long CPUFUNC(op_e4e0_5)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3135; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3135: ; +return 14; +} +unsigned long CPUFUNC(op_e4e8_5)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3136; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3136: ; +return 16; +} +unsigned long CPUFUNC(op_e4f0_5)(uint32_t opcode) /* ROXRW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 79; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3137; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3137: ; +return 18; +} +unsigned long CPUFUNC(op_e4f8_5)(uint32_t opcode) /* ROXRW */ +{ + OpcodeFamily = 79; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3138; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3138: ; +return 16; +} +unsigned long CPUFUNC(op_e4f9_5)(uint32_t opcode) /* ROXRW */ +{ + OpcodeFamily = 79; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3139; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (GET_XFLG) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); + COPY_CARRY; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3139: ; +return 20; +} +unsigned long CPUFUNC(op_e5d0_5)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3140; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3140: ; +return 12; +} +unsigned long CPUFUNC(op_e5d8_5)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3141; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3141: ; +return 12; +} +unsigned long CPUFUNC(op_e5e0_5)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3142; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3142: ; +return 14; +} +unsigned long CPUFUNC(op_e5e8_5)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3143; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3143: ; +return 16; +} +unsigned long CPUFUNC(op_e5f0_5)(uint32_t opcode) /* ROXLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 78; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3144; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3144: ; +return 18; +} +unsigned long CPUFUNC(op_e5f8_5)(uint32_t opcode) /* ROXLW */ +{ + OpcodeFamily = 78; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3145; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3145: ; +return 16; +} +unsigned long CPUFUNC(op_e5f9_5)(uint32_t opcode) /* ROXLW */ +{ + OpcodeFamily = 78; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3146; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (GET_XFLG) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); + COPY_CARRY; +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3146: ; +return 20; +} +unsigned long CPUFUNC(op_e6d0_5)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3147; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3147: ; +return 12; +} +unsigned long CPUFUNC(op_e6d8_5)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3148; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3148: ; +return 12; +} +unsigned long CPUFUNC(op_e6e0_5)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3149; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3149: ; +return 14; +} +unsigned long CPUFUNC(op_e6e8_5)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3150; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3150: ; +return 16; +} +unsigned long CPUFUNC(op_e6f0_5)(uint32_t opcode) /* RORW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 77; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3151; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3151: ; +return 18; +} +unsigned long CPUFUNC(op_e6f8_5)(uint32_t opcode) /* RORW */ +{ + OpcodeFamily = 77; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3152; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3152: ; +return 16; +} +unsigned long CPUFUNC(op_e6f9_5)(uint32_t opcode) /* RORW */ +{ + OpcodeFamily = 77; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3153; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 1; + val >>= 1; + if (carry) val |= 0x8000; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3153: ; +return 20; +} +unsigned long CPUFUNC(op_e7d0_5)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3154; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3154: ; +return 12; +} +unsigned long CPUFUNC(op_e7d8_5)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 12; +{{ uint32_t dataa = m68k_areg(regs, srcreg); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3155; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg(regs, srcreg) += 2; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3155: ; +return 12; +} +unsigned long CPUFUNC(op_e7e0_5)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 14; +{{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 2; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3156; + } +{{ int16_t data = m68k_read_memory_16(dataa); + m68k_areg (regs, srcreg) = dataa; +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(2); +fill_prefetch_2 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3156: ; +return 14; +} +unsigned long CPUFUNC(op_e7e8_5)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 16; +{{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3157; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3157: ; +return 16; +} +unsigned long CPUFUNC(op_e7f0_5)(uint32_t opcode) /* ROLW */ +{ + uint32_t srcreg = (opcode & 7); + OpcodeFamily = 76; CurrentInstrCycles = 18; +{{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); + BusCyclePenalty += 2; + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3158; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3158: ; +return 18; +} +unsigned long CPUFUNC(op_e7f8_5)(uint32_t opcode) /* ROLW */ +{ + OpcodeFamily = 76; CurrentInstrCycles = 16; +{{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 4; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3159; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(4); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3159: ; +return 16; +} +unsigned long CPUFUNC(op_e7f9_5)(uint32_t opcode) /* ROLW */ +{ + OpcodeFamily = 76; CurrentInstrCycles = 20; +{{ uint32_t dataa = get_ilong_prefetch(2); + if ((dataa & 1) != 0) { + last_fault_for_exception_3 = dataa; + last_op_for_exception_3 = opcode; + last_addr_for_exception_3 = m68k_getpc() + 6; + Exception(3, 0, M68000_EXC_SRC_CPU); + goto endlabel3160; + } +{{ int16_t data = m68k_read_memory_16(dataa); +{ uint16_t val = data; + uint32_t carry = val & 0x8000; + val <<= 1; + if (carry) val |= 1; + CLEAR_CZNV; + SET_ZFLG (((int16_t)(val)) == 0); + SET_NFLG (((int16_t)(val)) < 0); +SET_CFLG (carry >> 15); +m68k_incpc(6); +fill_prefetch_0 (); + m68k_write_memory_16(dataa,val); +}}}}}endlabel3160: ; +return 20; +} +#endif + diff --git a/waterbox/virtualjaguar/src/m68000/cpuextra.c b/waterbox/virtualjaguar/src/m68000/cpuextra.c new file mode 100644 index 0000000000..e98f1da812 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpuextra.c @@ -0,0 +1,509 @@ +// +// Stuff that's neither inline or generated by gencpu.c, but depended upon by +// cpuemu.c. +// +// Originally part of UAE by Bernd Schmidt +// and released under the GPL v2 or later +// + +#include "cpuextra.h" +#include "cpudefs.h" +#include "inlines.h" + + +uint16_t last_op_for_exception_3; // Opcode of faulting instruction +uint32_t last_addr_for_exception_3; // PC at fault time +uint32_t last_fault_for_exception_3; // Address that generated the exception + +int OpcodeFamily; // Used by cpuemu.c... +int BusCyclePenalty = 0; // Used by cpuemu.c... +int CurrentInstrCycles; + +struct regstruct regs; + + +// +// Make displacement effective address for 68000 +// +uint32_t get_disp_ea_000(uint32_t base, uint32_t dp) +{ + int reg = (dp >> 12) & 0x0F; + int32_t regd = regs.regs[reg]; + +#if 1 + if ((dp & 0x800) == 0) + regd = (int32_t)(int16_t)regd; + + return base + (int8_t)dp + regd; +#else + /* Branch-free code... benchmark this again now that + * things are no longer inline. + */ + int32_t regd16; + uint32_t mask; + mask = ((dp & 0x800) >> 11) - 1; + regd16 = (int32_t)(int16_t)regd; + regd16 &= mask; + mask = ~mask; + base += (int8_t)dp; + regd &= mask; + regd |= regd16; + return base + regd; +#endif +} + + +// +// Create the Status Register from the flags +// +void MakeSR(void) +{ + regs.sr = ((regs.s << 13) | (regs.intmask << 8) | (GET_XFLG << 4) + | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1) | GET_CFLG); +} + + +// +// Set up the flags from Status Register +// +void MakeFromSR(void) +{ + int olds = regs.s; + + regs.s = (regs.sr >> 13) & 1; + regs.intmask = (regs.sr >> 8) & 7; + SET_XFLG((regs.sr >> 4) & 1); + SET_NFLG((regs.sr >> 3) & 1); + SET_ZFLG((regs.sr >> 2) & 1); + SET_VFLG((regs.sr >> 1) & 1); + SET_CFLG(regs.sr & 1); + + if (olds != regs.s) + { + if (olds) + { + regs.isp = m68k_areg(regs, 7); + m68k_areg(regs, 7) = regs.usp; + } + else + { + regs.usp = m68k_areg(regs, 7); + m68k_areg(regs, 7) = regs.isp; + } + } + + /* Pending interrupts can occur again after a write to the SR: */ +//JLH: is this needed? +// set_special(SPCFLAG_DOINT); +} + + +// +// Rudimentary exception handling. This is really stripped down from what +// was in Hatari. +/* +NB: Seems that when an address exception occurs, it doesn't get handled properly + as per test1.cof. Need to figure out why it keeps going when it should wedge. :-P +*/ +// +// Handle exceptions. We need a special case to handle MFP exceptions +// on Atari ST, because it's possible to change the MFP's vector base +// and get a conflict with 'normal' cpu exceptions. +// +#if 0 +/* +This is the STOP # function. Dunno if exception handling occurs when it hits here or not, because don't know if the regs.s bit is set or not! +Seems to be... + +SR----------------- +1111 11 +5432 1098 7654 3210 +---- ---- ---- ---- + 1 1 + + +*/ +unsigned long CPUFUNC(op_4e72_5)(uint32_t opcode) /* STOP */ +{ + OpcodeFamily = 44; + CurrentInstrCycles = 4; + + if (!regs.s) + { + Exception(8, 0, M68000_EXC_SRC_CPU); + } + else + { + int16_t src = get_iword_prefetch(2); + regs.sr = src; + MakeFromSR(); + m68k_setstopped(1); + m68k_incpc(4); + fill_prefetch_0(); + } + + return 4; +} +#endif +//tmp... +void WriteLog(const char * text, ...); +void Exception(int nr, uint32_t oldpc, int ExceptionSource) +{ + uint32_t currpc = m68k_getpc(), newpc; + +// Need to figure out how to report this stuff without using printf on stdout :-/ +#if 0 +char excNames[33][64] = { + "???", "???", "Bus Error", "Address Error", + "Illegal Instruction", "Zero Divide", "CHK", "TrapV", + "Privilege Violation", "Trace", "Line A", "Line F", + "???", "???", "Format Error", "Uninitialized Interrupt", + "???", "???", "???", "???", + "???", "???", "???", "???", + "Spurious/Autovector", "???", "???", "???", + "???", "???", "???", "???", + "Trap #" +}; + +WriteLog("Exception #%i occurred! (%s)\n", nr, (nr < 32 ? excNames[nr] : (nr < 48 ? "Trap #" : "????"))); +WriteLog("Vector @ #%i = %08X\n", nr, m68k_read_memory_32(nr * 4)); +//abort(); +WriteLog("PC = $%08X\n", currpc); +WriteLog("A0 = $%08X A1 = $%08X A2 = $%08X A3 = $%08X\n", m68k_areg(regs, 0), m68k_areg(regs, 1), m68k_areg(regs, 2), m68k_areg(regs, 3)); +WriteLog("A4 = $%08X A5 = $%08X A6 = $%08X A7 = $%08X\n", m68k_areg(regs, 4), m68k_areg(regs, 5), m68k_areg(regs, 6), m68k_areg(regs, 7)); +WriteLog("D0 = $%08X D1 = $%08X D2 = $%08X D3 = $%08X\n", m68k_dreg(regs, 0), m68k_dreg(regs, 1), m68k_dreg(regs, 2), m68k_dreg(regs, 3)); +WriteLog("D4 = $%08X D5 = $%08X D6 = $%08X D7 = $%08X\n", m68k_dreg(regs, 4), m68k_dreg(regs, 5), m68k_dreg(regs, 6), m68k_dreg(regs, 7)); +WriteLog("\n"); + +uint32_t disPC = currpc - 10; +char buffer[128]; + +do +{ + uint32_t oldpc = disPC; + disPC += m68k_disassemble(buffer, disPC, 0); + WriteLog("%s%08X: %s\n", (oldpc == currpc ? ">" : " "), oldpc, buffer); +} +while (disPC < (currpc + 10)); +#endif + +/*if( nr>=2 && nr<10 ) fprintf(stderr,"Exception (-> %i bombs)!\n",nr);*/ + + MakeSR(); + + // Change to supervisor mode if necessary + if (!regs.s) + { + regs.usp = m68k_areg(regs, 7); + m68k_areg(regs, 7) = regs.isp; + regs.s = 1; + } + + // Create 68000 style stack frame + m68k_areg(regs, 7) -= 4; // Push PC on stack + m68k_write_memory_32(m68k_areg(regs, 7), currpc); + m68k_areg(regs, 7) -= 2; // Push SR on stack + m68k_write_memory_16(m68k_areg(regs, 7), regs.sr); + +// LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x\n", +// nr, currpc, BusErrorPC, get_long(4 * nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3); + +#if 0 + /* 68000 bus/address errors: */ + if ((nr == 2 || nr == 3) && ExceptionSource == M68000_EXC_SRC_CPU) + { + uint16_t specialstatus = 1; + + /* Special status word emulation isn't perfect yet... :-( */ + if (regs.sr & 0x2000) + specialstatus |= 0x4; + + m68k_areg(regs, 7) -= 8; + + if (nr == 3) /* Address error */ + { + specialstatus |= (last_op_for_exception_3 & (~0x1F)); /* [NP] unused bits of specialstatus are those of the last opcode ! */ + put_word(m68k_areg(regs, 7), specialstatus); + put_long(m68k_areg(regs, 7) + 2, last_fault_for_exception_3); + put_word(m68k_areg(regs, 7) + 6, last_op_for_exception_3); + put_long(m68k_areg(regs, 7) + 10, last_addr_for_exception_3); + +//JLH: Not now... +#if 0 + if (bExceptionDebugging) + { + fprintf(stderr,"Address Error at address $%x, PC=$%x\n", last_fault_for_exception_3, currpc); + DebugUI(); + } +#endif + } + else /* Bus error */ + { + specialstatus |= (get_word(BusErrorPC) & (~0x1F)); /* [NP] unused bits of special status are those of the last opcode ! */ + + if (bBusErrorReadWrite) + specialstatus |= 0x10; + + put_word(m68k_areg(regs, 7), specialstatus); + put_long(m68k_areg(regs, 7) + 2, BusErrorAddress); + put_word(m68k_areg(regs, 7) + 6, get_word(BusErrorPC)); /* Opcode */ + + /* [NP] PC stored in the stack frame is not necessarily pointing to the next instruction ! */ + /* FIXME : we should have a proper model for this, in the meantime we handle specific cases */ + if (get_word(BusErrorPC) == 0x21F8) /* move.l $0.w,$24.w (Transbeauce 2 loader) */ + put_long(m68k_areg(regs, 7) + 10, currpc - 2); /* correct PC is 2 bytes less than usual value */ + + /* Check for double bus errors: */ + if (regs.spcflags & SPCFLAG_BUSERROR) + { + fprintf(stderr, "Detected double bus error at address $%x, PC=$%lx => CPU halted!\n", + BusErrorAddress, (long)currpc); + unset_special(SPCFLAG_BUSERROR); + + if (bExceptionDebugging) + DebugUI(); + else + DlgAlert_Notice("Detected double bus error => CPU halted!\nEmulation needs to be reset.\n"); + + regs.intmask = 7; + m68k_setstopped(true); + return; + } + + if (bExceptionDebugging && BusErrorAddress != 0xFF8A00) + { + fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n", BusErrorAddress, (long)currpc); + DebugUI(); + } + } + } + +//Not now... +#if 0 + /* Set PC and flags */ + if (bExceptionDebugging && get_long(4 * nr) == 0) + { + write_log("Uninitialized exception handler #%i!\n", nr); + DebugUI(); + } +#endif + + newpc = get_long(4 * nr); + + if (newpc & 1) /* check new pc is odd */ + { + if (nr == 2 || nr == 3) /* address error during bus/address error -> stop emulation */ + { + fprintf(stderr,"Address Error during exception 2/3, aborting new PC=$%x\n", newpc); + DebugUI(); + } + else + { + fprintf(stderr,"Address Error during exception, new PC=$%x\n", newpc); + Exception(3, m68k_getpc(), M68000_EXC_SRC_CPU); + } + + return; + } +#endif + + m68k_setpc(m68k_read_memory_32(4 * nr)); + fill_prefetch_0(); + /* Handle trace flags depending on current state */ +//JLH:no exception_trace(nr); + +#if 0 + /* Handle exception cycles (special case for MFP) */ +// if (ExceptionSource == M68000_EXC_SRC_INT_MFP) +// { +// M68000_AddCycles(44 + 12); /* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */ +// } +// else + if (nr >= 24 && nr <= 31) + { +#if 0 + if (nr == 26) /* HBL */ + { + /* store current cycle pos when then interrupt was received (see video.c) */ + LastCycleHblException = Cycles_GetCounter(CYCLES_COUNTER_VIDEO); + M68000_AddCycles(44 + 12); /* Video Interrupt */ + } + else if (nr == 28) /* VBL */ + M68000_AddCycles(44 + 12); /* Video Interrupt */ + else +#endif + M68000_AddCycles(44 + 4); /* Other Interrupts */ + } + else if (nr >= 32 && nr <= 47) + { + M68000_AddCycles(34 - 4); /* Trap (total is 34, but cpuemu.c already adds 4) */ + } + else switch(nr) + { + case 2: M68000_AddCycles(50); break; /* Bus error */ + case 3: M68000_AddCycles(50); break; /* Address error */ + case 4: M68000_AddCycles(34); break; /* Illegal instruction */ + case 5: M68000_AddCycles(38); break; /* Div by zero */ + case 6: M68000_AddCycles(40); break; /* CHK */ + case 7: M68000_AddCycles(34); break; /* TRAPV */ + case 8: M68000_AddCycles(34); break; /* Privilege violation */ + case 9: M68000_AddCycles(34); break; /* Trace */ + case 10: M68000_AddCycles(34); break; /* Line-A - probably wrong */ + case 11: M68000_AddCycles(34); break; /* Line-F - probably wrong */ + default: + /* FIXME: Add right cycles value for MFP interrupts and copro exceptions ... */ + if (nr < 64) + M68000_AddCycles(4); /* Coprocessor and unassigned exceptions (???) */ + else + M68000_AddCycles(44 + 12); /* Must be a MFP or DSP interrupt */ + + break; + } +#endif +} + + +/* + The routines below take dividend and divisor as parameters. + They return 0 if division by zero, or exact number of cycles otherwise. + + The number of cycles returned assumes a register operand. + Effective address time must be added if memory operand. + + For 68000 only (not 68010, 68012, 68020, etc). + Probably valid for 68008 after adding the extra prefetch cycle. + + + Best and worst cases are for register operand: + (Note the difference with the documented range.) + + + DIVU: + + Overflow (always): 10 cycles. + Worst case: 136 cycles. + Best case: 76 cycles. + + + DIVS: + + Absolute overflow: 16-18 cycles. + Signed overflow is not detected prematurely. + + Worst case: 156 cycles. + Best case without signed overflow: 122 cycles. + Best case with signed overflow: 120 cycles + */ + +// +// DIVU +// Unsigned division +// +STATIC_INLINE int getDivu68kCycles_2 (uint32_t dividend, uint16_t divisor) +{ + int mcycles; + uint32_t hdivisor; + int i; + + if (divisor == 0) + return 0; + + // Overflow + if ((dividend >> 16) >= divisor) + return (mcycles = 5) * 2; + + mcycles = 38; + hdivisor = divisor << 16; + + for(i=0; i<15; i++) + { + uint32_t temp; + temp = dividend; + + dividend <<= 1; + + // If carry from shift + if ((int32_t)temp < 0) + dividend -= hdivisor; + else + { + mcycles += 2; + + if (dividend >= hdivisor) + { + dividend -= hdivisor; + mcycles--; + } + } + } + + return mcycles * 2; +} + + +// This is called by cpuemu.c +int getDivu68kCycles(uint32_t dividend, uint16_t divisor) +{ + int v = getDivu68kCycles_2(dividend, divisor) - 4; +// write_log ("U%d ", v); + return v; +} + + +// +// DIVS +// Signed division +// +STATIC_INLINE int getDivs68kCycles_2(int32_t dividend, int16_t divisor) +{ + int mcycles; + uint32_t aquot; + int i; + + if (divisor == 0) + return 0; + + mcycles = 6; + + if (dividend < 0) + mcycles++; + + // Check for absolute overflow + if (((uint32_t)abs(dividend) >> 16) >= (uint16_t)abs(divisor)) + return (mcycles + 2) * 2; + + // Absolute quotient + aquot = (uint32_t)abs(dividend) / (uint16_t)abs(divisor); + + mcycles += 55; + + if (divisor >= 0) + { + if (dividend >= 0) + mcycles--; + else + mcycles++; + } + + // Count 15 msbits in absolute of quotient + + for(i=0; i<15; i++) + { + if ((int16_t)aquot >= 0) + mcycles++; + + aquot <<= 1; + } + + return mcycles * 2; +} + + +// This is called by cpuemu.c +int getDivs68kCycles(int32_t dividend, int16_t divisor) +{ + int v = getDivs68kCycles_2(dividend, divisor) - 4; +// write_log ("S%d ", v); + return v; +} + diff --git a/waterbox/virtualjaguar/src/m68000/cpuextra.h b/waterbox/virtualjaguar/src/m68000/cpuextra.h new file mode 100644 index 0000000000..0efbbb4d7c --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpuextra.h @@ -0,0 +1,34 @@ +#ifndef __CPUEXTRA_H__ +#define __CPUEXTRA_H__ + +#include "sysdeps.h" + +typedef unsigned long cpuop_func(uint32_t); + +struct cputbl +{ + cpuop_func * handler; + int specific; + uint16_t opcode; +}; + +extern uint16_t last_op_for_exception_3; /* Opcode of faulting instruction */ +extern uint32_t last_addr_for_exception_3; /* PC at fault time */ +extern uint32_t last_fault_for_exception_3; /* Address that generated the exception */ + +/* Family of the latest instruction executed (to check for pairing) */ +extern int OpcodeFamily; /* see instrmnem in readcpu.h */ + +/* How many cycles to add to the current instruction in case a "misaligned" bus access is made */ +/* (used when addressing mode is d8(an,ix)) */ +extern int BusCyclePenalty; +extern int CurrentInstrCycles; + +extern uint32_t get_disp_ea_000(uint32_t base, uint32_t dp); +extern void MakeSR(void); +extern void MakeFromSR(void); +extern void Exception(int, uint32_t, int); +extern int getDivu68kCycles(uint32_t dividend, uint16_t divisor); +extern int getDivs68kCycles(int32_t dividend, int16_t divisor); + +#endif // __CPUEXTRA_H__ diff --git a/waterbox/virtualjaguar/src/m68000/cpustbl.c b/waterbox/virtualjaguar/src/m68000/cpustbl.c new file mode 100644 index 0000000000..91f632682b --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cpustbl.c @@ -0,0 +1,3172 @@ +#include "cpudefs.h" +#include "cpuextra.h" +#include "inlines.h" +#include "cputbl.h" +#define CPUFUNC(x) x##_ff +#ifdef NOFLAGS +#include "noflags.h" +#endif +const struct cputbl CPUFUNC(op_smalltbl_4)[] = { +{ CPUFUNC(op_0_4), 0, 0 }, /* OR */ +{ CPUFUNC(op_10_4), 0, 16 }, /* OR */ +{ CPUFUNC(op_18_4), 0, 24 }, /* OR */ +{ CPUFUNC(op_20_4), 0, 32 }, /* OR */ +{ CPUFUNC(op_28_4), 0, 40 }, /* OR */ +{ CPUFUNC(op_30_4), 0, 48 }, /* OR */ +{ CPUFUNC(op_38_4), 0, 56 }, /* OR */ +{ CPUFUNC(op_39_4), 0, 57 }, /* OR */ +{ CPUFUNC(op_3c_4), 0, 60 }, /* ORSR */ +{ CPUFUNC(op_40_4), 0, 64 }, /* OR */ +{ CPUFUNC(op_50_4), 0, 80 }, /* OR */ +{ CPUFUNC(op_58_4), 0, 88 }, /* OR */ +{ CPUFUNC(op_60_4), 0, 96 }, /* OR */ +{ CPUFUNC(op_68_4), 0, 104 }, /* OR */ +{ CPUFUNC(op_70_4), 0, 112 }, /* OR */ +{ CPUFUNC(op_78_4), 0, 120 }, /* OR */ +{ CPUFUNC(op_79_4), 0, 121 }, /* OR */ +{ CPUFUNC(op_7c_4), 0, 124 }, /* ORSR */ +{ CPUFUNC(op_80_4), 0, 128 }, /* OR */ +{ CPUFUNC(op_90_4), 0, 144 }, /* OR */ +{ CPUFUNC(op_98_4), 0, 152 }, /* OR */ +{ CPUFUNC(op_a0_4), 0, 160 }, /* OR */ +{ CPUFUNC(op_a8_4), 0, 168 }, /* OR */ +{ CPUFUNC(op_b0_4), 0, 176 }, /* OR */ +{ CPUFUNC(op_b8_4), 0, 184 }, /* OR */ +{ CPUFUNC(op_b9_4), 0, 185 }, /* OR */ +{ CPUFUNC(op_100_4), 0, 256 }, /* BTST */ +{ CPUFUNC(op_108_4), 0, 264 }, /* MVPMR */ +{ CPUFUNC(op_110_4), 0, 272 }, /* BTST */ +{ CPUFUNC(op_118_4), 0, 280 }, /* BTST */ +{ CPUFUNC(op_120_4), 0, 288 }, /* BTST */ +{ CPUFUNC(op_128_4), 0, 296 }, /* BTST */ +{ CPUFUNC(op_130_4), 0, 304 }, /* BTST */ +{ CPUFUNC(op_138_4), 0, 312 }, /* BTST */ +{ CPUFUNC(op_139_4), 0, 313 }, /* BTST */ +{ CPUFUNC(op_13a_4), 0, 314 }, /* BTST */ +{ CPUFUNC(op_13b_4), 0, 315 }, /* BTST */ +{ CPUFUNC(op_13c_4), 0, 316 }, /* BTST */ +{ CPUFUNC(op_140_4), 0, 320 }, /* BCHG */ +{ CPUFUNC(op_148_4), 0, 328 }, /* MVPMR */ +{ CPUFUNC(op_150_4), 0, 336 }, /* BCHG */ +{ CPUFUNC(op_158_4), 0, 344 }, /* BCHG */ +{ CPUFUNC(op_160_4), 0, 352 }, /* BCHG */ +{ CPUFUNC(op_168_4), 0, 360 }, /* BCHG */ +{ CPUFUNC(op_170_4), 0, 368 }, /* BCHG */ +{ CPUFUNC(op_178_4), 0, 376 }, /* BCHG */ +{ CPUFUNC(op_179_4), 0, 377 }, /* BCHG */ +{ CPUFUNC(op_17a_4), 0, 378 }, /* BCHG */ +{ CPUFUNC(op_17b_4), 0, 379 }, /* BCHG */ +{ CPUFUNC(op_180_4), 0, 384 }, /* BCLR */ +{ CPUFUNC(op_188_4), 0, 392 }, /* MVPRM */ +{ CPUFUNC(op_190_4), 0, 400 }, /* BCLR */ +{ CPUFUNC(op_198_4), 0, 408 }, /* BCLR */ +{ CPUFUNC(op_1a0_4), 0, 416 }, /* BCLR */ +{ CPUFUNC(op_1a8_4), 0, 424 }, /* BCLR */ +{ CPUFUNC(op_1b0_4), 0, 432 }, /* BCLR */ +{ CPUFUNC(op_1b8_4), 0, 440 }, /* BCLR */ +{ CPUFUNC(op_1b9_4), 0, 441 }, /* BCLR */ +{ CPUFUNC(op_1ba_4), 0, 442 }, /* BCLR */ +{ CPUFUNC(op_1bb_4), 0, 443 }, /* BCLR */ +{ CPUFUNC(op_1c0_4), 0, 448 }, /* BSET */ +{ CPUFUNC(op_1c8_4), 0, 456 }, /* MVPRM */ +{ CPUFUNC(op_1d0_4), 0, 464 }, /* BSET */ +{ CPUFUNC(op_1d8_4), 0, 472 }, /* BSET */ +{ CPUFUNC(op_1e0_4), 0, 480 }, /* BSET */ +{ CPUFUNC(op_1e8_4), 0, 488 }, /* BSET */ +{ CPUFUNC(op_1f0_4), 0, 496 }, /* BSET */ +{ CPUFUNC(op_1f8_4), 0, 504 }, /* BSET */ +{ CPUFUNC(op_1f9_4), 0, 505 }, /* BSET */ +{ CPUFUNC(op_1fa_4), 0, 506 }, /* BSET */ +{ CPUFUNC(op_1fb_4), 0, 507 }, /* BSET */ +{ CPUFUNC(op_200_4), 0, 512 }, /* AND */ +{ CPUFUNC(op_210_4), 0, 528 }, /* AND */ +{ CPUFUNC(op_218_4), 0, 536 }, /* AND */ +{ CPUFUNC(op_220_4), 0, 544 }, /* AND */ +{ CPUFUNC(op_228_4), 0, 552 }, /* AND */ +{ CPUFUNC(op_230_4), 0, 560 }, /* AND */ +{ CPUFUNC(op_238_4), 0, 568 }, /* AND */ +{ CPUFUNC(op_239_4), 0, 569 }, /* AND */ +{ CPUFUNC(op_23c_4), 0, 572 }, /* ANDSR */ +{ CPUFUNC(op_240_4), 0, 576 }, /* AND */ +{ CPUFUNC(op_250_4), 0, 592 }, /* AND */ +{ CPUFUNC(op_258_4), 0, 600 }, /* AND */ +{ CPUFUNC(op_260_4), 0, 608 }, /* AND */ +{ CPUFUNC(op_268_4), 0, 616 }, /* AND */ +{ CPUFUNC(op_270_4), 0, 624 }, /* AND */ +{ CPUFUNC(op_278_4), 0, 632 }, /* AND */ +{ CPUFUNC(op_279_4), 0, 633 }, /* AND */ +{ CPUFUNC(op_27c_4), 0, 636 }, /* ANDSR */ +{ CPUFUNC(op_280_4), 0, 640 }, /* AND */ +{ CPUFUNC(op_290_4), 0, 656 }, /* AND */ +{ CPUFUNC(op_298_4), 0, 664 }, /* AND */ +{ CPUFUNC(op_2a0_4), 0, 672 }, /* AND */ +{ CPUFUNC(op_2a8_4), 0, 680 }, /* AND */ +{ CPUFUNC(op_2b0_4), 0, 688 }, /* AND */ +{ CPUFUNC(op_2b8_4), 0, 696 }, /* AND */ +{ CPUFUNC(op_2b9_4), 0, 697 }, /* AND */ +{ CPUFUNC(op_400_4), 0, 1024 }, /* SUB */ +{ CPUFUNC(op_410_4), 0, 1040 }, /* SUB */ +{ CPUFUNC(op_418_4), 0, 1048 }, /* SUB */ +{ CPUFUNC(op_420_4), 0, 1056 }, /* SUB */ +{ CPUFUNC(op_428_4), 0, 1064 }, /* SUB */ +{ CPUFUNC(op_430_4), 0, 1072 }, /* SUB */ +{ CPUFUNC(op_438_4), 0, 1080 }, /* SUB */ +{ CPUFUNC(op_439_4), 0, 1081 }, /* SUB */ +{ CPUFUNC(op_440_4), 0, 1088 }, /* SUB */ +{ CPUFUNC(op_450_4), 0, 1104 }, /* SUB */ +{ CPUFUNC(op_458_4), 0, 1112 }, /* SUB */ +{ CPUFUNC(op_460_4), 0, 1120 }, /* SUB */ +{ CPUFUNC(op_468_4), 0, 1128 }, /* SUB */ +{ CPUFUNC(op_470_4), 0, 1136 }, /* SUB */ +{ CPUFUNC(op_478_4), 0, 1144 }, /* SUB */ +{ CPUFUNC(op_479_4), 0, 1145 }, /* SUB */ +{ CPUFUNC(op_480_4), 0, 1152 }, /* SUB */ +{ CPUFUNC(op_490_4), 0, 1168 }, /* SUB */ +{ CPUFUNC(op_498_4), 0, 1176 }, /* SUB */ +{ CPUFUNC(op_4a0_4), 0, 1184 }, /* SUB */ +{ CPUFUNC(op_4a8_4), 0, 1192 }, /* SUB */ +{ CPUFUNC(op_4b0_4), 0, 1200 }, /* SUB */ +{ CPUFUNC(op_4b8_4), 0, 1208 }, /* SUB */ +{ CPUFUNC(op_4b9_4), 0, 1209 }, /* SUB */ +{ CPUFUNC(op_600_4), 0, 1536 }, /* ADD */ +{ CPUFUNC(op_610_4), 0, 1552 }, /* ADD */ +{ CPUFUNC(op_618_4), 0, 1560 }, /* ADD */ +{ CPUFUNC(op_620_4), 0, 1568 }, /* ADD */ +{ CPUFUNC(op_628_4), 0, 1576 }, /* ADD */ +{ CPUFUNC(op_630_4), 0, 1584 }, /* ADD */ +{ CPUFUNC(op_638_4), 0, 1592 }, /* ADD */ +{ CPUFUNC(op_639_4), 0, 1593 }, /* ADD */ +{ CPUFUNC(op_640_4), 0, 1600 }, /* ADD */ +{ CPUFUNC(op_650_4), 0, 1616 }, /* ADD */ +{ CPUFUNC(op_658_4), 0, 1624 }, /* ADD */ +{ CPUFUNC(op_660_4), 0, 1632 }, /* ADD */ +{ CPUFUNC(op_668_4), 0, 1640 }, /* ADD */ +{ CPUFUNC(op_670_4), 0, 1648 }, /* ADD */ +{ CPUFUNC(op_678_4), 0, 1656 }, /* ADD */ +{ CPUFUNC(op_679_4), 0, 1657 }, /* ADD */ +{ CPUFUNC(op_680_4), 0, 1664 }, /* ADD */ +{ CPUFUNC(op_690_4), 0, 1680 }, /* ADD */ +{ CPUFUNC(op_698_4), 0, 1688 }, /* ADD */ +{ CPUFUNC(op_6a0_4), 0, 1696 }, /* ADD */ +{ CPUFUNC(op_6a8_4), 0, 1704 }, /* ADD */ +{ CPUFUNC(op_6b0_4), 0, 1712 }, /* ADD */ +{ CPUFUNC(op_6b8_4), 0, 1720 }, /* ADD */ +{ CPUFUNC(op_6b9_4), 0, 1721 }, /* ADD */ +{ CPUFUNC(op_800_4), 0, 2048 }, /* BTST */ +{ CPUFUNC(op_810_4), 0, 2064 }, /* BTST */ +{ CPUFUNC(op_818_4), 0, 2072 }, /* BTST */ +{ CPUFUNC(op_820_4), 0, 2080 }, /* BTST */ +{ CPUFUNC(op_828_4), 0, 2088 }, /* BTST */ +{ CPUFUNC(op_830_4), 0, 2096 }, /* BTST */ +{ CPUFUNC(op_838_4), 0, 2104 }, /* BTST */ +{ CPUFUNC(op_839_4), 0, 2105 }, /* BTST */ +{ CPUFUNC(op_83a_4), 0, 2106 }, /* BTST */ +{ CPUFUNC(op_83b_4), 0, 2107 }, /* BTST */ +{ CPUFUNC(op_83c_4), 0, 2108 }, /* BTST */ +{ CPUFUNC(op_840_4), 0, 2112 }, /* BCHG */ +{ CPUFUNC(op_850_4), 0, 2128 }, /* BCHG */ +{ CPUFUNC(op_858_4), 0, 2136 }, /* BCHG */ +{ CPUFUNC(op_860_4), 0, 2144 }, /* BCHG */ +{ CPUFUNC(op_868_4), 0, 2152 }, /* BCHG */ +{ CPUFUNC(op_870_4), 0, 2160 }, /* BCHG */ +{ CPUFUNC(op_878_4), 0, 2168 }, /* BCHG */ +{ CPUFUNC(op_879_4), 0, 2169 }, /* BCHG */ +{ CPUFUNC(op_87a_4), 0, 2170 }, /* BCHG */ +{ CPUFUNC(op_87b_4), 0, 2171 }, /* BCHG */ +{ CPUFUNC(op_880_4), 0, 2176 }, /* BCLR */ +{ CPUFUNC(op_890_4), 0, 2192 }, /* BCLR */ +{ CPUFUNC(op_898_4), 0, 2200 }, /* BCLR */ +{ CPUFUNC(op_8a0_4), 0, 2208 }, /* BCLR */ +{ CPUFUNC(op_8a8_4), 0, 2216 }, /* BCLR */ +{ CPUFUNC(op_8b0_4), 0, 2224 }, /* BCLR */ +{ CPUFUNC(op_8b8_4), 0, 2232 }, /* BCLR */ +{ CPUFUNC(op_8b9_4), 0, 2233 }, /* BCLR */ +{ CPUFUNC(op_8ba_4), 0, 2234 }, /* BCLR */ +{ CPUFUNC(op_8bb_4), 0, 2235 }, /* BCLR */ +{ CPUFUNC(op_8c0_4), 0, 2240 }, /* BSET */ +{ CPUFUNC(op_8d0_4), 0, 2256 }, /* BSET */ +{ CPUFUNC(op_8d8_4), 0, 2264 }, /* BSET */ +{ CPUFUNC(op_8e0_4), 0, 2272 }, /* BSET */ +{ CPUFUNC(op_8e8_4), 0, 2280 }, /* BSET */ +{ CPUFUNC(op_8f0_4), 0, 2288 }, /* BSET */ +{ CPUFUNC(op_8f8_4), 0, 2296 }, /* BSET */ +{ CPUFUNC(op_8f9_4), 0, 2297 }, /* BSET */ +{ CPUFUNC(op_8fa_4), 0, 2298 }, /* BSET */ +{ CPUFUNC(op_8fb_4), 0, 2299 }, /* BSET */ +{ CPUFUNC(op_a00_4), 0, 2560 }, /* EOR */ +{ CPUFUNC(op_a10_4), 0, 2576 }, /* EOR */ +{ CPUFUNC(op_a18_4), 0, 2584 }, /* EOR */ +{ CPUFUNC(op_a20_4), 0, 2592 }, /* EOR */ +{ CPUFUNC(op_a28_4), 0, 2600 }, /* EOR */ +{ CPUFUNC(op_a30_4), 0, 2608 }, /* EOR */ +{ CPUFUNC(op_a38_4), 0, 2616 }, /* EOR */ +{ CPUFUNC(op_a39_4), 0, 2617 }, /* EOR */ +{ CPUFUNC(op_a3c_4), 0, 2620 }, /* EORSR */ +{ CPUFUNC(op_a40_4), 0, 2624 }, /* EOR */ +{ CPUFUNC(op_a50_4), 0, 2640 }, /* EOR */ +{ CPUFUNC(op_a58_4), 0, 2648 }, /* EOR */ +{ CPUFUNC(op_a60_4), 0, 2656 }, /* EOR */ +{ CPUFUNC(op_a68_4), 0, 2664 }, /* EOR */ +{ CPUFUNC(op_a70_4), 0, 2672 }, /* EOR */ +{ CPUFUNC(op_a78_4), 0, 2680 }, /* EOR */ +{ CPUFUNC(op_a79_4), 0, 2681 }, /* EOR */ +{ CPUFUNC(op_a7c_4), 0, 2684 }, /* EORSR */ +{ CPUFUNC(op_a80_4), 0, 2688 }, /* EOR */ +{ CPUFUNC(op_a90_4), 0, 2704 }, /* EOR */ +{ CPUFUNC(op_a98_4), 0, 2712 }, /* EOR */ +{ CPUFUNC(op_aa0_4), 0, 2720 }, /* EOR */ +{ CPUFUNC(op_aa8_4), 0, 2728 }, /* EOR */ +{ CPUFUNC(op_ab0_4), 0, 2736 }, /* EOR */ +{ CPUFUNC(op_ab8_4), 0, 2744 }, /* EOR */ +{ CPUFUNC(op_ab9_4), 0, 2745 }, /* EOR */ +{ CPUFUNC(op_c00_4), 0, 3072 }, /* CMP */ +{ CPUFUNC(op_c10_4), 0, 3088 }, /* CMP */ +{ CPUFUNC(op_c18_4), 0, 3096 }, /* CMP */ +{ CPUFUNC(op_c20_4), 0, 3104 }, /* CMP */ +{ CPUFUNC(op_c28_4), 0, 3112 }, /* CMP */ +{ CPUFUNC(op_c30_4), 0, 3120 }, /* CMP */ +{ CPUFUNC(op_c38_4), 0, 3128 }, /* CMP */ +{ CPUFUNC(op_c39_4), 0, 3129 }, /* CMP */ +{ CPUFUNC(op_c3a_4), 0, 3130 }, /* CMP */ +{ CPUFUNC(op_c3b_4), 0, 3131 }, /* CMP */ +{ CPUFUNC(op_c40_4), 0, 3136 }, /* CMP */ +{ CPUFUNC(op_c50_4), 0, 3152 }, /* CMP */ +{ CPUFUNC(op_c58_4), 0, 3160 }, /* CMP */ +{ CPUFUNC(op_c60_4), 0, 3168 }, /* CMP */ +{ CPUFUNC(op_c68_4), 0, 3176 }, /* CMP */ +{ CPUFUNC(op_c70_4), 0, 3184 }, /* CMP */ +{ CPUFUNC(op_c78_4), 0, 3192 }, /* CMP */ +{ CPUFUNC(op_c79_4), 0, 3193 }, /* CMP */ +{ CPUFUNC(op_c7a_4), 0, 3194 }, /* CMP */ +{ CPUFUNC(op_c7b_4), 0, 3195 }, /* CMP */ +{ CPUFUNC(op_c80_4), 0, 3200 }, /* CMP */ +{ CPUFUNC(op_c90_4), 0, 3216 }, /* CMP */ +{ CPUFUNC(op_c98_4), 0, 3224 }, /* CMP */ +{ CPUFUNC(op_ca0_4), 0, 3232 }, /* CMP */ +{ CPUFUNC(op_ca8_4), 0, 3240 }, /* CMP */ +{ CPUFUNC(op_cb0_4), 0, 3248 }, /* CMP */ +{ CPUFUNC(op_cb8_4), 0, 3256 }, /* CMP */ +{ CPUFUNC(op_cb9_4), 0, 3257 }, /* CMP */ +{ CPUFUNC(op_cba_4), 0, 3258 }, /* CMP */ +{ CPUFUNC(op_cbb_4), 0, 3259 }, /* CMP */ +{ CPUFUNC(op_1000_4), 0, 4096 }, /* MOVE */ +{ CPUFUNC(op_1008_4), 0, 4104 }, /* MOVE */ +{ CPUFUNC(op_1010_4), 0, 4112 }, /* MOVE */ +{ CPUFUNC(op_1018_4), 0, 4120 }, /* MOVE */ +{ CPUFUNC(op_1020_4), 0, 4128 }, /* MOVE */ +{ CPUFUNC(op_1028_4), 0, 4136 }, /* MOVE */ +{ CPUFUNC(op_1030_4), 0, 4144 }, /* MOVE */ +{ CPUFUNC(op_1038_4), 0, 4152 }, /* MOVE */ +{ CPUFUNC(op_1039_4), 0, 4153 }, /* MOVE */ +{ CPUFUNC(op_103a_4), 0, 4154 }, /* MOVE */ +{ CPUFUNC(op_103b_4), 0, 4155 }, /* MOVE */ +{ CPUFUNC(op_103c_4), 0, 4156 }, /* MOVE */ +{ CPUFUNC(op_1080_4), 0, 4224 }, /* MOVE */ +{ CPUFUNC(op_1088_4), 0, 4232 }, /* MOVE */ +{ CPUFUNC(op_1090_4), 0, 4240 }, /* MOVE */ +{ CPUFUNC(op_1098_4), 0, 4248 }, /* MOVE */ +{ CPUFUNC(op_10a0_4), 0, 4256 }, /* MOVE */ +{ CPUFUNC(op_10a8_4), 0, 4264 }, /* MOVE */ +{ CPUFUNC(op_10b0_4), 0, 4272 }, /* MOVE */ +{ CPUFUNC(op_10b8_4), 0, 4280 }, /* MOVE */ +{ CPUFUNC(op_10b9_4), 0, 4281 }, /* MOVE */ +{ CPUFUNC(op_10ba_4), 0, 4282 }, /* MOVE */ +{ CPUFUNC(op_10bb_4), 0, 4283 }, /* MOVE */ +{ CPUFUNC(op_10bc_4), 0, 4284 }, /* MOVE */ +{ CPUFUNC(op_10c0_4), 0, 4288 }, /* MOVE */ +{ CPUFUNC(op_10c8_4), 0, 4296 }, /* MOVE */ +{ CPUFUNC(op_10d0_4), 0, 4304 }, /* MOVE */ +{ CPUFUNC(op_10d8_4), 0, 4312 }, /* MOVE */ +{ CPUFUNC(op_10e0_4), 0, 4320 }, /* MOVE */ +{ CPUFUNC(op_10e8_4), 0, 4328 }, /* MOVE */ +{ CPUFUNC(op_10f0_4), 0, 4336 }, /* MOVE */ +{ CPUFUNC(op_10f8_4), 0, 4344 }, /* MOVE */ +{ CPUFUNC(op_10f9_4), 0, 4345 }, /* MOVE */ +{ CPUFUNC(op_10fa_4), 0, 4346 }, /* MOVE */ +{ CPUFUNC(op_10fb_4), 0, 4347 }, /* MOVE */ +{ CPUFUNC(op_10fc_4), 0, 4348 }, /* MOVE */ +{ CPUFUNC(op_1100_4), 0, 4352 }, /* MOVE */ +{ CPUFUNC(op_1108_4), 0, 4360 }, /* MOVE */ +{ CPUFUNC(op_1110_4), 0, 4368 }, /* MOVE */ +{ CPUFUNC(op_1118_4), 0, 4376 }, /* MOVE */ +{ CPUFUNC(op_1120_4), 0, 4384 }, /* MOVE */ +{ CPUFUNC(op_1128_4), 0, 4392 }, /* MOVE */ +{ CPUFUNC(op_1130_4), 0, 4400 }, /* MOVE */ +{ CPUFUNC(op_1138_4), 0, 4408 }, /* MOVE */ +{ CPUFUNC(op_1139_4), 0, 4409 }, /* MOVE */ +{ CPUFUNC(op_113a_4), 0, 4410 }, /* MOVE */ +{ CPUFUNC(op_113b_4), 0, 4411 }, /* MOVE */ +{ CPUFUNC(op_113c_4), 0, 4412 }, /* MOVE */ +{ CPUFUNC(op_1140_4), 0, 4416 }, /* MOVE */ +{ CPUFUNC(op_1148_4), 0, 4424 }, /* MOVE */ +{ CPUFUNC(op_1150_4), 0, 4432 }, /* MOVE */ +{ CPUFUNC(op_1158_4), 0, 4440 }, /* MOVE */ +{ CPUFUNC(op_1160_4), 0, 4448 }, /* MOVE */ +{ CPUFUNC(op_1168_4), 0, 4456 }, /* MOVE */ +{ CPUFUNC(op_1170_4), 0, 4464 }, /* MOVE */ +{ CPUFUNC(op_1178_4), 0, 4472 }, /* MOVE */ +{ CPUFUNC(op_1179_4), 0, 4473 }, /* MOVE */ +{ CPUFUNC(op_117a_4), 0, 4474 }, /* MOVE */ +{ CPUFUNC(op_117b_4), 0, 4475 }, /* MOVE */ +{ CPUFUNC(op_117c_4), 0, 4476 }, /* MOVE */ +{ CPUFUNC(op_1180_4), 0, 4480 }, /* MOVE */ +{ CPUFUNC(op_1188_4), 0, 4488 }, /* MOVE */ +{ CPUFUNC(op_1190_4), 0, 4496 }, /* MOVE */ +{ CPUFUNC(op_1198_4), 0, 4504 }, /* MOVE */ +{ CPUFUNC(op_11a0_4), 0, 4512 }, /* MOVE */ +{ CPUFUNC(op_11a8_4), 0, 4520 }, /* MOVE */ +{ CPUFUNC(op_11b0_4), 0, 4528 }, /* MOVE */ +{ CPUFUNC(op_11b8_4), 0, 4536 }, /* MOVE */ +{ CPUFUNC(op_11b9_4), 0, 4537 }, /* MOVE */ +{ CPUFUNC(op_11ba_4), 0, 4538 }, /* MOVE */ +{ CPUFUNC(op_11bb_4), 0, 4539 }, /* MOVE */ +{ CPUFUNC(op_11bc_4), 0, 4540 }, /* MOVE */ +{ CPUFUNC(op_11c0_4), 0, 4544 }, /* MOVE */ +{ CPUFUNC(op_11c8_4), 0, 4552 }, /* MOVE */ +{ CPUFUNC(op_11d0_4), 0, 4560 }, /* MOVE */ +{ CPUFUNC(op_11d8_4), 0, 4568 }, /* MOVE */ +{ CPUFUNC(op_11e0_4), 0, 4576 }, /* MOVE */ +{ CPUFUNC(op_11e8_4), 0, 4584 }, /* MOVE */ +{ CPUFUNC(op_11f0_4), 0, 4592 }, /* MOVE */ +{ CPUFUNC(op_11f8_4), 0, 4600 }, /* MOVE */ +{ CPUFUNC(op_11f9_4), 0, 4601 }, /* MOVE */ +{ CPUFUNC(op_11fa_4), 0, 4602 }, /* MOVE */ +{ CPUFUNC(op_11fb_4), 0, 4603 }, /* MOVE */ +{ CPUFUNC(op_11fc_4), 0, 4604 }, /* MOVE */ +{ CPUFUNC(op_13c0_4), 0, 5056 }, /* MOVE */ +{ CPUFUNC(op_13c8_4), 0, 5064 }, /* MOVE */ +{ CPUFUNC(op_13d0_4), 0, 5072 }, /* MOVE */ +{ CPUFUNC(op_13d8_4), 0, 5080 }, /* MOVE */ +{ CPUFUNC(op_13e0_4), 0, 5088 }, /* MOVE */ +{ CPUFUNC(op_13e8_4), 0, 5096 }, /* MOVE */ +{ CPUFUNC(op_13f0_4), 0, 5104 }, /* MOVE */ +{ CPUFUNC(op_13f8_4), 0, 5112 }, /* MOVE */ +{ CPUFUNC(op_13f9_4), 0, 5113 }, /* MOVE */ +{ CPUFUNC(op_13fa_4), 0, 5114 }, /* MOVE */ +{ CPUFUNC(op_13fb_4), 0, 5115 }, /* MOVE */ +{ CPUFUNC(op_13fc_4), 0, 5116 }, /* MOVE */ +{ CPUFUNC(op_2000_4), 0, 8192 }, /* MOVE */ +{ CPUFUNC(op_2008_4), 0, 8200 }, /* MOVE */ +{ CPUFUNC(op_2010_4), 0, 8208 }, /* MOVE */ +{ CPUFUNC(op_2018_4), 0, 8216 }, /* MOVE */ +{ CPUFUNC(op_2020_4), 0, 8224 }, /* MOVE */ +{ CPUFUNC(op_2028_4), 0, 8232 }, /* MOVE */ +{ CPUFUNC(op_2030_4), 0, 8240 }, /* MOVE */ +{ CPUFUNC(op_2038_4), 0, 8248 }, /* MOVE */ +{ CPUFUNC(op_2039_4), 0, 8249 }, /* MOVE */ +{ CPUFUNC(op_203a_4), 0, 8250 }, /* MOVE */ +{ CPUFUNC(op_203b_4), 0, 8251 }, /* MOVE */ +{ CPUFUNC(op_203c_4), 0, 8252 }, /* MOVE */ +{ CPUFUNC(op_2040_4), 0, 8256 }, /* MOVEA */ +{ CPUFUNC(op_2048_4), 0, 8264 }, /* MOVEA */ +{ CPUFUNC(op_2050_4), 0, 8272 }, /* MOVEA */ +{ CPUFUNC(op_2058_4), 0, 8280 }, /* MOVEA */ +{ CPUFUNC(op_2060_4), 0, 8288 }, /* MOVEA */ +{ CPUFUNC(op_2068_4), 0, 8296 }, /* MOVEA */ +{ CPUFUNC(op_2070_4), 0, 8304 }, /* MOVEA */ +{ CPUFUNC(op_2078_4), 0, 8312 }, /* MOVEA */ +{ CPUFUNC(op_2079_4), 0, 8313 }, /* MOVEA */ +{ CPUFUNC(op_207a_4), 0, 8314 }, /* MOVEA */ +{ CPUFUNC(op_207b_4), 0, 8315 }, /* MOVEA */ +{ CPUFUNC(op_207c_4), 0, 8316 }, /* MOVEA */ +{ CPUFUNC(op_2080_4), 0, 8320 }, /* MOVE */ +{ CPUFUNC(op_2088_4), 0, 8328 }, /* MOVE */ +{ CPUFUNC(op_2090_4), 0, 8336 }, /* MOVE */ +{ CPUFUNC(op_2098_4), 0, 8344 }, /* MOVE */ +{ CPUFUNC(op_20a0_4), 0, 8352 }, /* MOVE */ +{ CPUFUNC(op_20a8_4), 0, 8360 }, /* MOVE */ +{ CPUFUNC(op_20b0_4), 0, 8368 }, /* MOVE */ +{ CPUFUNC(op_20b8_4), 0, 8376 }, /* MOVE */ +{ CPUFUNC(op_20b9_4), 0, 8377 }, /* MOVE */ +{ CPUFUNC(op_20ba_4), 0, 8378 }, /* MOVE */ +{ CPUFUNC(op_20bb_4), 0, 8379 }, /* MOVE */ +{ CPUFUNC(op_20bc_4), 0, 8380 }, /* MOVE */ +{ CPUFUNC(op_20c0_4), 0, 8384 }, /* MOVE */ +{ CPUFUNC(op_20c8_4), 0, 8392 }, /* MOVE */ +{ CPUFUNC(op_20d0_4), 0, 8400 }, /* MOVE */ +{ CPUFUNC(op_20d8_4), 0, 8408 }, /* MOVE */ +{ CPUFUNC(op_20e0_4), 0, 8416 }, /* MOVE */ +{ CPUFUNC(op_20e8_4), 0, 8424 }, /* MOVE */ +{ CPUFUNC(op_20f0_4), 0, 8432 }, /* MOVE */ +{ CPUFUNC(op_20f8_4), 0, 8440 }, /* MOVE */ +{ CPUFUNC(op_20f9_4), 0, 8441 }, /* MOVE */ +{ CPUFUNC(op_20fa_4), 0, 8442 }, /* MOVE */ +{ CPUFUNC(op_20fb_4), 0, 8443 }, /* MOVE */ +{ CPUFUNC(op_20fc_4), 0, 8444 }, /* MOVE */ +{ CPUFUNC(op_2100_4), 0, 8448 }, /* MOVE */ +{ CPUFUNC(op_2108_4), 0, 8456 }, /* MOVE */ +{ CPUFUNC(op_2110_4), 0, 8464 }, /* MOVE */ +{ CPUFUNC(op_2118_4), 0, 8472 }, /* MOVE */ +{ CPUFUNC(op_2120_4), 0, 8480 }, /* MOVE */ +{ CPUFUNC(op_2128_4), 0, 8488 }, /* MOVE */ +{ CPUFUNC(op_2130_4), 0, 8496 }, /* MOVE */ +{ CPUFUNC(op_2138_4), 0, 8504 }, /* MOVE */ +{ CPUFUNC(op_2139_4), 0, 8505 }, /* MOVE */ +{ CPUFUNC(op_213a_4), 0, 8506 }, /* MOVE */ +{ CPUFUNC(op_213b_4), 0, 8507 }, /* MOVE */ +{ CPUFUNC(op_213c_4), 0, 8508 }, /* MOVE */ +{ CPUFUNC(op_2140_4), 0, 8512 }, /* MOVE */ +{ CPUFUNC(op_2148_4), 0, 8520 }, /* MOVE */ +{ CPUFUNC(op_2150_4), 0, 8528 }, /* MOVE */ +{ CPUFUNC(op_2158_4), 0, 8536 }, /* MOVE */ +{ CPUFUNC(op_2160_4), 0, 8544 }, /* MOVE */ +{ CPUFUNC(op_2168_4), 0, 8552 }, /* MOVE */ +{ CPUFUNC(op_2170_4), 0, 8560 }, /* MOVE */ +{ CPUFUNC(op_2178_4), 0, 8568 }, /* MOVE */ +{ CPUFUNC(op_2179_4), 0, 8569 }, /* MOVE */ +{ CPUFUNC(op_217a_4), 0, 8570 }, /* MOVE */ +{ CPUFUNC(op_217b_4), 0, 8571 }, /* MOVE */ +{ CPUFUNC(op_217c_4), 0, 8572 }, /* MOVE */ +{ CPUFUNC(op_2180_4), 0, 8576 }, /* MOVE */ +{ CPUFUNC(op_2188_4), 0, 8584 }, /* MOVE */ +{ CPUFUNC(op_2190_4), 0, 8592 }, /* MOVE */ +{ CPUFUNC(op_2198_4), 0, 8600 }, /* MOVE */ +{ CPUFUNC(op_21a0_4), 0, 8608 }, /* MOVE */ +{ CPUFUNC(op_21a8_4), 0, 8616 }, /* MOVE */ +{ CPUFUNC(op_21b0_4), 0, 8624 }, /* MOVE */ +{ CPUFUNC(op_21b8_4), 0, 8632 }, /* MOVE */ +{ CPUFUNC(op_21b9_4), 0, 8633 }, /* MOVE */ +{ CPUFUNC(op_21ba_4), 0, 8634 }, /* MOVE */ +{ CPUFUNC(op_21bb_4), 0, 8635 }, /* MOVE */ +{ CPUFUNC(op_21bc_4), 0, 8636 }, /* MOVE */ +{ CPUFUNC(op_21c0_4), 0, 8640 }, /* MOVE */ +{ CPUFUNC(op_21c8_4), 0, 8648 }, /* MOVE */ +{ CPUFUNC(op_21d0_4), 0, 8656 }, /* MOVE */ +{ CPUFUNC(op_21d8_4), 0, 8664 }, /* MOVE */ +{ CPUFUNC(op_21e0_4), 0, 8672 }, /* MOVE */ +{ CPUFUNC(op_21e8_4), 0, 8680 }, /* MOVE */ +{ CPUFUNC(op_21f0_4), 0, 8688 }, /* MOVE */ +{ CPUFUNC(op_21f8_4), 0, 8696 }, /* MOVE */ +{ CPUFUNC(op_21f9_4), 0, 8697 }, /* MOVE */ +{ CPUFUNC(op_21fa_4), 0, 8698 }, /* MOVE */ +{ CPUFUNC(op_21fb_4), 0, 8699 }, /* MOVE */ +{ CPUFUNC(op_21fc_4), 0, 8700 }, /* MOVE */ +{ CPUFUNC(op_23c0_4), 0, 9152 }, /* MOVE */ +{ CPUFUNC(op_23c8_4), 0, 9160 }, /* MOVE */ +{ CPUFUNC(op_23d0_4), 0, 9168 }, /* MOVE */ +{ CPUFUNC(op_23d8_4), 0, 9176 }, /* MOVE */ +{ CPUFUNC(op_23e0_4), 0, 9184 }, /* MOVE */ +{ CPUFUNC(op_23e8_4), 0, 9192 }, /* MOVE */ +{ CPUFUNC(op_23f0_4), 0, 9200 }, /* MOVE */ +{ CPUFUNC(op_23f8_4), 0, 9208 }, /* MOVE */ +{ CPUFUNC(op_23f9_4), 0, 9209 }, /* MOVE */ +{ CPUFUNC(op_23fa_4), 0, 9210 }, /* MOVE */ +{ CPUFUNC(op_23fb_4), 0, 9211 }, /* MOVE */ +{ CPUFUNC(op_23fc_4), 0, 9212 }, /* MOVE */ +{ CPUFUNC(op_3000_4), 0, 12288 }, /* MOVE */ +{ CPUFUNC(op_3008_4), 0, 12296 }, /* MOVE */ +{ CPUFUNC(op_3010_4), 0, 12304 }, /* MOVE */ +{ CPUFUNC(op_3018_4), 0, 12312 }, /* MOVE */ +{ CPUFUNC(op_3020_4), 0, 12320 }, /* MOVE */ +{ CPUFUNC(op_3028_4), 0, 12328 }, /* MOVE */ +{ CPUFUNC(op_3030_4), 0, 12336 }, /* MOVE */ +{ CPUFUNC(op_3038_4), 0, 12344 }, /* MOVE */ +{ CPUFUNC(op_3039_4), 0, 12345 }, /* MOVE */ +{ CPUFUNC(op_303a_4), 0, 12346 }, /* MOVE */ +{ CPUFUNC(op_303b_4), 0, 12347 }, /* MOVE */ +{ CPUFUNC(op_303c_4), 0, 12348 }, /* MOVE */ +{ CPUFUNC(op_3040_4), 0, 12352 }, /* MOVEA */ +{ CPUFUNC(op_3048_4), 0, 12360 }, /* MOVEA */ +{ CPUFUNC(op_3050_4), 0, 12368 }, /* MOVEA */ +{ CPUFUNC(op_3058_4), 0, 12376 }, /* MOVEA */ +{ CPUFUNC(op_3060_4), 0, 12384 }, /* MOVEA */ +{ CPUFUNC(op_3068_4), 0, 12392 }, /* MOVEA */ +{ CPUFUNC(op_3070_4), 0, 12400 }, /* MOVEA */ +{ CPUFUNC(op_3078_4), 0, 12408 }, /* MOVEA */ +{ CPUFUNC(op_3079_4), 0, 12409 }, /* MOVEA */ +{ CPUFUNC(op_307a_4), 0, 12410 }, /* MOVEA */ +{ CPUFUNC(op_307b_4), 0, 12411 }, /* MOVEA */ +{ CPUFUNC(op_307c_4), 0, 12412 }, /* MOVEA */ +{ CPUFUNC(op_3080_4), 0, 12416 }, /* MOVE */ +{ CPUFUNC(op_3088_4), 0, 12424 }, /* MOVE */ +{ CPUFUNC(op_3090_4), 0, 12432 }, /* MOVE */ +{ CPUFUNC(op_3098_4), 0, 12440 }, /* MOVE */ +{ CPUFUNC(op_30a0_4), 0, 12448 }, /* MOVE */ +{ CPUFUNC(op_30a8_4), 0, 12456 }, /* MOVE */ +{ CPUFUNC(op_30b0_4), 0, 12464 }, /* MOVE */ +{ CPUFUNC(op_30b8_4), 0, 12472 }, /* MOVE */ +{ CPUFUNC(op_30b9_4), 0, 12473 }, /* MOVE */ +{ CPUFUNC(op_30ba_4), 0, 12474 }, /* MOVE */ +{ CPUFUNC(op_30bb_4), 0, 12475 }, /* MOVE */ +{ CPUFUNC(op_30bc_4), 0, 12476 }, /* MOVE */ +{ CPUFUNC(op_30c0_4), 0, 12480 }, /* MOVE */ +{ CPUFUNC(op_30c8_4), 0, 12488 }, /* MOVE */ +{ CPUFUNC(op_30d0_4), 0, 12496 }, /* MOVE */ +{ CPUFUNC(op_30d8_4), 0, 12504 }, /* MOVE */ +{ CPUFUNC(op_30e0_4), 0, 12512 }, /* MOVE */ +{ CPUFUNC(op_30e8_4), 0, 12520 }, /* MOVE */ +{ CPUFUNC(op_30f0_4), 0, 12528 }, /* MOVE */ +{ CPUFUNC(op_30f8_4), 0, 12536 }, /* MOVE */ +{ CPUFUNC(op_30f9_4), 0, 12537 }, /* MOVE */ +{ CPUFUNC(op_30fa_4), 0, 12538 }, /* MOVE */ +{ CPUFUNC(op_30fb_4), 0, 12539 }, /* MOVE */ +{ CPUFUNC(op_30fc_4), 0, 12540 }, /* MOVE */ +{ CPUFUNC(op_3100_4), 0, 12544 }, /* MOVE */ +{ CPUFUNC(op_3108_4), 0, 12552 }, /* MOVE */ +{ CPUFUNC(op_3110_4), 0, 12560 }, /* MOVE */ +{ CPUFUNC(op_3118_4), 0, 12568 }, /* MOVE */ +{ CPUFUNC(op_3120_4), 0, 12576 }, /* MOVE */ +{ CPUFUNC(op_3128_4), 0, 12584 }, /* MOVE */ +{ CPUFUNC(op_3130_4), 0, 12592 }, /* MOVE */ +{ CPUFUNC(op_3138_4), 0, 12600 }, /* MOVE */ +{ CPUFUNC(op_3139_4), 0, 12601 }, /* MOVE */ +{ CPUFUNC(op_313a_4), 0, 12602 }, /* MOVE */ +{ CPUFUNC(op_313b_4), 0, 12603 }, /* MOVE */ +{ CPUFUNC(op_313c_4), 0, 12604 }, /* MOVE */ +{ CPUFUNC(op_3140_4), 0, 12608 }, /* MOVE */ +{ CPUFUNC(op_3148_4), 0, 12616 }, /* MOVE */ +{ CPUFUNC(op_3150_4), 0, 12624 }, /* MOVE */ +{ CPUFUNC(op_3158_4), 0, 12632 }, /* MOVE */ +{ CPUFUNC(op_3160_4), 0, 12640 }, /* MOVE */ +{ CPUFUNC(op_3168_4), 0, 12648 }, /* MOVE */ +{ CPUFUNC(op_3170_4), 0, 12656 }, /* MOVE */ +{ CPUFUNC(op_3178_4), 0, 12664 }, /* MOVE */ +{ CPUFUNC(op_3179_4), 0, 12665 }, /* MOVE */ +{ CPUFUNC(op_317a_4), 0, 12666 }, /* MOVE */ +{ CPUFUNC(op_317b_4), 0, 12667 }, /* MOVE */ +{ CPUFUNC(op_317c_4), 0, 12668 }, /* MOVE */ +{ CPUFUNC(op_3180_4), 0, 12672 }, /* MOVE */ +{ CPUFUNC(op_3188_4), 0, 12680 }, /* MOVE */ +{ CPUFUNC(op_3190_4), 0, 12688 }, /* MOVE */ +{ CPUFUNC(op_3198_4), 0, 12696 }, /* MOVE */ +{ CPUFUNC(op_31a0_4), 0, 12704 }, /* MOVE */ +{ CPUFUNC(op_31a8_4), 0, 12712 }, /* MOVE */ +{ CPUFUNC(op_31b0_4), 0, 12720 }, /* MOVE */ +{ CPUFUNC(op_31b8_4), 0, 12728 }, /* MOVE */ +{ CPUFUNC(op_31b9_4), 0, 12729 }, /* MOVE */ +{ CPUFUNC(op_31ba_4), 0, 12730 }, /* MOVE */ +{ CPUFUNC(op_31bb_4), 0, 12731 }, /* MOVE */ +{ CPUFUNC(op_31bc_4), 0, 12732 }, /* MOVE */ +{ CPUFUNC(op_31c0_4), 0, 12736 }, /* MOVE */ +{ CPUFUNC(op_31c8_4), 0, 12744 }, /* MOVE */ +{ CPUFUNC(op_31d0_4), 0, 12752 }, /* MOVE */ +{ CPUFUNC(op_31d8_4), 0, 12760 }, /* MOVE */ +{ CPUFUNC(op_31e0_4), 0, 12768 }, /* MOVE */ +{ CPUFUNC(op_31e8_4), 0, 12776 }, /* MOVE */ +{ CPUFUNC(op_31f0_4), 0, 12784 }, /* MOVE */ +{ CPUFUNC(op_31f8_4), 0, 12792 }, /* MOVE */ +{ CPUFUNC(op_31f9_4), 0, 12793 }, /* MOVE */ +{ CPUFUNC(op_31fa_4), 0, 12794 }, /* MOVE */ +{ CPUFUNC(op_31fb_4), 0, 12795 }, /* MOVE */ +{ CPUFUNC(op_31fc_4), 0, 12796 }, /* MOVE */ +{ CPUFUNC(op_33c0_4), 0, 13248 }, /* MOVE */ +{ CPUFUNC(op_33c8_4), 0, 13256 }, /* MOVE */ +{ CPUFUNC(op_33d0_4), 0, 13264 }, /* MOVE */ +{ CPUFUNC(op_33d8_4), 0, 13272 }, /* MOVE */ +{ CPUFUNC(op_33e0_4), 0, 13280 }, /* MOVE */ +{ CPUFUNC(op_33e8_4), 0, 13288 }, /* MOVE */ +{ CPUFUNC(op_33f0_4), 0, 13296 }, /* MOVE */ +{ CPUFUNC(op_33f8_4), 0, 13304 }, /* MOVE */ +{ CPUFUNC(op_33f9_4), 0, 13305 }, /* MOVE */ +{ CPUFUNC(op_33fa_4), 0, 13306 }, /* MOVE */ +{ CPUFUNC(op_33fb_4), 0, 13307 }, /* MOVE */ +{ CPUFUNC(op_33fc_4), 0, 13308 }, /* MOVE */ +{ CPUFUNC(op_4000_4), 0, 16384 }, /* NEGX */ +{ CPUFUNC(op_4010_4), 0, 16400 }, /* NEGX */ +{ CPUFUNC(op_4018_4), 0, 16408 }, /* NEGX */ +{ CPUFUNC(op_4020_4), 0, 16416 }, /* NEGX */ +{ CPUFUNC(op_4028_4), 0, 16424 }, /* NEGX */ +{ CPUFUNC(op_4030_4), 0, 16432 }, /* NEGX */ +{ CPUFUNC(op_4038_4), 0, 16440 }, /* NEGX */ +{ CPUFUNC(op_4039_4), 0, 16441 }, /* NEGX */ +{ CPUFUNC(op_4040_4), 0, 16448 }, /* NEGX */ +{ CPUFUNC(op_4050_4), 0, 16464 }, /* NEGX */ +{ CPUFUNC(op_4058_4), 0, 16472 }, /* NEGX */ +{ CPUFUNC(op_4060_4), 0, 16480 }, /* NEGX */ +{ CPUFUNC(op_4068_4), 0, 16488 }, /* NEGX */ +{ CPUFUNC(op_4070_4), 0, 16496 }, /* NEGX */ +{ CPUFUNC(op_4078_4), 0, 16504 }, /* NEGX */ +{ CPUFUNC(op_4079_4), 0, 16505 }, /* NEGX */ +{ CPUFUNC(op_4080_4), 0, 16512 }, /* NEGX */ +{ CPUFUNC(op_4090_4), 0, 16528 }, /* NEGX */ +{ CPUFUNC(op_4098_4), 0, 16536 }, /* NEGX */ +{ CPUFUNC(op_40a0_4), 0, 16544 }, /* NEGX */ +{ CPUFUNC(op_40a8_4), 0, 16552 }, /* NEGX */ +{ CPUFUNC(op_40b0_4), 0, 16560 }, /* NEGX */ +{ CPUFUNC(op_40b8_4), 0, 16568 }, /* NEGX */ +{ CPUFUNC(op_40b9_4), 0, 16569 }, /* NEGX */ +{ CPUFUNC(op_40c0_4), 0, 16576 }, /* MVSR2 */ +{ CPUFUNC(op_40d0_4), 0, 16592 }, /* MVSR2 */ +{ CPUFUNC(op_40d8_4), 0, 16600 }, /* MVSR2 */ +{ CPUFUNC(op_40e0_4), 0, 16608 }, /* MVSR2 */ +{ CPUFUNC(op_40e8_4), 0, 16616 }, /* MVSR2 */ +{ CPUFUNC(op_40f0_4), 0, 16624 }, /* MVSR2 */ +{ CPUFUNC(op_40f8_4), 0, 16632 }, /* MVSR2 */ +{ CPUFUNC(op_40f9_4), 0, 16633 }, /* MVSR2 */ +{ CPUFUNC(op_4180_4), 0, 16768 }, /* CHK */ +{ CPUFUNC(op_4190_4), 0, 16784 }, /* CHK */ +{ CPUFUNC(op_4198_4), 0, 16792 }, /* CHK */ +{ CPUFUNC(op_41a0_4), 0, 16800 }, /* CHK */ +{ CPUFUNC(op_41a8_4), 0, 16808 }, /* CHK */ +{ CPUFUNC(op_41b0_4), 0, 16816 }, /* CHK */ +{ CPUFUNC(op_41b8_4), 0, 16824 }, /* CHK */ +{ CPUFUNC(op_41b9_4), 0, 16825 }, /* CHK */ +{ CPUFUNC(op_41ba_4), 0, 16826 }, /* CHK */ +{ CPUFUNC(op_41bb_4), 0, 16827 }, /* CHK */ +{ CPUFUNC(op_41bc_4), 0, 16828 }, /* CHK */ +{ CPUFUNC(op_41d0_4), 0, 16848 }, /* LEA */ +{ CPUFUNC(op_41e8_4), 0, 16872 }, /* LEA */ +{ CPUFUNC(op_41f0_4), 0, 16880 }, /* LEA */ +{ CPUFUNC(op_41f8_4), 0, 16888 }, /* LEA */ +{ CPUFUNC(op_41f9_4), 0, 16889 }, /* LEA */ +{ CPUFUNC(op_41fa_4), 0, 16890 }, /* LEA */ +{ CPUFUNC(op_41fb_4), 0, 16891 }, /* LEA */ +{ CPUFUNC(op_4200_4), 0, 16896 }, /* CLR */ +{ CPUFUNC(op_4210_4), 0, 16912 }, /* CLR */ +{ CPUFUNC(op_4218_4), 0, 16920 }, /* CLR */ +{ CPUFUNC(op_4220_4), 0, 16928 }, /* CLR */ +{ CPUFUNC(op_4228_4), 0, 16936 }, /* CLR */ +{ CPUFUNC(op_4230_4), 0, 16944 }, /* CLR */ +{ CPUFUNC(op_4238_4), 0, 16952 }, /* CLR */ +{ CPUFUNC(op_4239_4), 0, 16953 }, /* CLR */ +{ CPUFUNC(op_4240_4), 0, 16960 }, /* CLR */ +{ CPUFUNC(op_4250_4), 0, 16976 }, /* CLR */ +{ CPUFUNC(op_4258_4), 0, 16984 }, /* CLR */ +{ CPUFUNC(op_4260_4), 0, 16992 }, /* CLR */ +{ CPUFUNC(op_4268_4), 0, 17000 }, /* CLR */ +{ CPUFUNC(op_4270_4), 0, 17008 }, /* CLR */ +{ CPUFUNC(op_4278_4), 0, 17016 }, /* CLR */ +{ CPUFUNC(op_4279_4), 0, 17017 }, /* CLR */ +{ CPUFUNC(op_4280_4), 0, 17024 }, /* CLR */ +{ CPUFUNC(op_4290_4), 0, 17040 }, /* CLR */ +{ CPUFUNC(op_4298_4), 0, 17048 }, /* CLR */ +{ CPUFUNC(op_42a0_4), 0, 17056 }, /* CLR */ +{ CPUFUNC(op_42a8_4), 0, 17064 }, /* CLR */ +{ CPUFUNC(op_42b0_4), 0, 17072 }, /* CLR */ +{ CPUFUNC(op_42b8_4), 0, 17080 }, /* CLR */ +{ CPUFUNC(op_42b9_4), 0, 17081 }, /* CLR */ +{ CPUFUNC(op_4400_4), 0, 17408 }, /* NEG */ +{ CPUFUNC(op_4410_4), 0, 17424 }, /* NEG */ +{ CPUFUNC(op_4418_4), 0, 17432 }, /* NEG */ +{ CPUFUNC(op_4420_4), 0, 17440 }, /* NEG */ +{ CPUFUNC(op_4428_4), 0, 17448 }, /* NEG */ +{ CPUFUNC(op_4430_4), 0, 17456 }, /* NEG */ +{ CPUFUNC(op_4438_4), 0, 17464 }, /* NEG */ +{ CPUFUNC(op_4439_4), 0, 17465 }, /* NEG */ +{ CPUFUNC(op_4440_4), 0, 17472 }, /* NEG */ +{ CPUFUNC(op_4450_4), 0, 17488 }, /* NEG */ +{ CPUFUNC(op_4458_4), 0, 17496 }, /* NEG */ +{ CPUFUNC(op_4460_4), 0, 17504 }, /* NEG */ +{ CPUFUNC(op_4468_4), 0, 17512 }, /* NEG */ +{ CPUFUNC(op_4470_4), 0, 17520 }, /* NEG */ +{ CPUFUNC(op_4478_4), 0, 17528 }, /* NEG */ +{ CPUFUNC(op_4479_4), 0, 17529 }, /* NEG */ +{ CPUFUNC(op_4480_4), 0, 17536 }, /* NEG */ +{ CPUFUNC(op_4490_4), 0, 17552 }, /* NEG */ +{ CPUFUNC(op_4498_4), 0, 17560 }, /* NEG */ +{ CPUFUNC(op_44a0_4), 0, 17568 }, /* NEG */ +{ CPUFUNC(op_44a8_4), 0, 17576 }, /* NEG */ +{ CPUFUNC(op_44b0_4), 0, 17584 }, /* NEG */ +{ CPUFUNC(op_44b8_4), 0, 17592 }, /* NEG */ +{ CPUFUNC(op_44b9_4), 0, 17593 }, /* NEG */ +{ CPUFUNC(op_44c0_4), 0, 17600 }, /* MV2SR */ +{ CPUFUNC(op_44d0_4), 0, 17616 }, /* MV2SR */ +{ CPUFUNC(op_44d8_4), 0, 17624 }, /* MV2SR */ +{ CPUFUNC(op_44e0_4), 0, 17632 }, /* MV2SR */ +{ CPUFUNC(op_44e8_4), 0, 17640 }, /* MV2SR */ +{ CPUFUNC(op_44f0_4), 0, 17648 }, /* MV2SR */ +{ CPUFUNC(op_44f8_4), 0, 17656 }, /* MV2SR */ +{ CPUFUNC(op_44f9_4), 0, 17657 }, /* MV2SR */ +{ CPUFUNC(op_44fa_4), 0, 17658 }, /* MV2SR */ +{ CPUFUNC(op_44fb_4), 0, 17659 }, /* MV2SR */ +{ CPUFUNC(op_44fc_4), 0, 17660 }, /* MV2SR */ +{ CPUFUNC(op_4600_4), 0, 17920 }, /* NOT */ +{ CPUFUNC(op_4610_4), 0, 17936 }, /* NOT */ +{ CPUFUNC(op_4618_4), 0, 17944 }, /* NOT */ +{ CPUFUNC(op_4620_4), 0, 17952 }, /* NOT */ +{ CPUFUNC(op_4628_4), 0, 17960 }, /* NOT */ +{ CPUFUNC(op_4630_4), 0, 17968 }, /* NOT */ +{ CPUFUNC(op_4638_4), 0, 17976 }, /* NOT */ +{ CPUFUNC(op_4639_4), 0, 17977 }, /* NOT */ +{ CPUFUNC(op_4640_4), 0, 17984 }, /* NOT */ +{ CPUFUNC(op_4650_4), 0, 18000 }, /* NOT */ +{ CPUFUNC(op_4658_4), 0, 18008 }, /* NOT */ +{ CPUFUNC(op_4660_4), 0, 18016 }, /* NOT */ +{ CPUFUNC(op_4668_4), 0, 18024 }, /* NOT */ +{ CPUFUNC(op_4670_4), 0, 18032 }, /* NOT */ +{ CPUFUNC(op_4678_4), 0, 18040 }, /* NOT */ +{ CPUFUNC(op_4679_4), 0, 18041 }, /* NOT */ +{ CPUFUNC(op_4680_4), 0, 18048 }, /* NOT */ +{ CPUFUNC(op_4690_4), 0, 18064 }, /* NOT */ +{ CPUFUNC(op_4698_4), 0, 18072 }, /* NOT */ +{ CPUFUNC(op_46a0_4), 0, 18080 }, /* NOT */ +{ CPUFUNC(op_46a8_4), 0, 18088 }, /* NOT */ +{ CPUFUNC(op_46b0_4), 0, 18096 }, /* NOT */ +{ CPUFUNC(op_46b8_4), 0, 18104 }, /* NOT */ +{ CPUFUNC(op_46b9_4), 0, 18105 }, /* NOT */ +{ CPUFUNC(op_46c0_4), 0, 18112 }, /* MV2SR */ +{ CPUFUNC(op_46d0_4), 0, 18128 }, /* MV2SR */ +{ CPUFUNC(op_46d8_4), 0, 18136 }, /* MV2SR */ +{ CPUFUNC(op_46e0_4), 0, 18144 }, /* MV2SR */ +{ CPUFUNC(op_46e8_4), 0, 18152 }, /* MV2SR */ +{ CPUFUNC(op_46f0_4), 0, 18160 }, /* MV2SR */ +{ CPUFUNC(op_46f8_4), 0, 18168 }, /* MV2SR */ +{ CPUFUNC(op_46f9_4), 0, 18169 }, /* MV2SR */ +{ CPUFUNC(op_46fa_4), 0, 18170 }, /* MV2SR */ +{ CPUFUNC(op_46fb_4), 0, 18171 }, /* MV2SR */ +{ CPUFUNC(op_46fc_4), 0, 18172 }, /* MV2SR */ +{ CPUFUNC(op_4800_4), 0, 18432 }, /* NBCD */ +{ CPUFUNC(op_4810_4), 0, 18448 }, /* NBCD */ +{ CPUFUNC(op_4818_4), 0, 18456 }, /* NBCD */ +{ CPUFUNC(op_4820_4), 0, 18464 }, /* NBCD */ +{ CPUFUNC(op_4828_4), 0, 18472 }, /* NBCD */ +{ CPUFUNC(op_4830_4), 0, 18480 }, /* NBCD */ +{ CPUFUNC(op_4838_4), 0, 18488 }, /* NBCD */ +{ CPUFUNC(op_4839_4), 0, 18489 }, /* NBCD */ +{ CPUFUNC(op_4840_4), 0, 18496 }, /* SWAP */ +{ CPUFUNC(op_4850_4), 0, 18512 }, /* PEA */ +{ CPUFUNC(op_4868_4), 0, 18536 }, /* PEA */ +{ CPUFUNC(op_4870_4), 0, 18544 }, /* PEA */ +{ CPUFUNC(op_4878_4), 0, 18552 }, /* PEA */ +{ CPUFUNC(op_4879_4), 0, 18553 }, /* PEA */ +{ CPUFUNC(op_487a_4), 0, 18554 }, /* PEA */ +{ CPUFUNC(op_487b_4), 0, 18555 }, /* PEA */ +{ CPUFUNC(op_4880_4), 0, 18560 }, /* EXT */ +{ CPUFUNC(op_4890_4), 0, 18576 }, /* MVMLE */ +{ CPUFUNC(op_48a0_4), 0, 18592 }, /* MVMLE */ +{ CPUFUNC(op_48a8_4), 0, 18600 }, /* MVMLE */ +{ CPUFUNC(op_48b0_4), 0, 18608 }, /* MVMLE */ +{ CPUFUNC(op_48b8_4), 0, 18616 }, /* MVMLE */ +{ CPUFUNC(op_48b9_4), 0, 18617 }, /* MVMLE */ +{ CPUFUNC(op_48c0_4), 0, 18624 }, /* EXT */ +{ CPUFUNC(op_48d0_4), 0, 18640 }, /* MVMLE */ +{ CPUFUNC(op_48e0_4), 0, 18656 }, /* MVMLE */ +{ CPUFUNC(op_48e8_4), 0, 18664 }, /* MVMLE */ +{ CPUFUNC(op_48f0_4), 0, 18672 }, /* MVMLE */ +{ CPUFUNC(op_48f8_4), 0, 18680 }, /* MVMLE */ +{ CPUFUNC(op_48f9_4), 0, 18681 }, /* MVMLE */ +{ CPUFUNC(op_4a00_4), 0, 18944 }, /* TST */ +{ CPUFUNC(op_4a10_4), 0, 18960 }, /* TST */ +{ CPUFUNC(op_4a18_4), 0, 18968 }, /* TST */ +{ CPUFUNC(op_4a20_4), 0, 18976 }, /* TST */ +{ CPUFUNC(op_4a28_4), 0, 18984 }, /* TST */ +{ CPUFUNC(op_4a30_4), 0, 18992 }, /* TST */ +{ CPUFUNC(op_4a38_4), 0, 19000 }, /* TST */ +{ CPUFUNC(op_4a39_4), 0, 19001 }, /* TST */ +{ CPUFUNC(op_4a3a_4), 0, 19002 }, /* TST */ +{ CPUFUNC(op_4a3b_4), 0, 19003 }, /* TST */ +{ CPUFUNC(op_4a3c_4), 0, 19004 }, /* TST */ +{ CPUFUNC(op_4a40_4), 0, 19008 }, /* TST */ +{ CPUFUNC(op_4a48_4), 0, 19016 }, /* TST */ +{ CPUFUNC(op_4a50_4), 0, 19024 }, /* TST */ +{ CPUFUNC(op_4a58_4), 0, 19032 }, /* TST */ +{ CPUFUNC(op_4a60_4), 0, 19040 }, /* TST */ +{ CPUFUNC(op_4a68_4), 0, 19048 }, /* TST */ +{ CPUFUNC(op_4a70_4), 0, 19056 }, /* TST */ +{ CPUFUNC(op_4a78_4), 0, 19064 }, /* TST */ +{ CPUFUNC(op_4a79_4), 0, 19065 }, /* TST */ +{ CPUFUNC(op_4a7a_4), 0, 19066 }, /* TST */ +{ CPUFUNC(op_4a7b_4), 0, 19067 }, /* TST */ +{ CPUFUNC(op_4a7c_4), 0, 19068 }, /* TST */ +{ CPUFUNC(op_4a80_4), 0, 19072 }, /* TST */ +{ CPUFUNC(op_4a88_4), 0, 19080 }, /* TST */ +{ CPUFUNC(op_4a90_4), 0, 19088 }, /* TST */ +{ CPUFUNC(op_4a98_4), 0, 19096 }, /* TST */ +{ CPUFUNC(op_4aa0_4), 0, 19104 }, /* TST */ +{ CPUFUNC(op_4aa8_4), 0, 19112 }, /* TST */ +{ CPUFUNC(op_4ab0_4), 0, 19120 }, /* TST */ +{ CPUFUNC(op_4ab8_4), 0, 19128 }, /* TST */ +{ CPUFUNC(op_4ab9_4), 0, 19129 }, /* TST */ +{ CPUFUNC(op_4aba_4), 0, 19130 }, /* TST */ +{ CPUFUNC(op_4abb_4), 0, 19131 }, /* TST */ +{ CPUFUNC(op_4abc_4), 0, 19132 }, /* TST */ +{ CPUFUNC(op_4ac0_4), 0, 19136 }, /* TAS */ +{ CPUFUNC(op_4ad0_4), 0, 19152 }, /* TAS */ +{ CPUFUNC(op_4ad8_4), 0, 19160 }, /* TAS */ +{ CPUFUNC(op_4ae0_4), 0, 19168 }, /* TAS */ +{ CPUFUNC(op_4ae8_4), 0, 19176 }, /* TAS */ +{ CPUFUNC(op_4af0_4), 0, 19184 }, /* TAS */ +{ CPUFUNC(op_4af8_4), 0, 19192 }, /* TAS */ +{ CPUFUNC(op_4af9_4), 0, 19193 }, /* TAS */ +{ CPUFUNC(op_4c90_4), 0, 19600 }, /* MVMEL */ +{ CPUFUNC(op_4c98_4), 0, 19608 }, /* MVMEL */ +{ CPUFUNC(op_4ca8_4), 0, 19624 }, /* MVMEL */ +{ CPUFUNC(op_4cb0_4), 0, 19632 }, /* MVMEL */ +{ CPUFUNC(op_4cb8_4), 0, 19640 }, /* MVMEL */ +{ CPUFUNC(op_4cb9_4), 0, 19641 }, /* MVMEL */ +{ CPUFUNC(op_4cba_4), 0, 19642 }, /* MVMEL */ +{ CPUFUNC(op_4cbb_4), 0, 19643 }, /* MVMEL */ +{ CPUFUNC(op_4cd0_4), 0, 19664 }, /* MVMEL */ +{ CPUFUNC(op_4cd8_4), 0, 19672 }, /* MVMEL */ +{ CPUFUNC(op_4ce8_4), 0, 19688 }, /* MVMEL */ +{ CPUFUNC(op_4cf0_4), 0, 19696 }, /* MVMEL */ +{ CPUFUNC(op_4cf8_4), 0, 19704 }, /* MVMEL */ +{ CPUFUNC(op_4cf9_4), 0, 19705 }, /* MVMEL */ +{ CPUFUNC(op_4cfa_4), 0, 19706 }, /* MVMEL */ +{ CPUFUNC(op_4cfb_4), 0, 19707 }, /* MVMEL */ +{ CPUFUNC(op_4e40_4), 0, 20032 }, /* TRAP */ +{ CPUFUNC(op_4e50_4), 0, 20048 }, /* LINK */ +{ CPUFUNC(op_4e58_4), 0, 20056 }, /* UNLK */ +{ CPUFUNC(op_4e60_4), 0, 20064 }, /* MVR2USP */ +{ CPUFUNC(op_4e68_4), 0, 20072 }, /* MVUSP2R */ +{ CPUFUNC(op_4e70_4), 0, 20080 }, /* RESET */ +{ CPUFUNC(op_4e71_4), 0, 20081 }, /* NOP */ +{ CPUFUNC(op_4e72_4), 0, 20082 }, /* STOP */ +{ CPUFUNC(op_4e73_4), 0, 20083 }, /* RTE */ +{ CPUFUNC(op_4e74_4), 0, 20084 }, /* RTD */ +{ CPUFUNC(op_4e75_4), 0, 20085 }, /* RTS */ +{ CPUFUNC(op_4e76_4), 0, 20086 }, /* TRAPV */ +{ CPUFUNC(op_4e77_4), 0, 20087 }, /* RTR */ +{ CPUFUNC(op_4e90_4), 0, 20112 }, /* JSR */ +{ CPUFUNC(op_4ea8_4), 0, 20136 }, /* JSR */ +{ CPUFUNC(op_4eb0_4), 0, 20144 }, /* JSR */ +{ CPUFUNC(op_4eb8_4), 0, 20152 }, /* JSR */ +{ CPUFUNC(op_4eb9_4), 0, 20153 }, /* JSR */ +{ CPUFUNC(op_4eba_4), 0, 20154 }, /* JSR */ +{ CPUFUNC(op_4ebb_4), 0, 20155 }, /* JSR */ +{ CPUFUNC(op_4ed0_4), 0, 20176 }, /* JMP */ +{ CPUFUNC(op_4ee8_4), 0, 20200 }, /* JMP */ +{ CPUFUNC(op_4ef0_4), 0, 20208 }, /* JMP */ +{ CPUFUNC(op_4ef8_4), 0, 20216 }, /* JMP */ +{ CPUFUNC(op_4ef9_4), 0, 20217 }, /* JMP */ +{ CPUFUNC(op_4efa_4), 0, 20218 }, /* JMP */ +{ CPUFUNC(op_4efb_4), 0, 20219 }, /* JMP */ +{ CPUFUNC(op_5000_4), 0, 20480 }, /* ADD */ +{ CPUFUNC(op_5010_4), 0, 20496 }, /* ADD */ +{ CPUFUNC(op_5018_4), 0, 20504 }, /* ADD */ +{ CPUFUNC(op_5020_4), 0, 20512 }, /* ADD */ +{ CPUFUNC(op_5028_4), 0, 20520 }, /* ADD */ +{ CPUFUNC(op_5030_4), 0, 20528 }, /* ADD */ +{ CPUFUNC(op_5038_4), 0, 20536 }, /* ADD */ +{ CPUFUNC(op_5039_4), 0, 20537 }, /* ADD */ +{ CPUFUNC(op_5040_4), 0, 20544 }, /* ADD */ +{ CPUFUNC(op_5048_4), 0, 20552 }, /* ADDA */ +{ CPUFUNC(op_5050_4), 0, 20560 }, /* ADD */ +{ CPUFUNC(op_5058_4), 0, 20568 }, /* ADD */ +{ CPUFUNC(op_5060_4), 0, 20576 }, /* ADD */ +{ CPUFUNC(op_5068_4), 0, 20584 }, /* ADD */ +{ CPUFUNC(op_5070_4), 0, 20592 }, /* ADD */ +{ CPUFUNC(op_5078_4), 0, 20600 }, /* ADD */ +{ CPUFUNC(op_5079_4), 0, 20601 }, /* ADD */ +{ CPUFUNC(op_5080_4), 0, 20608 }, /* ADD */ +{ CPUFUNC(op_5088_4), 0, 20616 }, /* ADDA */ +{ CPUFUNC(op_5090_4), 0, 20624 }, /* ADD */ +{ CPUFUNC(op_5098_4), 0, 20632 }, /* ADD */ +{ CPUFUNC(op_50a0_4), 0, 20640 }, /* ADD */ +{ CPUFUNC(op_50a8_4), 0, 20648 }, /* ADD */ +{ CPUFUNC(op_50b0_4), 0, 20656 }, /* ADD */ +{ CPUFUNC(op_50b8_4), 0, 20664 }, /* ADD */ +{ CPUFUNC(op_50b9_4), 0, 20665 }, /* ADD */ +{ CPUFUNC(op_50c0_4), 0, 20672 }, /* Scc */ +{ CPUFUNC(op_50c8_4), 0, 20680 }, /* DBcc */ +{ CPUFUNC(op_50d0_4), 0, 20688 }, /* Scc */ +{ CPUFUNC(op_50d8_4), 0, 20696 }, /* Scc */ +{ CPUFUNC(op_50e0_4), 0, 20704 }, /* Scc */ +{ CPUFUNC(op_50e8_4), 0, 20712 }, /* Scc */ +{ CPUFUNC(op_50f0_4), 0, 20720 }, /* Scc */ +{ CPUFUNC(op_50f8_4), 0, 20728 }, /* Scc */ +{ CPUFUNC(op_50f9_4), 0, 20729 }, /* Scc */ +{ CPUFUNC(op_5100_4), 0, 20736 }, /* SUB */ +{ CPUFUNC(op_5110_4), 0, 20752 }, /* SUB */ +{ CPUFUNC(op_5118_4), 0, 20760 }, /* SUB */ +{ CPUFUNC(op_5120_4), 0, 20768 }, /* SUB */ +{ CPUFUNC(op_5128_4), 0, 20776 }, /* SUB */ +{ CPUFUNC(op_5130_4), 0, 20784 }, /* SUB */ +{ CPUFUNC(op_5138_4), 0, 20792 }, /* SUB */ +{ CPUFUNC(op_5139_4), 0, 20793 }, /* SUB */ +{ CPUFUNC(op_5140_4), 0, 20800 }, /* SUB */ +{ CPUFUNC(op_5148_4), 0, 20808 }, /* SUBA */ +{ CPUFUNC(op_5150_4), 0, 20816 }, /* SUB */ +{ CPUFUNC(op_5158_4), 0, 20824 }, /* SUB */ +{ CPUFUNC(op_5160_4), 0, 20832 }, /* SUB */ +{ CPUFUNC(op_5168_4), 0, 20840 }, /* SUB */ +{ CPUFUNC(op_5170_4), 0, 20848 }, /* SUB */ +{ CPUFUNC(op_5178_4), 0, 20856 }, /* SUB */ +{ CPUFUNC(op_5179_4), 0, 20857 }, /* SUB */ +{ CPUFUNC(op_5180_4), 0, 20864 }, /* SUB */ +{ CPUFUNC(op_5188_4), 0, 20872 }, /* SUBA */ +{ CPUFUNC(op_5190_4), 0, 20880 }, /* SUB */ +{ CPUFUNC(op_5198_4), 0, 20888 }, /* SUB */ +{ CPUFUNC(op_51a0_4), 0, 20896 }, /* SUB */ +{ CPUFUNC(op_51a8_4), 0, 20904 }, /* SUB */ +{ CPUFUNC(op_51b0_4), 0, 20912 }, /* SUB */ +{ CPUFUNC(op_51b8_4), 0, 20920 }, /* SUB */ +{ CPUFUNC(op_51b9_4), 0, 20921 }, /* SUB */ +{ CPUFUNC(op_51c0_4), 0, 20928 }, /* Scc */ +{ CPUFUNC(op_51c8_4), 0, 20936 }, /* DBcc */ +{ CPUFUNC(op_51d0_4), 0, 20944 }, /* Scc */ +{ CPUFUNC(op_51d8_4), 0, 20952 }, /* Scc */ +{ CPUFUNC(op_51e0_4), 0, 20960 }, /* Scc */ +{ CPUFUNC(op_51e8_4), 0, 20968 }, /* Scc */ +{ CPUFUNC(op_51f0_4), 0, 20976 }, /* Scc */ +{ CPUFUNC(op_51f8_4), 0, 20984 }, /* Scc */ +{ CPUFUNC(op_51f9_4), 0, 20985 }, /* Scc */ +{ CPUFUNC(op_52c0_4), 0, 21184 }, /* Scc */ +{ CPUFUNC(op_52c8_4), 0, 21192 }, /* DBcc */ +{ CPUFUNC(op_52d0_4), 0, 21200 }, /* Scc */ +{ CPUFUNC(op_52d8_4), 0, 21208 }, /* Scc */ +{ CPUFUNC(op_52e0_4), 0, 21216 }, /* Scc */ +{ CPUFUNC(op_52e8_4), 0, 21224 }, /* Scc */ +{ CPUFUNC(op_52f0_4), 0, 21232 }, /* Scc */ +{ CPUFUNC(op_52f8_4), 0, 21240 }, /* Scc */ +{ CPUFUNC(op_52f9_4), 0, 21241 }, /* Scc */ +{ CPUFUNC(op_53c0_4), 0, 21440 }, /* Scc */ +{ CPUFUNC(op_53c8_4), 0, 21448 }, /* DBcc */ +{ CPUFUNC(op_53d0_4), 0, 21456 }, /* Scc */ +{ CPUFUNC(op_53d8_4), 0, 21464 }, /* Scc */ +{ CPUFUNC(op_53e0_4), 0, 21472 }, /* Scc */ +{ CPUFUNC(op_53e8_4), 0, 21480 }, /* Scc */ +{ CPUFUNC(op_53f0_4), 0, 21488 }, /* Scc */ +{ CPUFUNC(op_53f8_4), 0, 21496 }, /* Scc */ +{ CPUFUNC(op_53f9_4), 0, 21497 }, /* Scc */ +{ CPUFUNC(op_54c0_4), 0, 21696 }, /* Scc */ +{ CPUFUNC(op_54c8_4), 0, 21704 }, /* DBcc */ +{ CPUFUNC(op_54d0_4), 0, 21712 }, /* Scc */ +{ CPUFUNC(op_54d8_4), 0, 21720 }, /* Scc */ +{ CPUFUNC(op_54e0_4), 0, 21728 }, /* Scc */ +{ CPUFUNC(op_54e8_4), 0, 21736 }, /* Scc */ +{ CPUFUNC(op_54f0_4), 0, 21744 }, /* Scc */ +{ CPUFUNC(op_54f8_4), 0, 21752 }, /* Scc */ +{ CPUFUNC(op_54f9_4), 0, 21753 }, /* Scc */ +{ CPUFUNC(op_55c0_4), 0, 21952 }, /* Scc */ +{ CPUFUNC(op_55c8_4), 0, 21960 }, /* DBcc */ +{ CPUFUNC(op_55d0_4), 0, 21968 }, /* Scc */ +{ CPUFUNC(op_55d8_4), 0, 21976 }, /* Scc */ +{ CPUFUNC(op_55e0_4), 0, 21984 }, /* Scc */ +{ CPUFUNC(op_55e8_4), 0, 21992 }, /* Scc */ +{ CPUFUNC(op_55f0_4), 0, 22000 }, /* Scc */ +{ CPUFUNC(op_55f8_4), 0, 22008 }, /* Scc */ +{ CPUFUNC(op_55f9_4), 0, 22009 }, /* Scc */ +{ CPUFUNC(op_56c0_4), 0, 22208 }, /* Scc */ +{ CPUFUNC(op_56c8_4), 0, 22216 }, /* DBcc */ +{ CPUFUNC(op_56d0_4), 0, 22224 }, /* Scc */ +{ CPUFUNC(op_56d8_4), 0, 22232 }, /* Scc */ +{ CPUFUNC(op_56e0_4), 0, 22240 }, /* Scc */ +{ CPUFUNC(op_56e8_4), 0, 22248 }, /* Scc */ +{ CPUFUNC(op_56f0_4), 0, 22256 }, /* Scc */ +{ CPUFUNC(op_56f8_4), 0, 22264 }, /* Scc */ +{ CPUFUNC(op_56f9_4), 0, 22265 }, /* Scc */ +{ CPUFUNC(op_57c0_4), 0, 22464 }, /* Scc */ +{ CPUFUNC(op_57c8_4), 0, 22472 }, /* DBcc */ +{ CPUFUNC(op_57d0_4), 0, 22480 }, /* Scc */ +{ CPUFUNC(op_57d8_4), 0, 22488 }, /* Scc */ +{ CPUFUNC(op_57e0_4), 0, 22496 }, /* Scc */ +{ CPUFUNC(op_57e8_4), 0, 22504 }, /* Scc */ +{ CPUFUNC(op_57f0_4), 0, 22512 }, /* Scc */ +{ CPUFUNC(op_57f8_4), 0, 22520 }, /* Scc */ +{ CPUFUNC(op_57f9_4), 0, 22521 }, /* Scc */ +{ CPUFUNC(op_58c0_4), 0, 22720 }, /* Scc */ +{ CPUFUNC(op_58c8_4), 0, 22728 }, /* DBcc */ +{ CPUFUNC(op_58d0_4), 0, 22736 }, /* Scc */ +{ CPUFUNC(op_58d8_4), 0, 22744 }, /* Scc */ +{ CPUFUNC(op_58e0_4), 0, 22752 }, /* Scc */ +{ CPUFUNC(op_58e8_4), 0, 22760 }, /* Scc */ +{ CPUFUNC(op_58f0_4), 0, 22768 }, /* Scc */ +{ CPUFUNC(op_58f8_4), 0, 22776 }, /* Scc */ +{ CPUFUNC(op_58f9_4), 0, 22777 }, /* Scc */ +{ CPUFUNC(op_59c0_4), 0, 22976 }, /* Scc */ +{ CPUFUNC(op_59c8_4), 0, 22984 }, /* DBcc */ +{ CPUFUNC(op_59d0_4), 0, 22992 }, /* Scc */ +{ CPUFUNC(op_59d8_4), 0, 23000 }, /* Scc */ +{ CPUFUNC(op_59e0_4), 0, 23008 }, /* Scc */ +{ CPUFUNC(op_59e8_4), 0, 23016 }, /* Scc */ +{ CPUFUNC(op_59f0_4), 0, 23024 }, /* Scc */ +{ CPUFUNC(op_59f8_4), 0, 23032 }, /* Scc */ +{ CPUFUNC(op_59f9_4), 0, 23033 }, /* Scc */ +{ CPUFUNC(op_5ac0_4), 0, 23232 }, /* Scc */ +{ CPUFUNC(op_5ac8_4), 0, 23240 }, /* DBcc */ +{ CPUFUNC(op_5ad0_4), 0, 23248 }, /* Scc */ +{ CPUFUNC(op_5ad8_4), 0, 23256 }, /* Scc */ +{ CPUFUNC(op_5ae0_4), 0, 23264 }, /* Scc */ +{ CPUFUNC(op_5ae8_4), 0, 23272 }, /* Scc */ +{ CPUFUNC(op_5af0_4), 0, 23280 }, /* Scc */ +{ CPUFUNC(op_5af8_4), 0, 23288 }, /* Scc */ +{ CPUFUNC(op_5af9_4), 0, 23289 }, /* Scc */ +{ CPUFUNC(op_5bc0_4), 0, 23488 }, /* Scc */ +{ CPUFUNC(op_5bc8_4), 0, 23496 }, /* DBcc */ +{ CPUFUNC(op_5bd0_4), 0, 23504 }, /* Scc */ +{ CPUFUNC(op_5bd8_4), 0, 23512 }, /* Scc */ +{ CPUFUNC(op_5be0_4), 0, 23520 }, /* Scc */ +{ CPUFUNC(op_5be8_4), 0, 23528 }, /* Scc */ +{ CPUFUNC(op_5bf0_4), 0, 23536 }, /* Scc */ +{ CPUFUNC(op_5bf8_4), 0, 23544 }, /* Scc */ +{ CPUFUNC(op_5bf9_4), 0, 23545 }, /* Scc */ +{ CPUFUNC(op_5cc0_4), 0, 23744 }, /* Scc */ +{ CPUFUNC(op_5cc8_4), 0, 23752 }, /* DBcc */ +{ CPUFUNC(op_5cd0_4), 0, 23760 }, /* Scc */ +{ CPUFUNC(op_5cd8_4), 0, 23768 }, /* Scc */ +{ CPUFUNC(op_5ce0_4), 0, 23776 }, /* Scc */ +{ CPUFUNC(op_5ce8_4), 0, 23784 }, /* Scc */ +{ CPUFUNC(op_5cf0_4), 0, 23792 }, /* Scc */ +{ CPUFUNC(op_5cf8_4), 0, 23800 }, /* Scc */ +{ CPUFUNC(op_5cf9_4), 0, 23801 }, /* Scc */ +{ CPUFUNC(op_5dc0_4), 0, 24000 }, /* Scc */ +{ CPUFUNC(op_5dc8_4), 0, 24008 }, /* DBcc */ +{ CPUFUNC(op_5dd0_4), 0, 24016 }, /* Scc */ +{ CPUFUNC(op_5dd8_4), 0, 24024 }, /* Scc */ +{ CPUFUNC(op_5de0_4), 0, 24032 }, /* Scc */ +{ CPUFUNC(op_5de8_4), 0, 24040 }, /* Scc */ +{ CPUFUNC(op_5df0_4), 0, 24048 }, /* Scc */ +{ CPUFUNC(op_5df8_4), 0, 24056 }, /* Scc */ +{ CPUFUNC(op_5df9_4), 0, 24057 }, /* Scc */ +{ CPUFUNC(op_5ec0_4), 0, 24256 }, /* Scc */ +{ CPUFUNC(op_5ec8_4), 0, 24264 }, /* DBcc */ +{ CPUFUNC(op_5ed0_4), 0, 24272 }, /* Scc */ +{ CPUFUNC(op_5ed8_4), 0, 24280 }, /* Scc */ +{ CPUFUNC(op_5ee0_4), 0, 24288 }, /* Scc */ +{ CPUFUNC(op_5ee8_4), 0, 24296 }, /* Scc */ +{ CPUFUNC(op_5ef0_4), 0, 24304 }, /* Scc */ +{ CPUFUNC(op_5ef8_4), 0, 24312 }, /* Scc */ +{ CPUFUNC(op_5ef9_4), 0, 24313 }, /* Scc */ +{ CPUFUNC(op_5fc0_4), 0, 24512 }, /* Scc */ +{ CPUFUNC(op_5fc8_4), 0, 24520 }, /* DBcc */ +{ CPUFUNC(op_5fd0_4), 0, 24528 }, /* Scc */ +{ CPUFUNC(op_5fd8_4), 0, 24536 }, /* Scc */ +{ CPUFUNC(op_5fe0_4), 0, 24544 }, /* Scc */ +{ CPUFUNC(op_5fe8_4), 0, 24552 }, /* Scc */ +{ CPUFUNC(op_5ff0_4), 0, 24560 }, /* Scc */ +{ CPUFUNC(op_5ff8_4), 0, 24568 }, /* Scc */ +{ CPUFUNC(op_5ff9_4), 0, 24569 }, /* Scc */ +{ CPUFUNC(op_6000_4), 0, 24576 }, /* Bcc */ +{ CPUFUNC(op_6001_4), 0, 24577 }, /* Bcc */ +{ CPUFUNC(op_60ff_4), 0, 24831 }, /* Bcc */ +{ CPUFUNC(op_6100_4), 0, 24832 }, /* BSR */ +{ CPUFUNC(op_6101_4), 0, 24833 }, /* BSR */ +{ CPUFUNC(op_61ff_4), 0, 25087 }, /* BSR */ +{ CPUFUNC(op_6200_4), 0, 25088 }, /* Bcc */ +{ CPUFUNC(op_6201_4), 0, 25089 }, /* Bcc */ +{ CPUFUNC(op_62ff_4), 0, 25343 }, /* Bcc */ +{ CPUFUNC(op_6300_4), 0, 25344 }, /* Bcc */ +{ CPUFUNC(op_6301_4), 0, 25345 }, /* Bcc */ +{ CPUFUNC(op_63ff_4), 0, 25599 }, /* Bcc */ +{ CPUFUNC(op_6400_4), 0, 25600 }, /* Bcc */ +{ CPUFUNC(op_6401_4), 0, 25601 }, /* Bcc */ +{ CPUFUNC(op_64ff_4), 0, 25855 }, /* Bcc */ +{ CPUFUNC(op_6500_4), 0, 25856 }, /* Bcc */ +{ CPUFUNC(op_6501_4), 0, 25857 }, /* Bcc */ +{ CPUFUNC(op_65ff_4), 0, 26111 }, /* Bcc */ +{ CPUFUNC(op_6600_4), 0, 26112 }, /* Bcc */ +{ CPUFUNC(op_6601_4), 0, 26113 }, /* Bcc */ +{ CPUFUNC(op_66ff_4), 0, 26367 }, /* Bcc */ +{ CPUFUNC(op_6700_4), 0, 26368 }, /* Bcc */ +{ CPUFUNC(op_6701_4), 0, 26369 }, /* Bcc */ +{ CPUFUNC(op_67ff_4), 0, 26623 }, /* Bcc */ +{ CPUFUNC(op_6800_4), 0, 26624 }, /* Bcc */ +{ CPUFUNC(op_6801_4), 0, 26625 }, /* Bcc */ +{ CPUFUNC(op_68ff_4), 0, 26879 }, /* Bcc */ +{ CPUFUNC(op_6900_4), 0, 26880 }, /* Bcc */ +{ CPUFUNC(op_6901_4), 0, 26881 }, /* Bcc */ +{ CPUFUNC(op_69ff_4), 0, 27135 }, /* Bcc */ +{ CPUFUNC(op_6a00_4), 0, 27136 }, /* Bcc */ +{ CPUFUNC(op_6a01_4), 0, 27137 }, /* Bcc */ +{ CPUFUNC(op_6aff_4), 0, 27391 }, /* Bcc */ +{ CPUFUNC(op_6b00_4), 0, 27392 }, /* Bcc */ +{ CPUFUNC(op_6b01_4), 0, 27393 }, /* Bcc */ +{ CPUFUNC(op_6bff_4), 0, 27647 }, /* Bcc */ +{ CPUFUNC(op_6c00_4), 0, 27648 }, /* Bcc */ +{ CPUFUNC(op_6c01_4), 0, 27649 }, /* Bcc */ +{ CPUFUNC(op_6cff_4), 0, 27903 }, /* Bcc */ +{ CPUFUNC(op_6d00_4), 0, 27904 }, /* Bcc */ +{ CPUFUNC(op_6d01_4), 0, 27905 }, /* Bcc */ +{ CPUFUNC(op_6dff_4), 0, 28159 }, /* Bcc */ +{ CPUFUNC(op_6e00_4), 0, 28160 }, /* Bcc */ +{ CPUFUNC(op_6e01_4), 0, 28161 }, /* Bcc */ +{ CPUFUNC(op_6eff_4), 0, 28415 }, /* Bcc */ +{ CPUFUNC(op_6f00_4), 0, 28416 }, /* Bcc */ +{ CPUFUNC(op_6f01_4), 0, 28417 }, /* Bcc */ +{ CPUFUNC(op_6fff_4), 0, 28671 }, /* Bcc */ +{ CPUFUNC(op_7000_4), 0, 28672 }, /* MOVE */ +{ CPUFUNC(op_8000_4), 0, 32768 }, /* OR */ +{ CPUFUNC(op_8010_4), 0, 32784 }, /* OR */ +{ CPUFUNC(op_8018_4), 0, 32792 }, /* OR */ +{ CPUFUNC(op_8020_4), 0, 32800 }, /* OR */ +{ CPUFUNC(op_8028_4), 0, 32808 }, /* OR */ +{ CPUFUNC(op_8030_4), 0, 32816 }, /* OR */ +{ CPUFUNC(op_8038_4), 0, 32824 }, /* OR */ +{ CPUFUNC(op_8039_4), 0, 32825 }, /* OR */ +{ CPUFUNC(op_803a_4), 0, 32826 }, /* OR */ +{ CPUFUNC(op_803b_4), 0, 32827 }, /* OR */ +{ CPUFUNC(op_803c_4), 0, 32828 }, /* OR */ +{ CPUFUNC(op_8040_4), 0, 32832 }, /* OR */ +{ CPUFUNC(op_8050_4), 0, 32848 }, /* OR */ +{ CPUFUNC(op_8058_4), 0, 32856 }, /* OR */ +{ CPUFUNC(op_8060_4), 0, 32864 }, /* OR */ +{ CPUFUNC(op_8068_4), 0, 32872 }, /* OR */ +{ CPUFUNC(op_8070_4), 0, 32880 }, /* OR */ +{ CPUFUNC(op_8078_4), 0, 32888 }, /* OR */ +{ CPUFUNC(op_8079_4), 0, 32889 }, /* OR */ +{ CPUFUNC(op_807a_4), 0, 32890 }, /* OR */ +{ CPUFUNC(op_807b_4), 0, 32891 }, /* OR */ +{ CPUFUNC(op_807c_4), 0, 32892 }, /* OR */ +{ CPUFUNC(op_8080_4), 0, 32896 }, /* OR */ +{ CPUFUNC(op_8090_4), 0, 32912 }, /* OR */ +{ CPUFUNC(op_8098_4), 0, 32920 }, /* OR */ +{ CPUFUNC(op_80a0_4), 0, 32928 }, /* OR */ +{ CPUFUNC(op_80a8_4), 0, 32936 }, /* OR */ +{ CPUFUNC(op_80b0_4), 0, 32944 }, /* OR */ +{ CPUFUNC(op_80b8_4), 0, 32952 }, /* OR */ +{ CPUFUNC(op_80b9_4), 0, 32953 }, /* OR */ +{ CPUFUNC(op_80ba_4), 0, 32954 }, /* OR */ +{ CPUFUNC(op_80bb_4), 0, 32955 }, /* OR */ +{ CPUFUNC(op_80bc_4), 0, 32956 }, /* OR */ +{ CPUFUNC(op_80c0_4), 0, 32960 }, /* DIVU */ +{ CPUFUNC(op_80d0_4), 0, 32976 }, /* DIVU */ +{ CPUFUNC(op_80d8_4), 0, 32984 }, /* DIVU */ +{ CPUFUNC(op_80e0_4), 0, 32992 }, /* DIVU */ +{ CPUFUNC(op_80e8_4), 0, 33000 }, /* DIVU */ +{ CPUFUNC(op_80f0_4), 0, 33008 }, /* DIVU */ +{ CPUFUNC(op_80f8_4), 0, 33016 }, /* DIVU */ +{ CPUFUNC(op_80f9_4), 0, 33017 }, /* DIVU */ +{ CPUFUNC(op_80fa_4), 0, 33018 }, /* DIVU */ +{ CPUFUNC(op_80fb_4), 0, 33019 }, /* DIVU */ +{ CPUFUNC(op_80fc_4), 0, 33020 }, /* DIVU */ +{ CPUFUNC(op_8100_4), 0, 33024 }, /* SBCD */ +{ CPUFUNC(op_8108_4), 0, 33032 }, /* SBCD */ +{ CPUFUNC(op_8110_4), 0, 33040 }, /* OR */ +{ CPUFUNC(op_8118_4), 0, 33048 }, /* OR */ +{ CPUFUNC(op_8120_4), 0, 33056 }, /* OR */ +{ CPUFUNC(op_8128_4), 0, 33064 }, /* OR */ +{ CPUFUNC(op_8130_4), 0, 33072 }, /* OR */ +{ CPUFUNC(op_8138_4), 0, 33080 }, /* OR */ +{ CPUFUNC(op_8139_4), 0, 33081 }, /* OR */ +{ CPUFUNC(op_8150_4), 0, 33104 }, /* OR */ +{ CPUFUNC(op_8158_4), 0, 33112 }, /* OR */ +{ CPUFUNC(op_8160_4), 0, 33120 }, /* OR */ +{ CPUFUNC(op_8168_4), 0, 33128 }, /* OR */ +{ CPUFUNC(op_8170_4), 0, 33136 }, /* OR */ +{ CPUFUNC(op_8178_4), 0, 33144 }, /* OR */ +{ CPUFUNC(op_8179_4), 0, 33145 }, /* OR */ +{ CPUFUNC(op_8190_4), 0, 33168 }, /* OR */ +{ CPUFUNC(op_8198_4), 0, 33176 }, /* OR */ +{ CPUFUNC(op_81a0_4), 0, 33184 }, /* OR */ +{ CPUFUNC(op_81a8_4), 0, 33192 }, /* OR */ +{ CPUFUNC(op_81b0_4), 0, 33200 }, /* OR */ +{ CPUFUNC(op_81b8_4), 0, 33208 }, /* OR */ +{ CPUFUNC(op_81b9_4), 0, 33209 }, /* OR */ +{ CPUFUNC(op_81c0_4), 0, 33216 }, /* DIVS */ +{ CPUFUNC(op_81d0_4), 0, 33232 }, /* DIVS */ +{ CPUFUNC(op_81d8_4), 0, 33240 }, /* DIVS */ +{ CPUFUNC(op_81e0_4), 0, 33248 }, /* DIVS */ +{ CPUFUNC(op_81e8_4), 0, 33256 }, /* DIVS */ +{ CPUFUNC(op_81f0_4), 0, 33264 }, /* DIVS */ +{ CPUFUNC(op_81f8_4), 0, 33272 }, /* DIVS */ +{ CPUFUNC(op_81f9_4), 0, 33273 }, /* DIVS */ +{ CPUFUNC(op_81fa_4), 0, 33274 }, /* DIVS */ +{ CPUFUNC(op_81fb_4), 0, 33275 }, /* DIVS */ +{ CPUFUNC(op_81fc_4), 0, 33276 }, /* DIVS */ +{ CPUFUNC(op_9000_4), 0, 36864 }, /* SUB */ +{ CPUFUNC(op_9010_4), 0, 36880 }, /* SUB */ +{ CPUFUNC(op_9018_4), 0, 36888 }, /* SUB */ +{ CPUFUNC(op_9020_4), 0, 36896 }, /* SUB */ +{ CPUFUNC(op_9028_4), 0, 36904 }, /* SUB */ +{ CPUFUNC(op_9030_4), 0, 36912 }, /* SUB */ +{ CPUFUNC(op_9038_4), 0, 36920 }, /* SUB */ +{ CPUFUNC(op_9039_4), 0, 36921 }, /* SUB */ +{ CPUFUNC(op_903a_4), 0, 36922 }, /* SUB */ +{ CPUFUNC(op_903b_4), 0, 36923 }, /* SUB */ +{ CPUFUNC(op_903c_4), 0, 36924 }, /* SUB */ +{ CPUFUNC(op_9040_4), 0, 36928 }, /* SUB */ +{ CPUFUNC(op_9048_4), 0, 36936 }, /* SUB */ +{ CPUFUNC(op_9050_4), 0, 36944 }, /* SUB */ +{ CPUFUNC(op_9058_4), 0, 36952 }, /* SUB */ +{ CPUFUNC(op_9060_4), 0, 36960 }, /* SUB */ +{ CPUFUNC(op_9068_4), 0, 36968 }, /* SUB */ +{ CPUFUNC(op_9070_4), 0, 36976 }, /* SUB */ +{ CPUFUNC(op_9078_4), 0, 36984 }, /* SUB */ +{ CPUFUNC(op_9079_4), 0, 36985 }, /* SUB */ +{ CPUFUNC(op_907a_4), 0, 36986 }, /* SUB */ +{ CPUFUNC(op_907b_4), 0, 36987 }, /* SUB */ +{ CPUFUNC(op_907c_4), 0, 36988 }, /* SUB */ +{ CPUFUNC(op_9080_4), 0, 36992 }, /* SUB */ +{ CPUFUNC(op_9088_4), 0, 37000 }, /* SUB */ +{ CPUFUNC(op_9090_4), 0, 37008 }, /* SUB */ +{ CPUFUNC(op_9098_4), 0, 37016 }, /* SUB */ +{ CPUFUNC(op_90a0_4), 0, 37024 }, /* SUB */ +{ CPUFUNC(op_90a8_4), 0, 37032 }, /* SUB */ +{ CPUFUNC(op_90b0_4), 0, 37040 }, /* SUB */ +{ CPUFUNC(op_90b8_4), 0, 37048 }, /* SUB */ +{ CPUFUNC(op_90b9_4), 0, 37049 }, /* SUB */ +{ CPUFUNC(op_90ba_4), 0, 37050 }, /* SUB */ +{ CPUFUNC(op_90bb_4), 0, 37051 }, /* SUB */ +{ CPUFUNC(op_90bc_4), 0, 37052 }, /* SUB */ +{ CPUFUNC(op_90c0_4), 0, 37056 }, /* SUBA */ +{ CPUFUNC(op_90c8_4), 0, 37064 }, /* SUBA */ +{ CPUFUNC(op_90d0_4), 0, 37072 }, /* SUBA */ +{ CPUFUNC(op_90d8_4), 0, 37080 }, /* SUBA */ +{ CPUFUNC(op_90e0_4), 0, 37088 }, /* SUBA */ +{ CPUFUNC(op_90e8_4), 0, 37096 }, /* SUBA */ +{ CPUFUNC(op_90f0_4), 0, 37104 }, /* SUBA */ +{ CPUFUNC(op_90f8_4), 0, 37112 }, /* SUBA */ +{ CPUFUNC(op_90f9_4), 0, 37113 }, /* SUBA */ +{ CPUFUNC(op_90fa_4), 0, 37114 }, /* SUBA */ +{ CPUFUNC(op_90fb_4), 0, 37115 }, /* SUBA */ +{ CPUFUNC(op_90fc_4), 0, 37116 }, /* SUBA */ +{ CPUFUNC(op_9100_4), 0, 37120 }, /* SUBX */ +{ CPUFUNC(op_9108_4), 0, 37128 }, /* SUBX */ +{ CPUFUNC(op_9110_4), 0, 37136 }, /* SUB */ +{ CPUFUNC(op_9118_4), 0, 37144 }, /* SUB */ +{ CPUFUNC(op_9120_4), 0, 37152 }, /* SUB */ +{ CPUFUNC(op_9128_4), 0, 37160 }, /* SUB */ +{ CPUFUNC(op_9130_4), 0, 37168 }, /* SUB */ +{ CPUFUNC(op_9138_4), 0, 37176 }, /* SUB */ +{ CPUFUNC(op_9139_4), 0, 37177 }, /* SUB */ +{ CPUFUNC(op_9140_4), 0, 37184 }, /* SUBX */ +{ CPUFUNC(op_9148_4), 0, 37192 }, /* SUBX */ +{ CPUFUNC(op_9150_4), 0, 37200 }, /* SUB */ +{ CPUFUNC(op_9158_4), 0, 37208 }, /* SUB */ +{ CPUFUNC(op_9160_4), 0, 37216 }, /* SUB */ +{ CPUFUNC(op_9168_4), 0, 37224 }, /* SUB */ +{ CPUFUNC(op_9170_4), 0, 37232 }, /* SUB */ +{ CPUFUNC(op_9178_4), 0, 37240 }, /* SUB */ +{ CPUFUNC(op_9179_4), 0, 37241 }, /* SUB */ +{ CPUFUNC(op_9180_4), 0, 37248 }, /* SUBX */ +{ CPUFUNC(op_9188_4), 0, 37256 }, /* SUBX */ +{ CPUFUNC(op_9190_4), 0, 37264 }, /* SUB */ +{ CPUFUNC(op_9198_4), 0, 37272 }, /* SUB */ +{ CPUFUNC(op_91a0_4), 0, 37280 }, /* SUB */ +{ CPUFUNC(op_91a8_4), 0, 37288 }, /* SUB */ +{ CPUFUNC(op_91b0_4), 0, 37296 }, /* SUB */ +{ CPUFUNC(op_91b8_4), 0, 37304 }, /* SUB */ +{ CPUFUNC(op_91b9_4), 0, 37305 }, /* SUB */ +{ CPUFUNC(op_91c0_4), 0, 37312 }, /* SUBA */ +{ CPUFUNC(op_91c8_4), 0, 37320 }, /* SUBA */ +{ CPUFUNC(op_91d0_4), 0, 37328 }, /* SUBA */ +{ CPUFUNC(op_91d8_4), 0, 37336 }, /* SUBA */ +{ CPUFUNC(op_91e0_4), 0, 37344 }, /* SUBA */ +{ CPUFUNC(op_91e8_4), 0, 37352 }, /* SUBA */ +{ CPUFUNC(op_91f0_4), 0, 37360 }, /* SUBA */ +{ CPUFUNC(op_91f8_4), 0, 37368 }, /* SUBA */ +{ CPUFUNC(op_91f9_4), 0, 37369 }, /* SUBA */ +{ CPUFUNC(op_91fa_4), 0, 37370 }, /* SUBA */ +{ CPUFUNC(op_91fb_4), 0, 37371 }, /* SUBA */ +{ CPUFUNC(op_91fc_4), 0, 37372 }, /* SUBA */ +{ CPUFUNC(op_b000_4), 0, 45056 }, /* CMP */ +{ CPUFUNC(op_b010_4), 0, 45072 }, /* CMP */ +{ CPUFUNC(op_b018_4), 0, 45080 }, /* CMP */ +{ CPUFUNC(op_b020_4), 0, 45088 }, /* CMP */ +{ CPUFUNC(op_b028_4), 0, 45096 }, /* CMP */ +{ CPUFUNC(op_b030_4), 0, 45104 }, /* CMP */ +{ CPUFUNC(op_b038_4), 0, 45112 }, /* CMP */ +{ CPUFUNC(op_b039_4), 0, 45113 }, /* CMP */ +{ CPUFUNC(op_b03a_4), 0, 45114 }, /* CMP */ +{ CPUFUNC(op_b03b_4), 0, 45115 }, /* CMP */ +{ CPUFUNC(op_b03c_4), 0, 45116 }, /* CMP */ +{ CPUFUNC(op_b040_4), 0, 45120 }, /* CMP */ +{ CPUFUNC(op_b048_4), 0, 45128 }, /* CMP */ +{ CPUFUNC(op_b050_4), 0, 45136 }, /* CMP */ +{ CPUFUNC(op_b058_4), 0, 45144 }, /* CMP */ +{ CPUFUNC(op_b060_4), 0, 45152 }, /* CMP */ +{ CPUFUNC(op_b068_4), 0, 45160 }, /* CMP */ +{ CPUFUNC(op_b070_4), 0, 45168 }, /* CMP */ +{ CPUFUNC(op_b078_4), 0, 45176 }, /* CMP */ +{ CPUFUNC(op_b079_4), 0, 45177 }, /* CMP */ +{ CPUFUNC(op_b07a_4), 0, 45178 }, /* CMP */ +{ CPUFUNC(op_b07b_4), 0, 45179 }, /* CMP */ +{ CPUFUNC(op_b07c_4), 0, 45180 }, /* CMP */ +{ CPUFUNC(op_b080_4), 0, 45184 }, /* CMP */ +{ CPUFUNC(op_b088_4), 0, 45192 }, /* CMP */ +{ CPUFUNC(op_b090_4), 0, 45200 }, /* CMP */ +{ CPUFUNC(op_b098_4), 0, 45208 }, /* CMP */ +{ CPUFUNC(op_b0a0_4), 0, 45216 }, /* CMP */ +{ CPUFUNC(op_b0a8_4), 0, 45224 }, /* CMP */ +{ CPUFUNC(op_b0b0_4), 0, 45232 }, /* CMP */ +{ CPUFUNC(op_b0b8_4), 0, 45240 }, /* CMP */ +{ CPUFUNC(op_b0b9_4), 0, 45241 }, /* CMP */ +{ CPUFUNC(op_b0ba_4), 0, 45242 }, /* CMP */ +{ CPUFUNC(op_b0bb_4), 0, 45243 }, /* CMP */ +{ CPUFUNC(op_b0bc_4), 0, 45244 }, /* CMP */ +{ CPUFUNC(op_b0c0_4), 0, 45248 }, /* CMPA */ +{ CPUFUNC(op_b0c8_4), 0, 45256 }, /* CMPA */ +{ CPUFUNC(op_b0d0_4), 0, 45264 }, /* CMPA */ +{ CPUFUNC(op_b0d8_4), 0, 45272 }, /* CMPA */ +{ CPUFUNC(op_b0e0_4), 0, 45280 }, /* CMPA */ +{ CPUFUNC(op_b0e8_4), 0, 45288 }, /* CMPA */ +{ CPUFUNC(op_b0f0_4), 0, 45296 }, /* CMPA */ +{ CPUFUNC(op_b0f8_4), 0, 45304 }, /* CMPA */ +{ CPUFUNC(op_b0f9_4), 0, 45305 }, /* CMPA */ +{ CPUFUNC(op_b0fa_4), 0, 45306 }, /* CMPA */ +{ CPUFUNC(op_b0fb_4), 0, 45307 }, /* CMPA */ +{ CPUFUNC(op_b0fc_4), 0, 45308 }, /* CMPA */ +{ CPUFUNC(op_b100_4), 0, 45312 }, /* EOR */ +{ CPUFUNC(op_b108_4), 0, 45320 }, /* CMPM */ +{ CPUFUNC(op_b110_4), 0, 45328 }, /* EOR */ +{ CPUFUNC(op_b118_4), 0, 45336 }, /* EOR */ +{ CPUFUNC(op_b120_4), 0, 45344 }, /* EOR */ +{ CPUFUNC(op_b128_4), 0, 45352 }, /* EOR */ +{ CPUFUNC(op_b130_4), 0, 45360 }, /* EOR */ +{ CPUFUNC(op_b138_4), 0, 45368 }, /* EOR */ +{ CPUFUNC(op_b139_4), 0, 45369 }, /* EOR */ +{ CPUFUNC(op_b140_4), 0, 45376 }, /* EOR */ +{ CPUFUNC(op_b148_4), 0, 45384 }, /* CMPM */ +{ CPUFUNC(op_b150_4), 0, 45392 }, /* EOR */ +{ CPUFUNC(op_b158_4), 0, 45400 }, /* EOR */ +{ CPUFUNC(op_b160_4), 0, 45408 }, /* EOR */ +{ CPUFUNC(op_b168_4), 0, 45416 }, /* EOR */ +{ CPUFUNC(op_b170_4), 0, 45424 }, /* EOR */ +{ CPUFUNC(op_b178_4), 0, 45432 }, /* EOR */ +{ CPUFUNC(op_b179_4), 0, 45433 }, /* EOR */ +{ CPUFUNC(op_b180_4), 0, 45440 }, /* EOR */ +{ CPUFUNC(op_b188_4), 0, 45448 }, /* CMPM */ +{ CPUFUNC(op_b190_4), 0, 45456 }, /* EOR */ +{ CPUFUNC(op_b198_4), 0, 45464 }, /* EOR */ +{ CPUFUNC(op_b1a0_4), 0, 45472 }, /* EOR */ +{ CPUFUNC(op_b1a8_4), 0, 45480 }, /* EOR */ +{ CPUFUNC(op_b1b0_4), 0, 45488 }, /* EOR */ +{ CPUFUNC(op_b1b8_4), 0, 45496 }, /* EOR */ +{ CPUFUNC(op_b1b9_4), 0, 45497 }, /* EOR */ +{ CPUFUNC(op_b1c0_4), 0, 45504 }, /* CMPA */ +{ CPUFUNC(op_b1c8_4), 0, 45512 }, /* CMPA */ +{ CPUFUNC(op_b1d0_4), 0, 45520 }, /* CMPA */ +{ CPUFUNC(op_b1d8_4), 0, 45528 }, /* CMPA */ +{ CPUFUNC(op_b1e0_4), 0, 45536 }, /* CMPA */ +{ CPUFUNC(op_b1e8_4), 0, 45544 }, /* CMPA */ +{ CPUFUNC(op_b1f0_4), 0, 45552 }, /* CMPA */ +{ CPUFUNC(op_b1f8_4), 0, 45560 }, /* CMPA */ +{ CPUFUNC(op_b1f9_4), 0, 45561 }, /* CMPA */ +{ CPUFUNC(op_b1fa_4), 0, 45562 }, /* CMPA */ +{ CPUFUNC(op_b1fb_4), 0, 45563 }, /* CMPA */ +{ CPUFUNC(op_b1fc_4), 0, 45564 }, /* CMPA */ +{ CPUFUNC(op_c000_4), 0, 49152 }, /* AND */ +{ CPUFUNC(op_c010_4), 0, 49168 }, /* AND */ +{ CPUFUNC(op_c018_4), 0, 49176 }, /* AND */ +{ CPUFUNC(op_c020_4), 0, 49184 }, /* AND */ +{ CPUFUNC(op_c028_4), 0, 49192 }, /* AND */ +{ CPUFUNC(op_c030_4), 0, 49200 }, /* AND */ +{ CPUFUNC(op_c038_4), 0, 49208 }, /* AND */ +{ CPUFUNC(op_c039_4), 0, 49209 }, /* AND */ +{ CPUFUNC(op_c03a_4), 0, 49210 }, /* AND */ +{ CPUFUNC(op_c03b_4), 0, 49211 }, /* AND */ +{ CPUFUNC(op_c03c_4), 0, 49212 }, /* AND */ +{ CPUFUNC(op_c040_4), 0, 49216 }, /* AND */ +{ CPUFUNC(op_c050_4), 0, 49232 }, /* AND */ +{ CPUFUNC(op_c058_4), 0, 49240 }, /* AND */ +{ CPUFUNC(op_c060_4), 0, 49248 }, /* AND */ +{ CPUFUNC(op_c068_4), 0, 49256 }, /* AND */ +{ CPUFUNC(op_c070_4), 0, 49264 }, /* AND */ +{ CPUFUNC(op_c078_4), 0, 49272 }, /* AND */ +{ CPUFUNC(op_c079_4), 0, 49273 }, /* AND */ +{ CPUFUNC(op_c07a_4), 0, 49274 }, /* AND */ +{ CPUFUNC(op_c07b_4), 0, 49275 }, /* AND */ +{ CPUFUNC(op_c07c_4), 0, 49276 }, /* AND */ +{ CPUFUNC(op_c080_4), 0, 49280 }, /* AND */ +{ CPUFUNC(op_c090_4), 0, 49296 }, /* AND */ +{ CPUFUNC(op_c098_4), 0, 49304 }, /* AND */ +{ CPUFUNC(op_c0a0_4), 0, 49312 }, /* AND */ +{ CPUFUNC(op_c0a8_4), 0, 49320 }, /* AND */ +{ CPUFUNC(op_c0b0_4), 0, 49328 }, /* AND */ +{ CPUFUNC(op_c0b8_4), 0, 49336 }, /* AND */ +{ CPUFUNC(op_c0b9_4), 0, 49337 }, /* AND */ +{ CPUFUNC(op_c0ba_4), 0, 49338 }, /* AND */ +{ CPUFUNC(op_c0bb_4), 0, 49339 }, /* AND */ +{ CPUFUNC(op_c0bc_4), 0, 49340 }, /* AND */ +{ CPUFUNC(op_c0c0_4), 0, 49344 }, /* MULU */ +{ CPUFUNC(op_c0d0_4), 0, 49360 }, /* MULU */ +{ CPUFUNC(op_c0d8_4), 0, 49368 }, /* MULU */ +{ CPUFUNC(op_c0e0_4), 0, 49376 }, /* MULU */ +{ CPUFUNC(op_c0e8_4), 0, 49384 }, /* MULU */ +{ CPUFUNC(op_c0f0_4), 0, 49392 }, /* MULU */ +{ CPUFUNC(op_c0f8_4), 0, 49400 }, /* MULU */ +{ CPUFUNC(op_c0f9_4), 0, 49401 }, /* MULU */ +{ CPUFUNC(op_c0fa_4), 0, 49402 }, /* MULU */ +{ CPUFUNC(op_c0fb_4), 0, 49403 }, /* MULU */ +{ CPUFUNC(op_c0fc_4), 0, 49404 }, /* MULU */ +{ CPUFUNC(op_c100_4), 0, 49408 }, /* ABCD */ +{ CPUFUNC(op_c108_4), 0, 49416 }, /* ABCD */ +{ CPUFUNC(op_c110_4), 0, 49424 }, /* AND */ +{ CPUFUNC(op_c118_4), 0, 49432 }, /* AND */ +{ CPUFUNC(op_c120_4), 0, 49440 }, /* AND */ +{ CPUFUNC(op_c128_4), 0, 49448 }, /* AND */ +{ CPUFUNC(op_c130_4), 0, 49456 }, /* AND */ +{ CPUFUNC(op_c138_4), 0, 49464 }, /* AND */ +{ CPUFUNC(op_c139_4), 0, 49465 }, /* AND */ +{ CPUFUNC(op_c140_4), 0, 49472 }, /* EXG */ +{ CPUFUNC(op_c148_4), 0, 49480 }, /* EXG */ +{ CPUFUNC(op_c150_4), 0, 49488 }, /* AND */ +{ CPUFUNC(op_c158_4), 0, 49496 }, /* AND */ +{ CPUFUNC(op_c160_4), 0, 49504 }, /* AND */ +{ CPUFUNC(op_c168_4), 0, 49512 }, /* AND */ +{ CPUFUNC(op_c170_4), 0, 49520 }, /* AND */ +{ CPUFUNC(op_c178_4), 0, 49528 }, /* AND */ +{ CPUFUNC(op_c179_4), 0, 49529 }, /* AND */ +{ CPUFUNC(op_c188_4), 0, 49544 }, /* EXG */ +{ CPUFUNC(op_c190_4), 0, 49552 }, /* AND */ +{ CPUFUNC(op_c198_4), 0, 49560 }, /* AND */ +{ CPUFUNC(op_c1a0_4), 0, 49568 }, /* AND */ +{ CPUFUNC(op_c1a8_4), 0, 49576 }, /* AND */ +{ CPUFUNC(op_c1b0_4), 0, 49584 }, /* AND */ +{ CPUFUNC(op_c1b8_4), 0, 49592 }, /* AND */ +{ CPUFUNC(op_c1b9_4), 0, 49593 }, /* AND */ +{ CPUFUNC(op_c1c0_4), 0, 49600 }, /* MULS */ +{ CPUFUNC(op_c1d0_4), 0, 49616 }, /* MULS */ +{ CPUFUNC(op_c1d8_4), 0, 49624 }, /* MULS */ +{ CPUFUNC(op_c1e0_4), 0, 49632 }, /* MULS */ +{ CPUFUNC(op_c1e8_4), 0, 49640 }, /* MULS */ +{ CPUFUNC(op_c1f0_4), 0, 49648 }, /* MULS */ +{ CPUFUNC(op_c1f8_4), 0, 49656 }, /* MULS */ +{ CPUFUNC(op_c1f9_4), 0, 49657 }, /* MULS */ +{ CPUFUNC(op_c1fa_4), 0, 49658 }, /* MULS */ +{ CPUFUNC(op_c1fb_4), 0, 49659 }, /* MULS */ +{ CPUFUNC(op_c1fc_4), 0, 49660 }, /* MULS */ +{ CPUFUNC(op_d000_4), 0, 53248 }, /* ADD */ +{ CPUFUNC(op_d010_4), 0, 53264 }, /* ADD */ +{ CPUFUNC(op_d018_4), 0, 53272 }, /* ADD */ +{ CPUFUNC(op_d020_4), 0, 53280 }, /* ADD */ +{ CPUFUNC(op_d028_4), 0, 53288 }, /* ADD */ +{ CPUFUNC(op_d030_4), 0, 53296 }, /* ADD */ +{ CPUFUNC(op_d038_4), 0, 53304 }, /* ADD */ +{ CPUFUNC(op_d039_4), 0, 53305 }, /* ADD */ +{ CPUFUNC(op_d03a_4), 0, 53306 }, /* ADD */ +{ CPUFUNC(op_d03b_4), 0, 53307 }, /* ADD */ +{ CPUFUNC(op_d03c_4), 0, 53308 }, /* ADD */ +{ CPUFUNC(op_d040_4), 0, 53312 }, /* ADD */ +{ CPUFUNC(op_d048_4), 0, 53320 }, /* ADD */ +{ CPUFUNC(op_d050_4), 0, 53328 }, /* ADD */ +{ CPUFUNC(op_d058_4), 0, 53336 }, /* ADD */ +{ CPUFUNC(op_d060_4), 0, 53344 }, /* ADD */ +{ CPUFUNC(op_d068_4), 0, 53352 }, /* ADD */ +{ CPUFUNC(op_d070_4), 0, 53360 }, /* ADD */ +{ CPUFUNC(op_d078_4), 0, 53368 }, /* ADD */ +{ CPUFUNC(op_d079_4), 0, 53369 }, /* ADD */ +{ CPUFUNC(op_d07a_4), 0, 53370 }, /* ADD */ +{ CPUFUNC(op_d07b_4), 0, 53371 }, /* ADD */ +{ CPUFUNC(op_d07c_4), 0, 53372 }, /* ADD */ +{ CPUFUNC(op_d080_4), 0, 53376 }, /* ADD */ +{ CPUFUNC(op_d088_4), 0, 53384 }, /* ADD */ +{ CPUFUNC(op_d090_4), 0, 53392 }, /* ADD */ +{ CPUFUNC(op_d098_4), 0, 53400 }, /* ADD */ +{ CPUFUNC(op_d0a0_4), 0, 53408 }, /* ADD */ +{ CPUFUNC(op_d0a8_4), 0, 53416 }, /* ADD */ +{ CPUFUNC(op_d0b0_4), 0, 53424 }, /* ADD */ +{ CPUFUNC(op_d0b8_4), 0, 53432 }, /* ADD */ +{ CPUFUNC(op_d0b9_4), 0, 53433 }, /* ADD */ +{ CPUFUNC(op_d0ba_4), 0, 53434 }, /* ADD */ +{ CPUFUNC(op_d0bb_4), 0, 53435 }, /* ADD */ +{ CPUFUNC(op_d0bc_4), 0, 53436 }, /* ADD */ +{ CPUFUNC(op_d0c0_4), 0, 53440 }, /* ADDA */ +{ CPUFUNC(op_d0c8_4), 0, 53448 }, /* ADDA */ +{ CPUFUNC(op_d0d0_4), 0, 53456 }, /* ADDA */ +{ CPUFUNC(op_d0d8_4), 0, 53464 }, /* ADDA */ +{ CPUFUNC(op_d0e0_4), 0, 53472 }, /* ADDA */ +{ CPUFUNC(op_d0e8_4), 0, 53480 }, /* ADDA */ +{ CPUFUNC(op_d0f0_4), 0, 53488 }, /* ADDA */ +{ CPUFUNC(op_d0f8_4), 0, 53496 }, /* ADDA */ +{ CPUFUNC(op_d0f9_4), 0, 53497 }, /* ADDA */ +{ CPUFUNC(op_d0fa_4), 0, 53498 }, /* ADDA */ +{ CPUFUNC(op_d0fb_4), 0, 53499 }, /* ADDA */ +{ CPUFUNC(op_d0fc_4), 0, 53500 }, /* ADDA */ +{ CPUFUNC(op_d100_4), 0, 53504 }, /* ADDX */ +{ CPUFUNC(op_d108_4), 0, 53512 }, /* ADDX */ +{ CPUFUNC(op_d110_4), 0, 53520 }, /* ADD */ +{ CPUFUNC(op_d118_4), 0, 53528 }, /* ADD */ +{ CPUFUNC(op_d120_4), 0, 53536 }, /* ADD */ +{ CPUFUNC(op_d128_4), 0, 53544 }, /* ADD */ +{ CPUFUNC(op_d130_4), 0, 53552 }, /* ADD */ +{ CPUFUNC(op_d138_4), 0, 53560 }, /* ADD */ +{ CPUFUNC(op_d139_4), 0, 53561 }, /* ADD */ +{ CPUFUNC(op_d140_4), 0, 53568 }, /* ADDX */ +{ CPUFUNC(op_d148_4), 0, 53576 }, /* ADDX */ +{ CPUFUNC(op_d150_4), 0, 53584 }, /* ADD */ +{ CPUFUNC(op_d158_4), 0, 53592 }, /* ADD */ +{ CPUFUNC(op_d160_4), 0, 53600 }, /* ADD */ +{ CPUFUNC(op_d168_4), 0, 53608 }, /* ADD */ +{ CPUFUNC(op_d170_4), 0, 53616 }, /* ADD */ +{ CPUFUNC(op_d178_4), 0, 53624 }, /* ADD */ +{ CPUFUNC(op_d179_4), 0, 53625 }, /* ADD */ +{ CPUFUNC(op_d180_4), 0, 53632 }, /* ADDX */ +{ CPUFUNC(op_d188_4), 0, 53640 }, /* ADDX */ +{ CPUFUNC(op_d190_4), 0, 53648 }, /* ADD */ +{ CPUFUNC(op_d198_4), 0, 53656 }, /* ADD */ +{ CPUFUNC(op_d1a0_4), 0, 53664 }, /* ADD */ +{ CPUFUNC(op_d1a8_4), 0, 53672 }, /* ADD */ +{ CPUFUNC(op_d1b0_4), 0, 53680 }, /* ADD */ +{ CPUFUNC(op_d1b8_4), 0, 53688 }, /* ADD */ +{ CPUFUNC(op_d1b9_4), 0, 53689 }, /* ADD */ +{ CPUFUNC(op_d1c0_4), 0, 53696 }, /* ADDA */ +{ CPUFUNC(op_d1c8_4), 0, 53704 }, /* ADDA */ +{ CPUFUNC(op_d1d0_4), 0, 53712 }, /* ADDA */ +{ CPUFUNC(op_d1d8_4), 0, 53720 }, /* ADDA */ +{ CPUFUNC(op_d1e0_4), 0, 53728 }, /* ADDA */ +{ CPUFUNC(op_d1e8_4), 0, 53736 }, /* ADDA */ +{ CPUFUNC(op_d1f0_4), 0, 53744 }, /* ADDA */ +{ CPUFUNC(op_d1f8_4), 0, 53752 }, /* ADDA */ +{ CPUFUNC(op_d1f9_4), 0, 53753 }, /* ADDA */ +{ CPUFUNC(op_d1fa_4), 0, 53754 }, /* ADDA */ +{ CPUFUNC(op_d1fb_4), 0, 53755 }, /* ADDA */ +{ CPUFUNC(op_d1fc_4), 0, 53756 }, /* ADDA */ +{ CPUFUNC(op_e000_4), 0, 57344 }, /* ASR */ +{ CPUFUNC(op_e008_4), 0, 57352 }, /* LSR */ +{ CPUFUNC(op_e010_4), 0, 57360 }, /* ROXR */ +{ CPUFUNC(op_e018_4), 0, 57368 }, /* ROR */ +{ CPUFUNC(op_e020_4), 0, 57376 }, /* ASR */ +{ CPUFUNC(op_e028_4), 0, 57384 }, /* LSR */ +{ CPUFUNC(op_e030_4), 0, 57392 }, /* ROXR */ +{ CPUFUNC(op_e038_4), 0, 57400 }, /* ROR */ +{ CPUFUNC(op_e040_4), 0, 57408 }, /* ASR */ +{ CPUFUNC(op_e048_4), 0, 57416 }, /* LSR */ +{ CPUFUNC(op_e050_4), 0, 57424 }, /* ROXR */ +{ CPUFUNC(op_e058_4), 0, 57432 }, /* ROR */ +{ CPUFUNC(op_e060_4), 0, 57440 }, /* ASR */ +{ CPUFUNC(op_e068_4), 0, 57448 }, /* LSR */ +{ CPUFUNC(op_e070_4), 0, 57456 }, /* ROXR */ +{ CPUFUNC(op_e078_4), 0, 57464 }, /* ROR */ +{ CPUFUNC(op_e080_4), 0, 57472 }, /* ASR */ +{ CPUFUNC(op_e088_4), 0, 57480 }, /* LSR */ +{ CPUFUNC(op_e090_4), 0, 57488 }, /* ROXR */ +{ CPUFUNC(op_e098_4), 0, 57496 }, /* ROR */ +{ CPUFUNC(op_e0a0_4), 0, 57504 }, /* ASR */ +{ CPUFUNC(op_e0a8_4), 0, 57512 }, /* LSR */ +{ CPUFUNC(op_e0b0_4), 0, 57520 }, /* ROXR */ +{ CPUFUNC(op_e0b8_4), 0, 57528 }, /* ROR */ +{ CPUFUNC(op_e0d0_4), 0, 57552 }, /* ASRW */ +{ CPUFUNC(op_e0d8_4), 0, 57560 }, /* ASRW */ +{ CPUFUNC(op_e0e0_4), 0, 57568 }, /* ASRW */ +{ CPUFUNC(op_e0e8_4), 0, 57576 }, /* ASRW */ +{ CPUFUNC(op_e0f0_4), 0, 57584 }, /* ASRW */ +{ CPUFUNC(op_e0f8_4), 0, 57592 }, /* ASRW */ +{ CPUFUNC(op_e0f9_4), 0, 57593 }, /* ASRW */ +{ CPUFUNC(op_e100_4), 0, 57600 }, /* ASL */ +{ CPUFUNC(op_e108_4), 0, 57608 }, /* LSL */ +{ CPUFUNC(op_e110_4), 0, 57616 }, /* ROXL */ +{ CPUFUNC(op_e118_4), 0, 57624 }, /* ROL */ +{ CPUFUNC(op_e120_4), 0, 57632 }, /* ASL */ +{ CPUFUNC(op_e128_4), 0, 57640 }, /* LSL */ +{ CPUFUNC(op_e130_4), 0, 57648 }, /* ROXL */ +{ CPUFUNC(op_e138_4), 0, 57656 }, /* ROL */ +{ CPUFUNC(op_e140_4), 0, 57664 }, /* ASL */ +{ CPUFUNC(op_e148_4), 0, 57672 }, /* LSL */ +{ CPUFUNC(op_e150_4), 0, 57680 }, /* ROXL */ +{ CPUFUNC(op_e158_4), 0, 57688 }, /* ROL */ +{ CPUFUNC(op_e160_4), 0, 57696 }, /* ASL */ +{ CPUFUNC(op_e168_4), 0, 57704 }, /* LSL */ +{ CPUFUNC(op_e170_4), 0, 57712 }, /* ROXL */ +{ CPUFUNC(op_e178_4), 0, 57720 }, /* ROL */ +{ CPUFUNC(op_e180_4), 0, 57728 }, /* ASL */ +{ CPUFUNC(op_e188_4), 0, 57736 }, /* LSL */ +{ CPUFUNC(op_e190_4), 0, 57744 }, /* ROXL */ +{ CPUFUNC(op_e198_4), 0, 57752 }, /* ROL */ +{ CPUFUNC(op_e1a0_4), 0, 57760 }, /* ASL */ +{ CPUFUNC(op_e1a8_4), 0, 57768 }, /* LSL */ +{ CPUFUNC(op_e1b0_4), 0, 57776 }, /* ROXL */ +{ CPUFUNC(op_e1b8_4), 0, 57784 }, /* ROL */ +{ CPUFUNC(op_e1d0_4), 0, 57808 }, /* ASLW */ +{ CPUFUNC(op_e1d8_4), 0, 57816 }, /* ASLW */ +{ CPUFUNC(op_e1e0_4), 0, 57824 }, /* ASLW */ +{ CPUFUNC(op_e1e8_4), 0, 57832 }, /* ASLW */ +{ CPUFUNC(op_e1f0_4), 0, 57840 }, /* ASLW */ +{ CPUFUNC(op_e1f8_4), 0, 57848 }, /* ASLW */ +{ CPUFUNC(op_e1f9_4), 0, 57849 }, /* ASLW */ +{ CPUFUNC(op_e2d0_4), 0, 58064 }, /* LSRW */ +{ CPUFUNC(op_e2d8_4), 0, 58072 }, /* LSRW */ +{ CPUFUNC(op_e2e0_4), 0, 58080 }, /* LSRW */ +{ CPUFUNC(op_e2e8_4), 0, 58088 }, /* LSRW */ +{ CPUFUNC(op_e2f0_4), 0, 58096 }, /* LSRW */ +{ CPUFUNC(op_e2f8_4), 0, 58104 }, /* LSRW */ +{ CPUFUNC(op_e2f9_4), 0, 58105 }, /* LSRW */ +{ CPUFUNC(op_e3d0_4), 0, 58320 }, /* LSLW */ +{ CPUFUNC(op_e3d8_4), 0, 58328 }, /* LSLW */ +{ CPUFUNC(op_e3e0_4), 0, 58336 }, /* LSLW */ +{ CPUFUNC(op_e3e8_4), 0, 58344 }, /* LSLW */ +{ CPUFUNC(op_e3f0_4), 0, 58352 }, /* LSLW */ +{ CPUFUNC(op_e3f8_4), 0, 58360 }, /* LSLW */ +{ CPUFUNC(op_e3f9_4), 0, 58361 }, /* LSLW */ +{ CPUFUNC(op_e4d0_4), 0, 58576 }, /* ROXRW */ +{ CPUFUNC(op_e4d8_4), 0, 58584 }, /* ROXRW */ +{ CPUFUNC(op_e4e0_4), 0, 58592 }, /* ROXRW */ +{ CPUFUNC(op_e4e8_4), 0, 58600 }, /* ROXRW */ +{ CPUFUNC(op_e4f0_4), 0, 58608 }, /* ROXRW */ +{ CPUFUNC(op_e4f8_4), 0, 58616 }, /* ROXRW */ +{ CPUFUNC(op_e4f9_4), 0, 58617 }, /* ROXRW */ +{ CPUFUNC(op_e5d0_4), 0, 58832 }, /* ROXLW */ +{ CPUFUNC(op_e5d8_4), 0, 58840 }, /* ROXLW */ +{ CPUFUNC(op_e5e0_4), 0, 58848 }, /* ROXLW */ +{ CPUFUNC(op_e5e8_4), 0, 58856 }, /* ROXLW */ +{ CPUFUNC(op_e5f0_4), 0, 58864 }, /* ROXLW */ +{ CPUFUNC(op_e5f8_4), 0, 58872 }, /* ROXLW */ +{ CPUFUNC(op_e5f9_4), 0, 58873 }, /* ROXLW */ +{ CPUFUNC(op_e6d0_4), 0, 59088 }, /* RORW */ +{ CPUFUNC(op_e6d8_4), 0, 59096 }, /* RORW */ +{ CPUFUNC(op_e6e0_4), 0, 59104 }, /* RORW */ +{ CPUFUNC(op_e6e8_4), 0, 59112 }, /* RORW */ +{ CPUFUNC(op_e6f0_4), 0, 59120 }, /* RORW */ +{ CPUFUNC(op_e6f8_4), 0, 59128 }, /* RORW */ +{ CPUFUNC(op_e6f9_4), 0, 59129 }, /* RORW */ +{ CPUFUNC(op_e7d0_4), 0, 59344 }, /* ROLW */ +{ CPUFUNC(op_e7d8_4), 0, 59352 }, /* ROLW */ +{ CPUFUNC(op_e7e0_4), 0, 59360 }, /* ROLW */ +{ CPUFUNC(op_e7e8_4), 0, 59368 }, /* ROLW */ +{ CPUFUNC(op_e7f0_4), 0, 59376 }, /* ROLW */ +{ CPUFUNC(op_e7f8_4), 0, 59384 }, /* ROLW */ +{ CPUFUNC(op_e7f9_4), 0, 59385 }, /* ROLW */ +{ 0, 0, 0 }}; +const struct cputbl CPUFUNC(op_smalltbl_5)[] = { +{ CPUFUNC(op_0_5), 0, 0 }, /* OR */ +{ CPUFUNC(op_10_5), 0, 16 }, /* OR */ +{ CPUFUNC(op_18_5), 0, 24 }, /* OR */ +{ CPUFUNC(op_20_5), 0, 32 }, /* OR */ +{ CPUFUNC(op_28_5), 0, 40 }, /* OR */ +{ CPUFUNC(op_30_5), 0, 48 }, /* OR */ +{ CPUFUNC(op_38_5), 0, 56 }, /* OR */ +{ CPUFUNC(op_39_5), 0, 57 }, /* OR */ +{ CPUFUNC(op_3c_5), 0, 60 }, /* ORSR */ +{ CPUFUNC(op_40_5), 0, 64 }, /* OR */ +{ CPUFUNC(op_50_5), 0, 80 }, /* OR */ +{ CPUFUNC(op_58_5), 0, 88 }, /* OR */ +{ CPUFUNC(op_60_5), 0, 96 }, /* OR */ +{ CPUFUNC(op_68_5), 0, 104 }, /* OR */ +{ CPUFUNC(op_70_5), 0, 112 }, /* OR */ +{ CPUFUNC(op_78_5), 0, 120 }, /* OR */ +{ CPUFUNC(op_79_5), 0, 121 }, /* OR */ +{ CPUFUNC(op_7c_5), 0, 124 }, /* ORSR */ +{ CPUFUNC(op_80_5), 0, 128 }, /* OR */ +{ CPUFUNC(op_90_5), 0, 144 }, /* OR */ +{ CPUFUNC(op_98_5), 0, 152 }, /* OR */ +{ CPUFUNC(op_a0_5), 0, 160 }, /* OR */ +{ CPUFUNC(op_a8_5), 0, 168 }, /* OR */ +{ CPUFUNC(op_b0_5), 0, 176 }, /* OR */ +{ CPUFUNC(op_b8_5), 0, 184 }, /* OR */ +{ CPUFUNC(op_b9_5), 0, 185 }, /* OR */ +{ CPUFUNC(op_100_5), 0, 256 }, /* BTST */ +{ CPUFUNC(op_108_5), 0, 264 }, /* MVPMR */ +{ CPUFUNC(op_110_5), 0, 272 }, /* BTST */ +{ CPUFUNC(op_118_5), 0, 280 }, /* BTST */ +{ CPUFUNC(op_120_5), 0, 288 }, /* BTST */ +{ CPUFUNC(op_128_5), 0, 296 }, /* BTST */ +{ CPUFUNC(op_130_5), 0, 304 }, /* BTST */ +{ CPUFUNC(op_138_5), 0, 312 }, /* BTST */ +{ CPUFUNC(op_139_5), 0, 313 }, /* BTST */ +{ CPUFUNC(op_13a_5), 0, 314 }, /* BTST */ +{ CPUFUNC(op_13b_5), 0, 315 }, /* BTST */ +{ CPUFUNC(op_13c_5), 0, 316 }, /* BTST */ +{ CPUFUNC(op_140_5), 0, 320 }, /* BCHG */ +{ CPUFUNC(op_148_5), 0, 328 }, /* MVPMR */ +{ CPUFUNC(op_150_5), 0, 336 }, /* BCHG */ +{ CPUFUNC(op_158_5), 0, 344 }, /* BCHG */ +{ CPUFUNC(op_160_5), 0, 352 }, /* BCHG */ +{ CPUFUNC(op_168_5), 0, 360 }, /* BCHG */ +{ CPUFUNC(op_170_5), 0, 368 }, /* BCHG */ +{ CPUFUNC(op_178_5), 0, 376 }, /* BCHG */ +{ CPUFUNC(op_179_5), 0, 377 }, /* BCHG */ +{ CPUFUNC(op_17a_5), 0, 378 }, /* BCHG */ +{ CPUFUNC(op_17b_5), 0, 379 }, /* BCHG */ +{ CPUFUNC(op_180_5), 0, 384 }, /* BCLR */ +{ CPUFUNC(op_188_5), 0, 392 }, /* MVPRM */ +{ CPUFUNC(op_190_5), 0, 400 }, /* BCLR */ +{ CPUFUNC(op_198_5), 0, 408 }, /* BCLR */ +{ CPUFUNC(op_1a0_5), 0, 416 }, /* BCLR */ +{ CPUFUNC(op_1a8_5), 0, 424 }, /* BCLR */ +{ CPUFUNC(op_1b0_5), 0, 432 }, /* BCLR */ +{ CPUFUNC(op_1b8_5), 0, 440 }, /* BCLR */ +{ CPUFUNC(op_1b9_5), 0, 441 }, /* BCLR */ +{ CPUFUNC(op_1ba_5), 0, 442 }, /* BCLR */ +{ CPUFUNC(op_1bb_5), 0, 443 }, /* BCLR */ +{ CPUFUNC(op_1c0_5), 0, 448 }, /* BSET */ +{ CPUFUNC(op_1c8_5), 0, 456 }, /* MVPRM */ +{ CPUFUNC(op_1d0_5), 0, 464 }, /* BSET */ +{ CPUFUNC(op_1d8_5), 0, 472 }, /* BSET */ +{ CPUFUNC(op_1e0_5), 0, 480 }, /* BSET */ +{ CPUFUNC(op_1e8_5), 0, 488 }, /* BSET */ +{ CPUFUNC(op_1f0_5), 0, 496 }, /* BSET */ +{ CPUFUNC(op_1f8_5), 0, 504 }, /* BSET */ +{ CPUFUNC(op_1f9_5), 0, 505 }, /* BSET */ +{ CPUFUNC(op_1fa_5), 0, 506 }, /* BSET */ +{ CPUFUNC(op_1fb_5), 0, 507 }, /* BSET */ +{ CPUFUNC(op_200_5), 0, 512 }, /* AND */ +{ CPUFUNC(op_210_5), 0, 528 }, /* AND */ +{ CPUFUNC(op_218_5), 0, 536 }, /* AND */ +{ CPUFUNC(op_220_5), 0, 544 }, /* AND */ +{ CPUFUNC(op_228_5), 0, 552 }, /* AND */ +{ CPUFUNC(op_230_5), 0, 560 }, /* AND */ +{ CPUFUNC(op_238_5), 0, 568 }, /* AND */ +{ CPUFUNC(op_239_5), 0, 569 }, /* AND */ +{ CPUFUNC(op_23c_5), 0, 572 }, /* ANDSR */ +{ CPUFUNC(op_240_5), 0, 576 }, /* AND */ +{ CPUFUNC(op_250_5), 0, 592 }, /* AND */ +{ CPUFUNC(op_258_5), 0, 600 }, /* AND */ +{ CPUFUNC(op_260_5), 0, 608 }, /* AND */ +{ CPUFUNC(op_268_5), 0, 616 }, /* AND */ +{ CPUFUNC(op_270_5), 0, 624 }, /* AND */ +{ CPUFUNC(op_278_5), 0, 632 }, /* AND */ +{ CPUFUNC(op_279_5), 0, 633 }, /* AND */ +{ CPUFUNC(op_27c_5), 0, 636 }, /* ANDSR */ +{ CPUFUNC(op_280_5), 0, 640 }, /* AND */ +{ CPUFUNC(op_290_5), 0, 656 }, /* AND */ +{ CPUFUNC(op_298_5), 0, 664 }, /* AND */ +{ CPUFUNC(op_2a0_5), 0, 672 }, /* AND */ +{ CPUFUNC(op_2a8_5), 0, 680 }, /* AND */ +{ CPUFUNC(op_2b0_5), 0, 688 }, /* AND */ +{ CPUFUNC(op_2b8_5), 0, 696 }, /* AND */ +{ CPUFUNC(op_2b9_5), 0, 697 }, /* AND */ +{ CPUFUNC(op_400_5), 0, 1024 }, /* SUB */ +{ CPUFUNC(op_410_5), 0, 1040 }, /* SUB */ +{ CPUFUNC(op_418_5), 0, 1048 }, /* SUB */ +{ CPUFUNC(op_420_5), 0, 1056 }, /* SUB */ +{ CPUFUNC(op_428_5), 0, 1064 }, /* SUB */ +{ CPUFUNC(op_430_5), 0, 1072 }, /* SUB */ +{ CPUFUNC(op_438_5), 0, 1080 }, /* SUB */ +{ CPUFUNC(op_439_5), 0, 1081 }, /* SUB */ +{ CPUFUNC(op_440_5), 0, 1088 }, /* SUB */ +{ CPUFUNC(op_450_5), 0, 1104 }, /* SUB */ +{ CPUFUNC(op_458_5), 0, 1112 }, /* SUB */ +{ CPUFUNC(op_460_5), 0, 1120 }, /* SUB */ +{ CPUFUNC(op_468_5), 0, 1128 }, /* SUB */ +{ CPUFUNC(op_470_5), 0, 1136 }, /* SUB */ +{ CPUFUNC(op_478_5), 0, 1144 }, /* SUB */ +{ CPUFUNC(op_479_5), 0, 1145 }, /* SUB */ +{ CPUFUNC(op_480_5), 0, 1152 }, /* SUB */ +{ CPUFUNC(op_490_5), 0, 1168 }, /* SUB */ +{ CPUFUNC(op_498_5), 0, 1176 }, /* SUB */ +{ CPUFUNC(op_4a0_5), 0, 1184 }, /* SUB */ +{ CPUFUNC(op_4a8_5), 0, 1192 }, /* SUB */ +{ CPUFUNC(op_4b0_5), 0, 1200 }, /* SUB */ +{ CPUFUNC(op_4b8_5), 0, 1208 }, /* SUB */ +{ CPUFUNC(op_4b9_5), 0, 1209 }, /* SUB */ +{ CPUFUNC(op_600_5), 0, 1536 }, /* ADD */ +{ CPUFUNC(op_610_5), 0, 1552 }, /* ADD */ +{ CPUFUNC(op_618_5), 0, 1560 }, /* ADD */ +{ CPUFUNC(op_620_5), 0, 1568 }, /* ADD */ +{ CPUFUNC(op_628_5), 0, 1576 }, /* ADD */ +{ CPUFUNC(op_630_5), 0, 1584 }, /* ADD */ +{ CPUFUNC(op_638_5), 0, 1592 }, /* ADD */ +{ CPUFUNC(op_639_5), 0, 1593 }, /* ADD */ +{ CPUFUNC(op_640_5), 0, 1600 }, /* ADD */ +{ CPUFUNC(op_650_5), 0, 1616 }, /* ADD */ +{ CPUFUNC(op_658_5), 0, 1624 }, /* ADD */ +{ CPUFUNC(op_660_5), 0, 1632 }, /* ADD */ +{ CPUFUNC(op_668_5), 0, 1640 }, /* ADD */ +{ CPUFUNC(op_670_5), 0, 1648 }, /* ADD */ +{ CPUFUNC(op_678_5), 0, 1656 }, /* ADD */ +{ CPUFUNC(op_679_5), 0, 1657 }, /* ADD */ +{ CPUFUNC(op_680_5), 0, 1664 }, /* ADD */ +{ CPUFUNC(op_690_5), 0, 1680 }, /* ADD */ +{ CPUFUNC(op_698_5), 0, 1688 }, /* ADD */ +{ CPUFUNC(op_6a0_5), 0, 1696 }, /* ADD */ +{ CPUFUNC(op_6a8_5), 0, 1704 }, /* ADD */ +{ CPUFUNC(op_6b0_5), 0, 1712 }, /* ADD */ +{ CPUFUNC(op_6b8_5), 0, 1720 }, /* ADD */ +{ CPUFUNC(op_6b9_5), 0, 1721 }, /* ADD */ +{ CPUFUNC(op_800_5), 0, 2048 }, /* BTST */ +{ CPUFUNC(op_810_5), 0, 2064 }, /* BTST */ +{ CPUFUNC(op_818_5), 0, 2072 }, /* BTST */ +{ CPUFUNC(op_820_5), 0, 2080 }, /* BTST */ +{ CPUFUNC(op_828_5), 0, 2088 }, /* BTST */ +{ CPUFUNC(op_830_5), 0, 2096 }, /* BTST */ +{ CPUFUNC(op_838_5), 0, 2104 }, /* BTST */ +{ CPUFUNC(op_839_5), 0, 2105 }, /* BTST */ +{ CPUFUNC(op_83a_5), 0, 2106 }, /* BTST */ +{ CPUFUNC(op_83b_5), 0, 2107 }, /* BTST */ +{ CPUFUNC(op_83c_5), 0, 2108 }, /* BTST */ +{ CPUFUNC(op_840_5), 0, 2112 }, /* BCHG */ +{ CPUFUNC(op_850_5), 0, 2128 }, /* BCHG */ +{ CPUFUNC(op_858_5), 0, 2136 }, /* BCHG */ +{ CPUFUNC(op_860_5), 0, 2144 }, /* BCHG */ +{ CPUFUNC(op_868_5), 0, 2152 }, /* BCHG */ +{ CPUFUNC(op_870_5), 0, 2160 }, /* BCHG */ +{ CPUFUNC(op_878_5), 0, 2168 }, /* BCHG */ +{ CPUFUNC(op_879_5), 0, 2169 }, /* BCHG */ +{ CPUFUNC(op_87a_5), 0, 2170 }, /* BCHG */ +{ CPUFUNC(op_87b_5), 0, 2171 }, /* BCHG */ +{ CPUFUNC(op_880_5), 0, 2176 }, /* BCLR */ +{ CPUFUNC(op_890_5), 0, 2192 }, /* BCLR */ +{ CPUFUNC(op_898_5), 0, 2200 }, /* BCLR */ +{ CPUFUNC(op_8a0_5), 0, 2208 }, /* BCLR */ +{ CPUFUNC(op_8a8_5), 0, 2216 }, /* BCLR */ +{ CPUFUNC(op_8b0_5), 0, 2224 }, /* BCLR */ +{ CPUFUNC(op_8b8_5), 0, 2232 }, /* BCLR */ +{ CPUFUNC(op_8b9_5), 0, 2233 }, /* BCLR */ +{ CPUFUNC(op_8ba_5), 0, 2234 }, /* BCLR */ +{ CPUFUNC(op_8bb_5), 0, 2235 }, /* BCLR */ +{ CPUFUNC(op_8c0_5), 0, 2240 }, /* BSET */ +{ CPUFUNC(op_8d0_5), 0, 2256 }, /* BSET */ +{ CPUFUNC(op_8d8_5), 0, 2264 }, /* BSET */ +{ CPUFUNC(op_8e0_5), 0, 2272 }, /* BSET */ +{ CPUFUNC(op_8e8_5), 0, 2280 }, /* BSET */ +{ CPUFUNC(op_8f0_5), 0, 2288 }, /* BSET */ +{ CPUFUNC(op_8f8_5), 0, 2296 }, /* BSET */ +{ CPUFUNC(op_8f9_5), 0, 2297 }, /* BSET */ +{ CPUFUNC(op_8fa_5), 0, 2298 }, /* BSET */ +{ CPUFUNC(op_8fb_5), 0, 2299 }, /* BSET */ +{ CPUFUNC(op_a00_5), 0, 2560 }, /* EOR */ +{ CPUFUNC(op_a10_5), 0, 2576 }, /* EOR */ +{ CPUFUNC(op_a18_5), 0, 2584 }, /* EOR */ +{ CPUFUNC(op_a20_5), 0, 2592 }, /* EOR */ +{ CPUFUNC(op_a28_5), 0, 2600 }, /* EOR */ +{ CPUFUNC(op_a30_5), 0, 2608 }, /* EOR */ +{ CPUFUNC(op_a38_5), 0, 2616 }, /* EOR */ +{ CPUFUNC(op_a39_5), 0, 2617 }, /* EOR */ +{ CPUFUNC(op_a3c_5), 0, 2620 }, /* EORSR */ +{ CPUFUNC(op_a40_5), 0, 2624 }, /* EOR */ +{ CPUFUNC(op_a50_5), 0, 2640 }, /* EOR */ +{ CPUFUNC(op_a58_5), 0, 2648 }, /* EOR */ +{ CPUFUNC(op_a60_5), 0, 2656 }, /* EOR */ +{ CPUFUNC(op_a68_5), 0, 2664 }, /* EOR */ +{ CPUFUNC(op_a70_5), 0, 2672 }, /* EOR */ +{ CPUFUNC(op_a78_5), 0, 2680 }, /* EOR */ +{ CPUFUNC(op_a79_5), 0, 2681 }, /* EOR */ +{ CPUFUNC(op_a7c_5), 0, 2684 }, /* EORSR */ +{ CPUFUNC(op_a80_5), 0, 2688 }, /* EOR */ +{ CPUFUNC(op_a90_5), 0, 2704 }, /* EOR */ +{ CPUFUNC(op_a98_5), 0, 2712 }, /* EOR */ +{ CPUFUNC(op_aa0_5), 0, 2720 }, /* EOR */ +{ CPUFUNC(op_aa8_5), 0, 2728 }, /* EOR */ +{ CPUFUNC(op_ab0_5), 0, 2736 }, /* EOR */ +{ CPUFUNC(op_ab8_5), 0, 2744 }, /* EOR */ +{ CPUFUNC(op_ab9_5), 0, 2745 }, /* EOR */ +{ CPUFUNC(op_c00_5), 0, 3072 }, /* CMP */ +{ CPUFUNC(op_c10_5), 0, 3088 }, /* CMP */ +{ CPUFUNC(op_c18_5), 0, 3096 }, /* CMP */ +{ CPUFUNC(op_c20_5), 0, 3104 }, /* CMP */ +{ CPUFUNC(op_c28_5), 0, 3112 }, /* CMP */ +{ CPUFUNC(op_c30_5), 0, 3120 }, /* CMP */ +{ CPUFUNC(op_c38_5), 0, 3128 }, /* CMP */ +{ CPUFUNC(op_c39_5), 0, 3129 }, /* CMP */ +{ CPUFUNC(op_c3a_5), 0, 3130 }, /* CMP */ +{ CPUFUNC(op_c3b_5), 0, 3131 }, /* CMP */ +{ CPUFUNC(op_c40_5), 0, 3136 }, /* CMP */ +{ CPUFUNC(op_c50_5), 0, 3152 }, /* CMP */ +{ CPUFUNC(op_c58_5), 0, 3160 }, /* CMP */ +{ CPUFUNC(op_c60_5), 0, 3168 }, /* CMP */ +{ CPUFUNC(op_c68_5), 0, 3176 }, /* CMP */ +{ CPUFUNC(op_c70_5), 0, 3184 }, /* CMP */ +{ CPUFUNC(op_c78_5), 0, 3192 }, /* CMP */ +{ CPUFUNC(op_c79_5), 0, 3193 }, /* CMP */ +{ CPUFUNC(op_c7a_5), 0, 3194 }, /* CMP */ +{ CPUFUNC(op_c7b_5), 0, 3195 }, /* CMP */ +{ CPUFUNC(op_c80_5), 0, 3200 }, /* CMP */ +{ CPUFUNC(op_c90_5), 0, 3216 }, /* CMP */ +{ CPUFUNC(op_c98_5), 0, 3224 }, /* CMP */ +{ CPUFUNC(op_ca0_5), 0, 3232 }, /* CMP */ +{ CPUFUNC(op_ca8_5), 0, 3240 }, /* CMP */ +{ CPUFUNC(op_cb0_5), 0, 3248 }, /* CMP */ +{ CPUFUNC(op_cb8_5), 0, 3256 }, /* CMP */ +{ CPUFUNC(op_cb9_5), 0, 3257 }, /* CMP */ +{ CPUFUNC(op_cba_5), 0, 3258 }, /* CMP */ +{ CPUFUNC(op_cbb_5), 0, 3259 }, /* CMP */ +{ CPUFUNC(op_1000_5), 0, 4096 }, /* MOVE */ +{ CPUFUNC(op_1008_5), 0, 4104 }, /* MOVE */ +{ CPUFUNC(op_1010_5), 0, 4112 }, /* MOVE */ +{ CPUFUNC(op_1018_5), 0, 4120 }, /* MOVE */ +{ CPUFUNC(op_1020_5), 0, 4128 }, /* MOVE */ +{ CPUFUNC(op_1028_5), 0, 4136 }, /* MOVE */ +{ CPUFUNC(op_1030_5), 0, 4144 }, /* MOVE */ +{ CPUFUNC(op_1038_5), 0, 4152 }, /* MOVE */ +{ CPUFUNC(op_1039_5), 0, 4153 }, /* MOVE */ +{ CPUFUNC(op_103a_5), 0, 4154 }, /* MOVE */ +{ CPUFUNC(op_103b_5), 0, 4155 }, /* MOVE */ +{ CPUFUNC(op_103c_5), 0, 4156 }, /* MOVE */ +{ CPUFUNC(op_1080_5), 0, 4224 }, /* MOVE */ +{ CPUFUNC(op_1088_5), 0, 4232 }, /* MOVE */ +{ CPUFUNC(op_1090_5), 0, 4240 }, /* MOVE */ +{ CPUFUNC(op_1098_5), 0, 4248 }, /* MOVE */ +{ CPUFUNC(op_10a0_5), 0, 4256 }, /* MOVE */ +{ CPUFUNC(op_10a8_5), 0, 4264 }, /* MOVE */ +{ CPUFUNC(op_10b0_5), 0, 4272 }, /* MOVE */ +{ CPUFUNC(op_10b8_5), 0, 4280 }, /* MOVE */ +{ CPUFUNC(op_10b9_5), 0, 4281 }, /* MOVE */ +{ CPUFUNC(op_10ba_5), 0, 4282 }, /* MOVE */ +{ CPUFUNC(op_10bb_5), 0, 4283 }, /* MOVE */ +{ CPUFUNC(op_10bc_5), 0, 4284 }, /* MOVE */ +{ CPUFUNC(op_10c0_5), 0, 4288 }, /* MOVE */ +{ CPUFUNC(op_10c8_5), 0, 4296 }, /* MOVE */ +{ CPUFUNC(op_10d0_5), 0, 4304 }, /* MOVE */ +{ CPUFUNC(op_10d8_5), 0, 4312 }, /* MOVE */ +{ CPUFUNC(op_10e0_5), 0, 4320 }, /* MOVE */ +{ CPUFUNC(op_10e8_5), 0, 4328 }, /* MOVE */ +{ CPUFUNC(op_10f0_5), 0, 4336 }, /* MOVE */ +{ CPUFUNC(op_10f8_5), 0, 4344 }, /* MOVE */ +{ CPUFUNC(op_10f9_5), 0, 4345 }, /* MOVE */ +{ CPUFUNC(op_10fa_5), 0, 4346 }, /* MOVE */ +{ CPUFUNC(op_10fb_5), 0, 4347 }, /* MOVE */ +{ CPUFUNC(op_10fc_5), 0, 4348 }, /* MOVE */ +{ CPUFUNC(op_1100_5), 0, 4352 }, /* MOVE */ +{ CPUFUNC(op_1108_5), 0, 4360 }, /* MOVE */ +{ CPUFUNC(op_1110_5), 0, 4368 }, /* MOVE */ +{ CPUFUNC(op_1118_5), 0, 4376 }, /* MOVE */ +{ CPUFUNC(op_1120_5), 0, 4384 }, /* MOVE */ +{ CPUFUNC(op_1128_5), 0, 4392 }, /* MOVE */ +{ CPUFUNC(op_1130_5), 0, 4400 }, /* MOVE */ +{ CPUFUNC(op_1138_5), 0, 4408 }, /* MOVE */ +{ CPUFUNC(op_1139_5), 0, 4409 }, /* MOVE */ +{ CPUFUNC(op_113a_5), 0, 4410 }, /* MOVE */ +{ CPUFUNC(op_113b_5), 0, 4411 }, /* MOVE */ +{ CPUFUNC(op_113c_5), 0, 4412 }, /* MOVE */ +{ CPUFUNC(op_1140_5), 0, 4416 }, /* MOVE */ +{ CPUFUNC(op_1148_5), 0, 4424 }, /* MOVE */ +{ CPUFUNC(op_1150_5), 0, 4432 }, /* MOVE */ +{ CPUFUNC(op_1158_5), 0, 4440 }, /* MOVE */ +{ CPUFUNC(op_1160_5), 0, 4448 }, /* MOVE */ +{ CPUFUNC(op_1168_5), 0, 4456 }, /* MOVE */ +{ CPUFUNC(op_1170_5), 0, 4464 }, /* MOVE */ +{ CPUFUNC(op_1178_5), 0, 4472 }, /* MOVE */ +{ CPUFUNC(op_1179_5), 0, 4473 }, /* MOVE */ +{ CPUFUNC(op_117a_5), 0, 4474 }, /* MOVE */ +{ CPUFUNC(op_117b_5), 0, 4475 }, /* MOVE */ +{ CPUFUNC(op_117c_5), 0, 4476 }, /* MOVE */ +{ CPUFUNC(op_1180_5), 0, 4480 }, /* MOVE */ +{ CPUFUNC(op_1188_5), 0, 4488 }, /* MOVE */ +{ CPUFUNC(op_1190_5), 0, 4496 }, /* MOVE */ +{ CPUFUNC(op_1198_5), 0, 4504 }, /* MOVE */ +{ CPUFUNC(op_11a0_5), 0, 4512 }, /* MOVE */ +{ CPUFUNC(op_11a8_5), 0, 4520 }, /* MOVE */ +{ CPUFUNC(op_11b0_5), 0, 4528 }, /* MOVE */ +{ CPUFUNC(op_11b8_5), 0, 4536 }, /* MOVE */ +{ CPUFUNC(op_11b9_5), 0, 4537 }, /* MOVE */ +{ CPUFUNC(op_11ba_5), 0, 4538 }, /* MOVE */ +{ CPUFUNC(op_11bb_5), 0, 4539 }, /* MOVE */ +{ CPUFUNC(op_11bc_5), 0, 4540 }, /* MOVE */ +{ CPUFUNC(op_11c0_5), 0, 4544 }, /* MOVE */ +{ CPUFUNC(op_11c8_5), 0, 4552 }, /* MOVE */ +{ CPUFUNC(op_11d0_5), 0, 4560 }, /* MOVE */ +{ CPUFUNC(op_11d8_5), 0, 4568 }, /* MOVE */ +{ CPUFUNC(op_11e0_5), 0, 4576 }, /* MOVE */ +{ CPUFUNC(op_11e8_5), 0, 4584 }, /* MOVE */ +{ CPUFUNC(op_11f0_5), 0, 4592 }, /* MOVE */ +{ CPUFUNC(op_11f8_5), 0, 4600 }, /* MOVE */ +{ CPUFUNC(op_11f9_5), 0, 4601 }, /* MOVE */ +{ CPUFUNC(op_11fa_5), 0, 4602 }, /* MOVE */ +{ CPUFUNC(op_11fb_5), 0, 4603 }, /* MOVE */ +{ CPUFUNC(op_11fc_5), 0, 4604 }, /* MOVE */ +{ CPUFUNC(op_13c0_5), 0, 5056 }, /* MOVE */ +{ CPUFUNC(op_13c8_5), 0, 5064 }, /* MOVE */ +{ CPUFUNC(op_13d0_5), 0, 5072 }, /* MOVE */ +{ CPUFUNC(op_13d8_5), 0, 5080 }, /* MOVE */ +{ CPUFUNC(op_13e0_5), 0, 5088 }, /* MOVE */ +{ CPUFUNC(op_13e8_5), 0, 5096 }, /* MOVE */ +{ CPUFUNC(op_13f0_5), 0, 5104 }, /* MOVE */ +{ CPUFUNC(op_13f8_5), 0, 5112 }, /* MOVE */ +{ CPUFUNC(op_13f9_5), 0, 5113 }, /* MOVE */ +{ CPUFUNC(op_13fa_5), 0, 5114 }, /* MOVE */ +{ CPUFUNC(op_13fb_5), 0, 5115 }, /* MOVE */ +{ CPUFUNC(op_13fc_5), 0, 5116 }, /* MOVE */ +{ CPUFUNC(op_2000_5), 0, 8192 }, /* MOVE */ +{ CPUFUNC(op_2008_5), 0, 8200 }, /* MOVE */ +{ CPUFUNC(op_2010_5), 0, 8208 }, /* MOVE */ +{ CPUFUNC(op_2018_5), 0, 8216 }, /* MOVE */ +{ CPUFUNC(op_2020_5), 0, 8224 }, /* MOVE */ +{ CPUFUNC(op_2028_5), 0, 8232 }, /* MOVE */ +{ CPUFUNC(op_2030_5), 0, 8240 }, /* MOVE */ +{ CPUFUNC(op_2038_5), 0, 8248 }, /* MOVE */ +{ CPUFUNC(op_2039_5), 0, 8249 }, /* MOVE */ +{ CPUFUNC(op_203a_5), 0, 8250 }, /* MOVE */ +{ CPUFUNC(op_203b_5), 0, 8251 }, /* MOVE */ +{ CPUFUNC(op_203c_5), 0, 8252 }, /* MOVE */ +{ CPUFUNC(op_2040_5), 0, 8256 }, /* MOVEA */ +{ CPUFUNC(op_2048_5), 0, 8264 }, /* MOVEA */ +{ CPUFUNC(op_2050_5), 0, 8272 }, /* MOVEA */ +{ CPUFUNC(op_2058_5), 0, 8280 }, /* MOVEA */ +{ CPUFUNC(op_2060_5), 0, 8288 }, /* MOVEA */ +{ CPUFUNC(op_2068_5), 0, 8296 }, /* MOVEA */ +{ CPUFUNC(op_2070_5), 0, 8304 }, /* MOVEA */ +{ CPUFUNC(op_2078_5), 0, 8312 }, /* MOVEA */ +{ CPUFUNC(op_2079_5), 0, 8313 }, /* MOVEA */ +{ CPUFUNC(op_207a_5), 0, 8314 }, /* MOVEA */ +{ CPUFUNC(op_207b_5), 0, 8315 }, /* MOVEA */ +{ CPUFUNC(op_207c_5), 0, 8316 }, /* MOVEA */ +{ CPUFUNC(op_2080_5), 0, 8320 }, /* MOVE */ +{ CPUFUNC(op_2088_5), 0, 8328 }, /* MOVE */ +{ CPUFUNC(op_2090_5), 0, 8336 }, /* MOVE */ +{ CPUFUNC(op_2098_5), 0, 8344 }, /* MOVE */ +{ CPUFUNC(op_20a0_5), 0, 8352 }, /* MOVE */ +{ CPUFUNC(op_20a8_5), 0, 8360 }, /* MOVE */ +{ CPUFUNC(op_20b0_5), 0, 8368 }, /* MOVE */ +{ CPUFUNC(op_20b8_5), 0, 8376 }, /* MOVE */ +{ CPUFUNC(op_20b9_5), 0, 8377 }, /* MOVE */ +{ CPUFUNC(op_20ba_5), 0, 8378 }, /* MOVE */ +{ CPUFUNC(op_20bb_5), 0, 8379 }, /* MOVE */ +{ CPUFUNC(op_20bc_5), 0, 8380 }, /* MOVE */ +{ CPUFUNC(op_20c0_5), 0, 8384 }, /* MOVE */ +{ CPUFUNC(op_20c8_5), 0, 8392 }, /* MOVE */ +{ CPUFUNC(op_20d0_5), 0, 8400 }, /* MOVE */ +{ CPUFUNC(op_20d8_5), 0, 8408 }, /* MOVE */ +{ CPUFUNC(op_20e0_5), 0, 8416 }, /* MOVE */ +{ CPUFUNC(op_20e8_5), 0, 8424 }, /* MOVE */ +{ CPUFUNC(op_20f0_5), 0, 8432 }, /* MOVE */ +{ CPUFUNC(op_20f8_5), 0, 8440 }, /* MOVE */ +{ CPUFUNC(op_20f9_5), 0, 8441 }, /* MOVE */ +{ CPUFUNC(op_20fa_5), 0, 8442 }, /* MOVE */ +{ CPUFUNC(op_20fb_5), 0, 8443 }, /* MOVE */ +{ CPUFUNC(op_20fc_5), 0, 8444 }, /* MOVE */ +{ CPUFUNC(op_2100_5), 0, 8448 }, /* MOVE */ +{ CPUFUNC(op_2108_5), 0, 8456 }, /* MOVE */ +{ CPUFUNC(op_2110_5), 0, 8464 }, /* MOVE */ +{ CPUFUNC(op_2118_5), 0, 8472 }, /* MOVE */ +{ CPUFUNC(op_2120_5), 0, 8480 }, /* MOVE */ +{ CPUFUNC(op_2128_5), 0, 8488 }, /* MOVE */ +{ CPUFUNC(op_2130_5), 0, 8496 }, /* MOVE */ +{ CPUFUNC(op_2138_5), 0, 8504 }, /* MOVE */ +{ CPUFUNC(op_2139_5), 0, 8505 }, /* MOVE */ +{ CPUFUNC(op_213a_5), 0, 8506 }, /* MOVE */ +{ CPUFUNC(op_213b_5), 0, 8507 }, /* MOVE */ +{ CPUFUNC(op_213c_5), 0, 8508 }, /* MOVE */ +{ CPUFUNC(op_2140_5), 0, 8512 }, /* MOVE */ +{ CPUFUNC(op_2148_5), 0, 8520 }, /* MOVE */ +{ CPUFUNC(op_2150_5), 0, 8528 }, /* MOVE */ +{ CPUFUNC(op_2158_5), 0, 8536 }, /* MOVE */ +{ CPUFUNC(op_2160_5), 0, 8544 }, /* MOVE */ +{ CPUFUNC(op_2168_5), 0, 8552 }, /* MOVE */ +{ CPUFUNC(op_2170_5), 0, 8560 }, /* MOVE */ +{ CPUFUNC(op_2178_5), 0, 8568 }, /* MOVE */ +{ CPUFUNC(op_2179_5), 0, 8569 }, /* MOVE */ +{ CPUFUNC(op_217a_5), 0, 8570 }, /* MOVE */ +{ CPUFUNC(op_217b_5), 0, 8571 }, /* MOVE */ +{ CPUFUNC(op_217c_5), 0, 8572 }, /* MOVE */ +{ CPUFUNC(op_2180_5), 0, 8576 }, /* MOVE */ +{ CPUFUNC(op_2188_5), 0, 8584 }, /* MOVE */ +{ CPUFUNC(op_2190_5), 0, 8592 }, /* MOVE */ +{ CPUFUNC(op_2198_5), 0, 8600 }, /* MOVE */ +{ CPUFUNC(op_21a0_5), 0, 8608 }, /* MOVE */ +{ CPUFUNC(op_21a8_5), 0, 8616 }, /* MOVE */ +{ CPUFUNC(op_21b0_5), 0, 8624 }, /* MOVE */ +{ CPUFUNC(op_21b8_5), 0, 8632 }, /* MOVE */ +{ CPUFUNC(op_21b9_5), 0, 8633 }, /* MOVE */ +{ CPUFUNC(op_21ba_5), 0, 8634 }, /* MOVE */ +{ CPUFUNC(op_21bb_5), 0, 8635 }, /* MOVE */ +{ CPUFUNC(op_21bc_5), 0, 8636 }, /* MOVE */ +{ CPUFUNC(op_21c0_5), 0, 8640 }, /* MOVE */ +{ CPUFUNC(op_21c8_5), 0, 8648 }, /* MOVE */ +{ CPUFUNC(op_21d0_5), 0, 8656 }, /* MOVE */ +{ CPUFUNC(op_21d8_5), 0, 8664 }, /* MOVE */ +{ CPUFUNC(op_21e0_5), 0, 8672 }, /* MOVE */ +{ CPUFUNC(op_21e8_5), 0, 8680 }, /* MOVE */ +{ CPUFUNC(op_21f0_5), 0, 8688 }, /* MOVE */ +{ CPUFUNC(op_21f8_5), 0, 8696 }, /* MOVE */ +{ CPUFUNC(op_21f9_5), 0, 8697 }, /* MOVE */ +{ CPUFUNC(op_21fa_5), 0, 8698 }, /* MOVE */ +{ CPUFUNC(op_21fb_5), 0, 8699 }, /* MOVE */ +{ CPUFUNC(op_21fc_5), 0, 8700 }, /* MOVE */ +{ CPUFUNC(op_23c0_5), 0, 9152 }, /* MOVE */ +{ CPUFUNC(op_23c8_5), 0, 9160 }, /* MOVE */ +{ CPUFUNC(op_23d0_5), 0, 9168 }, /* MOVE */ +{ CPUFUNC(op_23d8_5), 0, 9176 }, /* MOVE */ +{ CPUFUNC(op_23e0_5), 0, 9184 }, /* MOVE */ +{ CPUFUNC(op_23e8_5), 0, 9192 }, /* MOVE */ +{ CPUFUNC(op_23f0_5), 0, 9200 }, /* MOVE */ +{ CPUFUNC(op_23f8_5), 0, 9208 }, /* MOVE */ +{ CPUFUNC(op_23f9_5), 0, 9209 }, /* MOVE */ +{ CPUFUNC(op_23fa_5), 0, 9210 }, /* MOVE */ +{ CPUFUNC(op_23fb_5), 0, 9211 }, /* MOVE */ +{ CPUFUNC(op_23fc_5), 0, 9212 }, /* MOVE */ +{ CPUFUNC(op_3000_5), 0, 12288 }, /* MOVE */ +{ CPUFUNC(op_3008_5), 0, 12296 }, /* MOVE */ +{ CPUFUNC(op_3010_5), 0, 12304 }, /* MOVE */ +{ CPUFUNC(op_3018_5), 0, 12312 }, /* MOVE */ +{ CPUFUNC(op_3020_5), 0, 12320 }, /* MOVE */ +{ CPUFUNC(op_3028_5), 0, 12328 }, /* MOVE */ +{ CPUFUNC(op_3030_5), 0, 12336 }, /* MOVE */ +{ CPUFUNC(op_3038_5), 0, 12344 }, /* MOVE */ +{ CPUFUNC(op_3039_5), 0, 12345 }, /* MOVE */ +{ CPUFUNC(op_303a_5), 0, 12346 }, /* MOVE */ +{ CPUFUNC(op_303b_5), 0, 12347 }, /* MOVE */ +{ CPUFUNC(op_303c_5), 0, 12348 }, /* MOVE */ +{ CPUFUNC(op_3040_5), 0, 12352 }, /* MOVEA */ +{ CPUFUNC(op_3048_5), 0, 12360 }, /* MOVEA */ +{ CPUFUNC(op_3050_5), 0, 12368 }, /* MOVEA */ +{ CPUFUNC(op_3058_5), 0, 12376 }, /* MOVEA */ +{ CPUFUNC(op_3060_5), 0, 12384 }, /* MOVEA */ +{ CPUFUNC(op_3068_5), 0, 12392 }, /* MOVEA */ +{ CPUFUNC(op_3070_5), 0, 12400 }, /* MOVEA */ +{ CPUFUNC(op_3078_5), 0, 12408 }, /* MOVEA */ +{ CPUFUNC(op_3079_5), 0, 12409 }, /* MOVEA */ +{ CPUFUNC(op_307a_5), 0, 12410 }, /* MOVEA */ +{ CPUFUNC(op_307b_5), 0, 12411 }, /* MOVEA */ +{ CPUFUNC(op_307c_5), 0, 12412 }, /* MOVEA */ +{ CPUFUNC(op_3080_5), 0, 12416 }, /* MOVE */ +{ CPUFUNC(op_3088_5), 0, 12424 }, /* MOVE */ +{ CPUFUNC(op_3090_5), 0, 12432 }, /* MOVE */ +{ CPUFUNC(op_3098_5), 0, 12440 }, /* MOVE */ +{ CPUFUNC(op_30a0_5), 0, 12448 }, /* MOVE */ +{ CPUFUNC(op_30a8_5), 0, 12456 }, /* MOVE */ +{ CPUFUNC(op_30b0_5), 0, 12464 }, /* MOVE */ +{ CPUFUNC(op_30b8_5), 0, 12472 }, /* MOVE */ +{ CPUFUNC(op_30b9_5), 0, 12473 }, /* MOVE */ +{ CPUFUNC(op_30ba_5), 0, 12474 }, /* MOVE */ +{ CPUFUNC(op_30bb_5), 0, 12475 }, /* MOVE */ +{ CPUFUNC(op_30bc_5), 0, 12476 }, /* MOVE */ +{ CPUFUNC(op_30c0_5), 0, 12480 }, /* MOVE */ +{ CPUFUNC(op_30c8_5), 0, 12488 }, /* MOVE */ +{ CPUFUNC(op_30d0_5), 0, 12496 }, /* MOVE */ +{ CPUFUNC(op_30d8_5), 0, 12504 }, /* MOVE */ +{ CPUFUNC(op_30e0_5), 0, 12512 }, /* MOVE */ +{ CPUFUNC(op_30e8_5), 0, 12520 }, /* MOVE */ +{ CPUFUNC(op_30f0_5), 0, 12528 }, /* MOVE */ +{ CPUFUNC(op_30f8_5), 0, 12536 }, /* MOVE */ +{ CPUFUNC(op_30f9_5), 0, 12537 }, /* MOVE */ +{ CPUFUNC(op_30fa_5), 0, 12538 }, /* MOVE */ +{ CPUFUNC(op_30fb_5), 0, 12539 }, /* MOVE */ +{ CPUFUNC(op_30fc_5), 0, 12540 }, /* MOVE */ +{ CPUFUNC(op_3100_5), 0, 12544 }, /* MOVE */ +{ CPUFUNC(op_3108_5), 0, 12552 }, /* MOVE */ +{ CPUFUNC(op_3110_5), 0, 12560 }, /* MOVE */ +{ CPUFUNC(op_3118_5), 0, 12568 }, /* MOVE */ +{ CPUFUNC(op_3120_5), 0, 12576 }, /* MOVE */ +{ CPUFUNC(op_3128_5), 0, 12584 }, /* MOVE */ +{ CPUFUNC(op_3130_5), 0, 12592 }, /* MOVE */ +{ CPUFUNC(op_3138_5), 0, 12600 }, /* MOVE */ +{ CPUFUNC(op_3139_5), 0, 12601 }, /* MOVE */ +{ CPUFUNC(op_313a_5), 0, 12602 }, /* MOVE */ +{ CPUFUNC(op_313b_5), 0, 12603 }, /* MOVE */ +{ CPUFUNC(op_313c_5), 0, 12604 }, /* MOVE */ +{ CPUFUNC(op_3140_5), 0, 12608 }, /* MOVE */ +{ CPUFUNC(op_3148_5), 0, 12616 }, /* MOVE */ +{ CPUFUNC(op_3150_5), 0, 12624 }, /* MOVE */ +{ CPUFUNC(op_3158_5), 0, 12632 }, /* MOVE */ +{ CPUFUNC(op_3160_5), 0, 12640 }, /* MOVE */ +{ CPUFUNC(op_3168_5), 0, 12648 }, /* MOVE */ +{ CPUFUNC(op_3170_5), 0, 12656 }, /* MOVE */ +{ CPUFUNC(op_3178_5), 0, 12664 }, /* MOVE */ +{ CPUFUNC(op_3179_5), 0, 12665 }, /* MOVE */ +{ CPUFUNC(op_317a_5), 0, 12666 }, /* MOVE */ +{ CPUFUNC(op_317b_5), 0, 12667 }, /* MOVE */ +{ CPUFUNC(op_317c_5), 0, 12668 }, /* MOVE */ +{ CPUFUNC(op_3180_5), 0, 12672 }, /* MOVE */ +{ CPUFUNC(op_3188_5), 0, 12680 }, /* MOVE */ +{ CPUFUNC(op_3190_5), 0, 12688 }, /* MOVE */ +{ CPUFUNC(op_3198_5), 0, 12696 }, /* MOVE */ +{ CPUFUNC(op_31a0_5), 0, 12704 }, /* MOVE */ +{ CPUFUNC(op_31a8_5), 0, 12712 }, /* MOVE */ +{ CPUFUNC(op_31b0_5), 0, 12720 }, /* MOVE */ +{ CPUFUNC(op_31b8_5), 0, 12728 }, /* MOVE */ +{ CPUFUNC(op_31b9_5), 0, 12729 }, /* MOVE */ +{ CPUFUNC(op_31ba_5), 0, 12730 }, /* MOVE */ +{ CPUFUNC(op_31bb_5), 0, 12731 }, /* MOVE */ +{ CPUFUNC(op_31bc_5), 0, 12732 }, /* MOVE */ +{ CPUFUNC(op_31c0_5), 0, 12736 }, /* MOVE */ +{ CPUFUNC(op_31c8_5), 0, 12744 }, /* MOVE */ +{ CPUFUNC(op_31d0_5), 0, 12752 }, /* MOVE */ +{ CPUFUNC(op_31d8_5), 0, 12760 }, /* MOVE */ +{ CPUFUNC(op_31e0_5), 0, 12768 }, /* MOVE */ +{ CPUFUNC(op_31e8_5), 0, 12776 }, /* MOVE */ +{ CPUFUNC(op_31f0_5), 0, 12784 }, /* MOVE */ +{ CPUFUNC(op_31f8_5), 0, 12792 }, /* MOVE */ +{ CPUFUNC(op_31f9_5), 0, 12793 }, /* MOVE */ +{ CPUFUNC(op_31fa_5), 0, 12794 }, /* MOVE */ +{ CPUFUNC(op_31fb_5), 0, 12795 }, /* MOVE */ +{ CPUFUNC(op_31fc_5), 0, 12796 }, /* MOVE */ +{ CPUFUNC(op_33c0_5), 0, 13248 }, /* MOVE */ +{ CPUFUNC(op_33c8_5), 0, 13256 }, /* MOVE */ +{ CPUFUNC(op_33d0_5), 0, 13264 }, /* MOVE */ +{ CPUFUNC(op_33d8_5), 0, 13272 }, /* MOVE */ +{ CPUFUNC(op_33e0_5), 0, 13280 }, /* MOVE */ +{ CPUFUNC(op_33e8_5), 0, 13288 }, /* MOVE */ +{ CPUFUNC(op_33f0_5), 0, 13296 }, /* MOVE */ +{ CPUFUNC(op_33f8_5), 0, 13304 }, /* MOVE */ +{ CPUFUNC(op_33f9_5), 0, 13305 }, /* MOVE */ +{ CPUFUNC(op_33fa_5), 0, 13306 }, /* MOVE */ +{ CPUFUNC(op_33fb_5), 0, 13307 }, /* MOVE */ +{ CPUFUNC(op_33fc_5), 0, 13308 }, /* MOVE */ +{ CPUFUNC(op_4000_5), 0, 16384 }, /* NEGX */ +{ CPUFUNC(op_4010_5), 0, 16400 }, /* NEGX */ +{ CPUFUNC(op_4018_5), 0, 16408 }, /* NEGX */ +{ CPUFUNC(op_4020_5), 0, 16416 }, /* NEGX */ +{ CPUFUNC(op_4028_5), 0, 16424 }, /* NEGX */ +{ CPUFUNC(op_4030_5), 0, 16432 }, /* NEGX */ +{ CPUFUNC(op_4038_5), 0, 16440 }, /* NEGX */ +{ CPUFUNC(op_4039_5), 0, 16441 }, /* NEGX */ +{ CPUFUNC(op_4040_5), 0, 16448 }, /* NEGX */ +{ CPUFUNC(op_4050_5), 0, 16464 }, /* NEGX */ +{ CPUFUNC(op_4058_5), 0, 16472 }, /* NEGX */ +{ CPUFUNC(op_4060_5), 0, 16480 }, /* NEGX */ +{ CPUFUNC(op_4068_5), 0, 16488 }, /* NEGX */ +{ CPUFUNC(op_4070_5), 0, 16496 }, /* NEGX */ +{ CPUFUNC(op_4078_5), 0, 16504 }, /* NEGX */ +{ CPUFUNC(op_4079_5), 0, 16505 }, /* NEGX */ +{ CPUFUNC(op_4080_5), 0, 16512 }, /* NEGX */ +{ CPUFUNC(op_4090_5), 0, 16528 }, /* NEGX */ +{ CPUFUNC(op_4098_5), 0, 16536 }, /* NEGX */ +{ CPUFUNC(op_40a0_5), 0, 16544 }, /* NEGX */ +{ CPUFUNC(op_40a8_5), 0, 16552 }, /* NEGX */ +{ CPUFUNC(op_40b0_5), 0, 16560 }, /* NEGX */ +{ CPUFUNC(op_40b8_5), 0, 16568 }, /* NEGX */ +{ CPUFUNC(op_40b9_5), 0, 16569 }, /* NEGX */ +{ CPUFUNC(op_40c0_5), 0, 16576 }, /* MVSR2 */ +{ CPUFUNC(op_40d0_5), 0, 16592 }, /* MVSR2 */ +{ CPUFUNC(op_40d8_5), 0, 16600 }, /* MVSR2 */ +{ CPUFUNC(op_40e0_5), 0, 16608 }, /* MVSR2 */ +{ CPUFUNC(op_40e8_5), 0, 16616 }, /* MVSR2 */ +{ CPUFUNC(op_40f0_5), 0, 16624 }, /* MVSR2 */ +{ CPUFUNC(op_40f8_5), 0, 16632 }, /* MVSR2 */ +{ CPUFUNC(op_40f9_5), 0, 16633 }, /* MVSR2 */ +{ CPUFUNC(op_4180_5), 0, 16768 }, /* CHK */ +{ CPUFUNC(op_4190_5), 0, 16784 }, /* CHK */ +{ CPUFUNC(op_4198_5), 0, 16792 }, /* CHK */ +{ CPUFUNC(op_41a0_5), 0, 16800 }, /* CHK */ +{ CPUFUNC(op_41a8_5), 0, 16808 }, /* CHK */ +{ CPUFUNC(op_41b0_5), 0, 16816 }, /* CHK */ +{ CPUFUNC(op_41b8_5), 0, 16824 }, /* CHK */ +{ CPUFUNC(op_41b9_5), 0, 16825 }, /* CHK */ +{ CPUFUNC(op_41ba_5), 0, 16826 }, /* CHK */ +{ CPUFUNC(op_41bb_5), 0, 16827 }, /* CHK */ +{ CPUFUNC(op_41bc_5), 0, 16828 }, /* CHK */ +{ CPUFUNC(op_41d0_5), 0, 16848 }, /* LEA */ +{ CPUFUNC(op_41e8_5), 0, 16872 }, /* LEA */ +{ CPUFUNC(op_41f0_5), 0, 16880 }, /* LEA */ +{ CPUFUNC(op_41f8_5), 0, 16888 }, /* LEA */ +{ CPUFUNC(op_41f9_5), 0, 16889 }, /* LEA */ +{ CPUFUNC(op_41fa_5), 0, 16890 }, /* LEA */ +{ CPUFUNC(op_41fb_5), 0, 16891 }, /* LEA */ +{ CPUFUNC(op_4200_5), 0, 16896 }, /* CLR */ +{ CPUFUNC(op_4210_5), 0, 16912 }, /* CLR */ +{ CPUFUNC(op_4218_5), 0, 16920 }, /* CLR */ +{ CPUFUNC(op_4220_5), 0, 16928 }, /* CLR */ +{ CPUFUNC(op_4228_5), 0, 16936 }, /* CLR */ +{ CPUFUNC(op_4230_5), 0, 16944 }, /* CLR */ +{ CPUFUNC(op_4238_5), 0, 16952 }, /* CLR */ +{ CPUFUNC(op_4239_5), 0, 16953 }, /* CLR */ +{ CPUFUNC(op_4240_5), 0, 16960 }, /* CLR */ +{ CPUFUNC(op_4250_5), 0, 16976 }, /* CLR */ +{ CPUFUNC(op_4258_5), 0, 16984 }, /* CLR */ +{ CPUFUNC(op_4260_5), 0, 16992 }, /* CLR */ +{ CPUFUNC(op_4268_5), 0, 17000 }, /* CLR */ +{ CPUFUNC(op_4270_5), 0, 17008 }, /* CLR */ +{ CPUFUNC(op_4278_5), 0, 17016 }, /* CLR */ +{ CPUFUNC(op_4279_5), 0, 17017 }, /* CLR */ +{ CPUFUNC(op_4280_5), 0, 17024 }, /* CLR */ +{ CPUFUNC(op_4290_5), 0, 17040 }, /* CLR */ +{ CPUFUNC(op_4298_5), 0, 17048 }, /* CLR */ +{ CPUFUNC(op_42a0_5), 0, 17056 }, /* CLR */ +{ CPUFUNC(op_42a8_5), 0, 17064 }, /* CLR */ +{ CPUFUNC(op_42b0_5), 0, 17072 }, /* CLR */ +{ CPUFUNC(op_42b8_5), 0, 17080 }, /* CLR */ +{ CPUFUNC(op_42b9_5), 0, 17081 }, /* CLR */ +{ CPUFUNC(op_4400_5), 0, 17408 }, /* NEG */ +{ CPUFUNC(op_4410_5), 0, 17424 }, /* NEG */ +{ CPUFUNC(op_4418_5), 0, 17432 }, /* NEG */ +{ CPUFUNC(op_4420_5), 0, 17440 }, /* NEG */ +{ CPUFUNC(op_4428_5), 0, 17448 }, /* NEG */ +{ CPUFUNC(op_4430_5), 0, 17456 }, /* NEG */ +{ CPUFUNC(op_4438_5), 0, 17464 }, /* NEG */ +{ CPUFUNC(op_4439_5), 0, 17465 }, /* NEG */ +{ CPUFUNC(op_4440_5), 0, 17472 }, /* NEG */ +{ CPUFUNC(op_4450_5), 0, 17488 }, /* NEG */ +{ CPUFUNC(op_4458_5), 0, 17496 }, /* NEG */ +{ CPUFUNC(op_4460_5), 0, 17504 }, /* NEG */ +{ CPUFUNC(op_4468_5), 0, 17512 }, /* NEG */ +{ CPUFUNC(op_4470_5), 0, 17520 }, /* NEG */ +{ CPUFUNC(op_4478_5), 0, 17528 }, /* NEG */ +{ CPUFUNC(op_4479_5), 0, 17529 }, /* NEG */ +{ CPUFUNC(op_4480_5), 0, 17536 }, /* NEG */ +{ CPUFUNC(op_4490_5), 0, 17552 }, /* NEG */ +{ CPUFUNC(op_4498_5), 0, 17560 }, /* NEG */ +{ CPUFUNC(op_44a0_5), 0, 17568 }, /* NEG */ +{ CPUFUNC(op_44a8_5), 0, 17576 }, /* NEG */ +{ CPUFUNC(op_44b0_5), 0, 17584 }, /* NEG */ +{ CPUFUNC(op_44b8_5), 0, 17592 }, /* NEG */ +{ CPUFUNC(op_44b9_5), 0, 17593 }, /* NEG */ +{ CPUFUNC(op_44c0_5), 0, 17600 }, /* MV2SR */ +{ CPUFUNC(op_44d0_5), 0, 17616 }, /* MV2SR */ +{ CPUFUNC(op_44d8_5), 0, 17624 }, /* MV2SR */ +{ CPUFUNC(op_44e0_5), 0, 17632 }, /* MV2SR */ +{ CPUFUNC(op_44e8_5), 0, 17640 }, /* MV2SR */ +{ CPUFUNC(op_44f0_5), 0, 17648 }, /* MV2SR */ +{ CPUFUNC(op_44f8_5), 0, 17656 }, /* MV2SR */ +{ CPUFUNC(op_44f9_5), 0, 17657 }, /* MV2SR */ +{ CPUFUNC(op_44fa_5), 0, 17658 }, /* MV2SR */ +{ CPUFUNC(op_44fb_5), 0, 17659 }, /* MV2SR */ +{ CPUFUNC(op_44fc_5), 0, 17660 }, /* MV2SR */ +{ CPUFUNC(op_4600_5), 0, 17920 }, /* NOT */ +{ CPUFUNC(op_4610_5), 0, 17936 }, /* NOT */ +{ CPUFUNC(op_4618_5), 0, 17944 }, /* NOT */ +{ CPUFUNC(op_4620_5), 0, 17952 }, /* NOT */ +{ CPUFUNC(op_4628_5), 0, 17960 }, /* NOT */ +{ CPUFUNC(op_4630_5), 0, 17968 }, /* NOT */ +{ CPUFUNC(op_4638_5), 0, 17976 }, /* NOT */ +{ CPUFUNC(op_4639_5), 0, 17977 }, /* NOT */ +{ CPUFUNC(op_4640_5), 0, 17984 }, /* NOT */ +{ CPUFUNC(op_4650_5), 0, 18000 }, /* NOT */ +{ CPUFUNC(op_4658_5), 0, 18008 }, /* NOT */ +{ CPUFUNC(op_4660_5), 0, 18016 }, /* NOT */ +{ CPUFUNC(op_4668_5), 0, 18024 }, /* NOT */ +{ CPUFUNC(op_4670_5), 0, 18032 }, /* NOT */ +{ CPUFUNC(op_4678_5), 0, 18040 }, /* NOT */ +{ CPUFUNC(op_4679_5), 0, 18041 }, /* NOT */ +{ CPUFUNC(op_4680_5), 0, 18048 }, /* NOT */ +{ CPUFUNC(op_4690_5), 0, 18064 }, /* NOT */ +{ CPUFUNC(op_4698_5), 0, 18072 }, /* NOT */ +{ CPUFUNC(op_46a0_5), 0, 18080 }, /* NOT */ +{ CPUFUNC(op_46a8_5), 0, 18088 }, /* NOT */ +{ CPUFUNC(op_46b0_5), 0, 18096 }, /* NOT */ +{ CPUFUNC(op_46b8_5), 0, 18104 }, /* NOT */ +{ CPUFUNC(op_46b9_5), 0, 18105 }, /* NOT */ +{ CPUFUNC(op_46c0_5), 0, 18112 }, /* MV2SR */ +{ CPUFUNC(op_46d0_5), 0, 18128 }, /* MV2SR */ +{ CPUFUNC(op_46d8_5), 0, 18136 }, /* MV2SR */ +{ CPUFUNC(op_46e0_5), 0, 18144 }, /* MV2SR */ +{ CPUFUNC(op_46e8_5), 0, 18152 }, /* MV2SR */ +{ CPUFUNC(op_46f0_5), 0, 18160 }, /* MV2SR */ +{ CPUFUNC(op_46f8_5), 0, 18168 }, /* MV2SR */ +{ CPUFUNC(op_46f9_5), 0, 18169 }, /* MV2SR */ +{ CPUFUNC(op_46fa_5), 0, 18170 }, /* MV2SR */ +{ CPUFUNC(op_46fb_5), 0, 18171 }, /* MV2SR */ +{ CPUFUNC(op_46fc_5), 0, 18172 }, /* MV2SR */ +{ CPUFUNC(op_4800_5), 0, 18432 }, /* NBCD */ +{ CPUFUNC(op_4810_5), 0, 18448 }, /* NBCD */ +{ CPUFUNC(op_4818_5), 0, 18456 }, /* NBCD */ +{ CPUFUNC(op_4820_5), 0, 18464 }, /* NBCD */ +{ CPUFUNC(op_4828_5), 0, 18472 }, /* NBCD */ +{ CPUFUNC(op_4830_5), 0, 18480 }, /* NBCD */ +{ CPUFUNC(op_4838_5), 0, 18488 }, /* NBCD */ +{ CPUFUNC(op_4839_5), 0, 18489 }, /* NBCD */ +{ CPUFUNC(op_4840_5), 0, 18496 }, /* SWAP */ +{ CPUFUNC(op_4850_5), 0, 18512 }, /* PEA */ +{ CPUFUNC(op_4868_5), 0, 18536 }, /* PEA */ +{ CPUFUNC(op_4870_5), 0, 18544 }, /* PEA */ +{ CPUFUNC(op_4878_5), 0, 18552 }, /* PEA */ +{ CPUFUNC(op_4879_5), 0, 18553 }, /* PEA */ +{ CPUFUNC(op_487a_5), 0, 18554 }, /* PEA */ +{ CPUFUNC(op_487b_5), 0, 18555 }, /* PEA */ +{ CPUFUNC(op_4880_5), 0, 18560 }, /* EXT */ +{ CPUFUNC(op_4890_5), 0, 18576 }, /* MVMLE */ +{ CPUFUNC(op_48a0_5), 0, 18592 }, /* MVMLE */ +{ CPUFUNC(op_48a8_5), 0, 18600 }, /* MVMLE */ +{ CPUFUNC(op_48b0_5), 0, 18608 }, /* MVMLE */ +{ CPUFUNC(op_48b8_5), 0, 18616 }, /* MVMLE */ +{ CPUFUNC(op_48b9_5), 0, 18617 }, /* MVMLE */ +{ CPUFUNC(op_48c0_5), 0, 18624 }, /* EXT */ +{ CPUFUNC(op_48d0_5), 0, 18640 }, /* MVMLE */ +{ CPUFUNC(op_48e0_5), 0, 18656 }, /* MVMLE */ +{ CPUFUNC(op_48e8_5), 0, 18664 }, /* MVMLE */ +{ CPUFUNC(op_48f0_5), 0, 18672 }, /* MVMLE */ +{ CPUFUNC(op_48f8_5), 0, 18680 }, /* MVMLE */ +{ CPUFUNC(op_48f9_5), 0, 18681 }, /* MVMLE */ +{ CPUFUNC(op_4a00_5), 0, 18944 }, /* TST */ +{ CPUFUNC(op_4a10_5), 0, 18960 }, /* TST */ +{ CPUFUNC(op_4a18_5), 0, 18968 }, /* TST */ +{ CPUFUNC(op_4a20_5), 0, 18976 }, /* TST */ +{ CPUFUNC(op_4a28_5), 0, 18984 }, /* TST */ +{ CPUFUNC(op_4a30_5), 0, 18992 }, /* TST */ +{ CPUFUNC(op_4a38_5), 0, 19000 }, /* TST */ +{ CPUFUNC(op_4a39_5), 0, 19001 }, /* TST */ +{ CPUFUNC(op_4a3a_5), 0, 19002 }, /* TST */ +{ CPUFUNC(op_4a3b_5), 0, 19003 }, /* TST */ +{ CPUFUNC(op_4a3c_5), 0, 19004 }, /* TST */ +{ CPUFUNC(op_4a40_5), 0, 19008 }, /* TST */ +{ CPUFUNC(op_4a48_5), 0, 19016 }, /* TST */ +{ CPUFUNC(op_4a50_5), 0, 19024 }, /* TST */ +{ CPUFUNC(op_4a58_5), 0, 19032 }, /* TST */ +{ CPUFUNC(op_4a60_5), 0, 19040 }, /* TST */ +{ CPUFUNC(op_4a68_5), 0, 19048 }, /* TST */ +{ CPUFUNC(op_4a70_5), 0, 19056 }, /* TST */ +{ CPUFUNC(op_4a78_5), 0, 19064 }, /* TST */ +{ CPUFUNC(op_4a79_5), 0, 19065 }, /* TST */ +{ CPUFUNC(op_4a7a_5), 0, 19066 }, /* TST */ +{ CPUFUNC(op_4a7b_5), 0, 19067 }, /* TST */ +{ CPUFUNC(op_4a7c_5), 0, 19068 }, /* TST */ +{ CPUFUNC(op_4a80_5), 0, 19072 }, /* TST */ +{ CPUFUNC(op_4a88_5), 0, 19080 }, /* TST */ +{ CPUFUNC(op_4a90_5), 0, 19088 }, /* TST */ +{ CPUFUNC(op_4a98_5), 0, 19096 }, /* TST */ +{ CPUFUNC(op_4aa0_5), 0, 19104 }, /* TST */ +{ CPUFUNC(op_4aa8_5), 0, 19112 }, /* TST */ +{ CPUFUNC(op_4ab0_5), 0, 19120 }, /* TST */ +{ CPUFUNC(op_4ab8_5), 0, 19128 }, /* TST */ +{ CPUFUNC(op_4ab9_5), 0, 19129 }, /* TST */ +{ CPUFUNC(op_4aba_5), 0, 19130 }, /* TST */ +{ CPUFUNC(op_4abb_5), 0, 19131 }, /* TST */ +{ CPUFUNC(op_4abc_5), 0, 19132 }, /* TST */ +{ CPUFUNC(op_4ac0_5), 0, 19136 }, /* TAS */ +{ CPUFUNC(op_4ad0_5), 0, 19152 }, /* TAS */ +{ CPUFUNC(op_4ad8_5), 0, 19160 }, /* TAS */ +{ CPUFUNC(op_4ae0_5), 0, 19168 }, /* TAS */ +{ CPUFUNC(op_4ae8_5), 0, 19176 }, /* TAS */ +{ CPUFUNC(op_4af0_5), 0, 19184 }, /* TAS */ +{ CPUFUNC(op_4af8_5), 0, 19192 }, /* TAS */ +{ CPUFUNC(op_4af9_5), 0, 19193 }, /* TAS */ +{ CPUFUNC(op_4c90_5), 0, 19600 }, /* MVMEL */ +{ CPUFUNC(op_4c98_5), 0, 19608 }, /* MVMEL */ +{ CPUFUNC(op_4ca8_5), 0, 19624 }, /* MVMEL */ +{ CPUFUNC(op_4cb0_5), 0, 19632 }, /* MVMEL */ +{ CPUFUNC(op_4cb8_5), 0, 19640 }, /* MVMEL */ +{ CPUFUNC(op_4cb9_5), 0, 19641 }, /* MVMEL */ +{ CPUFUNC(op_4cba_5), 0, 19642 }, /* MVMEL */ +{ CPUFUNC(op_4cbb_5), 0, 19643 }, /* MVMEL */ +{ CPUFUNC(op_4cd0_5), 0, 19664 }, /* MVMEL */ +{ CPUFUNC(op_4cd8_5), 0, 19672 }, /* MVMEL */ +{ CPUFUNC(op_4ce8_5), 0, 19688 }, /* MVMEL */ +{ CPUFUNC(op_4cf0_5), 0, 19696 }, /* MVMEL */ +{ CPUFUNC(op_4cf8_5), 0, 19704 }, /* MVMEL */ +{ CPUFUNC(op_4cf9_5), 0, 19705 }, /* MVMEL */ +{ CPUFUNC(op_4cfa_5), 0, 19706 }, /* MVMEL */ +{ CPUFUNC(op_4cfb_5), 0, 19707 }, /* MVMEL */ +{ CPUFUNC(op_4e40_5), 0, 20032 }, /* TRAP */ +{ CPUFUNC(op_4e50_5), 0, 20048 }, /* LINK */ +{ CPUFUNC(op_4e58_5), 0, 20056 }, /* UNLK */ +{ CPUFUNC(op_4e60_5), 0, 20064 }, /* MVR2USP */ +{ CPUFUNC(op_4e68_5), 0, 20072 }, /* MVUSP2R */ +{ CPUFUNC(op_4e70_5), 0, 20080 }, /* RESET */ +{ CPUFUNC(op_4e71_5), 0, 20081 }, /* NOP */ +{ CPUFUNC(op_4e72_5), 0, 20082 }, /* STOP */ +{ CPUFUNC(op_4e73_5), 0, 20083 }, /* RTE */ +{ CPUFUNC(op_4e74_5), 0, 20084 }, /* RTD */ +{ CPUFUNC(op_4e75_5), 0, 20085 }, /* RTS */ +{ CPUFUNC(op_4e76_5), 0, 20086 }, /* TRAPV */ +{ CPUFUNC(op_4e77_5), 0, 20087 }, /* RTR */ +{ CPUFUNC(op_4e90_5), 0, 20112 }, /* JSR */ +{ CPUFUNC(op_4ea8_5), 0, 20136 }, /* JSR */ +{ CPUFUNC(op_4eb0_5), 0, 20144 }, /* JSR */ +{ CPUFUNC(op_4eb8_5), 0, 20152 }, /* JSR */ +{ CPUFUNC(op_4eb9_5), 0, 20153 }, /* JSR */ +{ CPUFUNC(op_4eba_5), 0, 20154 }, /* JSR */ +{ CPUFUNC(op_4ebb_5), 0, 20155 }, /* JSR */ +{ CPUFUNC(op_4ed0_5), 0, 20176 }, /* JMP */ +{ CPUFUNC(op_4ee8_5), 0, 20200 }, /* JMP */ +{ CPUFUNC(op_4ef0_5), 0, 20208 }, /* JMP */ +{ CPUFUNC(op_4ef8_5), 0, 20216 }, /* JMP */ +{ CPUFUNC(op_4ef9_5), 0, 20217 }, /* JMP */ +{ CPUFUNC(op_4efa_5), 0, 20218 }, /* JMP */ +{ CPUFUNC(op_4efb_5), 0, 20219 }, /* JMP */ +{ CPUFUNC(op_5000_5), 0, 20480 }, /* ADD */ +{ CPUFUNC(op_5010_5), 0, 20496 }, /* ADD */ +{ CPUFUNC(op_5018_5), 0, 20504 }, /* ADD */ +{ CPUFUNC(op_5020_5), 0, 20512 }, /* ADD */ +{ CPUFUNC(op_5028_5), 0, 20520 }, /* ADD */ +{ CPUFUNC(op_5030_5), 0, 20528 }, /* ADD */ +{ CPUFUNC(op_5038_5), 0, 20536 }, /* ADD */ +{ CPUFUNC(op_5039_5), 0, 20537 }, /* ADD */ +{ CPUFUNC(op_5040_5), 0, 20544 }, /* ADD */ +{ CPUFUNC(op_5048_5), 0, 20552 }, /* ADDA */ +{ CPUFUNC(op_5050_5), 0, 20560 }, /* ADD */ +{ CPUFUNC(op_5058_5), 0, 20568 }, /* ADD */ +{ CPUFUNC(op_5060_5), 0, 20576 }, /* ADD */ +{ CPUFUNC(op_5068_5), 0, 20584 }, /* ADD */ +{ CPUFUNC(op_5070_5), 0, 20592 }, /* ADD */ +{ CPUFUNC(op_5078_5), 0, 20600 }, /* ADD */ +{ CPUFUNC(op_5079_5), 0, 20601 }, /* ADD */ +{ CPUFUNC(op_5080_5), 0, 20608 }, /* ADD */ +{ CPUFUNC(op_5088_5), 0, 20616 }, /* ADDA */ +{ CPUFUNC(op_5090_5), 0, 20624 }, /* ADD */ +{ CPUFUNC(op_5098_5), 0, 20632 }, /* ADD */ +{ CPUFUNC(op_50a0_5), 0, 20640 }, /* ADD */ +{ CPUFUNC(op_50a8_5), 0, 20648 }, /* ADD */ +{ CPUFUNC(op_50b0_5), 0, 20656 }, /* ADD */ +{ CPUFUNC(op_50b8_5), 0, 20664 }, /* ADD */ +{ CPUFUNC(op_50b9_5), 0, 20665 }, /* ADD */ +{ CPUFUNC(op_50c0_5), 0, 20672 }, /* Scc */ +{ CPUFUNC(op_50c8_5), 0, 20680 }, /* DBcc */ +{ CPUFUNC(op_50d0_5), 0, 20688 }, /* Scc */ +{ CPUFUNC(op_50d8_5), 0, 20696 }, /* Scc */ +{ CPUFUNC(op_50e0_5), 0, 20704 }, /* Scc */ +{ CPUFUNC(op_50e8_5), 0, 20712 }, /* Scc */ +{ CPUFUNC(op_50f0_5), 0, 20720 }, /* Scc */ +{ CPUFUNC(op_50f8_5), 0, 20728 }, /* Scc */ +{ CPUFUNC(op_50f9_5), 0, 20729 }, /* Scc */ +{ CPUFUNC(op_5100_5), 0, 20736 }, /* SUB */ +{ CPUFUNC(op_5110_5), 0, 20752 }, /* SUB */ +{ CPUFUNC(op_5118_5), 0, 20760 }, /* SUB */ +{ CPUFUNC(op_5120_5), 0, 20768 }, /* SUB */ +{ CPUFUNC(op_5128_5), 0, 20776 }, /* SUB */ +{ CPUFUNC(op_5130_5), 0, 20784 }, /* SUB */ +{ CPUFUNC(op_5138_5), 0, 20792 }, /* SUB */ +{ CPUFUNC(op_5139_5), 0, 20793 }, /* SUB */ +{ CPUFUNC(op_5140_5), 0, 20800 }, /* SUB */ +{ CPUFUNC(op_5148_5), 0, 20808 }, /* SUBA */ +{ CPUFUNC(op_5150_5), 0, 20816 }, /* SUB */ +{ CPUFUNC(op_5158_5), 0, 20824 }, /* SUB */ +{ CPUFUNC(op_5160_5), 0, 20832 }, /* SUB */ +{ CPUFUNC(op_5168_5), 0, 20840 }, /* SUB */ +{ CPUFUNC(op_5170_5), 0, 20848 }, /* SUB */ +{ CPUFUNC(op_5178_5), 0, 20856 }, /* SUB */ +{ CPUFUNC(op_5179_5), 0, 20857 }, /* SUB */ +{ CPUFUNC(op_5180_5), 0, 20864 }, /* SUB */ +{ CPUFUNC(op_5188_5), 0, 20872 }, /* SUBA */ +{ CPUFUNC(op_5190_5), 0, 20880 }, /* SUB */ +{ CPUFUNC(op_5198_5), 0, 20888 }, /* SUB */ +{ CPUFUNC(op_51a0_5), 0, 20896 }, /* SUB */ +{ CPUFUNC(op_51a8_5), 0, 20904 }, /* SUB */ +{ CPUFUNC(op_51b0_5), 0, 20912 }, /* SUB */ +{ CPUFUNC(op_51b8_5), 0, 20920 }, /* SUB */ +{ CPUFUNC(op_51b9_5), 0, 20921 }, /* SUB */ +{ CPUFUNC(op_51c0_5), 0, 20928 }, /* Scc */ +{ CPUFUNC(op_51c8_5), 0, 20936 }, /* DBcc */ +{ CPUFUNC(op_51d0_5), 0, 20944 }, /* Scc */ +{ CPUFUNC(op_51d8_5), 0, 20952 }, /* Scc */ +{ CPUFUNC(op_51e0_5), 0, 20960 }, /* Scc */ +{ CPUFUNC(op_51e8_5), 0, 20968 }, /* Scc */ +{ CPUFUNC(op_51f0_5), 0, 20976 }, /* Scc */ +{ CPUFUNC(op_51f8_5), 0, 20984 }, /* Scc */ +{ CPUFUNC(op_51f9_5), 0, 20985 }, /* Scc */ +{ CPUFUNC(op_52c0_5), 0, 21184 }, /* Scc */ +{ CPUFUNC(op_52c8_5), 0, 21192 }, /* DBcc */ +{ CPUFUNC(op_52d0_5), 0, 21200 }, /* Scc */ +{ CPUFUNC(op_52d8_5), 0, 21208 }, /* Scc */ +{ CPUFUNC(op_52e0_5), 0, 21216 }, /* Scc */ +{ CPUFUNC(op_52e8_5), 0, 21224 }, /* Scc */ +{ CPUFUNC(op_52f0_5), 0, 21232 }, /* Scc */ +{ CPUFUNC(op_52f8_5), 0, 21240 }, /* Scc */ +{ CPUFUNC(op_52f9_5), 0, 21241 }, /* Scc */ +{ CPUFUNC(op_53c0_5), 0, 21440 }, /* Scc */ +{ CPUFUNC(op_53c8_5), 0, 21448 }, /* DBcc */ +{ CPUFUNC(op_53d0_5), 0, 21456 }, /* Scc */ +{ CPUFUNC(op_53d8_5), 0, 21464 }, /* Scc */ +{ CPUFUNC(op_53e0_5), 0, 21472 }, /* Scc */ +{ CPUFUNC(op_53e8_5), 0, 21480 }, /* Scc */ +{ CPUFUNC(op_53f0_5), 0, 21488 }, /* Scc */ +{ CPUFUNC(op_53f8_5), 0, 21496 }, /* Scc */ +{ CPUFUNC(op_53f9_5), 0, 21497 }, /* Scc */ +{ CPUFUNC(op_54c0_5), 0, 21696 }, /* Scc */ +{ CPUFUNC(op_54c8_5), 0, 21704 }, /* DBcc */ +{ CPUFUNC(op_54d0_5), 0, 21712 }, /* Scc */ +{ CPUFUNC(op_54d8_5), 0, 21720 }, /* Scc */ +{ CPUFUNC(op_54e0_5), 0, 21728 }, /* Scc */ +{ CPUFUNC(op_54e8_5), 0, 21736 }, /* Scc */ +{ CPUFUNC(op_54f0_5), 0, 21744 }, /* Scc */ +{ CPUFUNC(op_54f8_5), 0, 21752 }, /* Scc */ +{ CPUFUNC(op_54f9_5), 0, 21753 }, /* Scc */ +{ CPUFUNC(op_55c0_5), 0, 21952 }, /* Scc */ +{ CPUFUNC(op_55c8_5), 0, 21960 }, /* DBcc */ +{ CPUFUNC(op_55d0_5), 0, 21968 }, /* Scc */ +{ CPUFUNC(op_55d8_5), 0, 21976 }, /* Scc */ +{ CPUFUNC(op_55e0_5), 0, 21984 }, /* Scc */ +{ CPUFUNC(op_55e8_5), 0, 21992 }, /* Scc */ +{ CPUFUNC(op_55f0_5), 0, 22000 }, /* Scc */ +{ CPUFUNC(op_55f8_5), 0, 22008 }, /* Scc */ +{ CPUFUNC(op_55f9_5), 0, 22009 }, /* Scc */ +{ CPUFUNC(op_56c0_5), 0, 22208 }, /* Scc */ +{ CPUFUNC(op_56c8_5), 0, 22216 }, /* DBcc */ +{ CPUFUNC(op_56d0_5), 0, 22224 }, /* Scc */ +{ CPUFUNC(op_56d8_5), 0, 22232 }, /* Scc */ +{ CPUFUNC(op_56e0_5), 0, 22240 }, /* Scc */ +{ CPUFUNC(op_56e8_5), 0, 22248 }, /* Scc */ +{ CPUFUNC(op_56f0_5), 0, 22256 }, /* Scc */ +{ CPUFUNC(op_56f8_5), 0, 22264 }, /* Scc */ +{ CPUFUNC(op_56f9_5), 0, 22265 }, /* Scc */ +{ CPUFUNC(op_57c0_5), 0, 22464 }, /* Scc */ +{ CPUFUNC(op_57c8_5), 0, 22472 }, /* DBcc */ +{ CPUFUNC(op_57d0_5), 0, 22480 }, /* Scc */ +{ CPUFUNC(op_57d8_5), 0, 22488 }, /* Scc */ +{ CPUFUNC(op_57e0_5), 0, 22496 }, /* Scc */ +{ CPUFUNC(op_57e8_5), 0, 22504 }, /* Scc */ +{ CPUFUNC(op_57f0_5), 0, 22512 }, /* Scc */ +{ CPUFUNC(op_57f8_5), 0, 22520 }, /* Scc */ +{ CPUFUNC(op_57f9_5), 0, 22521 }, /* Scc */ +{ CPUFUNC(op_58c0_5), 0, 22720 }, /* Scc */ +{ CPUFUNC(op_58c8_5), 0, 22728 }, /* DBcc */ +{ CPUFUNC(op_58d0_5), 0, 22736 }, /* Scc */ +{ CPUFUNC(op_58d8_5), 0, 22744 }, /* Scc */ +{ CPUFUNC(op_58e0_5), 0, 22752 }, /* Scc */ +{ CPUFUNC(op_58e8_5), 0, 22760 }, /* Scc */ +{ CPUFUNC(op_58f0_5), 0, 22768 }, /* Scc */ +{ CPUFUNC(op_58f8_5), 0, 22776 }, /* Scc */ +{ CPUFUNC(op_58f9_5), 0, 22777 }, /* Scc */ +{ CPUFUNC(op_59c0_5), 0, 22976 }, /* Scc */ +{ CPUFUNC(op_59c8_5), 0, 22984 }, /* DBcc */ +{ CPUFUNC(op_59d0_5), 0, 22992 }, /* Scc */ +{ CPUFUNC(op_59d8_5), 0, 23000 }, /* Scc */ +{ CPUFUNC(op_59e0_5), 0, 23008 }, /* Scc */ +{ CPUFUNC(op_59e8_5), 0, 23016 }, /* Scc */ +{ CPUFUNC(op_59f0_5), 0, 23024 }, /* Scc */ +{ CPUFUNC(op_59f8_5), 0, 23032 }, /* Scc */ +{ CPUFUNC(op_59f9_5), 0, 23033 }, /* Scc */ +{ CPUFUNC(op_5ac0_5), 0, 23232 }, /* Scc */ +{ CPUFUNC(op_5ac8_5), 0, 23240 }, /* DBcc */ +{ CPUFUNC(op_5ad0_5), 0, 23248 }, /* Scc */ +{ CPUFUNC(op_5ad8_5), 0, 23256 }, /* Scc */ +{ CPUFUNC(op_5ae0_5), 0, 23264 }, /* Scc */ +{ CPUFUNC(op_5ae8_5), 0, 23272 }, /* Scc */ +{ CPUFUNC(op_5af0_5), 0, 23280 }, /* Scc */ +{ CPUFUNC(op_5af8_5), 0, 23288 }, /* Scc */ +{ CPUFUNC(op_5af9_5), 0, 23289 }, /* Scc */ +{ CPUFUNC(op_5bc0_5), 0, 23488 }, /* Scc */ +{ CPUFUNC(op_5bc8_5), 0, 23496 }, /* DBcc */ +{ CPUFUNC(op_5bd0_5), 0, 23504 }, /* Scc */ +{ CPUFUNC(op_5bd8_5), 0, 23512 }, /* Scc */ +{ CPUFUNC(op_5be0_5), 0, 23520 }, /* Scc */ +{ CPUFUNC(op_5be8_5), 0, 23528 }, /* Scc */ +{ CPUFUNC(op_5bf0_5), 0, 23536 }, /* Scc */ +{ CPUFUNC(op_5bf8_5), 0, 23544 }, /* Scc */ +{ CPUFUNC(op_5bf9_5), 0, 23545 }, /* Scc */ +{ CPUFUNC(op_5cc0_5), 0, 23744 }, /* Scc */ +{ CPUFUNC(op_5cc8_5), 0, 23752 }, /* DBcc */ +{ CPUFUNC(op_5cd0_5), 0, 23760 }, /* Scc */ +{ CPUFUNC(op_5cd8_5), 0, 23768 }, /* Scc */ +{ CPUFUNC(op_5ce0_5), 0, 23776 }, /* Scc */ +{ CPUFUNC(op_5ce8_5), 0, 23784 }, /* Scc */ +{ CPUFUNC(op_5cf0_5), 0, 23792 }, /* Scc */ +{ CPUFUNC(op_5cf8_5), 0, 23800 }, /* Scc */ +{ CPUFUNC(op_5cf9_5), 0, 23801 }, /* Scc */ +{ CPUFUNC(op_5dc0_5), 0, 24000 }, /* Scc */ +{ CPUFUNC(op_5dc8_5), 0, 24008 }, /* DBcc */ +{ CPUFUNC(op_5dd0_5), 0, 24016 }, /* Scc */ +{ CPUFUNC(op_5dd8_5), 0, 24024 }, /* Scc */ +{ CPUFUNC(op_5de0_5), 0, 24032 }, /* Scc */ +{ CPUFUNC(op_5de8_5), 0, 24040 }, /* Scc */ +{ CPUFUNC(op_5df0_5), 0, 24048 }, /* Scc */ +{ CPUFUNC(op_5df8_5), 0, 24056 }, /* Scc */ +{ CPUFUNC(op_5df9_5), 0, 24057 }, /* Scc */ +{ CPUFUNC(op_5ec0_5), 0, 24256 }, /* Scc */ +{ CPUFUNC(op_5ec8_5), 0, 24264 }, /* DBcc */ +{ CPUFUNC(op_5ed0_5), 0, 24272 }, /* Scc */ +{ CPUFUNC(op_5ed8_5), 0, 24280 }, /* Scc */ +{ CPUFUNC(op_5ee0_5), 0, 24288 }, /* Scc */ +{ CPUFUNC(op_5ee8_5), 0, 24296 }, /* Scc */ +{ CPUFUNC(op_5ef0_5), 0, 24304 }, /* Scc */ +{ CPUFUNC(op_5ef8_5), 0, 24312 }, /* Scc */ +{ CPUFUNC(op_5ef9_5), 0, 24313 }, /* Scc */ +{ CPUFUNC(op_5fc0_5), 0, 24512 }, /* Scc */ +{ CPUFUNC(op_5fc8_5), 0, 24520 }, /* DBcc */ +{ CPUFUNC(op_5fd0_5), 0, 24528 }, /* Scc */ +{ CPUFUNC(op_5fd8_5), 0, 24536 }, /* Scc */ +{ CPUFUNC(op_5fe0_5), 0, 24544 }, /* Scc */ +{ CPUFUNC(op_5fe8_5), 0, 24552 }, /* Scc */ +{ CPUFUNC(op_5ff0_5), 0, 24560 }, /* Scc */ +{ CPUFUNC(op_5ff8_5), 0, 24568 }, /* Scc */ +{ CPUFUNC(op_5ff9_5), 0, 24569 }, /* Scc */ +{ CPUFUNC(op_6000_5), 0, 24576 }, /* Bcc */ +{ CPUFUNC(op_6001_5), 0, 24577 }, /* Bcc */ +{ CPUFUNC(op_60ff_5), 0, 24831 }, /* Bcc */ +{ CPUFUNC(op_6100_5), 0, 24832 }, /* BSR */ +{ CPUFUNC(op_6101_5), 0, 24833 }, /* BSR */ +{ CPUFUNC(op_61ff_5), 0, 25087 }, /* BSR */ +{ CPUFUNC(op_6200_5), 0, 25088 }, /* Bcc */ +{ CPUFUNC(op_6201_5), 0, 25089 }, /* Bcc */ +{ CPUFUNC(op_62ff_5), 0, 25343 }, /* Bcc */ +{ CPUFUNC(op_6300_5), 0, 25344 }, /* Bcc */ +{ CPUFUNC(op_6301_5), 0, 25345 }, /* Bcc */ +{ CPUFUNC(op_63ff_5), 0, 25599 }, /* Bcc */ +{ CPUFUNC(op_6400_5), 0, 25600 }, /* Bcc */ +{ CPUFUNC(op_6401_5), 0, 25601 }, /* Bcc */ +{ CPUFUNC(op_64ff_5), 0, 25855 }, /* Bcc */ +{ CPUFUNC(op_6500_5), 0, 25856 }, /* Bcc */ +{ CPUFUNC(op_6501_5), 0, 25857 }, /* Bcc */ +{ CPUFUNC(op_65ff_5), 0, 26111 }, /* Bcc */ +{ CPUFUNC(op_6600_5), 0, 26112 }, /* Bcc */ +{ CPUFUNC(op_6601_5), 0, 26113 }, /* Bcc */ +{ CPUFUNC(op_66ff_5), 0, 26367 }, /* Bcc */ +{ CPUFUNC(op_6700_5), 0, 26368 }, /* Bcc */ +{ CPUFUNC(op_6701_5), 0, 26369 }, /* Bcc */ +{ CPUFUNC(op_67ff_5), 0, 26623 }, /* Bcc */ +{ CPUFUNC(op_6800_5), 0, 26624 }, /* Bcc */ +{ CPUFUNC(op_6801_5), 0, 26625 }, /* Bcc */ +{ CPUFUNC(op_68ff_5), 0, 26879 }, /* Bcc */ +{ CPUFUNC(op_6900_5), 0, 26880 }, /* Bcc */ +{ CPUFUNC(op_6901_5), 0, 26881 }, /* Bcc */ +{ CPUFUNC(op_69ff_5), 0, 27135 }, /* Bcc */ +{ CPUFUNC(op_6a00_5), 0, 27136 }, /* Bcc */ +{ CPUFUNC(op_6a01_5), 0, 27137 }, /* Bcc */ +{ CPUFUNC(op_6aff_5), 0, 27391 }, /* Bcc */ +{ CPUFUNC(op_6b00_5), 0, 27392 }, /* Bcc */ +{ CPUFUNC(op_6b01_5), 0, 27393 }, /* Bcc */ +{ CPUFUNC(op_6bff_5), 0, 27647 }, /* Bcc */ +{ CPUFUNC(op_6c00_5), 0, 27648 }, /* Bcc */ +{ CPUFUNC(op_6c01_5), 0, 27649 }, /* Bcc */ +{ CPUFUNC(op_6cff_5), 0, 27903 }, /* Bcc */ +{ CPUFUNC(op_6d00_5), 0, 27904 }, /* Bcc */ +{ CPUFUNC(op_6d01_5), 0, 27905 }, /* Bcc */ +{ CPUFUNC(op_6dff_5), 0, 28159 }, /* Bcc */ +{ CPUFUNC(op_6e00_5), 0, 28160 }, /* Bcc */ +{ CPUFUNC(op_6e01_5), 0, 28161 }, /* Bcc */ +{ CPUFUNC(op_6eff_5), 0, 28415 }, /* Bcc */ +{ CPUFUNC(op_6f00_5), 0, 28416 }, /* Bcc */ +{ CPUFUNC(op_6f01_5), 0, 28417 }, /* Bcc */ +{ CPUFUNC(op_6fff_5), 0, 28671 }, /* Bcc */ +{ CPUFUNC(op_7000_5), 0, 28672 }, /* MOVE */ +{ CPUFUNC(op_8000_5), 0, 32768 }, /* OR */ +{ CPUFUNC(op_8010_5), 0, 32784 }, /* OR */ +{ CPUFUNC(op_8018_5), 0, 32792 }, /* OR */ +{ CPUFUNC(op_8020_5), 0, 32800 }, /* OR */ +{ CPUFUNC(op_8028_5), 0, 32808 }, /* OR */ +{ CPUFUNC(op_8030_5), 0, 32816 }, /* OR */ +{ CPUFUNC(op_8038_5), 0, 32824 }, /* OR */ +{ CPUFUNC(op_8039_5), 0, 32825 }, /* OR */ +{ CPUFUNC(op_803a_5), 0, 32826 }, /* OR */ +{ CPUFUNC(op_803b_5), 0, 32827 }, /* OR */ +{ CPUFUNC(op_803c_5), 0, 32828 }, /* OR */ +{ CPUFUNC(op_8040_5), 0, 32832 }, /* OR */ +{ CPUFUNC(op_8050_5), 0, 32848 }, /* OR */ +{ CPUFUNC(op_8058_5), 0, 32856 }, /* OR */ +{ CPUFUNC(op_8060_5), 0, 32864 }, /* OR */ +{ CPUFUNC(op_8068_5), 0, 32872 }, /* OR */ +{ CPUFUNC(op_8070_5), 0, 32880 }, /* OR */ +{ CPUFUNC(op_8078_5), 0, 32888 }, /* OR */ +{ CPUFUNC(op_8079_5), 0, 32889 }, /* OR */ +{ CPUFUNC(op_807a_5), 0, 32890 }, /* OR */ +{ CPUFUNC(op_807b_5), 0, 32891 }, /* OR */ +{ CPUFUNC(op_807c_5), 0, 32892 }, /* OR */ +{ CPUFUNC(op_8080_5), 0, 32896 }, /* OR */ +{ CPUFUNC(op_8090_5), 0, 32912 }, /* OR */ +{ CPUFUNC(op_8098_5), 0, 32920 }, /* OR */ +{ CPUFUNC(op_80a0_5), 0, 32928 }, /* OR */ +{ CPUFUNC(op_80a8_5), 0, 32936 }, /* OR */ +{ CPUFUNC(op_80b0_5), 0, 32944 }, /* OR */ +{ CPUFUNC(op_80b8_5), 0, 32952 }, /* OR */ +{ CPUFUNC(op_80b9_5), 0, 32953 }, /* OR */ +{ CPUFUNC(op_80ba_5), 0, 32954 }, /* OR */ +{ CPUFUNC(op_80bb_5), 0, 32955 }, /* OR */ +{ CPUFUNC(op_80bc_5), 0, 32956 }, /* OR */ +{ CPUFUNC(op_80c0_5), 0, 32960 }, /* DIVU */ +{ CPUFUNC(op_80d0_5), 0, 32976 }, /* DIVU */ +{ CPUFUNC(op_80d8_5), 0, 32984 }, /* DIVU */ +{ CPUFUNC(op_80e0_5), 0, 32992 }, /* DIVU */ +{ CPUFUNC(op_80e8_5), 0, 33000 }, /* DIVU */ +{ CPUFUNC(op_80f0_5), 0, 33008 }, /* DIVU */ +{ CPUFUNC(op_80f8_5), 0, 33016 }, /* DIVU */ +{ CPUFUNC(op_80f9_5), 0, 33017 }, /* DIVU */ +{ CPUFUNC(op_80fa_5), 0, 33018 }, /* DIVU */ +{ CPUFUNC(op_80fb_5), 0, 33019 }, /* DIVU */ +{ CPUFUNC(op_80fc_5), 0, 33020 }, /* DIVU */ +{ CPUFUNC(op_8100_5), 0, 33024 }, /* SBCD */ +{ CPUFUNC(op_8108_5), 0, 33032 }, /* SBCD */ +{ CPUFUNC(op_8110_5), 0, 33040 }, /* OR */ +{ CPUFUNC(op_8118_5), 0, 33048 }, /* OR */ +{ CPUFUNC(op_8120_5), 0, 33056 }, /* OR */ +{ CPUFUNC(op_8128_5), 0, 33064 }, /* OR */ +{ CPUFUNC(op_8130_5), 0, 33072 }, /* OR */ +{ CPUFUNC(op_8138_5), 0, 33080 }, /* OR */ +{ CPUFUNC(op_8139_5), 0, 33081 }, /* OR */ +{ CPUFUNC(op_8150_5), 0, 33104 }, /* OR */ +{ CPUFUNC(op_8158_5), 0, 33112 }, /* OR */ +{ CPUFUNC(op_8160_5), 0, 33120 }, /* OR */ +{ CPUFUNC(op_8168_5), 0, 33128 }, /* OR */ +{ CPUFUNC(op_8170_5), 0, 33136 }, /* OR */ +{ CPUFUNC(op_8178_5), 0, 33144 }, /* OR */ +{ CPUFUNC(op_8179_5), 0, 33145 }, /* OR */ +{ CPUFUNC(op_8190_5), 0, 33168 }, /* OR */ +{ CPUFUNC(op_8198_5), 0, 33176 }, /* OR */ +{ CPUFUNC(op_81a0_5), 0, 33184 }, /* OR */ +{ CPUFUNC(op_81a8_5), 0, 33192 }, /* OR */ +{ CPUFUNC(op_81b0_5), 0, 33200 }, /* OR */ +{ CPUFUNC(op_81b8_5), 0, 33208 }, /* OR */ +{ CPUFUNC(op_81b9_5), 0, 33209 }, /* OR */ +{ CPUFUNC(op_81c0_5), 0, 33216 }, /* DIVS */ +{ CPUFUNC(op_81d0_5), 0, 33232 }, /* DIVS */ +{ CPUFUNC(op_81d8_5), 0, 33240 }, /* DIVS */ +{ CPUFUNC(op_81e0_5), 0, 33248 }, /* DIVS */ +{ CPUFUNC(op_81e8_5), 0, 33256 }, /* DIVS */ +{ CPUFUNC(op_81f0_5), 0, 33264 }, /* DIVS */ +{ CPUFUNC(op_81f8_5), 0, 33272 }, /* DIVS */ +{ CPUFUNC(op_81f9_5), 0, 33273 }, /* DIVS */ +{ CPUFUNC(op_81fa_5), 0, 33274 }, /* DIVS */ +{ CPUFUNC(op_81fb_5), 0, 33275 }, /* DIVS */ +{ CPUFUNC(op_81fc_5), 0, 33276 }, /* DIVS */ +{ CPUFUNC(op_9000_5), 0, 36864 }, /* SUB */ +{ CPUFUNC(op_9010_5), 0, 36880 }, /* SUB */ +{ CPUFUNC(op_9018_5), 0, 36888 }, /* SUB */ +{ CPUFUNC(op_9020_5), 0, 36896 }, /* SUB */ +{ CPUFUNC(op_9028_5), 0, 36904 }, /* SUB */ +{ CPUFUNC(op_9030_5), 0, 36912 }, /* SUB */ +{ CPUFUNC(op_9038_5), 0, 36920 }, /* SUB */ +{ CPUFUNC(op_9039_5), 0, 36921 }, /* SUB */ +{ CPUFUNC(op_903a_5), 0, 36922 }, /* SUB */ +{ CPUFUNC(op_903b_5), 0, 36923 }, /* SUB */ +{ CPUFUNC(op_903c_5), 0, 36924 }, /* SUB */ +{ CPUFUNC(op_9040_5), 0, 36928 }, /* SUB */ +{ CPUFUNC(op_9048_5), 0, 36936 }, /* SUB */ +{ CPUFUNC(op_9050_5), 0, 36944 }, /* SUB */ +{ CPUFUNC(op_9058_5), 0, 36952 }, /* SUB */ +{ CPUFUNC(op_9060_5), 0, 36960 }, /* SUB */ +{ CPUFUNC(op_9068_5), 0, 36968 }, /* SUB */ +{ CPUFUNC(op_9070_5), 0, 36976 }, /* SUB */ +{ CPUFUNC(op_9078_5), 0, 36984 }, /* SUB */ +{ CPUFUNC(op_9079_5), 0, 36985 }, /* SUB */ +{ CPUFUNC(op_907a_5), 0, 36986 }, /* SUB */ +{ CPUFUNC(op_907b_5), 0, 36987 }, /* SUB */ +{ CPUFUNC(op_907c_5), 0, 36988 }, /* SUB */ +{ CPUFUNC(op_9080_5), 0, 36992 }, /* SUB */ +{ CPUFUNC(op_9088_5), 0, 37000 }, /* SUB */ +{ CPUFUNC(op_9090_5), 0, 37008 }, /* SUB */ +{ CPUFUNC(op_9098_5), 0, 37016 }, /* SUB */ +{ CPUFUNC(op_90a0_5), 0, 37024 }, /* SUB */ +{ CPUFUNC(op_90a8_5), 0, 37032 }, /* SUB */ +{ CPUFUNC(op_90b0_5), 0, 37040 }, /* SUB */ +{ CPUFUNC(op_90b8_5), 0, 37048 }, /* SUB */ +{ CPUFUNC(op_90b9_5), 0, 37049 }, /* SUB */ +{ CPUFUNC(op_90ba_5), 0, 37050 }, /* SUB */ +{ CPUFUNC(op_90bb_5), 0, 37051 }, /* SUB */ +{ CPUFUNC(op_90bc_5), 0, 37052 }, /* SUB */ +{ CPUFUNC(op_90c0_5), 0, 37056 }, /* SUBA */ +{ CPUFUNC(op_90c8_5), 0, 37064 }, /* SUBA */ +{ CPUFUNC(op_90d0_5), 0, 37072 }, /* SUBA */ +{ CPUFUNC(op_90d8_5), 0, 37080 }, /* SUBA */ +{ CPUFUNC(op_90e0_5), 0, 37088 }, /* SUBA */ +{ CPUFUNC(op_90e8_5), 0, 37096 }, /* SUBA */ +{ CPUFUNC(op_90f0_5), 0, 37104 }, /* SUBA */ +{ CPUFUNC(op_90f8_5), 0, 37112 }, /* SUBA */ +{ CPUFUNC(op_90f9_5), 0, 37113 }, /* SUBA */ +{ CPUFUNC(op_90fa_5), 0, 37114 }, /* SUBA */ +{ CPUFUNC(op_90fb_5), 0, 37115 }, /* SUBA */ +{ CPUFUNC(op_90fc_5), 0, 37116 }, /* SUBA */ +{ CPUFUNC(op_9100_5), 0, 37120 }, /* SUBX */ +{ CPUFUNC(op_9108_5), 0, 37128 }, /* SUBX */ +{ CPUFUNC(op_9110_5), 0, 37136 }, /* SUB */ +{ CPUFUNC(op_9118_5), 0, 37144 }, /* SUB */ +{ CPUFUNC(op_9120_5), 0, 37152 }, /* SUB */ +{ CPUFUNC(op_9128_5), 0, 37160 }, /* SUB */ +{ CPUFUNC(op_9130_5), 0, 37168 }, /* SUB */ +{ CPUFUNC(op_9138_5), 0, 37176 }, /* SUB */ +{ CPUFUNC(op_9139_5), 0, 37177 }, /* SUB */ +{ CPUFUNC(op_9140_5), 0, 37184 }, /* SUBX */ +{ CPUFUNC(op_9148_5), 0, 37192 }, /* SUBX */ +{ CPUFUNC(op_9150_5), 0, 37200 }, /* SUB */ +{ CPUFUNC(op_9158_5), 0, 37208 }, /* SUB */ +{ CPUFUNC(op_9160_5), 0, 37216 }, /* SUB */ +{ CPUFUNC(op_9168_5), 0, 37224 }, /* SUB */ +{ CPUFUNC(op_9170_5), 0, 37232 }, /* SUB */ +{ CPUFUNC(op_9178_5), 0, 37240 }, /* SUB */ +{ CPUFUNC(op_9179_5), 0, 37241 }, /* SUB */ +{ CPUFUNC(op_9180_5), 0, 37248 }, /* SUBX */ +{ CPUFUNC(op_9188_5), 0, 37256 }, /* SUBX */ +{ CPUFUNC(op_9190_5), 0, 37264 }, /* SUB */ +{ CPUFUNC(op_9198_5), 0, 37272 }, /* SUB */ +{ CPUFUNC(op_91a0_5), 0, 37280 }, /* SUB */ +{ CPUFUNC(op_91a8_5), 0, 37288 }, /* SUB */ +{ CPUFUNC(op_91b0_5), 0, 37296 }, /* SUB */ +{ CPUFUNC(op_91b8_5), 0, 37304 }, /* SUB */ +{ CPUFUNC(op_91b9_5), 0, 37305 }, /* SUB */ +{ CPUFUNC(op_91c0_5), 0, 37312 }, /* SUBA */ +{ CPUFUNC(op_91c8_5), 0, 37320 }, /* SUBA */ +{ CPUFUNC(op_91d0_5), 0, 37328 }, /* SUBA */ +{ CPUFUNC(op_91d8_5), 0, 37336 }, /* SUBA */ +{ CPUFUNC(op_91e0_5), 0, 37344 }, /* SUBA */ +{ CPUFUNC(op_91e8_5), 0, 37352 }, /* SUBA */ +{ CPUFUNC(op_91f0_5), 0, 37360 }, /* SUBA */ +{ CPUFUNC(op_91f8_5), 0, 37368 }, /* SUBA */ +{ CPUFUNC(op_91f9_5), 0, 37369 }, /* SUBA */ +{ CPUFUNC(op_91fa_5), 0, 37370 }, /* SUBA */ +{ CPUFUNC(op_91fb_5), 0, 37371 }, /* SUBA */ +{ CPUFUNC(op_91fc_5), 0, 37372 }, /* SUBA */ +{ CPUFUNC(op_b000_5), 0, 45056 }, /* CMP */ +{ CPUFUNC(op_b010_5), 0, 45072 }, /* CMP */ +{ CPUFUNC(op_b018_5), 0, 45080 }, /* CMP */ +{ CPUFUNC(op_b020_5), 0, 45088 }, /* CMP */ +{ CPUFUNC(op_b028_5), 0, 45096 }, /* CMP */ +{ CPUFUNC(op_b030_5), 0, 45104 }, /* CMP */ +{ CPUFUNC(op_b038_5), 0, 45112 }, /* CMP */ +{ CPUFUNC(op_b039_5), 0, 45113 }, /* CMP */ +{ CPUFUNC(op_b03a_5), 0, 45114 }, /* CMP */ +{ CPUFUNC(op_b03b_5), 0, 45115 }, /* CMP */ +{ CPUFUNC(op_b03c_5), 0, 45116 }, /* CMP */ +{ CPUFUNC(op_b040_5), 0, 45120 }, /* CMP */ +{ CPUFUNC(op_b048_5), 0, 45128 }, /* CMP */ +{ CPUFUNC(op_b050_5), 0, 45136 }, /* CMP */ +{ CPUFUNC(op_b058_5), 0, 45144 }, /* CMP */ +{ CPUFUNC(op_b060_5), 0, 45152 }, /* CMP */ +{ CPUFUNC(op_b068_5), 0, 45160 }, /* CMP */ +{ CPUFUNC(op_b070_5), 0, 45168 }, /* CMP */ +{ CPUFUNC(op_b078_5), 0, 45176 }, /* CMP */ +{ CPUFUNC(op_b079_5), 0, 45177 }, /* CMP */ +{ CPUFUNC(op_b07a_5), 0, 45178 }, /* CMP */ +{ CPUFUNC(op_b07b_5), 0, 45179 }, /* CMP */ +{ CPUFUNC(op_b07c_5), 0, 45180 }, /* CMP */ +{ CPUFUNC(op_b080_5), 0, 45184 }, /* CMP */ +{ CPUFUNC(op_b088_5), 0, 45192 }, /* CMP */ +{ CPUFUNC(op_b090_5), 0, 45200 }, /* CMP */ +{ CPUFUNC(op_b098_5), 0, 45208 }, /* CMP */ +{ CPUFUNC(op_b0a0_5), 0, 45216 }, /* CMP */ +{ CPUFUNC(op_b0a8_5), 0, 45224 }, /* CMP */ +{ CPUFUNC(op_b0b0_5), 0, 45232 }, /* CMP */ +{ CPUFUNC(op_b0b8_5), 0, 45240 }, /* CMP */ +{ CPUFUNC(op_b0b9_5), 0, 45241 }, /* CMP */ +{ CPUFUNC(op_b0ba_5), 0, 45242 }, /* CMP */ +{ CPUFUNC(op_b0bb_5), 0, 45243 }, /* CMP */ +{ CPUFUNC(op_b0bc_5), 0, 45244 }, /* CMP */ +{ CPUFUNC(op_b0c0_5), 0, 45248 }, /* CMPA */ +{ CPUFUNC(op_b0c8_5), 0, 45256 }, /* CMPA */ +{ CPUFUNC(op_b0d0_5), 0, 45264 }, /* CMPA */ +{ CPUFUNC(op_b0d8_5), 0, 45272 }, /* CMPA */ +{ CPUFUNC(op_b0e0_5), 0, 45280 }, /* CMPA */ +{ CPUFUNC(op_b0e8_5), 0, 45288 }, /* CMPA */ +{ CPUFUNC(op_b0f0_5), 0, 45296 }, /* CMPA */ +{ CPUFUNC(op_b0f8_5), 0, 45304 }, /* CMPA */ +{ CPUFUNC(op_b0f9_5), 0, 45305 }, /* CMPA */ +{ CPUFUNC(op_b0fa_5), 0, 45306 }, /* CMPA */ +{ CPUFUNC(op_b0fb_5), 0, 45307 }, /* CMPA */ +{ CPUFUNC(op_b0fc_5), 0, 45308 }, /* CMPA */ +{ CPUFUNC(op_b100_5), 0, 45312 }, /* EOR */ +{ CPUFUNC(op_b108_5), 0, 45320 }, /* CMPM */ +{ CPUFUNC(op_b110_5), 0, 45328 }, /* EOR */ +{ CPUFUNC(op_b118_5), 0, 45336 }, /* EOR */ +{ CPUFUNC(op_b120_5), 0, 45344 }, /* EOR */ +{ CPUFUNC(op_b128_5), 0, 45352 }, /* EOR */ +{ CPUFUNC(op_b130_5), 0, 45360 }, /* EOR */ +{ CPUFUNC(op_b138_5), 0, 45368 }, /* EOR */ +{ CPUFUNC(op_b139_5), 0, 45369 }, /* EOR */ +{ CPUFUNC(op_b140_5), 0, 45376 }, /* EOR */ +{ CPUFUNC(op_b148_5), 0, 45384 }, /* CMPM */ +{ CPUFUNC(op_b150_5), 0, 45392 }, /* EOR */ +{ CPUFUNC(op_b158_5), 0, 45400 }, /* EOR */ +{ CPUFUNC(op_b160_5), 0, 45408 }, /* EOR */ +{ CPUFUNC(op_b168_5), 0, 45416 }, /* EOR */ +{ CPUFUNC(op_b170_5), 0, 45424 }, /* EOR */ +{ CPUFUNC(op_b178_5), 0, 45432 }, /* EOR */ +{ CPUFUNC(op_b179_5), 0, 45433 }, /* EOR */ +{ CPUFUNC(op_b180_5), 0, 45440 }, /* EOR */ +{ CPUFUNC(op_b188_5), 0, 45448 }, /* CMPM */ +{ CPUFUNC(op_b190_5), 0, 45456 }, /* EOR */ +{ CPUFUNC(op_b198_5), 0, 45464 }, /* EOR */ +{ CPUFUNC(op_b1a0_5), 0, 45472 }, /* EOR */ +{ CPUFUNC(op_b1a8_5), 0, 45480 }, /* EOR */ +{ CPUFUNC(op_b1b0_5), 0, 45488 }, /* EOR */ +{ CPUFUNC(op_b1b8_5), 0, 45496 }, /* EOR */ +{ CPUFUNC(op_b1b9_5), 0, 45497 }, /* EOR */ +{ CPUFUNC(op_b1c0_5), 0, 45504 }, /* CMPA */ +{ CPUFUNC(op_b1c8_5), 0, 45512 }, /* CMPA */ +{ CPUFUNC(op_b1d0_5), 0, 45520 }, /* CMPA */ +{ CPUFUNC(op_b1d8_5), 0, 45528 }, /* CMPA */ +{ CPUFUNC(op_b1e0_5), 0, 45536 }, /* CMPA */ +{ CPUFUNC(op_b1e8_5), 0, 45544 }, /* CMPA */ +{ CPUFUNC(op_b1f0_5), 0, 45552 }, /* CMPA */ +{ CPUFUNC(op_b1f8_5), 0, 45560 }, /* CMPA */ +{ CPUFUNC(op_b1f9_5), 0, 45561 }, /* CMPA */ +{ CPUFUNC(op_b1fa_5), 0, 45562 }, /* CMPA */ +{ CPUFUNC(op_b1fb_5), 0, 45563 }, /* CMPA */ +{ CPUFUNC(op_b1fc_5), 0, 45564 }, /* CMPA */ +{ CPUFUNC(op_c000_5), 0, 49152 }, /* AND */ +{ CPUFUNC(op_c010_5), 0, 49168 }, /* AND */ +{ CPUFUNC(op_c018_5), 0, 49176 }, /* AND */ +{ CPUFUNC(op_c020_5), 0, 49184 }, /* AND */ +{ CPUFUNC(op_c028_5), 0, 49192 }, /* AND */ +{ CPUFUNC(op_c030_5), 0, 49200 }, /* AND */ +{ CPUFUNC(op_c038_5), 0, 49208 }, /* AND */ +{ CPUFUNC(op_c039_5), 0, 49209 }, /* AND */ +{ CPUFUNC(op_c03a_5), 0, 49210 }, /* AND */ +{ CPUFUNC(op_c03b_5), 0, 49211 }, /* AND */ +{ CPUFUNC(op_c03c_5), 0, 49212 }, /* AND */ +{ CPUFUNC(op_c040_5), 0, 49216 }, /* AND */ +{ CPUFUNC(op_c050_5), 0, 49232 }, /* AND */ +{ CPUFUNC(op_c058_5), 0, 49240 }, /* AND */ +{ CPUFUNC(op_c060_5), 0, 49248 }, /* AND */ +{ CPUFUNC(op_c068_5), 0, 49256 }, /* AND */ +{ CPUFUNC(op_c070_5), 0, 49264 }, /* AND */ +{ CPUFUNC(op_c078_5), 0, 49272 }, /* AND */ +{ CPUFUNC(op_c079_5), 0, 49273 }, /* AND */ +{ CPUFUNC(op_c07a_5), 0, 49274 }, /* AND */ +{ CPUFUNC(op_c07b_5), 0, 49275 }, /* AND */ +{ CPUFUNC(op_c07c_5), 0, 49276 }, /* AND */ +{ CPUFUNC(op_c080_5), 0, 49280 }, /* AND */ +{ CPUFUNC(op_c090_5), 0, 49296 }, /* AND */ +{ CPUFUNC(op_c098_5), 0, 49304 }, /* AND */ +{ CPUFUNC(op_c0a0_5), 0, 49312 }, /* AND */ +{ CPUFUNC(op_c0a8_5), 0, 49320 }, /* AND */ +{ CPUFUNC(op_c0b0_5), 0, 49328 }, /* AND */ +{ CPUFUNC(op_c0b8_5), 0, 49336 }, /* AND */ +{ CPUFUNC(op_c0b9_5), 0, 49337 }, /* AND */ +{ CPUFUNC(op_c0ba_5), 0, 49338 }, /* AND */ +{ CPUFUNC(op_c0bb_5), 0, 49339 }, /* AND */ +{ CPUFUNC(op_c0bc_5), 0, 49340 }, /* AND */ +{ CPUFUNC(op_c0c0_5), 0, 49344 }, /* MULU */ +{ CPUFUNC(op_c0d0_5), 0, 49360 }, /* MULU */ +{ CPUFUNC(op_c0d8_5), 0, 49368 }, /* MULU */ +{ CPUFUNC(op_c0e0_5), 0, 49376 }, /* MULU */ +{ CPUFUNC(op_c0e8_5), 0, 49384 }, /* MULU */ +{ CPUFUNC(op_c0f0_5), 0, 49392 }, /* MULU */ +{ CPUFUNC(op_c0f8_5), 0, 49400 }, /* MULU */ +{ CPUFUNC(op_c0f9_5), 0, 49401 }, /* MULU */ +{ CPUFUNC(op_c0fa_5), 0, 49402 }, /* MULU */ +{ CPUFUNC(op_c0fb_5), 0, 49403 }, /* MULU */ +{ CPUFUNC(op_c0fc_5), 0, 49404 }, /* MULU */ +{ CPUFUNC(op_c100_5), 0, 49408 }, /* ABCD */ +{ CPUFUNC(op_c108_5), 0, 49416 }, /* ABCD */ +{ CPUFUNC(op_c110_5), 0, 49424 }, /* AND */ +{ CPUFUNC(op_c118_5), 0, 49432 }, /* AND */ +{ CPUFUNC(op_c120_5), 0, 49440 }, /* AND */ +{ CPUFUNC(op_c128_5), 0, 49448 }, /* AND */ +{ CPUFUNC(op_c130_5), 0, 49456 }, /* AND */ +{ CPUFUNC(op_c138_5), 0, 49464 }, /* AND */ +{ CPUFUNC(op_c139_5), 0, 49465 }, /* AND */ +{ CPUFUNC(op_c140_5), 0, 49472 }, /* EXG */ +{ CPUFUNC(op_c148_5), 0, 49480 }, /* EXG */ +{ CPUFUNC(op_c150_5), 0, 49488 }, /* AND */ +{ CPUFUNC(op_c158_5), 0, 49496 }, /* AND */ +{ CPUFUNC(op_c160_5), 0, 49504 }, /* AND */ +{ CPUFUNC(op_c168_5), 0, 49512 }, /* AND */ +{ CPUFUNC(op_c170_5), 0, 49520 }, /* AND */ +{ CPUFUNC(op_c178_5), 0, 49528 }, /* AND */ +{ CPUFUNC(op_c179_5), 0, 49529 }, /* AND */ +{ CPUFUNC(op_c188_5), 0, 49544 }, /* EXG */ +{ CPUFUNC(op_c190_5), 0, 49552 }, /* AND */ +{ CPUFUNC(op_c198_5), 0, 49560 }, /* AND */ +{ CPUFUNC(op_c1a0_5), 0, 49568 }, /* AND */ +{ CPUFUNC(op_c1a8_5), 0, 49576 }, /* AND */ +{ CPUFUNC(op_c1b0_5), 0, 49584 }, /* AND */ +{ CPUFUNC(op_c1b8_5), 0, 49592 }, /* AND */ +{ CPUFUNC(op_c1b9_5), 0, 49593 }, /* AND */ +{ CPUFUNC(op_c1c0_5), 0, 49600 }, /* MULS */ +{ CPUFUNC(op_c1d0_5), 0, 49616 }, /* MULS */ +{ CPUFUNC(op_c1d8_5), 0, 49624 }, /* MULS */ +{ CPUFUNC(op_c1e0_5), 0, 49632 }, /* MULS */ +{ CPUFUNC(op_c1e8_5), 0, 49640 }, /* MULS */ +{ CPUFUNC(op_c1f0_5), 0, 49648 }, /* MULS */ +{ CPUFUNC(op_c1f8_5), 0, 49656 }, /* MULS */ +{ CPUFUNC(op_c1f9_5), 0, 49657 }, /* MULS */ +{ CPUFUNC(op_c1fa_5), 0, 49658 }, /* MULS */ +{ CPUFUNC(op_c1fb_5), 0, 49659 }, /* MULS */ +{ CPUFUNC(op_c1fc_5), 0, 49660 }, /* MULS */ +{ CPUFUNC(op_d000_5), 0, 53248 }, /* ADD */ +{ CPUFUNC(op_d010_5), 0, 53264 }, /* ADD */ +{ CPUFUNC(op_d018_5), 0, 53272 }, /* ADD */ +{ CPUFUNC(op_d020_5), 0, 53280 }, /* ADD */ +{ CPUFUNC(op_d028_5), 0, 53288 }, /* ADD */ +{ CPUFUNC(op_d030_5), 0, 53296 }, /* ADD */ +{ CPUFUNC(op_d038_5), 0, 53304 }, /* ADD */ +{ CPUFUNC(op_d039_5), 0, 53305 }, /* ADD */ +{ CPUFUNC(op_d03a_5), 0, 53306 }, /* ADD */ +{ CPUFUNC(op_d03b_5), 0, 53307 }, /* ADD */ +{ CPUFUNC(op_d03c_5), 0, 53308 }, /* ADD */ +{ CPUFUNC(op_d040_5), 0, 53312 }, /* ADD */ +{ CPUFUNC(op_d048_5), 0, 53320 }, /* ADD */ +{ CPUFUNC(op_d050_5), 0, 53328 }, /* ADD */ +{ CPUFUNC(op_d058_5), 0, 53336 }, /* ADD */ +{ CPUFUNC(op_d060_5), 0, 53344 }, /* ADD */ +{ CPUFUNC(op_d068_5), 0, 53352 }, /* ADD */ +{ CPUFUNC(op_d070_5), 0, 53360 }, /* ADD */ +{ CPUFUNC(op_d078_5), 0, 53368 }, /* ADD */ +{ CPUFUNC(op_d079_5), 0, 53369 }, /* ADD */ +{ CPUFUNC(op_d07a_5), 0, 53370 }, /* ADD */ +{ CPUFUNC(op_d07b_5), 0, 53371 }, /* ADD */ +{ CPUFUNC(op_d07c_5), 0, 53372 }, /* ADD */ +{ CPUFUNC(op_d080_5), 0, 53376 }, /* ADD */ +{ CPUFUNC(op_d088_5), 0, 53384 }, /* ADD */ +{ CPUFUNC(op_d090_5), 0, 53392 }, /* ADD */ +{ CPUFUNC(op_d098_5), 0, 53400 }, /* ADD */ +{ CPUFUNC(op_d0a0_5), 0, 53408 }, /* ADD */ +{ CPUFUNC(op_d0a8_5), 0, 53416 }, /* ADD */ +{ CPUFUNC(op_d0b0_5), 0, 53424 }, /* ADD */ +{ CPUFUNC(op_d0b8_5), 0, 53432 }, /* ADD */ +{ CPUFUNC(op_d0b9_5), 0, 53433 }, /* ADD */ +{ CPUFUNC(op_d0ba_5), 0, 53434 }, /* ADD */ +{ CPUFUNC(op_d0bb_5), 0, 53435 }, /* ADD */ +{ CPUFUNC(op_d0bc_5), 0, 53436 }, /* ADD */ +{ CPUFUNC(op_d0c0_5), 0, 53440 }, /* ADDA */ +{ CPUFUNC(op_d0c8_5), 0, 53448 }, /* ADDA */ +{ CPUFUNC(op_d0d0_5), 0, 53456 }, /* ADDA */ +{ CPUFUNC(op_d0d8_5), 0, 53464 }, /* ADDA */ +{ CPUFUNC(op_d0e0_5), 0, 53472 }, /* ADDA */ +{ CPUFUNC(op_d0e8_5), 0, 53480 }, /* ADDA */ +{ CPUFUNC(op_d0f0_5), 0, 53488 }, /* ADDA */ +{ CPUFUNC(op_d0f8_5), 0, 53496 }, /* ADDA */ +{ CPUFUNC(op_d0f9_5), 0, 53497 }, /* ADDA */ +{ CPUFUNC(op_d0fa_5), 0, 53498 }, /* ADDA */ +{ CPUFUNC(op_d0fb_5), 0, 53499 }, /* ADDA */ +{ CPUFUNC(op_d0fc_5), 0, 53500 }, /* ADDA */ +{ CPUFUNC(op_d100_5), 0, 53504 }, /* ADDX */ +{ CPUFUNC(op_d108_5), 0, 53512 }, /* ADDX */ +{ CPUFUNC(op_d110_5), 0, 53520 }, /* ADD */ +{ CPUFUNC(op_d118_5), 0, 53528 }, /* ADD */ +{ CPUFUNC(op_d120_5), 0, 53536 }, /* ADD */ +{ CPUFUNC(op_d128_5), 0, 53544 }, /* ADD */ +{ CPUFUNC(op_d130_5), 0, 53552 }, /* ADD */ +{ CPUFUNC(op_d138_5), 0, 53560 }, /* ADD */ +{ CPUFUNC(op_d139_5), 0, 53561 }, /* ADD */ +{ CPUFUNC(op_d140_5), 0, 53568 }, /* ADDX */ +{ CPUFUNC(op_d148_5), 0, 53576 }, /* ADDX */ +{ CPUFUNC(op_d150_5), 0, 53584 }, /* ADD */ +{ CPUFUNC(op_d158_5), 0, 53592 }, /* ADD */ +{ CPUFUNC(op_d160_5), 0, 53600 }, /* ADD */ +{ CPUFUNC(op_d168_5), 0, 53608 }, /* ADD */ +{ CPUFUNC(op_d170_5), 0, 53616 }, /* ADD */ +{ CPUFUNC(op_d178_5), 0, 53624 }, /* ADD */ +{ CPUFUNC(op_d179_5), 0, 53625 }, /* ADD */ +{ CPUFUNC(op_d180_5), 0, 53632 }, /* ADDX */ +{ CPUFUNC(op_d188_5), 0, 53640 }, /* ADDX */ +{ CPUFUNC(op_d190_5), 0, 53648 }, /* ADD */ +{ CPUFUNC(op_d198_5), 0, 53656 }, /* ADD */ +{ CPUFUNC(op_d1a0_5), 0, 53664 }, /* ADD */ +{ CPUFUNC(op_d1a8_5), 0, 53672 }, /* ADD */ +{ CPUFUNC(op_d1b0_5), 0, 53680 }, /* ADD */ +{ CPUFUNC(op_d1b8_5), 0, 53688 }, /* ADD */ +{ CPUFUNC(op_d1b9_5), 0, 53689 }, /* ADD */ +{ CPUFUNC(op_d1c0_5), 0, 53696 }, /* ADDA */ +{ CPUFUNC(op_d1c8_5), 0, 53704 }, /* ADDA */ +{ CPUFUNC(op_d1d0_5), 0, 53712 }, /* ADDA */ +{ CPUFUNC(op_d1d8_5), 0, 53720 }, /* ADDA */ +{ CPUFUNC(op_d1e0_5), 0, 53728 }, /* ADDA */ +{ CPUFUNC(op_d1e8_5), 0, 53736 }, /* ADDA */ +{ CPUFUNC(op_d1f0_5), 0, 53744 }, /* ADDA */ +{ CPUFUNC(op_d1f8_5), 0, 53752 }, /* ADDA */ +{ CPUFUNC(op_d1f9_5), 0, 53753 }, /* ADDA */ +{ CPUFUNC(op_d1fa_5), 0, 53754 }, /* ADDA */ +{ CPUFUNC(op_d1fb_5), 0, 53755 }, /* ADDA */ +{ CPUFUNC(op_d1fc_5), 0, 53756 }, /* ADDA */ +{ CPUFUNC(op_e000_5), 0, 57344 }, /* ASR */ +{ CPUFUNC(op_e008_5), 0, 57352 }, /* LSR */ +{ CPUFUNC(op_e010_5), 0, 57360 }, /* ROXR */ +{ CPUFUNC(op_e018_5), 0, 57368 }, /* ROR */ +{ CPUFUNC(op_e020_5), 0, 57376 }, /* ASR */ +{ CPUFUNC(op_e028_5), 0, 57384 }, /* LSR */ +{ CPUFUNC(op_e030_5), 0, 57392 }, /* ROXR */ +{ CPUFUNC(op_e038_5), 0, 57400 }, /* ROR */ +{ CPUFUNC(op_e040_5), 0, 57408 }, /* ASR */ +{ CPUFUNC(op_e048_5), 0, 57416 }, /* LSR */ +{ CPUFUNC(op_e050_5), 0, 57424 }, /* ROXR */ +{ CPUFUNC(op_e058_5), 0, 57432 }, /* ROR */ +{ CPUFUNC(op_e060_5), 0, 57440 }, /* ASR */ +{ CPUFUNC(op_e068_5), 0, 57448 }, /* LSR */ +{ CPUFUNC(op_e070_5), 0, 57456 }, /* ROXR */ +{ CPUFUNC(op_e078_5), 0, 57464 }, /* ROR */ +{ CPUFUNC(op_e080_5), 0, 57472 }, /* ASR */ +{ CPUFUNC(op_e088_5), 0, 57480 }, /* LSR */ +{ CPUFUNC(op_e090_5), 0, 57488 }, /* ROXR */ +{ CPUFUNC(op_e098_5), 0, 57496 }, /* ROR */ +{ CPUFUNC(op_e0a0_5), 0, 57504 }, /* ASR */ +{ CPUFUNC(op_e0a8_5), 0, 57512 }, /* LSR */ +{ CPUFUNC(op_e0b0_5), 0, 57520 }, /* ROXR */ +{ CPUFUNC(op_e0b8_5), 0, 57528 }, /* ROR */ +{ CPUFUNC(op_e0d0_5), 0, 57552 }, /* ASRW */ +{ CPUFUNC(op_e0d8_5), 0, 57560 }, /* ASRW */ +{ CPUFUNC(op_e0e0_5), 0, 57568 }, /* ASRW */ +{ CPUFUNC(op_e0e8_5), 0, 57576 }, /* ASRW */ +{ CPUFUNC(op_e0f0_5), 0, 57584 }, /* ASRW */ +{ CPUFUNC(op_e0f8_5), 0, 57592 }, /* ASRW */ +{ CPUFUNC(op_e0f9_5), 0, 57593 }, /* ASRW */ +{ CPUFUNC(op_e100_5), 0, 57600 }, /* ASL */ +{ CPUFUNC(op_e108_5), 0, 57608 }, /* LSL */ +{ CPUFUNC(op_e110_5), 0, 57616 }, /* ROXL */ +{ CPUFUNC(op_e118_5), 0, 57624 }, /* ROL */ +{ CPUFUNC(op_e120_5), 0, 57632 }, /* ASL */ +{ CPUFUNC(op_e128_5), 0, 57640 }, /* LSL */ +{ CPUFUNC(op_e130_5), 0, 57648 }, /* ROXL */ +{ CPUFUNC(op_e138_5), 0, 57656 }, /* ROL */ +{ CPUFUNC(op_e140_5), 0, 57664 }, /* ASL */ +{ CPUFUNC(op_e148_5), 0, 57672 }, /* LSL */ +{ CPUFUNC(op_e150_5), 0, 57680 }, /* ROXL */ +{ CPUFUNC(op_e158_5), 0, 57688 }, /* ROL */ +{ CPUFUNC(op_e160_5), 0, 57696 }, /* ASL */ +{ CPUFUNC(op_e168_5), 0, 57704 }, /* LSL */ +{ CPUFUNC(op_e170_5), 0, 57712 }, /* ROXL */ +{ CPUFUNC(op_e178_5), 0, 57720 }, /* ROL */ +{ CPUFUNC(op_e180_5), 0, 57728 }, /* ASL */ +{ CPUFUNC(op_e188_5), 0, 57736 }, /* LSL */ +{ CPUFUNC(op_e190_5), 0, 57744 }, /* ROXL */ +{ CPUFUNC(op_e198_5), 0, 57752 }, /* ROL */ +{ CPUFUNC(op_e1a0_5), 0, 57760 }, /* ASL */ +{ CPUFUNC(op_e1a8_5), 0, 57768 }, /* LSL */ +{ CPUFUNC(op_e1b0_5), 0, 57776 }, /* ROXL */ +{ CPUFUNC(op_e1b8_5), 0, 57784 }, /* ROL */ +{ CPUFUNC(op_e1d0_5), 0, 57808 }, /* ASLW */ +{ CPUFUNC(op_e1d8_5), 0, 57816 }, /* ASLW */ +{ CPUFUNC(op_e1e0_5), 0, 57824 }, /* ASLW */ +{ CPUFUNC(op_e1e8_5), 0, 57832 }, /* ASLW */ +{ CPUFUNC(op_e1f0_5), 0, 57840 }, /* ASLW */ +{ CPUFUNC(op_e1f8_5), 0, 57848 }, /* ASLW */ +{ CPUFUNC(op_e1f9_5), 0, 57849 }, /* ASLW */ +{ CPUFUNC(op_e2d0_5), 0, 58064 }, /* LSRW */ +{ CPUFUNC(op_e2d8_5), 0, 58072 }, /* LSRW */ +{ CPUFUNC(op_e2e0_5), 0, 58080 }, /* LSRW */ +{ CPUFUNC(op_e2e8_5), 0, 58088 }, /* LSRW */ +{ CPUFUNC(op_e2f0_5), 0, 58096 }, /* LSRW */ +{ CPUFUNC(op_e2f8_5), 0, 58104 }, /* LSRW */ +{ CPUFUNC(op_e2f9_5), 0, 58105 }, /* LSRW */ +{ CPUFUNC(op_e3d0_5), 0, 58320 }, /* LSLW */ +{ CPUFUNC(op_e3d8_5), 0, 58328 }, /* LSLW */ +{ CPUFUNC(op_e3e0_5), 0, 58336 }, /* LSLW */ +{ CPUFUNC(op_e3e8_5), 0, 58344 }, /* LSLW */ +{ CPUFUNC(op_e3f0_5), 0, 58352 }, /* LSLW */ +{ CPUFUNC(op_e3f8_5), 0, 58360 }, /* LSLW */ +{ CPUFUNC(op_e3f9_5), 0, 58361 }, /* LSLW */ +{ CPUFUNC(op_e4d0_5), 0, 58576 }, /* ROXRW */ +{ CPUFUNC(op_e4d8_5), 0, 58584 }, /* ROXRW */ +{ CPUFUNC(op_e4e0_5), 0, 58592 }, /* ROXRW */ +{ CPUFUNC(op_e4e8_5), 0, 58600 }, /* ROXRW */ +{ CPUFUNC(op_e4f0_5), 0, 58608 }, /* ROXRW */ +{ CPUFUNC(op_e4f8_5), 0, 58616 }, /* ROXRW */ +{ CPUFUNC(op_e4f9_5), 0, 58617 }, /* ROXRW */ +{ CPUFUNC(op_e5d0_5), 0, 58832 }, /* ROXLW */ +{ CPUFUNC(op_e5d8_5), 0, 58840 }, /* ROXLW */ +{ CPUFUNC(op_e5e0_5), 0, 58848 }, /* ROXLW */ +{ CPUFUNC(op_e5e8_5), 0, 58856 }, /* ROXLW */ +{ CPUFUNC(op_e5f0_5), 0, 58864 }, /* ROXLW */ +{ CPUFUNC(op_e5f8_5), 0, 58872 }, /* ROXLW */ +{ CPUFUNC(op_e5f9_5), 0, 58873 }, /* ROXLW */ +{ CPUFUNC(op_e6d0_5), 0, 59088 }, /* RORW */ +{ CPUFUNC(op_e6d8_5), 0, 59096 }, /* RORW */ +{ CPUFUNC(op_e6e0_5), 0, 59104 }, /* RORW */ +{ CPUFUNC(op_e6e8_5), 0, 59112 }, /* RORW */ +{ CPUFUNC(op_e6f0_5), 0, 59120 }, /* RORW */ +{ CPUFUNC(op_e6f8_5), 0, 59128 }, /* RORW */ +{ CPUFUNC(op_e6f9_5), 0, 59129 }, /* RORW */ +{ CPUFUNC(op_e7d0_5), 0, 59344 }, /* ROLW */ +{ CPUFUNC(op_e7d8_5), 0, 59352 }, /* ROLW */ +{ CPUFUNC(op_e7e0_5), 0, 59360 }, /* ROLW */ +{ CPUFUNC(op_e7e8_5), 0, 59368 }, /* ROLW */ +{ CPUFUNC(op_e7f0_5), 0, 59376 }, /* ROLW */ +{ CPUFUNC(op_e7f8_5), 0, 59384 }, /* ROLW */ +{ CPUFUNC(op_e7f9_5), 0, 59385 }, /* ROLW */ +{ 0, 0, 0 }}; diff --git a/waterbox/virtualjaguar/src/m68000/cputbl.h b/waterbox/virtualjaguar/src/m68000/cputbl.h new file mode 100644 index 0000000000..e5be860448 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/cputbl.h @@ -0,0 +1,6320 @@ +extern cpuop_func op_0_4_nf; +extern cpuop_func op_0_4_ff; +extern cpuop_func op_10_4_nf; +extern cpuop_func op_10_4_ff; +extern cpuop_func op_18_4_nf; +extern cpuop_func op_18_4_ff; +extern cpuop_func op_20_4_nf; +extern cpuop_func op_20_4_ff; +extern cpuop_func op_28_4_nf; +extern cpuop_func op_28_4_ff; +extern cpuop_func op_30_4_nf; +extern cpuop_func op_30_4_ff; +extern cpuop_func op_38_4_nf; +extern cpuop_func op_38_4_ff; +extern cpuop_func op_39_4_nf; +extern cpuop_func op_39_4_ff; +extern cpuop_func op_3c_4_nf; +extern cpuop_func op_3c_4_ff; +extern cpuop_func op_40_4_nf; +extern cpuop_func op_40_4_ff; +extern cpuop_func op_50_4_nf; +extern cpuop_func op_50_4_ff; +extern cpuop_func op_58_4_nf; +extern cpuop_func op_58_4_ff; +extern cpuop_func op_60_4_nf; +extern cpuop_func op_60_4_ff; +extern cpuop_func op_68_4_nf; +extern cpuop_func op_68_4_ff; +extern cpuop_func op_70_4_nf; +extern cpuop_func op_70_4_ff; +extern cpuop_func op_78_4_nf; +extern cpuop_func op_78_4_ff; +extern cpuop_func op_79_4_nf; +extern cpuop_func op_79_4_ff; +extern cpuop_func op_7c_4_nf; +extern cpuop_func op_7c_4_ff; +extern cpuop_func op_80_4_nf; +extern cpuop_func op_80_4_ff; +extern cpuop_func op_90_4_nf; +extern cpuop_func op_90_4_ff; +extern cpuop_func op_98_4_nf; +extern cpuop_func op_98_4_ff; +extern cpuop_func op_a0_4_nf; +extern cpuop_func op_a0_4_ff; +extern cpuop_func op_a8_4_nf; +extern cpuop_func op_a8_4_ff; +extern cpuop_func op_b0_4_nf; +extern cpuop_func op_b0_4_ff; +extern cpuop_func op_b8_4_nf; +extern cpuop_func op_b8_4_ff; +extern cpuop_func op_b9_4_nf; +extern cpuop_func op_b9_4_ff; +extern cpuop_func op_100_4_nf; +extern cpuop_func op_100_4_ff; +extern cpuop_func op_108_4_nf; +extern cpuop_func op_108_4_ff; +extern cpuop_func op_110_4_nf; +extern cpuop_func op_110_4_ff; +extern cpuop_func op_118_4_nf; +extern cpuop_func op_118_4_ff; +extern cpuop_func op_120_4_nf; +extern cpuop_func op_120_4_ff; +extern cpuop_func op_128_4_nf; +extern cpuop_func op_128_4_ff; +extern cpuop_func op_130_4_nf; +extern cpuop_func op_130_4_ff; +extern cpuop_func op_138_4_nf; +extern cpuop_func op_138_4_ff; +extern cpuop_func op_139_4_nf; +extern cpuop_func op_139_4_ff; +extern cpuop_func op_13a_4_nf; +extern cpuop_func op_13a_4_ff; +extern cpuop_func op_13b_4_nf; +extern cpuop_func op_13b_4_ff; +extern cpuop_func op_13c_4_nf; +extern cpuop_func op_13c_4_ff; +extern cpuop_func op_140_4_nf; +extern cpuop_func op_140_4_ff; +extern cpuop_func op_148_4_nf; +extern cpuop_func op_148_4_ff; +extern cpuop_func op_150_4_nf; +extern cpuop_func op_150_4_ff; +extern cpuop_func op_158_4_nf; +extern cpuop_func op_158_4_ff; +extern cpuop_func op_160_4_nf; +extern cpuop_func op_160_4_ff; +extern cpuop_func op_168_4_nf; +extern cpuop_func op_168_4_ff; +extern cpuop_func op_170_4_nf; +extern cpuop_func op_170_4_ff; +extern cpuop_func op_178_4_nf; +extern cpuop_func op_178_4_ff; +extern cpuop_func op_179_4_nf; +extern cpuop_func op_179_4_ff; +extern cpuop_func op_17a_4_nf; +extern cpuop_func op_17a_4_ff; +extern cpuop_func op_17b_4_nf; +extern cpuop_func op_17b_4_ff; +extern cpuop_func op_180_4_nf; +extern cpuop_func op_180_4_ff; +extern cpuop_func op_188_4_nf; +extern cpuop_func op_188_4_ff; +extern cpuop_func op_190_4_nf; +extern cpuop_func op_190_4_ff; +extern cpuop_func op_198_4_nf; +extern cpuop_func op_198_4_ff; +extern cpuop_func op_1a0_4_nf; +extern cpuop_func op_1a0_4_ff; +extern cpuop_func op_1a8_4_nf; +extern cpuop_func op_1a8_4_ff; +extern cpuop_func op_1b0_4_nf; +extern cpuop_func op_1b0_4_ff; +extern cpuop_func op_1b8_4_nf; +extern cpuop_func op_1b8_4_ff; +extern cpuop_func op_1b9_4_nf; +extern cpuop_func op_1b9_4_ff; +extern cpuop_func op_1ba_4_nf; +extern cpuop_func op_1ba_4_ff; +extern cpuop_func op_1bb_4_nf; +extern cpuop_func op_1bb_4_ff; +extern cpuop_func op_1c0_4_nf; +extern cpuop_func op_1c0_4_ff; +extern cpuop_func op_1c8_4_nf; +extern cpuop_func op_1c8_4_ff; +extern cpuop_func op_1d0_4_nf; +extern cpuop_func op_1d0_4_ff; +extern cpuop_func op_1d8_4_nf; +extern cpuop_func op_1d8_4_ff; +extern cpuop_func op_1e0_4_nf; +extern cpuop_func op_1e0_4_ff; +extern cpuop_func op_1e8_4_nf; +extern cpuop_func op_1e8_4_ff; +extern cpuop_func op_1f0_4_nf; +extern cpuop_func op_1f0_4_ff; +extern cpuop_func op_1f8_4_nf; +extern cpuop_func op_1f8_4_ff; +extern cpuop_func op_1f9_4_nf; +extern cpuop_func op_1f9_4_ff; +extern cpuop_func op_1fa_4_nf; +extern cpuop_func op_1fa_4_ff; +extern cpuop_func op_1fb_4_nf; +extern cpuop_func op_1fb_4_ff; +extern cpuop_func op_200_4_nf; +extern cpuop_func op_200_4_ff; +extern cpuop_func op_210_4_nf; +extern cpuop_func op_210_4_ff; +extern cpuop_func op_218_4_nf; +extern cpuop_func op_218_4_ff; +extern cpuop_func op_220_4_nf; +extern cpuop_func op_220_4_ff; +extern cpuop_func op_228_4_nf; +extern cpuop_func op_228_4_ff; +extern cpuop_func op_230_4_nf; +extern cpuop_func op_230_4_ff; +extern cpuop_func op_238_4_nf; +extern cpuop_func op_238_4_ff; +extern cpuop_func op_239_4_nf; +extern cpuop_func op_239_4_ff; +extern cpuop_func op_23c_4_nf; +extern cpuop_func op_23c_4_ff; +extern cpuop_func op_240_4_nf; +extern cpuop_func op_240_4_ff; +extern cpuop_func op_250_4_nf; +extern cpuop_func op_250_4_ff; +extern cpuop_func op_258_4_nf; +extern cpuop_func op_258_4_ff; +extern cpuop_func op_260_4_nf; +extern cpuop_func op_260_4_ff; +extern cpuop_func op_268_4_nf; +extern cpuop_func op_268_4_ff; +extern cpuop_func op_270_4_nf; +extern cpuop_func op_270_4_ff; +extern cpuop_func op_278_4_nf; +extern cpuop_func op_278_4_ff; +extern cpuop_func op_279_4_nf; +extern cpuop_func op_279_4_ff; +extern cpuop_func op_27c_4_nf; +extern cpuop_func op_27c_4_ff; +extern cpuop_func op_280_4_nf; +extern cpuop_func op_280_4_ff; +extern cpuop_func op_290_4_nf; +extern cpuop_func op_290_4_ff; +extern cpuop_func op_298_4_nf; +extern cpuop_func op_298_4_ff; +extern cpuop_func op_2a0_4_nf; +extern cpuop_func op_2a0_4_ff; +extern cpuop_func op_2a8_4_nf; +extern cpuop_func op_2a8_4_ff; +extern cpuop_func op_2b0_4_nf; +extern cpuop_func op_2b0_4_ff; +extern cpuop_func op_2b8_4_nf; +extern cpuop_func op_2b8_4_ff; +extern cpuop_func op_2b9_4_nf; +extern cpuop_func op_2b9_4_ff; +extern cpuop_func op_400_4_nf; +extern cpuop_func op_400_4_ff; +extern cpuop_func op_410_4_nf; +extern cpuop_func op_410_4_ff; +extern cpuop_func op_418_4_nf; +extern cpuop_func op_418_4_ff; +extern cpuop_func op_420_4_nf; +extern cpuop_func op_420_4_ff; +extern cpuop_func op_428_4_nf; +extern cpuop_func op_428_4_ff; +extern cpuop_func op_430_4_nf; +extern cpuop_func op_430_4_ff; +extern cpuop_func op_438_4_nf; +extern cpuop_func op_438_4_ff; +extern cpuop_func op_439_4_nf; +extern cpuop_func op_439_4_ff; +extern cpuop_func op_440_4_nf; +extern cpuop_func op_440_4_ff; +extern cpuop_func op_450_4_nf; +extern cpuop_func op_450_4_ff; +extern cpuop_func op_458_4_nf; +extern cpuop_func op_458_4_ff; +extern cpuop_func op_460_4_nf; +extern cpuop_func op_460_4_ff; +extern cpuop_func op_468_4_nf; +extern cpuop_func op_468_4_ff; +extern cpuop_func op_470_4_nf; +extern cpuop_func op_470_4_ff; +extern cpuop_func op_478_4_nf; +extern cpuop_func op_478_4_ff; +extern cpuop_func op_479_4_nf; +extern cpuop_func op_479_4_ff; +extern cpuop_func op_480_4_nf; +extern cpuop_func op_480_4_ff; +extern cpuop_func op_490_4_nf; +extern cpuop_func op_490_4_ff; +extern cpuop_func op_498_4_nf; +extern cpuop_func op_498_4_ff; +extern cpuop_func op_4a0_4_nf; +extern cpuop_func op_4a0_4_ff; +extern cpuop_func op_4a8_4_nf; +extern cpuop_func op_4a8_4_ff; +extern cpuop_func op_4b0_4_nf; +extern cpuop_func op_4b0_4_ff; +extern cpuop_func op_4b8_4_nf; +extern cpuop_func op_4b8_4_ff; +extern cpuop_func op_4b9_4_nf; +extern cpuop_func op_4b9_4_ff; +extern cpuop_func op_600_4_nf; +extern cpuop_func op_600_4_ff; +extern cpuop_func op_610_4_nf; +extern cpuop_func op_610_4_ff; +extern cpuop_func op_618_4_nf; +extern cpuop_func op_618_4_ff; +extern cpuop_func op_620_4_nf; +extern cpuop_func op_620_4_ff; +extern cpuop_func op_628_4_nf; +extern cpuop_func op_628_4_ff; +extern cpuop_func op_630_4_nf; +extern cpuop_func op_630_4_ff; +extern cpuop_func op_638_4_nf; +extern cpuop_func op_638_4_ff; +extern cpuop_func op_639_4_nf; +extern cpuop_func op_639_4_ff; +extern cpuop_func op_640_4_nf; +extern cpuop_func op_640_4_ff; +extern cpuop_func op_650_4_nf; +extern cpuop_func op_650_4_ff; +extern cpuop_func op_658_4_nf; +extern cpuop_func op_658_4_ff; +extern cpuop_func op_660_4_nf; +extern cpuop_func op_660_4_ff; +extern cpuop_func op_668_4_nf; +extern cpuop_func op_668_4_ff; +extern cpuop_func op_670_4_nf; +extern cpuop_func op_670_4_ff; +extern cpuop_func op_678_4_nf; +extern cpuop_func op_678_4_ff; +extern cpuop_func op_679_4_nf; +extern cpuop_func op_679_4_ff; +extern cpuop_func op_680_4_nf; +extern cpuop_func op_680_4_ff; +extern cpuop_func op_690_4_nf; +extern cpuop_func op_690_4_ff; +extern cpuop_func op_698_4_nf; +extern cpuop_func op_698_4_ff; +extern cpuop_func op_6a0_4_nf; +extern cpuop_func op_6a0_4_ff; +extern cpuop_func op_6a8_4_nf; +extern cpuop_func op_6a8_4_ff; +extern cpuop_func op_6b0_4_nf; +extern cpuop_func op_6b0_4_ff; +extern cpuop_func op_6b8_4_nf; +extern cpuop_func op_6b8_4_ff; +extern cpuop_func op_6b9_4_nf; +extern cpuop_func op_6b9_4_ff; +extern cpuop_func op_800_4_nf; +extern cpuop_func op_800_4_ff; +extern cpuop_func op_810_4_nf; +extern cpuop_func op_810_4_ff; +extern cpuop_func op_818_4_nf; +extern cpuop_func op_818_4_ff; +extern cpuop_func op_820_4_nf; +extern cpuop_func op_820_4_ff; +extern cpuop_func op_828_4_nf; +extern cpuop_func op_828_4_ff; +extern cpuop_func op_830_4_nf; +extern cpuop_func op_830_4_ff; +extern cpuop_func op_838_4_nf; +extern cpuop_func op_838_4_ff; +extern cpuop_func op_839_4_nf; +extern cpuop_func op_839_4_ff; +extern cpuop_func op_83a_4_nf; +extern cpuop_func op_83a_4_ff; +extern cpuop_func op_83b_4_nf; +extern cpuop_func op_83b_4_ff; +extern cpuop_func op_83c_4_nf; +extern cpuop_func op_83c_4_ff; +extern cpuop_func op_840_4_nf; +extern cpuop_func op_840_4_ff; +extern cpuop_func op_850_4_nf; +extern cpuop_func op_850_4_ff; +extern cpuop_func op_858_4_nf; +extern cpuop_func op_858_4_ff; +extern cpuop_func op_860_4_nf; +extern cpuop_func op_860_4_ff; +extern cpuop_func op_868_4_nf; +extern cpuop_func op_868_4_ff; +extern cpuop_func op_870_4_nf; +extern cpuop_func op_870_4_ff; +extern cpuop_func op_878_4_nf; +extern cpuop_func op_878_4_ff; +extern cpuop_func op_879_4_nf; +extern cpuop_func op_879_4_ff; +extern cpuop_func op_87a_4_nf; +extern cpuop_func op_87a_4_ff; +extern cpuop_func op_87b_4_nf; +extern cpuop_func op_87b_4_ff; +extern cpuop_func op_880_4_nf; +extern cpuop_func op_880_4_ff; +extern cpuop_func op_890_4_nf; +extern cpuop_func op_890_4_ff; +extern cpuop_func op_898_4_nf; +extern cpuop_func op_898_4_ff; +extern cpuop_func op_8a0_4_nf; +extern cpuop_func op_8a0_4_ff; +extern cpuop_func op_8a8_4_nf; +extern cpuop_func op_8a8_4_ff; +extern cpuop_func op_8b0_4_nf; +extern cpuop_func op_8b0_4_ff; +extern cpuop_func op_8b8_4_nf; +extern cpuop_func op_8b8_4_ff; +extern cpuop_func op_8b9_4_nf; +extern cpuop_func op_8b9_4_ff; +extern cpuop_func op_8ba_4_nf; +extern cpuop_func op_8ba_4_ff; +extern cpuop_func op_8bb_4_nf; +extern cpuop_func op_8bb_4_ff; +extern cpuop_func op_8c0_4_nf; +extern cpuop_func op_8c0_4_ff; +extern cpuop_func op_8d0_4_nf; +extern cpuop_func op_8d0_4_ff; +extern cpuop_func op_8d8_4_nf; +extern cpuop_func op_8d8_4_ff; +extern cpuop_func op_8e0_4_nf; +extern cpuop_func op_8e0_4_ff; +extern cpuop_func op_8e8_4_nf; +extern cpuop_func op_8e8_4_ff; +extern cpuop_func op_8f0_4_nf; +extern cpuop_func op_8f0_4_ff; +extern cpuop_func op_8f8_4_nf; +extern cpuop_func op_8f8_4_ff; +extern cpuop_func op_8f9_4_nf; +extern cpuop_func op_8f9_4_ff; +extern cpuop_func op_8fa_4_nf; +extern cpuop_func op_8fa_4_ff; +extern cpuop_func op_8fb_4_nf; +extern cpuop_func op_8fb_4_ff; +extern cpuop_func op_a00_4_nf; +extern cpuop_func op_a00_4_ff; +extern cpuop_func op_a10_4_nf; +extern cpuop_func op_a10_4_ff; +extern cpuop_func op_a18_4_nf; +extern cpuop_func op_a18_4_ff; +extern cpuop_func op_a20_4_nf; +extern cpuop_func op_a20_4_ff; +extern cpuop_func op_a28_4_nf; +extern cpuop_func op_a28_4_ff; +extern cpuop_func op_a30_4_nf; +extern cpuop_func op_a30_4_ff; +extern cpuop_func op_a38_4_nf; +extern cpuop_func op_a38_4_ff; +extern cpuop_func op_a39_4_nf; +extern cpuop_func op_a39_4_ff; +extern cpuop_func op_a3c_4_nf; +extern cpuop_func op_a3c_4_ff; +extern cpuop_func op_a40_4_nf; +extern cpuop_func op_a40_4_ff; +extern cpuop_func op_a50_4_nf; +extern cpuop_func op_a50_4_ff; +extern cpuop_func op_a58_4_nf; +extern cpuop_func op_a58_4_ff; +extern cpuop_func op_a60_4_nf; +extern cpuop_func op_a60_4_ff; +extern cpuop_func op_a68_4_nf; +extern cpuop_func op_a68_4_ff; +extern cpuop_func op_a70_4_nf; +extern cpuop_func op_a70_4_ff; +extern cpuop_func op_a78_4_nf; +extern cpuop_func op_a78_4_ff; +extern cpuop_func op_a79_4_nf; +extern cpuop_func op_a79_4_ff; +extern cpuop_func op_a7c_4_nf; +extern cpuop_func op_a7c_4_ff; +extern cpuop_func op_a80_4_nf; +extern cpuop_func op_a80_4_ff; +extern cpuop_func op_a90_4_nf; +extern cpuop_func op_a90_4_ff; +extern cpuop_func op_a98_4_nf; +extern cpuop_func op_a98_4_ff; +extern cpuop_func op_aa0_4_nf; +extern cpuop_func op_aa0_4_ff; +extern cpuop_func op_aa8_4_nf; +extern cpuop_func op_aa8_4_ff; +extern cpuop_func op_ab0_4_nf; +extern cpuop_func op_ab0_4_ff; +extern cpuop_func op_ab8_4_nf; +extern cpuop_func op_ab8_4_ff; +extern cpuop_func op_ab9_4_nf; +extern cpuop_func op_ab9_4_ff; +extern cpuop_func op_c00_4_nf; +extern cpuop_func op_c00_4_ff; +extern cpuop_func op_c10_4_nf; +extern cpuop_func op_c10_4_ff; +extern cpuop_func op_c18_4_nf; +extern cpuop_func op_c18_4_ff; +extern cpuop_func op_c20_4_nf; +extern cpuop_func op_c20_4_ff; +extern cpuop_func op_c28_4_nf; +extern cpuop_func op_c28_4_ff; +extern cpuop_func op_c30_4_nf; +extern cpuop_func op_c30_4_ff; +extern cpuop_func op_c38_4_nf; +extern cpuop_func op_c38_4_ff; +extern cpuop_func op_c39_4_nf; +extern cpuop_func op_c39_4_ff; +extern cpuop_func op_c3a_4_nf; +extern cpuop_func op_c3a_4_ff; +extern cpuop_func op_c3b_4_nf; +extern cpuop_func op_c3b_4_ff; +extern cpuop_func op_c40_4_nf; +extern cpuop_func op_c40_4_ff; +extern cpuop_func op_c50_4_nf; +extern cpuop_func op_c50_4_ff; +extern cpuop_func op_c58_4_nf; +extern cpuop_func op_c58_4_ff; +extern cpuop_func op_c60_4_nf; +extern cpuop_func op_c60_4_ff; +extern cpuop_func op_c68_4_nf; +extern cpuop_func op_c68_4_ff; +extern cpuop_func op_c70_4_nf; +extern cpuop_func op_c70_4_ff; +extern cpuop_func op_c78_4_nf; +extern cpuop_func op_c78_4_ff; +extern cpuop_func op_c79_4_nf; +extern cpuop_func op_c79_4_ff; +extern cpuop_func op_c7a_4_nf; +extern cpuop_func op_c7a_4_ff; +extern cpuop_func op_c7b_4_nf; +extern cpuop_func op_c7b_4_ff; +extern cpuop_func op_c80_4_nf; +extern cpuop_func op_c80_4_ff; +extern cpuop_func op_c90_4_nf; +extern cpuop_func op_c90_4_ff; +extern cpuop_func op_c98_4_nf; +extern cpuop_func op_c98_4_ff; +extern cpuop_func op_ca0_4_nf; +extern cpuop_func op_ca0_4_ff; +extern cpuop_func op_ca8_4_nf; +extern cpuop_func op_ca8_4_ff; +extern cpuop_func op_cb0_4_nf; +extern cpuop_func op_cb0_4_ff; +extern cpuop_func op_cb8_4_nf; +extern cpuop_func op_cb8_4_ff; +extern cpuop_func op_cb9_4_nf; +extern cpuop_func op_cb9_4_ff; +extern cpuop_func op_cba_4_nf; +extern cpuop_func op_cba_4_ff; +extern cpuop_func op_cbb_4_nf; +extern cpuop_func op_cbb_4_ff; +extern cpuop_func op_1000_4_nf; +extern cpuop_func op_1000_4_ff; +extern cpuop_func op_1008_4_nf; +extern cpuop_func op_1008_4_ff; +extern cpuop_func op_1010_4_nf; +extern cpuop_func op_1010_4_ff; +extern cpuop_func op_1018_4_nf; +extern cpuop_func op_1018_4_ff; +extern cpuop_func op_1020_4_nf; +extern cpuop_func op_1020_4_ff; +extern cpuop_func op_1028_4_nf; +extern cpuop_func op_1028_4_ff; +extern cpuop_func op_1030_4_nf; +extern cpuop_func op_1030_4_ff; +extern cpuop_func op_1038_4_nf; +extern cpuop_func op_1038_4_ff; +extern cpuop_func op_1039_4_nf; +extern cpuop_func op_1039_4_ff; +extern cpuop_func op_103a_4_nf; +extern cpuop_func op_103a_4_ff; +extern cpuop_func op_103b_4_nf; +extern cpuop_func op_103b_4_ff; +extern cpuop_func op_103c_4_nf; +extern cpuop_func op_103c_4_ff; +extern cpuop_func op_1080_4_nf; +extern cpuop_func op_1080_4_ff; +extern cpuop_func op_1088_4_nf; +extern cpuop_func op_1088_4_ff; +extern cpuop_func op_1090_4_nf; +extern cpuop_func op_1090_4_ff; +extern cpuop_func op_1098_4_nf; +extern cpuop_func op_1098_4_ff; +extern cpuop_func op_10a0_4_nf; +extern cpuop_func op_10a0_4_ff; +extern cpuop_func op_10a8_4_nf; +extern cpuop_func op_10a8_4_ff; +extern cpuop_func op_10b0_4_nf; +extern cpuop_func op_10b0_4_ff; +extern cpuop_func op_10b8_4_nf; +extern cpuop_func op_10b8_4_ff; +extern cpuop_func op_10b9_4_nf; +extern cpuop_func op_10b9_4_ff; +extern cpuop_func op_10ba_4_nf; +extern cpuop_func op_10ba_4_ff; +extern cpuop_func op_10bb_4_nf; +extern cpuop_func op_10bb_4_ff; +extern cpuop_func op_10bc_4_nf; +extern cpuop_func op_10bc_4_ff; +extern cpuop_func op_10c0_4_nf; +extern cpuop_func op_10c0_4_ff; +extern cpuop_func op_10c8_4_nf; +extern cpuop_func op_10c8_4_ff; +extern cpuop_func op_10d0_4_nf; +extern cpuop_func op_10d0_4_ff; +extern cpuop_func op_10d8_4_nf; +extern cpuop_func op_10d8_4_ff; +extern cpuop_func op_10e0_4_nf; +extern cpuop_func op_10e0_4_ff; +extern cpuop_func op_10e8_4_nf; +extern cpuop_func op_10e8_4_ff; +extern cpuop_func op_10f0_4_nf; +extern cpuop_func op_10f0_4_ff; +extern cpuop_func op_10f8_4_nf; +extern cpuop_func op_10f8_4_ff; +extern cpuop_func op_10f9_4_nf; +extern cpuop_func op_10f9_4_ff; +extern cpuop_func op_10fa_4_nf; +extern cpuop_func op_10fa_4_ff; +extern cpuop_func op_10fb_4_nf; +extern cpuop_func op_10fb_4_ff; +extern cpuop_func op_10fc_4_nf; +extern cpuop_func op_10fc_4_ff; +extern cpuop_func op_1100_4_nf; +extern cpuop_func op_1100_4_ff; +extern cpuop_func op_1108_4_nf; +extern cpuop_func op_1108_4_ff; +extern cpuop_func op_1110_4_nf; +extern cpuop_func op_1110_4_ff; +extern cpuop_func op_1118_4_nf; +extern cpuop_func op_1118_4_ff; +extern cpuop_func op_1120_4_nf; +extern cpuop_func op_1120_4_ff; +extern cpuop_func op_1128_4_nf; +extern cpuop_func op_1128_4_ff; +extern cpuop_func op_1130_4_nf; +extern cpuop_func op_1130_4_ff; +extern cpuop_func op_1138_4_nf; +extern cpuop_func op_1138_4_ff; +extern cpuop_func op_1139_4_nf; +extern cpuop_func op_1139_4_ff; +extern cpuop_func op_113a_4_nf; +extern cpuop_func op_113a_4_ff; +extern cpuop_func op_113b_4_nf; +extern cpuop_func op_113b_4_ff; +extern cpuop_func op_113c_4_nf; +extern cpuop_func op_113c_4_ff; +extern cpuop_func op_1140_4_nf; +extern cpuop_func op_1140_4_ff; +extern cpuop_func op_1148_4_nf; +extern cpuop_func op_1148_4_ff; +extern cpuop_func op_1150_4_nf; +extern cpuop_func op_1150_4_ff; +extern cpuop_func op_1158_4_nf; +extern cpuop_func op_1158_4_ff; +extern cpuop_func op_1160_4_nf; +extern cpuop_func op_1160_4_ff; +extern cpuop_func op_1168_4_nf; +extern cpuop_func op_1168_4_ff; +extern cpuop_func op_1170_4_nf; +extern cpuop_func op_1170_4_ff; +extern cpuop_func op_1178_4_nf; +extern cpuop_func op_1178_4_ff; +extern cpuop_func op_1179_4_nf; +extern cpuop_func op_1179_4_ff; +extern cpuop_func op_117a_4_nf; +extern cpuop_func op_117a_4_ff; +extern cpuop_func op_117b_4_nf; +extern cpuop_func op_117b_4_ff; +extern cpuop_func op_117c_4_nf; +extern cpuop_func op_117c_4_ff; +extern cpuop_func op_1180_4_nf; +extern cpuop_func op_1180_4_ff; +extern cpuop_func op_1188_4_nf; +extern cpuop_func op_1188_4_ff; +extern cpuop_func op_1190_4_nf; +extern cpuop_func op_1190_4_ff; +extern cpuop_func op_1198_4_nf; +extern cpuop_func op_1198_4_ff; +extern cpuop_func op_11a0_4_nf; +extern cpuop_func op_11a0_4_ff; +extern cpuop_func op_11a8_4_nf; +extern cpuop_func op_11a8_4_ff; +extern cpuop_func op_11b0_4_nf; +extern cpuop_func op_11b0_4_ff; +extern cpuop_func op_11b8_4_nf; +extern cpuop_func op_11b8_4_ff; +extern cpuop_func op_11b9_4_nf; +extern cpuop_func op_11b9_4_ff; +extern cpuop_func op_11ba_4_nf; +extern cpuop_func op_11ba_4_ff; +extern cpuop_func op_11bb_4_nf; +extern cpuop_func op_11bb_4_ff; +extern cpuop_func op_11bc_4_nf; +extern cpuop_func op_11bc_4_ff; +extern cpuop_func op_11c0_4_nf; +extern cpuop_func op_11c0_4_ff; +extern cpuop_func op_11c8_4_nf; +extern cpuop_func op_11c8_4_ff; +extern cpuop_func op_11d0_4_nf; +extern cpuop_func op_11d0_4_ff; +extern cpuop_func op_11d8_4_nf; +extern cpuop_func op_11d8_4_ff; +extern cpuop_func op_11e0_4_nf; +extern cpuop_func op_11e0_4_ff; +extern cpuop_func op_11e8_4_nf; +extern cpuop_func op_11e8_4_ff; +extern cpuop_func op_11f0_4_nf; +extern cpuop_func op_11f0_4_ff; +extern cpuop_func op_11f8_4_nf; +extern cpuop_func op_11f8_4_ff; +extern cpuop_func op_11f9_4_nf; +extern cpuop_func op_11f9_4_ff; +extern cpuop_func op_11fa_4_nf; +extern cpuop_func op_11fa_4_ff; +extern cpuop_func op_11fb_4_nf; +extern cpuop_func op_11fb_4_ff; +extern cpuop_func op_11fc_4_nf; +extern cpuop_func op_11fc_4_ff; +extern cpuop_func op_13c0_4_nf; +extern cpuop_func op_13c0_4_ff; +extern cpuop_func op_13c8_4_nf; +extern cpuop_func op_13c8_4_ff; +extern cpuop_func op_13d0_4_nf; +extern cpuop_func op_13d0_4_ff; +extern cpuop_func op_13d8_4_nf; +extern cpuop_func op_13d8_4_ff; +extern cpuop_func op_13e0_4_nf; +extern cpuop_func op_13e0_4_ff; +extern cpuop_func op_13e8_4_nf; +extern cpuop_func op_13e8_4_ff; +extern cpuop_func op_13f0_4_nf; +extern cpuop_func op_13f0_4_ff; +extern cpuop_func op_13f8_4_nf; +extern cpuop_func op_13f8_4_ff; +extern cpuop_func op_13f9_4_nf; +extern cpuop_func op_13f9_4_ff; +extern cpuop_func op_13fa_4_nf; +extern cpuop_func op_13fa_4_ff; +extern cpuop_func op_13fb_4_nf; +extern cpuop_func op_13fb_4_ff; +extern cpuop_func op_13fc_4_nf; +extern cpuop_func op_13fc_4_ff; +extern cpuop_func op_2000_4_nf; +extern cpuop_func op_2000_4_ff; +extern cpuop_func op_2008_4_nf; +extern cpuop_func op_2008_4_ff; +extern cpuop_func op_2010_4_nf; +extern cpuop_func op_2010_4_ff; +extern cpuop_func op_2018_4_nf; +extern cpuop_func op_2018_4_ff; +extern cpuop_func op_2020_4_nf; +extern cpuop_func op_2020_4_ff; +extern cpuop_func op_2028_4_nf; +extern cpuop_func op_2028_4_ff; +extern cpuop_func op_2030_4_nf; +extern cpuop_func op_2030_4_ff; +extern cpuop_func op_2038_4_nf; +extern cpuop_func op_2038_4_ff; +extern cpuop_func op_2039_4_nf; +extern cpuop_func op_2039_4_ff; +extern cpuop_func op_203a_4_nf; +extern cpuop_func op_203a_4_ff; +extern cpuop_func op_203b_4_nf; +extern cpuop_func op_203b_4_ff; +extern cpuop_func op_203c_4_nf; +extern cpuop_func op_203c_4_ff; +extern cpuop_func op_2040_4_nf; +extern cpuop_func op_2040_4_ff; +extern cpuop_func op_2048_4_nf; +extern cpuop_func op_2048_4_ff; +extern cpuop_func op_2050_4_nf; +extern cpuop_func op_2050_4_ff; +extern cpuop_func op_2058_4_nf; +extern cpuop_func op_2058_4_ff; +extern cpuop_func op_2060_4_nf; +extern cpuop_func op_2060_4_ff; +extern cpuop_func op_2068_4_nf; +extern cpuop_func op_2068_4_ff; +extern cpuop_func op_2070_4_nf; +extern cpuop_func op_2070_4_ff; +extern cpuop_func op_2078_4_nf; +extern cpuop_func op_2078_4_ff; +extern cpuop_func op_2079_4_nf; +extern cpuop_func op_2079_4_ff; +extern cpuop_func op_207a_4_nf; +extern cpuop_func op_207a_4_ff; +extern cpuop_func op_207b_4_nf; +extern cpuop_func op_207b_4_ff; +extern cpuop_func op_207c_4_nf; +extern cpuop_func op_207c_4_ff; +extern cpuop_func op_2080_4_nf; +extern cpuop_func op_2080_4_ff; +extern cpuop_func op_2088_4_nf; +extern cpuop_func op_2088_4_ff; +extern cpuop_func op_2090_4_nf; +extern cpuop_func op_2090_4_ff; +extern cpuop_func op_2098_4_nf; +extern cpuop_func op_2098_4_ff; +extern cpuop_func op_20a0_4_nf; +extern cpuop_func op_20a0_4_ff; +extern cpuop_func op_20a8_4_nf; +extern cpuop_func op_20a8_4_ff; +extern cpuop_func op_20b0_4_nf; +extern cpuop_func op_20b0_4_ff; +extern cpuop_func op_20b8_4_nf; +extern cpuop_func op_20b8_4_ff; +extern cpuop_func op_20b9_4_nf; +extern cpuop_func op_20b9_4_ff; +extern cpuop_func op_20ba_4_nf; +extern cpuop_func op_20ba_4_ff; +extern cpuop_func op_20bb_4_nf; +extern cpuop_func op_20bb_4_ff; +extern cpuop_func op_20bc_4_nf; +extern cpuop_func op_20bc_4_ff; +extern cpuop_func op_20c0_4_nf; +extern cpuop_func op_20c0_4_ff; +extern cpuop_func op_20c8_4_nf; +extern cpuop_func op_20c8_4_ff; +extern cpuop_func op_20d0_4_nf; +extern cpuop_func op_20d0_4_ff; +extern cpuop_func op_20d8_4_nf; +extern cpuop_func op_20d8_4_ff; +extern cpuop_func op_20e0_4_nf; +extern cpuop_func op_20e0_4_ff; +extern cpuop_func op_20e8_4_nf; +extern cpuop_func op_20e8_4_ff; +extern cpuop_func op_20f0_4_nf; +extern cpuop_func op_20f0_4_ff; +extern cpuop_func op_20f8_4_nf; +extern cpuop_func op_20f8_4_ff; +extern cpuop_func op_20f9_4_nf; +extern cpuop_func op_20f9_4_ff; +extern cpuop_func op_20fa_4_nf; +extern cpuop_func op_20fa_4_ff; +extern cpuop_func op_20fb_4_nf; +extern cpuop_func op_20fb_4_ff; +extern cpuop_func op_20fc_4_nf; +extern cpuop_func op_20fc_4_ff; +extern cpuop_func op_2100_4_nf; +extern cpuop_func op_2100_4_ff; +extern cpuop_func op_2108_4_nf; +extern cpuop_func op_2108_4_ff; +extern cpuop_func op_2110_4_nf; +extern cpuop_func op_2110_4_ff; +extern cpuop_func op_2118_4_nf; +extern cpuop_func op_2118_4_ff; +extern cpuop_func op_2120_4_nf; +extern cpuop_func op_2120_4_ff; +extern cpuop_func op_2128_4_nf; +extern cpuop_func op_2128_4_ff; +extern cpuop_func op_2130_4_nf; +extern cpuop_func op_2130_4_ff; +extern cpuop_func op_2138_4_nf; +extern cpuop_func op_2138_4_ff; +extern cpuop_func op_2139_4_nf; +extern cpuop_func op_2139_4_ff; +extern cpuop_func op_213a_4_nf; +extern cpuop_func op_213a_4_ff; +extern cpuop_func op_213b_4_nf; +extern cpuop_func op_213b_4_ff; +extern cpuop_func op_213c_4_nf; +extern cpuop_func op_213c_4_ff; +extern cpuop_func op_2140_4_nf; +extern cpuop_func op_2140_4_ff; +extern cpuop_func op_2148_4_nf; +extern cpuop_func op_2148_4_ff; +extern cpuop_func op_2150_4_nf; +extern cpuop_func op_2150_4_ff; +extern cpuop_func op_2158_4_nf; +extern cpuop_func op_2158_4_ff; +extern cpuop_func op_2160_4_nf; +extern cpuop_func op_2160_4_ff; +extern cpuop_func op_2168_4_nf; +extern cpuop_func op_2168_4_ff; +extern cpuop_func op_2170_4_nf; +extern cpuop_func op_2170_4_ff; +extern cpuop_func op_2178_4_nf; +extern cpuop_func op_2178_4_ff; +extern cpuop_func op_2179_4_nf; +extern cpuop_func op_2179_4_ff; +extern cpuop_func op_217a_4_nf; +extern cpuop_func op_217a_4_ff; +extern cpuop_func op_217b_4_nf; +extern cpuop_func op_217b_4_ff; +extern cpuop_func op_217c_4_nf; +extern cpuop_func op_217c_4_ff; +extern cpuop_func op_2180_4_nf; +extern cpuop_func op_2180_4_ff; +extern cpuop_func op_2188_4_nf; +extern cpuop_func op_2188_4_ff; +extern cpuop_func op_2190_4_nf; +extern cpuop_func op_2190_4_ff; +extern cpuop_func op_2198_4_nf; +extern cpuop_func op_2198_4_ff; +extern cpuop_func op_21a0_4_nf; +extern cpuop_func op_21a0_4_ff; +extern cpuop_func op_21a8_4_nf; +extern cpuop_func op_21a8_4_ff; +extern cpuop_func op_21b0_4_nf; +extern cpuop_func op_21b0_4_ff; +extern cpuop_func op_21b8_4_nf; +extern cpuop_func op_21b8_4_ff; +extern cpuop_func op_21b9_4_nf; +extern cpuop_func op_21b9_4_ff; +extern cpuop_func op_21ba_4_nf; +extern cpuop_func op_21ba_4_ff; +extern cpuop_func op_21bb_4_nf; +extern cpuop_func op_21bb_4_ff; +extern cpuop_func op_21bc_4_nf; +extern cpuop_func op_21bc_4_ff; +extern cpuop_func op_21c0_4_nf; +extern cpuop_func op_21c0_4_ff; +extern cpuop_func op_21c8_4_nf; +extern cpuop_func op_21c8_4_ff; +extern cpuop_func op_21d0_4_nf; +extern cpuop_func op_21d0_4_ff; +extern cpuop_func op_21d8_4_nf; +extern cpuop_func op_21d8_4_ff; +extern cpuop_func op_21e0_4_nf; +extern cpuop_func op_21e0_4_ff; +extern cpuop_func op_21e8_4_nf; +extern cpuop_func op_21e8_4_ff; +extern cpuop_func op_21f0_4_nf; +extern cpuop_func op_21f0_4_ff; +extern cpuop_func op_21f8_4_nf; +extern cpuop_func op_21f8_4_ff; +extern cpuop_func op_21f9_4_nf; +extern cpuop_func op_21f9_4_ff; +extern cpuop_func op_21fa_4_nf; +extern cpuop_func op_21fa_4_ff; +extern cpuop_func op_21fb_4_nf; +extern cpuop_func op_21fb_4_ff; +extern cpuop_func op_21fc_4_nf; +extern cpuop_func op_21fc_4_ff; +extern cpuop_func op_23c0_4_nf; +extern cpuop_func op_23c0_4_ff; +extern cpuop_func op_23c8_4_nf; +extern cpuop_func op_23c8_4_ff; +extern cpuop_func op_23d0_4_nf; +extern cpuop_func op_23d0_4_ff; +extern cpuop_func op_23d8_4_nf; +extern cpuop_func op_23d8_4_ff; +extern cpuop_func op_23e0_4_nf; +extern cpuop_func op_23e0_4_ff; +extern cpuop_func op_23e8_4_nf; +extern cpuop_func op_23e8_4_ff; +extern cpuop_func op_23f0_4_nf; +extern cpuop_func op_23f0_4_ff; +extern cpuop_func op_23f8_4_nf; +extern cpuop_func op_23f8_4_ff; +extern cpuop_func op_23f9_4_nf; +extern cpuop_func op_23f9_4_ff; +extern cpuop_func op_23fa_4_nf; +extern cpuop_func op_23fa_4_ff; +extern cpuop_func op_23fb_4_nf; +extern cpuop_func op_23fb_4_ff; +extern cpuop_func op_23fc_4_nf; +extern cpuop_func op_23fc_4_ff; +extern cpuop_func op_3000_4_nf; +extern cpuop_func op_3000_4_ff; +extern cpuop_func op_3008_4_nf; +extern cpuop_func op_3008_4_ff; +extern cpuop_func op_3010_4_nf; +extern cpuop_func op_3010_4_ff; +extern cpuop_func op_3018_4_nf; +extern cpuop_func op_3018_4_ff; +extern cpuop_func op_3020_4_nf; +extern cpuop_func op_3020_4_ff; +extern cpuop_func op_3028_4_nf; +extern cpuop_func op_3028_4_ff; +extern cpuop_func op_3030_4_nf; +extern cpuop_func op_3030_4_ff; +extern cpuop_func op_3038_4_nf; +extern cpuop_func op_3038_4_ff; +extern cpuop_func op_3039_4_nf; +extern cpuop_func op_3039_4_ff; +extern cpuop_func op_303a_4_nf; +extern cpuop_func op_303a_4_ff; +extern cpuop_func op_303b_4_nf; +extern cpuop_func op_303b_4_ff; +extern cpuop_func op_303c_4_nf; +extern cpuop_func op_303c_4_ff; +extern cpuop_func op_3040_4_nf; +extern cpuop_func op_3040_4_ff; +extern cpuop_func op_3048_4_nf; +extern cpuop_func op_3048_4_ff; +extern cpuop_func op_3050_4_nf; +extern cpuop_func op_3050_4_ff; +extern cpuop_func op_3058_4_nf; +extern cpuop_func op_3058_4_ff; +extern cpuop_func op_3060_4_nf; +extern cpuop_func op_3060_4_ff; +extern cpuop_func op_3068_4_nf; +extern cpuop_func op_3068_4_ff; +extern cpuop_func op_3070_4_nf; +extern cpuop_func op_3070_4_ff; +extern cpuop_func op_3078_4_nf; +extern cpuop_func op_3078_4_ff; +extern cpuop_func op_3079_4_nf; +extern cpuop_func op_3079_4_ff; +extern cpuop_func op_307a_4_nf; +extern cpuop_func op_307a_4_ff; +extern cpuop_func op_307b_4_nf; +extern cpuop_func op_307b_4_ff; +extern cpuop_func op_307c_4_nf; +extern cpuop_func op_307c_4_ff; +extern cpuop_func op_3080_4_nf; +extern cpuop_func op_3080_4_ff; +extern cpuop_func op_3088_4_nf; +extern cpuop_func op_3088_4_ff; +extern cpuop_func op_3090_4_nf; +extern cpuop_func op_3090_4_ff; +extern cpuop_func op_3098_4_nf; +extern cpuop_func op_3098_4_ff; +extern cpuop_func op_30a0_4_nf; +extern cpuop_func op_30a0_4_ff; +extern cpuop_func op_30a8_4_nf; +extern cpuop_func op_30a8_4_ff; +extern cpuop_func op_30b0_4_nf; +extern cpuop_func op_30b0_4_ff; +extern cpuop_func op_30b8_4_nf; +extern cpuop_func op_30b8_4_ff; +extern cpuop_func op_30b9_4_nf; +extern cpuop_func op_30b9_4_ff; +extern cpuop_func op_30ba_4_nf; +extern cpuop_func op_30ba_4_ff; +extern cpuop_func op_30bb_4_nf; +extern cpuop_func op_30bb_4_ff; +extern cpuop_func op_30bc_4_nf; +extern cpuop_func op_30bc_4_ff; +extern cpuop_func op_30c0_4_nf; +extern cpuop_func op_30c0_4_ff; +extern cpuop_func op_30c8_4_nf; +extern cpuop_func op_30c8_4_ff; +extern cpuop_func op_30d0_4_nf; +extern cpuop_func op_30d0_4_ff; +extern cpuop_func op_30d8_4_nf; +extern cpuop_func op_30d8_4_ff; +extern cpuop_func op_30e0_4_nf; +extern cpuop_func op_30e0_4_ff; +extern cpuop_func op_30e8_4_nf; +extern cpuop_func op_30e8_4_ff; +extern cpuop_func op_30f0_4_nf; +extern cpuop_func op_30f0_4_ff; +extern cpuop_func op_30f8_4_nf; +extern cpuop_func op_30f8_4_ff; +extern cpuop_func op_30f9_4_nf; +extern cpuop_func op_30f9_4_ff; +extern cpuop_func op_30fa_4_nf; +extern cpuop_func op_30fa_4_ff; +extern cpuop_func op_30fb_4_nf; +extern cpuop_func op_30fb_4_ff; +extern cpuop_func op_30fc_4_nf; +extern cpuop_func op_30fc_4_ff; +extern cpuop_func op_3100_4_nf; +extern cpuop_func op_3100_4_ff; +extern cpuop_func op_3108_4_nf; +extern cpuop_func op_3108_4_ff; +extern cpuop_func op_3110_4_nf; +extern cpuop_func op_3110_4_ff; +extern cpuop_func op_3118_4_nf; +extern cpuop_func op_3118_4_ff; +extern cpuop_func op_3120_4_nf; +extern cpuop_func op_3120_4_ff; +extern cpuop_func op_3128_4_nf; +extern cpuop_func op_3128_4_ff; +extern cpuop_func op_3130_4_nf; +extern cpuop_func op_3130_4_ff; +extern cpuop_func op_3138_4_nf; +extern cpuop_func op_3138_4_ff; +extern cpuop_func op_3139_4_nf; +extern cpuop_func op_3139_4_ff; +extern cpuop_func op_313a_4_nf; +extern cpuop_func op_313a_4_ff; +extern cpuop_func op_313b_4_nf; +extern cpuop_func op_313b_4_ff; +extern cpuop_func op_313c_4_nf; +extern cpuop_func op_313c_4_ff; +extern cpuop_func op_3140_4_nf; +extern cpuop_func op_3140_4_ff; +extern cpuop_func op_3148_4_nf; +extern cpuop_func op_3148_4_ff; +extern cpuop_func op_3150_4_nf; +extern cpuop_func op_3150_4_ff; +extern cpuop_func op_3158_4_nf; +extern cpuop_func op_3158_4_ff; +extern cpuop_func op_3160_4_nf; +extern cpuop_func op_3160_4_ff; +extern cpuop_func op_3168_4_nf; +extern cpuop_func op_3168_4_ff; +extern cpuop_func op_3170_4_nf; +extern cpuop_func op_3170_4_ff; +extern cpuop_func op_3178_4_nf; +extern cpuop_func op_3178_4_ff; +extern cpuop_func op_3179_4_nf; +extern cpuop_func op_3179_4_ff; +extern cpuop_func op_317a_4_nf; +extern cpuop_func op_317a_4_ff; +extern cpuop_func op_317b_4_nf; +extern cpuop_func op_317b_4_ff; +extern cpuop_func op_317c_4_nf; +extern cpuop_func op_317c_4_ff; +extern cpuop_func op_3180_4_nf; +extern cpuop_func op_3180_4_ff; +extern cpuop_func op_3188_4_nf; +extern cpuop_func op_3188_4_ff; +extern cpuop_func op_3190_4_nf; +extern cpuop_func op_3190_4_ff; +extern cpuop_func op_3198_4_nf; +extern cpuop_func op_3198_4_ff; +extern cpuop_func op_31a0_4_nf; +extern cpuop_func op_31a0_4_ff; +extern cpuop_func op_31a8_4_nf; +extern cpuop_func op_31a8_4_ff; +extern cpuop_func op_31b0_4_nf; +extern cpuop_func op_31b0_4_ff; +extern cpuop_func op_31b8_4_nf; +extern cpuop_func op_31b8_4_ff; +extern cpuop_func op_31b9_4_nf; +extern cpuop_func op_31b9_4_ff; +extern cpuop_func op_31ba_4_nf; +extern cpuop_func op_31ba_4_ff; +extern cpuop_func op_31bb_4_nf; +extern cpuop_func op_31bb_4_ff; +extern cpuop_func op_31bc_4_nf; +extern cpuop_func op_31bc_4_ff; +extern cpuop_func op_31c0_4_nf; +extern cpuop_func op_31c0_4_ff; +extern cpuop_func op_31c8_4_nf; +extern cpuop_func op_31c8_4_ff; +extern cpuop_func op_31d0_4_nf; +extern cpuop_func op_31d0_4_ff; +extern cpuop_func op_31d8_4_nf; +extern cpuop_func op_31d8_4_ff; +extern cpuop_func op_31e0_4_nf; +extern cpuop_func op_31e0_4_ff; +extern cpuop_func op_31e8_4_nf; +extern cpuop_func op_31e8_4_ff; +extern cpuop_func op_31f0_4_nf; +extern cpuop_func op_31f0_4_ff; +extern cpuop_func op_31f8_4_nf; +extern cpuop_func op_31f8_4_ff; +extern cpuop_func op_31f9_4_nf; +extern cpuop_func op_31f9_4_ff; +extern cpuop_func op_31fa_4_nf; +extern cpuop_func op_31fa_4_ff; +extern cpuop_func op_31fb_4_nf; +extern cpuop_func op_31fb_4_ff; +extern cpuop_func op_31fc_4_nf; +extern cpuop_func op_31fc_4_ff; +extern cpuop_func op_33c0_4_nf; +extern cpuop_func op_33c0_4_ff; +extern cpuop_func op_33c8_4_nf; +extern cpuop_func op_33c8_4_ff; +extern cpuop_func op_33d0_4_nf; +extern cpuop_func op_33d0_4_ff; +extern cpuop_func op_33d8_4_nf; +extern cpuop_func op_33d8_4_ff; +extern cpuop_func op_33e0_4_nf; +extern cpuop_func op_33e0_4_ff; +extern cpuop_func op_33e8_4_nf; +extern cpuop_func op_33e8_4_ff; +extern cpuop_func op_33f0_4_nf; +extern cpuop_func op_33f0_4_ff; +extern cpuop_func op_33f8_4_nf; +extern cpuop_func op_33f8_4_ff; +extern cpuop_func op_33f9_4_nf; +extern cpuop_func op_33f9_4_ff; +extern cpuop_func op_33fa_4_nf; +extern cpuop_func op_33fa_4_ff; +extern cpuop_func op_33fb_4_nf; +extern cpuop_func op_33fb_4_ff; +extern cpuop_func op_33fc_4_nf; +extern cpuop_func op_33fc_4_ff; +extern cpuop_func op_4000_4_nf; +extern cpuop_func op_4000_4_ff; +extern cpuop_func op_4010_4_nf; +extern cpuop_func op_4010_4_ff; +extern cpuop_func op_4018_4_nf; +extern cpuop_func op_4018_4_ff; +extern cpuop_func op_4020_4_nf; +extern cpuop_func op_4020_4_ff; +extern cpuop_func op_4028_4_nf; +extern cpuop_func op_4028_4_ff; +extern cpuop_func op_4030_4_nf; +extern cpuop_func op_4030_4_ff; +extern cpuop_func op_4038_4_nf; +extern cpuop_func op_4038_4_ff; +extern cpuop_func op_4039_4_nf; +extern cpuop_func op_4039_4_ff; +extern cpuop_func op_4040_4_nf; +extern cpuop_func op_4040_4_ff; +extern cpuop_func op_4050_4_nf; +extern cpuop_func op_4050_4_ff; +extern cpuop_func op_4058_4_nf; +extern cpuop_func op_4058_4_ff; +extern cpuop_func op_4060_4_nf; +extern cpuop_func op_4060_4_ff; +extern cpuop_func op_4068_4_nf; +extern cpuop_func op_4068_4_ff; +extern cpuop_func op_4070_4_nf; +extern cpuop_func op_4070_4_ff; +extern cpuop_func op_4078_4_nf; +extern cpuop_func op_4078_4_ff; +extern cpuop_func op_4079_4_nf; +extern cpuop_func op_4079_4_ff; +extern cpuop_func op_4080_4_nf; +extern cpuop_func op_4080_4_ff; +extern cpuop_func op_4090_4_nf; +extern cpuop_func op_4090_4_ff; +extern cpuop_func op_4098_4_nf; +extern cpuop_func op_4098_4_ff; +extern cpuop_func op_40a0_4_nf; +extern cpuop_func op_40a0_4_ff; +extern cpuop_func op_40a8_4_nf; +extern cpuop_func op_40a8_4_ff; +extern cpuop_func op_40b0_4_nf; +extern cpuop_func op_40b0_4_ff; +extern cpuop_func op_40b8_4_nf; +extern cpuop_func op_40b8_4_ff; +extern cpuop_func op_40b9_4_nf; +extern cpuop_func op_40b9_4_ff; +extern cpuop_func op_40c0_4_nf; +extern cpuop_func op_40c0_4_ff; +extern cpuop_func op_40d0_4_nf; +extern cpuop_func op_40d0_4_ff; +extern cpuop_func op_40d8_4_nf; +extern cpuop_func op_40d8_4_ff; +extern cpuop_func op_40e0_4_nf; +extern cpuop_func op_40e0_4_ff; +extern cpuop_func op_40e8_4_nf; +extern cpuop_func op_40e8_4_ff; +extern cpuop_func op_40f0_4_nf; +extern cpuop_func op_40f0_4_ff; +extern cpuop_func op_40f8_4_nf; +extern cpuop_func op_40f8_4_ff; +extern cpuop_func op_40f9_4_nf; +extern cpuop_func op_40f9_4_ff; +extern cpuop_func op_4180_4_nf; +extern cpuop_func op_4180_4_ff; +extern cpuop_func op_4190_4_nf; +extern cpuop_func op_4190_4_ff; +extern cpuop_func op_4198_4_nf; +extern cpuop_func op_4198_4_ff; +extern cpuop_func op_41a0_4_nf; +extern cpuop_func op_41a0_4_ff; +extern cpuop_func op_41a8_4_nf; +extern cpuop_func op_41a8_4_ff; +extern cpuop_func op_41b0_4_nf; +extern cpuop_func op_41b0_4_ff; +extern cpuop_func op_41b8_4_nf; +extern cpuop_func op_41b8_4_ff; +extern cpuop_func op_41b9_4_nf; +extern cpuop_func op_41b9_4_ff; +extern cpuop_func op_41ba_4_nf; +extern cpuop_func op_41ba_4_ff; +extern cpuop_func op_41bb_4_nf; +extern cpuop_func op_41bb_4_ff; +extern cpuop_func op_41bc_4_nf; +extern cpuop_func op_41bc_4_ff; +extern cpuop_func op_41d0_4_nf; +extern cpuop_func op_41d0_4_ff; +extern cpuop_func op_41e8_4_nf; +extern cpuop_func op_41e8_4_ff; +extern cpuop_func op_41f0_4_nf; +extern cpuop_func op_41f0_4_ff; +extern cpuop_func op_41f8_4_nf; +extern cpuop_func op_41f8_4_ff; +extern cpuop_func op_41f9_4_nf; +extern cpuop_func op_41f9_4_ff; +extern cpuop_func op_41fa_4_nf; +extern cpuop_func op_41fa_4_ff; +extern cpuop_func op_41fb_4_nf; +extern cpuop_func op_41fb_4_ff; +extern cpuop_func op_4200_4_nf; +extern cpuop_func op_4200_4_ff; +extern cpuop_func op_4210_4_nf; +extern cpuop_func op_4210_4_ff; +extern cpuop_func op_4218_4_nf; +extern cpuop_func op_4218_4_ff; +extern cpuop_func op_4220_4_nf; +extern cpuop_func op_4220_4_ff; +extern cpuop_func op_4228_4_nf; +extern cpuop_func op_4228_4_ff; +extern cpuop_func op_4230_4_nf; +extern cpuop_func op_4230_4_ff; +extern cpuop_func op_4238_4_nf; +extern cpuop_func op_4238_4_ff; +extern cpuop_func op_4239_4_nf; +extern cpuop_func op_4239_4_ff; +extern cpuop_func op_4240_4_nf; +extern cpuop_func op_4240_4_ff; +extern cpuop_func op_4250_4_nf; +extern cpuop_func op_4250_4_ff; +extern cpuop_func op_4258_4_nf; +extern cpuop_func op_4258_4_ff; +extern cpuop_func op_4260_4_nf; +extern cpuop_func op_4260_4_ff; +extern cpuop_func op_4268_4_nf; +extern cpuop_func op_4268_4_ff; +extern cpuop_func op_4270_4_nf; +extern cpuop_func op_4270_4_ff; +extern cpuop_func op_4278_4_nf; +extern cpuop_func op_4278_4_ff; +extern cpuop_func op_4279_4_nf; +extern cpuop_func op_4279_4_ff; +extern cpuop_func op_4280_4_nf; +extern cpuop_func op_4280_4_ff; +extern cpuop_func op_4290_4_nf; +extern cpuop_func op_4290_4_ff; +extern cpuop_func op_4298_4_nf; +extern cpuop_func op_4298_4_ff; +extern cpuop_func op_42a0_4_nf; +extern cpuop_func op_42a0_4_ff; +extern cpuop_func op_42a8_4_nf; +extern cpuop_func op_42a8_4_ff; +extern cpuop_func op_42b0_4_nf; +extern cpuop_func op_42b0_4_ff; +extern cpuop_func op_42b8_4_nf; +extern cpuop_func op_42b8_4_ff; +extern cpuop_func op_42b9_4_nf; +extern cpuop_func op_42b9_4_ff; +extern cpuop_func op_4400_4_nf; +extern cpuop_func op_4400_4_ff; +extern cpuop_func op_4410_4_nf; +extern cpuop_func op_4410_4_ff; +extern cpuop_func op_4418_4_nf; +extern cpuop_func op_4418_4_ff; +extern cpuop_func op_4420_4_nf; +extern cpuop_func op_4420_4_ff; +extern cpuop_func op_4428_4_nf; +extern cpuop_func op_4428_4_ff; +extern cpuop_func op_4430_4_nf; +extern cpuop_func op_4430_4_ff; +extern cpuop_func op_4438_4_nf; +extern cpuop_func op_4438_4_ff; +extern cpuop_func op_4439_4_nf; +extern cpuop_func op_4439_4_ff; +extern cpuop_func op_4440_4_nf; +extern cpuop_func op_4440_4_ff; +extern cpuop_func op_4450_4_nf; +extern cpuop_func op_4450_4_ff; +extern cpuop_func op_4458_4_nf; +extern cpuop_func op_4458_4_ff; +extern cpuop_func op_4460_4_nf; +extern cpuop_func op_4460_4_ff; +extern cpuop_func op_4468_4_nf; +extern cpuop_func op_4468_4_ff; +extern cpuop_func op_4470_4_nf; +extern cpuop_func op_4470_4_ff; +extern cpuop_func op_4478_4_nf; +extern cpuop_func op_4478_4_ff; +extern cpuop_func op_4479_4_nf; +extern cpuop_func op_4479_4_ff; +extern cpuop_func op_4480_4_nf; +extern cpuop_func op_4480_4_ff; +extern cpuop_func op_4490_4_nf; +extern cpuop_func op_4490_4_ff; +extern cpuop_func op_4498_4_nf; +extern cpuop_func op_4498_4_ff; +extern cpuop_func op_44a0_4_nf; +extern cpuop_func op_44a0_4_ff; +extern cpuop_func op_44a8_4_nf; +extern cpuop_func op_44a8_4_ff; +extern cpuop_func op_44b0_4_nf; +extern cpuop_func op_44b0_4_ff; +extern cpuop_func op_44b8_4_nf; +extern cpuop_func op_44b8_4_ff; +extern cpuop_func op_44b9_4_nf; +extern cpuop_func op_44b9_4_ff; +extern cpuop_func op_44c0_4_nf; +extern cpuop_func op_44c0_4_ff; +extern cpuop_func op_44d0_4_nf; +extern cpuop_func op_44d0_4_ff; +extern cpuop_func op_44d8_4_nf; +extern cpuop_func op_44d8_4_ff; +extern cpuop_func op_44e0_4_nf; +extern cpuop_func op_44e0_4_ff; +extern cpuop_func op_44e8_4_nf; +extern cpuop_func op_44e8_4_ff; +extern cpuop_func op_44f0_4_nf; +extern cpuop_func op_44f0_4_ff; +extern cpuop_func op_44f8_4_nf; +extern cpuop_func op_44f8_4_ff; +extern cpuop_func op_44f9_4_nf; +extern cpuop_func op_44f9_4_ff; +extern cpuop_func op_44fa_4_nf; +extern cpuop_func op_44fa_4_ff; +extern cpuop_func op_44fb_4_nf; +extern cpuop_func op_44fb_4_ff; +extern cpuop_func op_44fc_4_nf; +extern cpuop_func op_44fc_4_ff; +extern cpuop_func op_4600_4_nf; +extern cpuop_func op_4600_4_ff; +extern cpuop_func op_4610_4_nf; +extern cpuop_func op_4610_4_ff; +extern cpuop_func op_4618_4_nf; +extern cpuop_func op_4618_4_ff; +extern cpuop_func op_4620_4_nf; +extern cpuop_func op_4620_4_ff; +extern cpuop_func op_4628_4_nf; +extern cpuop_func op_4628_4_ff; +extern cpuop_func op_4630_4_nf; +extern cpuop_func op_4630_4_ff; +extern cpuop_func op_4638_4_nf; +extern cpuop_func op_4638_4_ff; +extern cpuop_func op_4639_4_nf; +extern cpuop_func op_4639_4_ff; +extern cpuop_func op_4640_4_nf; +extern cpuop_func op_4640_4_ff; +extern cpuop_func op_4650_4_nf; +extern cpuop_func op_4650_4_ff; +extern cpuop_func op_4658_4_nf; +extern cpuop_func op_4658_4_ff; +extern cpuop_func op_4660_4_nf; +extern cpuop_func op_4660_4_ff; +extern cpuop_func op_4668_4_nf; +extern cpuop_func op_4668_4_ff; +extern cpuop_func op_4670_4_nf; +extern cpuop_func op_4670_4_ff; +extern cpuop_func op_4678_4_nf; +extern cpuop_func op_4678_4_ff; +extern cpuop_func op_4679_4_nf; +extern cpuop_func op_4679_4_ff; +extern cpuop_func op_4680_4_nf; +extern cpuop_func op_4680_4_ff; +extern cpuop_func op_4690_4_nf; +extern cpuop_func op_4690_4_ff; +extern cpuop_func op_4698_4_nf; +extern cpuop_func op_4698_4_ff; +extern cpuop_func op_46a0_4_nf; +extern cpuop_func op_46a0_4_ff; +extern cpuop_func op_46a8_4_nf; +extern cpuop_func op_46a8_4_ff; +extern cpuop_func op_46b0_4_nf; +extern cpuop_func op_46b0_4_ff; +extern cpuop_func op_46b8_4_nf; +extern cpuop_func op_46b8_4_ff; +extern cpuop_func op_46b9_4_nf; +extern cpuop_func op_46b9_4_ff; +extern cpuop_func op_46c0_4_nf; +extern cpuop_func op_46c0_4_ff; +extern cpuop_func op_46d0_4_nf; +extern cpuop_func op_46d0_4_ff; +extern cpuop_func op_46d8_4_nf; +extern cpuop_func op_46d8_4_ff; +extern cpuop_func op_46e0_4_nf; +extern cpuop_func op_46e0_4_ff; +extern cpuop_func op_46e8_4_nf; +extern cpuop_func op_46e8_4_ff; +extern cpuop_func op_46f0_4_nf; +extern cpuop_func op_46f0_4_ff; +extern cpuop_func op_46f8_4_nf; +extern cpuop_func op_46f8_4_ff; +extern cpuop_func op_46f9_4_nf; +extern cpuop_func op_46f9_4_ff; +extern cpuop_func op_46fa_4_nf; +extern cpuop_func op_46fa_4_ff; +extern cpuop_func op_46fb_4_nf; +extern cpuop_func op_46fb_4_ff; +extern cpuop_func op_46fc_4_nf; +extern cpuop_func op_46fc_4_ff; +extern cpuop_func op_4800_4_nf; +extern cpuop_func op_4800_4_ff; +extern cpuop_func op_4810_4_nf; +extern cpuop_func op_4810_4_ff; +extern cpuop_func op_4818_4_nf; +extern cpuop_func op_4818_4_ff; +extern cpuop_func op_4820_4_nf; +extern cpuop_func op_4820_4_ff; +extern cpuop_func op_4828_4_nf; +extern cpuop_func op_4828_4_ff; +extern cpuop_func op_4830_4_nf; +extern cpuop_func op_4830_4_ff; +extern cpuop_func op_4838_4_nf; +extern cpuop_func op_4838_4_ff; +extern cpuop_func op_4839_4_nf; +extern cpuop_func op_4839_4_ff; +extern cpuop_func op_4840_4_nf; +extern cpuop_func op_4840_4_ff; +extern cpuop_func op_4850_4_nf; +extern cpuop_func op_4850_4_ff; +extern cpuop_func op_4868_4_nf; +extern cpuop_func op_4868_4_ff; +extern cpuop_func op_4870_4_nf; +extern cpuop_func op_4870_4_ff; +extern cpuop_func op_4878_4_nf; +extern cpuop_func op_4878_4_ff; +extern cpuop_func op_4879_4_nf; +extern cpuop_func op_4879_4_ff; +extern cpuop_func op_487a_4_nf; +extern cpuop_func op_487a_4_ff; +extern cpuop_func op_487b_4_nf; +extern cpuop_func op_487b_4_ff; +extern cpuop_func op_4880_4_nf; +extern cpuop_func op_4880_4_ff; +extern cpuop_func op_4890_4_nf; +extern cpuop_func op_4890_4_ff; +extern cpuop_func op_48a0_4_nf; +extern cpuop_func op_48a0_4_ff; +extern cpuop_func op_48a8_4_nf; +extern cpuop_func op_48a8_4_ff; +extern cpuop_func op_48b0_4_nf; +extern cpuop_func op_48b0_4_ff; +extern cpuop_func op_48b8_4_nf; +extern cpuop_func op_48b8_4_ff; +extern cpuop_func op_48b9_4_nf; +extern cpuop_func op_48b9_4_ff; +extern cpuop_func op_48c0_4_nf; +extern cpuop_func op_48c0_4_ff; +extern cpuop_func op_48d0_4_nf; +extern cpuop_func op_48d0_4_ff; +extern cpuop_func op_48e0_4_nf; +extern cpuop_func op_48e0_4_ff; +extern cpuop_func op_48e8_4_nf; +extern cpuop_func op_48e8_4_ff; +extern cpuop_func op_48f0_4_nf; +extern cpuop_func op_48f0_4_ff; +extern cpuop_func op_48f8_4_nf; +extern cpuop_func op_48f8_4_ff; +extern cpuop_func op_48f9_4_nf; +extern cpuop_func op_48f9_4_ff; +extern cpuop_func op_4a00_4_nf; +extern cpuop_func op_4a00_4_ff; +extern cpuop_func op_4a10_4_nf; +extern cpuop_func op_4a10_4_ff; +extern cpuop_func op_4a18_4_nf; +extern cpuop_func op_4a18_4_ff; +extern cpuop_func op_4a20_4_nf; +extern cpuop_func op_4a20_4_ff; +extern cpuop_func op_4a28_4_nf; +extern cpuop_func op_4a28_4_ff; +extern cpuop_func op_4a30_4_nf; +extern cpuop_func op_4a30_4_ff; +extern cpuop_func op_4a38_4_nf; +extern cpuop_func op_4a38_4_ff; +extern cpuop_func op_4a39_4_nf; +extern cpuop_func op_4a39_4_ff; +extern cpuop_func op_4a3a_4_nf; +extern cpuop_func op_4a3a_4_ff; +extern cpuop_func op_4a3b_4_nf; +extern cpuop_func op_4a3b_4_ff; +extern cpuop_func op_4a3c_4_nf; +extern cpuop_func op_4a3c_4_ff; +extern cpuop_func op_4a40_4_nf; +extern cpuop_func op_4a40_4_ff; +extern cpuop_func op_4a48_4_nf; +extern cpuop_func op_4a48_4_ff; +extern cpuop_func op_4a50_4_nf; +extern cpuop_func op_4a50_4_ff; +extern cpuop_func op_4a58_4_nf; +extern cpuop_func op_4a58_4_ff; +extern cpuop_func op_4a60_4_nf; +extern cpuop_func op_4a60_4_ff; +extern cpuop_func op_4a68_4_nf; +extern cpuop_func op_4a68_4_ff; +extern cpuop_func op_4a70_4_nf; +extern cpuop_func op_4a70_4_ff; +extern cpuop_func op_4a78_4_nf; +extern cpuop_func op_4a78_4_ff; +extern cpuop_func op_4a79_4_nf; +extern cpuop_func op_4a79_4_ff; +extern cpuop_func op_4a7a_4_nf; +extern cpuop_func op_4a7a_4_ff; +extern cpuop_func op_4a7b_4_nf; +extern cpuop_func op_4a7b_4_ff; +extern cpuop_func op_4a7c_4_nf; +extern cpuop_func op_4a7c_4_ff; +extern cpuop_func op_4a80_4_nf; +extern cpuop_func op_4a80_4_ff; +extern cpuop_func op_4a88_4_nf; +extern cpuop_func op_4a88_4_ff; +extern cpuop_func op_4a90_4_nf; +extern cpuop_func op_4a90_4_ff; +extern cpuop_func op_4a98_4_nf; +extern cpuop_func op_4a98_4_ff; +extern cpuop_func op_4aa0_4_nf; +extern cpuop_func op_4aa0_4_ff; +extern cpuop_func op_4aa8_4_nf; +extern cpuop_func op_4aa8_4_ff; +extern cpuop_func op_4ab0_4_nf; +extern cpuop_func op_4ab0_4_ff; +extern cpuop_func op_4ab8_4_nf; +extern cpuop_func op_4ab8_4_ff; +extern cpuop_func op_4ab9_4_nf; +extern cpuop_func op_4ab9_4_ff; +extern cpuop_func op_4aba_4_nf; +extern cpuop_func op_4aba_4_ff; +extern cpuop_func op_4abb_4_nf; +extern cpuop_func op_4abb_4_ff; +extern cpuop_func op_4abc_4_nf; +extern cpuop_func op_4abc_4_ff; +extern cpuop_func op_4ac0_4_nf; +extern cpuop_func op_4ac0_4_ff; +extern cpuop_func op_4ad0_4_nf; +extern cpuop_func op_4ad0_4_ff; +extern cpuop_func op_4ad8_4_nf; +extern cpuop_func op_4ad8_4_ff; +extern cpuop_func op_4ae0_4_nf; +extern cpuop_func op_4ae0_4_ff; +extern cpuop_func op_4ae8_4_nf; +extern cpuop_func op_4ae8_4_ff; +extern cpuop_func op_4af0_4_nf; +extern cpuop_func op_4af0_4_ff; +extern cpuop_func op_4af8_4_nf; +extern cpuop_func op_4af8_4_ff; +extern cpuop_func op_4af9_4_nf; +extern cpuop_func op_4af9_4_ff; +extern cpuop_func op_4c90_4_nf; +extern cpuop_func op_4c90_4_ff; +extern cpuop_func op_4c98_4_nf; +extern cpuop_func op_4c98_4_ff; +extern cpuop_func op_4ca8_4_nf; +extern cpuop_func op_4ca8_4_ff; +extern cpuop_func op_4cb0_4_nf; +extern cpuop_func op_4cb0_4_ff; +extern cpuop_func op_4cb8_4_nf; +extern cpuop_func op_4cb8_4_ff; +extern cpuop_func op_4cb9_4_nf; +extern cpuop_func op_4cb9_4_ff; +extern cpuop_func op_4cba_4_nf; +extern cpuop_func op_4cba_4_ff; +extern cpuop_func op_4cbb_4_nf; +extern cpuop_func op_4cbb_4_ff; +extern cpuop_func op_4cd0_4_nf; +extern cpuop_func op_4cd0_4_ff; +extern cpuop_func op_4cd8_4_nf; +extern cpuop_func op_4cd8_4_ff; +extern cpuop_func op_4ce8_4_nf; +extern cpuop_func op_4ce8_4_ff; +extern cpuop_func op_4cf0_4_nf; +extern cpuop_func op_4cf0_4_ff; +extern cpuop_func op_4cf8_4_nf; +extern cpuop_func op_4cf8_4_ff; +extern cpuop_func op_4cf9_4_nf; +extern cpuop_func op_4cf9_4_ff; +extern cpuop_func op_4cfa_4_nf; +extern cpuop_func op_4cfa_4_ff; +extern cpuop_func op_4cfb_4_nf; +extern cpuop_func op_4cfb_4_ff; +extern cpuop_func op_4e40_4_nf; +extern cpuop_func op_4e40_4_ff; +extern cpuop_func op_4e50_4_nf; +extern cpuop_func op_4e50_4_ff; +extern cpuop_func op_4e58_4_nf; +extern cpuop_func op_4e58_4_ff; +extern cpuop_func op_4e60_4_nf; +extern cpuop_func op_4e60_4_ff; +extern cpuop_func op_4e68_4_nf; +extern cpuop_func op_4e68_4_ff; +extern cpuop_func op_4e70_4_nf; +extern cpuop_func op_4e70_4_ff; +extern cpuop_func op_4e71_4_nf; +extern cpuop_func op_4e71_4_ff; +extern cpuop_func op_4e72_4_nf; +extern cpuop_func op_4e72_4_ff; +extern cpuop_func op_4e73_4_nf; +extern cpuop_func op_4e73_4_ff; +extern cpuop_func op_4e74_4_nf; +extern cpuop_func op_4e74_4_ff; +extern cpuop_func op_4e75_4_nf; +extern cpuop_func op_4e75_4_ff; +extern cpuop_func op_4e76_4_nf; +extern cpuop_func op_4e76_4_ff; +extern cpuop_func op_4e77_4_nf; +extern cpuop_func op_4e77_4_ff; +extern cpuop_func op_4e90_4_nf; +extern cpuop_func op_4e90_4_ff; +extern cpuop_func op_4ea8_4_nf; +extern cpuop_func op_4ea8_4_ff; +extern cpuop_func op_4eb0_4_nf; +extern cpuop_func op_4eb0_4_ff; +extern cpuop_func op_4eb8_4_nf; +extern cpuop_func op_4eb8_4_ff; +extern cpuop_func op_4eb9_4_nf; +extern cpuop_func op_4eb9_4_ff; +extern cpuop_func op_4eba_4_nf; +extern cpuop_func op_4eba_4_ff; +extern cpuop_func op_4ebb_4_nf; +extern cpuop_func op_4ebb_4_ff; +extern cpuop_func op_4ed0_4_nf; +extern cpuop_func op_4ed0_4_ff; +extern cpuop_func op_4ee8_4_nf; +extern cpuop_func op_4ee8_4_ff; +extern cpuop_func op_4ef0_4_nf; +extern cpuop_func op_4ef0_4_ff; +extern cpuop_func op_4ef8_4_nf; +extern cpuop_func op_4ef8_4_ff; +extern cpuop_func op_4ef9_4_nf; +extern cpuop_func op_4ef9_4_ff; +extern cpuop_func op_4efa_4_nf; +extern cpuop_func op_4efa_4_ff; +extern cpuop_func op_4efb_4_nf; +extern cpuop_func op_4efb_4_ff; +extern cpuop_func op_5000_4_nf; +extern cpuop_func op_5000_4_ff; +extern cpuop_func op_5010_4_nf; +extern cpuop_func op_5010_4_ff; +extern cpuop_func op_5018_4_nf; +extern cpuop_func op_5018_4_ff; +extern cpuop_func op_5020_4_nf; +extern cpuop_func op_5020_4_ff; +extern cpuop_func op_5028_4_nf; +extern cpuop_func op_5028_4_ff; +extern cpuop_func op_5030_4_nf; +extern cpuop_func op_5030_4_ff; +extern cpuop_func op_5038_4_nf; +extern cpuop_func op_5038_4_ff; +extern cpuop_func op_5039_4_nf; +extern cpuop_func op_5039_4_ff; +extern cpuop_func op_5040_4_nf; +extern cpuop_func op_5040_4_ff; +extern cpuop_func op_5048_4_nf; +extern cpuop_func op_5048_4_ff; +extern cpuop_func op_5050_4_nf; +extern cpuop_func op_5050_4_ff; +extern cpuop_func op_5058_4_nf; +extern cpuop_func op_5058_4_ff; +extern cpuop_func op_5060_4_nf; +extern cpuop_func op_5060_4_ff; +extern cpuop_func op_5068_4_nf; +extern cpuop_func op_5068_4_ff; +extern cpuop_func op_5070_4_nf; +extern cpuop_func op_5070_4_ff; +extern cpuop_func op_5078_4_nf; +extern cpuop_func op_5078_4_ff; +extern cpuop_func op_5079_4_nf; +extern cpuop_func op_5079_4_ff; +extern cpuop_func op_5080_4_nf; +extern cpuop_func op_5080_4_ff; +extern cpuop_func op_5088_4_nf; +extern cpuop_func op_5088_4_ff; +extern cpuop_func op_5090_4_nf; +extern cpuop_func op_5090_4_ff; +extern cpuop_func op_5098_4_nf; +extern cpuop_func op_5098_4_ff; +extern cpuop_func op_50a0_4_nf; +extern cpuop_func op_50a0_4_ff; +extern cpuop_func op_50a8_4_nf; +extern cpuop_func op_50a8_4_ff; +extern cpuop_func op_50b0_4_nf; +extern cpuop_func op_50b0_4_ff; +extern cpuop_func op_50b8_4_nf; +extern cpuop_func op_50b8_4_ff; +extern cpuop_func op_50b9_4_nf; +extern cpuop_func op_50b9_4_ff; +extern cpuop_func op_50c0_4_nf; +extern cpuop_func op_50c0_4_ff; +extern cpuop_func op_50c8_4_nf; +extern cpuop_func op_50c8_4_ff; +extern cpuop_func op_50d0_4_nf; +extern cpuop_func op_50d0_4_ff; +extern cpuop_func op_50d8_4_nf; +extern cpuop_func op_50d8_4_ff; +extern cpuop_func op_50e0_4_nf; +extern cpuop_func op_50e0_4_ff; +extern cpuop_func op_50e8_4_nf; +extern cpuop_func op_50e8_4_ff; +extern cpuop_func op_50f0_4_nf; +extern cpuop_func op_50f0_4_ff; +extern cpuop_func op_50f8_4_nf; +extern cpuop_func op_50f8_4_ff; +extern cpuop_func op_50f9_4_nf; +extern cpuop_func op_50f9_4_ff; +extern cpuop_func op_5100_4_nf; +extern cpuop_func op_5100_4_ff; +extern cpuop_func op_5110_4_nf; +extern cpuop_func op_5110_4_ff; +extern cpuop_func op_5118_4_nf; +extern cpuop_func op_5118_4_ff; +extern cpuop_func op_5120_4_nf; +extern cpuop_func op_5120_4_ff; +extern cpuop_func op_5128_4_nf; +extern cpuop_func op_5128_4_ff; +extern cpuop_func op_5130_4_nf; +extern cpuop_func op_5130_4_ff; +extern cpuop_func op_5138_4_nf; +extern cpuop_func op_5138_4_ff; +extern cpuop_func op_5139_4_nf; +extern cpuop_func op_5139_4_ff; +extern cpuop_func op_5140_4_nf; +extern cpuop_func op_5140_4_ff; +extern cpuop_func op_5148_4_nf; +extern cpuop_func op_5148_4_ff; +extern cpuop_func op_5150_4_nf; +extern cpuop_func op_5150_4_ff; +extern cpuop_func op_5158_4_nf; +extern cpuop_func op_5158_4_ff; +extern cpuop_func op_5160_4_nf; +extern cpuop_func op_5160_4_ff; +extern cpuop_func op_5168_4_nf; +extern cpuop_func op_5168_4_ff; +extern cpuop_func op_5170_4_nf; +extern cpuop_func op_5170_4_ff; +extern cpuop_func op_5178_4_nf; +extern cpuop_func op_5178_4_ff; +extern cpuop_func op_5179_4_nf; +extern cpuop_func op_5179_4_ff; +extern cpuop_func op_5180_4_nf; +extern cpuop_func op_5180_4_ff; +extern cpuop_func op_5188_4_nf; +extern cpuop_func op_5188_4_ff; +extern cpuop_func op_5190_4_nf; +extern cpuop_func op_5190_4_ff; +extern cpuop_func op_5198_4_nf; +extern cpuop_func op_5198_4_ff; +extern cpuop_func op_51a0_4_nf; +extern cpuop_func op_51a0_4_ff; +extern cpuop_func op_51a8_4_nf; +extern cpuop_func op_51a8_4_ff; +extern cpuop_func op_51b0_4_nf; +extern cpuop_func op_51b0_4_ff; +extern cpuop_func op_51b8_4_nf; +extern cpuop_func op_51b8_4_ff; +extern cpuop_func op_51b9_4_nf; +extern cpuop_func op_51b9_4_ff; +extern cpuop_func op_51c0_4_nf; +extern cpuop_func op_51c0_4_ff; +extern cpuop_func op_51c8_4_nf; +extern cpuop_func op_51c8_4_ff; +extern cpuop_func op_51d0_4_nf; +extern cpuop_func op_51d0_4_ff; +extern cpuop_func op_51d8_4_nf; +extern cpuop_func op_51d8_4_ff; +extern cpuop_func op_51e0_4_nf; +extern cpuop_func op_51e0_4_ff; +extern cpuop_func op_51e8_4_nf; +extern cpuop_func op_51e8_4_ff; +extern cpuop_func op_51f0_4_nf; +extern cpuop_func op_51f0_4_ff; +extern cpuop_func op_51f8_4_nf; +extern cpuop_func op_51f8_4_ff; +extern cpuop_func op_51f9_4_nf; +extern cpuop_func op_51f9_4_ff; +extern cpuop_func op_52c0_4_nf; +extern cpuop_func op_52c0_4_ff; +extern cpuop_func op_52c8_4_nf; +extern cpuop_func op_52c8_4_ff; +extern cpuop_func op_52d0_4_nf; +extern cpuop_func op_52d0_4_ff; +extern cpuop_func op_52d8_4_nf; +extern cpuop_func op_52d8_4_ff; +extern cpuop_func op_52e0_4_nf; +extern cpuop_func op_52e0_4_ff; +extern cpuop_func op_52e8_4_nf; +extern cpuop_func op_52e8_4_ff; +extern cpuop_func op_52f0_4_nf; +extern cpuop_func op_52f0_4_ff; +extern cpuop_func op_52f8_4_nf; +extern cpuop_func op_52f8_4_ff; +extern cpuop_func op_52f9_4_nf; +extern cpuop_func op_52f9_4_ff; +extern cpuop_func op_53c0_4_nf; +extern cpuop_func op_53c0_4_ff; +extern cpuop_func op_53c8_4_nf; +extern cpuop_func op_53c8_4_ff; +extern cpuop_func op_53d0_4_nf; +extern cpuop_func op_53d0_4_ff; +extern cpuop_func op_53d8_4_nf; +extern cpuop_func op_53d8_4_ff; +extern cpuop_func op_53e0_4_nf; +extern cpuop_func op_53e0_4_ff; +extern cpuop_func op_53e8_4_nf; +extern cpuop_func op_53e8_4_ff; +extern cpuop_func op_53f0_4_nf; +extern cpuop_func op_53f0_4_ff; +extern cpuop_func op_53f8_4_nf; +extern cpuop_func op_53f8_4_ff; +extern cpuop_func op_53f9_4_nf; +extern cpuop_func op_53f9_4_ff; +extern cpuop_func op_54c0_4_nf; +extern cpuop_func op_54c0_4_ff; +extern cpuop_func op_54c8_4_nf; +extern cpuop_func op_54c8_4_ff; +extern cpuop_func op_54d0_4_nf; +extern cpuop_func op_54d0_4_ff; +extern cpuop_func op_54d8_4_nf; +extern cpuop_func op_54d8_4_ff; +extern cpuop_func op_54e0_4_nf; +extern cpuop_func op_54e0_4_ff; +extern cpuop_func op_54e8_4_nf; +extern cpuop_func op_54e8_4_ff; +extern cpuop_func op_54f0_4_nf; +extern cpuop_func op_54f0_4_ff; +extern cpuop_func op_54f8_4_nf; +extern cpuop_func op_54f8_4_ff; +extern cpuop_func op_54f9_4_nf; +extern cpuop_func op_54f9_4_ff; +extern cpuop_func op_55c0_4_nf; +extern cpuop_func op_55c0_4_ff; +extern cpuop_func op_55c8_4_nf; +extern cpuop_func op_55c8_4_ff; +extern cpuop_func op_55d0_4_nf; +extern cpuop_func op_55d0_4_ff; +extern cpuop_func op_55d8_4_nf; +extern cpuop_func op_55d8_4_ff; +extern cpuop_func op_55e0_4_nf; +extern cpuop_func op_55e0_4_ff; +extern cpuop_func op_55e8_4_nf; +extern cpuop_func op_55e8_4_ff; +extern cpuop_func op_55f0_4_nf; +extern cpuop_func op_55f0_4_ff; +extern cpuop_func op_55f8_4_nf; +extern cpuop_func op_55f8_4_ff; +extern cpuop_func op_55f9_4_nf; +extern cpuop_func op_55f9_4_ff; +extern cpuop_func op_56c0_4_nf; +extern cpuop_func op_56c0_4_ff; +extern cpuop_func op_56c8_4_nf; +extern cpuop_func op_56c8_4_ff; +extern cpuop_func op_56d0_4_nf; +extern cpuop_func op_56d0_4_ff; +extern cpuop_func op_56d8_4_nf; +extern cpuop_func op_56d8_4_ff; +extern cpuop_func op_56e0_4_nf; +extern cpuop_func op_56e0_4_ff; +extern cpuop_func op_56e8_4_nf; +extern cpuop_func op_56e8_4_ff; +extern cpuop_func op_56f0_4_nf; +extern cpuop_func op_56f0_4_ff; +extern cpuop_func op_56f8_4_nf; +extern cpuop_func op_56f8_4_ff; +extern cpuop_func op_56f9_4_nf; +extern cpuop_func op_56f9_4_ff; +extern cpuop_func op_57c0_4_nf; +extern cpuop_func op_57c0_4_ff; +extern cpuop_func op_57c8_4_nf; +extern cpuop_func op_57c8_4_ff; +extern cpuop_func op_57d0_4_nf; +extern cpuop_func op_57d0_4_ff; +extern cpuop_func op_57d8_4_nf; +extern cpuop_func op_57d8_4_ff; +extern cpuop_func op_57e0_4_nf; +extern cpuop_func op_57e0_4_ff; +extern cpuop_func op_57e8_4_nf; +extern cpuop_func op_57e8_4_ff; +extern cpuop_func op_57f0_4_nf; +extern cpuop_func op_57f0_4_ff; +extern cpuop_func op_57f8_4_nf; +extern cpuop_func op_57f8_4_ff; +extern cpuop_func op_57f9_4_nf; +extern cpuop_func op_57f9_4_ff; +extern cpuop_func op_58c0_4_nf; +extern cpuop_func op_58c0_4_ff; +extern cpuop_func op_58c8_4_nf; +extern cpuop_func op_58c8_4_ff; +extern cpuop_func op_58d0_4_nf; +extern cpuop_func op_58d0_4_ff; +extern cpuop_func op_58d8_4_nf; +extern cpuop_func op_58d8_4_ff; +extern cpuop_func op_58e0_4_nf; +extern cpuop_func op_58e0_4_ff; +extern cpuop_func op_58e8_4_nf; +extern cpuop_func op_58e8_4_ff; +extern cpuop_func op_58f0_4_nf; +extern cpuop_func op_58f0_4_ff; +extern cpuop_func op_58f8_4_nf; +extern cpuop_func op_58f8_4_ff; +extern cpuop_func op_58f9_4_nf; +extern cpuop_func op_58f9_4_ff; +extern cpuop_func op_59c0_4_nf; +extern cpuop_func op_59c0_4_ff; +extern cpuop_func op_59c8_4_nf; +extern cpuop_func op_59c8_4_ff; +extern cpuop_func op_59d0_4_nf; +extern cpuop_func op_59d0_4_ff; +extern cpuop_func op_59d8_4_nf; +extern cpuop_func op_59d8_4_ff; +extern cpuop_func op_59e0_4_nf; +extern cpuop_func op_59e0_4_ff; +extern cpuop_func op_59e8_4_nf; +extern cpuop_func op_59e8_4_ff; +extern cpuop_func op_59f0_4_nf; +extern cpuop_func op_59f0_4_ff; +extern cpuop_func op_59f8_4_nf; +extern cpuop_func op_59f8_4_ff; +extern cpuop_func op_59f9_4_nf; +extern cpuop_func op_59f9_4_ff; +extern cpuop_func op_5ac0_4_nf; +extern cpuop_func op_5ac0_4_ff; +extern cpuop_func op_5ac8_4_nf; +extern cpuop_func op_5ac8_4_ff; +extern cpuop_func op_5ad0_4_nf; +extern cpuop_func op_5ad0_4_ff; +extern cpuop_func op_5ad8_4_nf; +extern cpuop_func op_5ad8_4_ff; +extern cpuop_func op_5ae0_4_nf; +extern cpuop_func op_5ae0_4_ff; +extern cpuop_func op_5ae8_4_nf; +extern cpuop_func op_5ae8_4_ff; +extern cpuop_func op_5af0_4_nf; +extern cpuop_func op_5af0_4_ff; +extern cpuop_func op_5af8_4_nf; +extern cpuop_func op_5af8_4_ff; +extern cpuop_func op_5af9_4_nf; +extern cpuop_func op_5af9_4_ff; +extern cpuop_func op_5bc0_4_nf; +extern cpuop_func op_5bc0_4_ff; +extern cpuop_func op_5bc8_4_nf; +extern cpuop_func op_5bc8_4_ff; +extern cpuop_func op_5bd0_4_nf; +extern cpuop_func op_5bd0_4_ff; +extern cpuop_func op_5bd8_4_nf; +extern cpuop_func op_5bd8_4_ff; +extern cpuop_func op_5be0_4_nf; +extern cpuop_func op_5be0_4_ff; +extern cpuop_func op_5be8_4_nf; +extern cpuop_func op_5be8_4_ff; +extern cpuop_func op_5bf0_4_nf; +extern cpuop_func op_5bf0_4_ff; +extern cpuop_func op_5bf8_4_nf; +extern cpuop_func op_5bf8_4_ff; +extern cpuop_func op_5bf9_4_nf; +extern cpuop_func op_5bf9_4_ff; +extern cpuop_func op_5cc0_4_nf; +extern cpuop_func op_5cc0_4_ff; +extern cpuop_func op_5cc8_4_nf; +extern cpuop_func op_5cc8_4_ff; +extern cpuop_func op_5cd0_4_nf; +extern cpuop_func op_5cd0_4_ff; +extern cpuop_func op_5cd8_4_nf; +extern cpuop_func op_5cd8_4_ff; +extern cpuop_func op_5ce0_4_nf; +extern cpuop_func op_5ce0_4_ff; +extern cpuop_func op_5ce8_4_nf; +extern cpuop_func op_5ce8_4_ff; +extern cpuop_func op_5cf0_4_nf; +extern cpuop_func op_5cf0_4_ff; +extern cpuop_func op_5cf8_4_nf; +extern cpuop_func op_5cf8_4_ff; +extern cpuop_func op_5cf9_4_nf; +extern cpuop_func op_5cf9_4_ff; +extern cpuop_func op_5dc0_4_nf; +extern cpuop_func op_5dc0_4_ff; +extern cpuop_func op_5dc8_4_nf; +extern cpuop_func op_5dc8_4_ff; +extern cpuop_func op_5dd0_4_nf; +extern cpuop_func op_5dd0_4_ff; +extern cpuop_func op_5dd8_4_nf; +extern cpuop_func op_5dd8_4_ff; +extern cpuop_func op_5de0_4_nf; +extern cpuop_func op_5de0_4_ff; +extern cpuop_func op_5de8_4_nf; +extern cpuop_func op_5de8_4_ff; +extern cpuop_func op_5df0_4_nf; +extern cpuop_func op_5df0_4_ff; +extern cpuop_func op_5df8_4_nf; +extern cpuop_func op_5df8_4_ff; +extern cpuop_func op_5df9_4_nf; +extern cpuop_func op_5df9_4_ff; +extern cpuop_func op_5ec0_4_nf; +extern cpuop_func op_5ec0_4_ff; +extern cpuop_func op_5ec8_4_nf; +extern cpuop_func op_5ec8_4_ff; +extern cpuop_func op_5ed0_4_nf; +extern cpuop_func op_5ed0_4_ff; +extern cpuop_func op_5ed8_4_nf; +extern cpuop_func op_5ed8_4_ff; +extern cpuop_func op_5ee0_4_nf; +extern cpuop_func op_5ee0_4_ff; +extern cpuop_func op_5ee8_4_nf; +extern cpuop_func op_5ee8_4_ff; +extern cpuop_func op_5ef0_4_nf; +extern cpuop_func op_5ef0_4_ff; +extern cpuop_func op_5ef8_4_nf; +extern cpuop_func op_5ef8_4_ff; +extern cpuop_func op_5ef9_4_nf; +extern cpuop_func op_5ef9_4_ff; +extern cpuop_func op_5fc0_4_nf; +extern cpuop_func op_5fc0_4_ff; +extern cpuop_func op_5fc8_4_nf; +extern cpuop_func op_5fc8_4_ff; +extern cpuop_func op_5fd0_4_nf; +extern cpuop_func op_5fd0_4_ff; +extern cpuop_func op_5fd8_4_nf; +extern cpuop_func op_5fd8_4_ff; +extern cpuop_func op_5fe0_4_nf; +extern cpuop_func op_5fe0_4_ff; +extern cpuop_func op_5fe8_4_nf; +extern cpuop_func op_5fe8_4_ff; +extern cpuop_func op_5ff0_4_nf; +extern cpuop_func op_5ff0_4_ff; +extern cpuop_func op_5ff8_4_nf; +extern cpuop_func op_5ff8_4_ff; +extern cpuop_func op_5ff9_4_nf; +extern cpuop_func op_5ff9_4_ff; +extern cpuop_func op_6000_4_nf; +extern cpuop_func op_6000_4_ff; +extern cpuop_func op_6001_4_nf; +extern cpuop_func op_6001_4_ff; +extern cpuop_func op_60ff_4_nf; +extern cpuop_func op_60ff_4_ff; +extern cpuop_func op_6100_4_nf; +extern cpuop_func op_6100_4_ff; +extern cpuop_func op_6101_4_nf; +extern cpuop_func op_6101_4_ff; +extern cpuop_func op_61ff_4_nf; +extern cpuop_func op_61ff_4_ff; +extern cpuop_func op_6200_4_nf; +extern cpuop_func op_6200_4_ff; +extern cpuop_func op_6201_4_nf; +extern cpuop_func op_6201_4_ff; +extern cpuop_func op_62ff_4_nf; +extern cpuop_func op_62ff_4_ff; +extern cpuop_func op_6300_4_nf; +extern cpuop_func op_6300_4_ff; +extern cpuop_func op_6301_4_nf; +extern cpuop_func op_6301_4_ff; +extern cpuop_func op_63ff_4_nf; +extern cpuop_func op_63ff_4_ff; +extern cpuop_func op_6400_4_nf; +extern cpuop_func op_6400_4_ff; +extern cpuop_func op_6401_4_nf; +extern cpuop_func op_6401_4_ff; +extern cpuop_func op_64ff_4_nf; +extern cpuop_func op_64ff_4_ff; +extern cpuop_func op_6500_4_nf; +extern cpuop_func op_6500_4_ff; +extern cpuop_func op_6501_4_nf; +extern cpuop_func op_6501_4_ff; +extern cpuop_func op_65ff_4_nf; +extern cpuop_func op_65ff_4_ff; +extern cpuop_func op_6600_4_nf; +extern cpuop_func op_6600_4_ff; +extern cpuop_func op_6601_4_nf; +extern cpuop_func op_6601_4_ff; +extern cpuop_func op_66ff_4_nf; +extern cpuop_func op_66ff_4_ff; +extern cpuop_func op_6700_4_nf; +extern cpuop_func op_6700_4_ff; +extern cpuop_func op_6701_4_nf; +extern cpuop_func op_6701_4_ff; +extern cpuop_func op_67ff_4_nf; +extern cpuop_func op_67ff_4_ff; +extern cpuop_func op_6800_4_nf; +extern cpuop_func op_6800_4_ff; +extern cpuop_func op_6801_4_nf; +extern cpuop_func op_6801_4_ff; +extern cpuop_func op_68ff_4_nf; +extern cpuop_func op_68ff_4_ff; +extern cpuop_func op_6900_4_nf; +extern cpuop_func op_6900_4_ff; +extern cpuop_func op_6901_4_nf; +extern cpuop_func op_6901_4_ff; +extern cpuop_func op_69ff_4_nf; +extern cpuop_func op_69ff_4_ff; +extern cpuop_func op_6a00_4_nf; +extern cpuop_func op_6a00_4_ff; +extern cpuop_func op_6a01_4_nf; +extern cpuop_func op_6a01_4_ff; +extern cpuop_func op_6aff_4_nf; +extern cpuop_func op_6aff_4_ff; +extern cpuop_func op_6b00_4_nf; +extern cpuop_func op_6b00_4_ff; +extern cpuop_func op_6b01_4_nf; +extern cpuop_func op_6b01_4_ff; +extern cpuop_func op_6bff_4_nf; +extern cpuop_func op_6bff_4_ff; +extern cpuop_func op_6c00_4_nf; +extern cpuop_func op_6c00_4_ff; +extern cpuop_func op_6c01_4_nf; +extern cpuop_func op_6c01_4_ff; +extern cpuop_func op_6cff_4_nf; +extern cpuop_func op_6cff_4_ff; +extern cpuop_func op_6d00_4_nf; +extern cpuop_func op_6d00_4_ff; +extern cpuop_func op_6d01_4_nf; +extern cpuop_func op_6d01_4_ff; +extern cpuop_func op_6dff_4_nf; +extern cpuop_func op_6dff_4_ff; +extern cpuop_func op_6e00_4_nf; +extern cpuop_func op_6e00_4_ff; +extern cpuop_func op_6e01_4_nf; +extern cpuop_func op_6e01_4_ff; +extern cpuop_func op_6eff_4_nf; +extern cpuop_func op_6eff_4_ff; +extern cpuop_func op_6f00_4_nf; +extern cpuop_func op_6f00_4_ff; +extern cpuop_func op_6f01_4_nf; +extern cpuop_func op_6f01_4_ff; +extern cpuop_func op_6fff_4_nf; +extern cpuop_func op_6fff_4_ff; +extern cpuop_func op_7000_4_nf; +extern cpuop_func op_7000_4_ff; +extern cpuop_func op_8000_4_nf; +extern cpuop_func op_8000_4_ff; +extern cpuop_func op_8010_4_nf; +extern cpuop_func op_8010_4_ff; +extern cpuop_func op_8018_4_nf; +extern cpuop_func op_8018_4_ff; +extern cpuop_func op_8020_4_nf; +extern cpuop_func op_8020_4_ff; +extern cpuop_func op_8028_4_nf; +extern cpuop_func op_8028_4_ff; +extern cpuop_func op_8030_4_nf; +extern cpuop_func op_8030_4_ff; +extern cpuop_func op_8038_4_nf; +extern cpuop_func op_8038_4_ff; +extern cpuop_func op_8039_4_nf; +extern cpuop_func op_8039_4_ff; +extern cpuop_func op_803a_4_nf; +extern cpuop_func op_803a_4_ff; +extern cpuop_func op_803b_4_nf; +extern cpuop_func op_803b_4_ff; +extern cpuop_func op_803c_4_nf; +extern cpuop_func op_803c_4_ff; +extern cpuop_func op_8040_4_nf; +extern cpuop_func op_8040_4_ff; +extern cpuop_func op_8050_4_nf; +extern cpuop_func op_8050_4_ff; +extern cpuop_func op_8058_4_nf; +extern cpuop_func op_8058_4_ff; +extern cpuop_func op_8060_4_nf; +extern cpuop_func op_8060_4_ff; +extern cpuop_func op_8068_4_nf; +extern cpuop_func op_8068_4_ff; +extern cpuop_func op_8070_4_nf; +extern cpuop_func op_8070_4_ff; +extern cpuop_func op_8078_4_nf; +extern cpuop_func op_8078_4_ff; +extern cpuop_func op_8079_4_nf; +extern cpuop_func op_8079_4_ff; +extern cpuop_func op_807a_4_nf; +extern cpuop_func op_807a_4_ff; +extern cpuop_func op_807b_4_nf; +extern cpuop_func op_807b_4_ff; +extern cpuop_func op_807c_4_nf; +extern cpuop_func op_807c_4_ff; +extern cpuop_func op_8080_4_nf; +extern cpuop_func op_8080_4_ff; +extern cpuop_func op_8090_4_nf; +extern cpuop_func op_8090_4_ff; +extern cpuop_func op_8098_4_nf; +extern cpuop_func op_8098_4_ff; +extern cpuop_func op_80a0_4_nf; +extern cpuop_func op_80a0_4_ff; +extern cpuop_func op_80a8_4_nf; +extern cpuop_func op_80a8_4_ff; +extern cpuop_func op_80b0_4_nf; +extern cpuop_func op_80b0_4_ff; +extern cpuop_func op_80b8_4_nf; +extern cpuop_func op_80b8_4_ff; +extern cpuop_func op_80b9_4_nf; +extern cpuop_func op_80b9_4_ff; +extern cpuop_func op_80ba_4_nf; +extern cpuop_func op_80ba_4_ff; +extern cpuop_func op_80bb_4_nf; +extern cpuop_func op_80bb_4_ff; +extern cpuop_func op_80bc_4_nf; +extern cpuop_func op_80bc_4_ff; +extern cpuop_func op_80c0_4_nf; +extern cpuop_func op_80c0_4_ff; +extern cpuop_func op_80d0_4_nf; +extern cpuop_func op_80d0_4_ff; +extern cpuop_func op_80d8_4_nf; +extern cpuop_func op_80d8_4_ff; +extern cpuop_func op_80e0_4_nf; +extern cpuop_func op_80e0_4_ff; +extern cpuop_func op_80e8_4_nf; +extern cpuop_func op_80e8_4_ff; +extern cpuop_func op_80f0_4_nf; +extern cpuop_func op_80f0_4_ff; +extern cpuop_func op_80f8_4_nf; +extern cpuop_func op_80f8_4_ff; +extern cpuop_func op_80f9_4_nf; +extern cpuop_func op_80f9_4_ff; +extern cpuop_func op_80fa_4_nf; +extern cpuop_func op_80fa_4_ff; +extern cpuop_func op_80fb_4_nf; +extern cpuop_func op_80fb_4_ff; +extern cpuop_func op_80fc_4_nf; +extern cpuop_func op_80fc_4_ff; +extern cpuop_func op_8100_4_nf; +extern cpuop_func op_8100_4_ff; +extern cpuop_func op_8108_4_nf; +extern cpuop_func op_8108_4_ff; +extern cpuop_func op_8110_4_nf; +extern cpuop_func op_8110_4_ff; +extern cpuop_func op_8118_4_nf; +extern cpuop_func op_8118_4_ff; +extern cpuop_func op_8120_4_nf; +extern cpuop_func op_8120_4_ff; +extern cpuop_func op_8128_4_nf; +extern cpuop_func op_8128_4_ff; +extern cpuop_func op_8130_4_nf; +extern cpuop_func op_8130_4_ff; +extern cpuop_func op_8138_4_nf; +extern cpuop_func op_8138_4_ff; +extern cpuop_func op_8139_4_nf; +extern cpuop_func op_8139_4_ff; +extern cpuop_func op_8150_4_nf; +extern cpuop_func op_8150_4_ff; +extern cpuop_func op_8158_4_nf; +extern cpuop_func op_8158_4_ff; +extern cpuop_func op_8160_4_nf; +extern cpuop_func op_8160_4_ff; +extern cpuop_func op_8168_4_nf; +extern cpuop_func op_8168_4_ff; +extern cpuop_func op_8170_4_nf; +extern cpuop_func op_8170_4_ff; +extern cpuop_func op_8178_4_nf; +extern cpuop_func op_8178_4_ff; +extern cpuop_func op_8179_4_nf; +extern cpuop_func op_8179_4_ff; +extern cpuop_func op_8190_4_nf; +extern cpuop_func op_8190_4_ff; +extern cpuop_func op_8198_4_nf; +extern cpuop_func op_8198_4_ff; +extern cpuop_func op_81a0_4_nf; +extern cpuop_func op_81a0_4_ff; +extern cpuop_func op_81a8_4_nf; +extern cpuop_func op_81a8_4_ff; +extern cpuop_func op_81b0_4_nf; +extern cpuop_func op_81b0_4_ff; +extern cpuop_func op_81b8_4_nf; +extern cpuop_func op_81b8_4_ff; +extern cpuop_func op_81b9_4_nf; +extern cpuop_func op_81b9_4_ff; +extern cpuop_func op_81c0_4_nf; +extern cpuop_func op_81c0_4_ff; +extern cpuop_func op_81d0_4_nf; +extern cpuop_func op_81d0_4_ff; +extern cpuop_func op_81d8_4_nf; +extern cpuop_func op_81d8_4_ff; +extern cpuop_func op_81e0_4_nf; +extern cpuop_func op_81e0_4_ff; +extern cpuop_func op_81e8_4_nf; +extern cpuop_func op_81e8_4_ff; +extern cpuop_func op_81f0_4_nf; +extern cpuop_func op_81f0_4_ff; +extern cpuop_func op_81f8_4_nf; +extern cpuop_func op_81f8_4_ff; +extern cpuop_func op_81f9_4_nf; +extern cpuop_func op_81f9_4_ff; +extern cpuop_func op_81fa_4_nf; +extern cpuop_func op_81fa_4_ff; +extern cpuop_func op_81fb_4_nf; +extern cpuop_func op_81fb_4_ff; +extern cpuop_func op_81fc_4_nf; +extern cpuop_func op_81fc_4_ff; +extern cpuop_func op_9000_4_nf; +extern cpuop_func op_9000_4_ff; +extern cpuop_func op_9010_4_nf; +extern cpuop_func op_9010_4_ff; +extern cpuop_func op_9018_4_nf; +extern cpuop_func op_9018_4_ff; +extern cpuop_func op_9020_4_nf; +extern cpuop_func op_9020_4_ff; +extern cpuop_func op_9028_4_nf; +extern cpuop_func op_9028_4_ff; +extern cpuop_func op_9030_4_nf; +extern cpuop_func op_9030_4_ff; +extern cpuop_func op_9038_4_nf; +extern cpuop_func op_9038_4_ff; +extern cpuop_func op_9039_4_nf; +extern cpuop_func op_9039_4_ff; +extern cpuop_func op_903a_4_nf; +extern cpuop_func op_903a_4_ff; +extern cpuop_func op_903b_4_nf; +extern cpuop_func op_903b_4_ff; +extern cpuop_func op_903c_4_nf; +extern cpuop_func op_903c_4_ff; +extern cpuop_func op_9040_4_nf; +extern cpuop_func op_9040_4_ff; +extern cpuop_func op_9048_4_nf; +extern cpuop_func op_9048_4_ff; +extern cpuop_func op_9050_4_nf; +extern cpuop_func op_9050_4_ff; +extern cpuop_func op_9058_4_nf; +extern cpuop_func op_9058_4_ff; +extern cpuop_func op_9060_4_nf; +extern cpuop_func op_9060_4_ff; +extern cpuop_func op_9068_4_nf; +extern cpuop_func op_9068_4_ff; +extern cpuop_func op_9070_4_nf; +extern cpuop_func op_9070_4_ff; +extern cpuop_func op_9078_4_nf; +extern cpuop_func op_9078_4_ff; +extern cpuop_func op_9079_4_nf; +extern cpuop_func op_9079_4_ff; +extern cpuop_func op_907a_4_nf; +extern cpuop_func op_907a_4_ff; +extern cpuop_func op_907b_4_nf; +extern cpuop_func op_907b_4_ff; +extern cpuop_func op_907c_4_nf; +extern cpuop_func op_907c_4_ff; +extern cpuop_func op_9080_4_nf; +extern cpuop_func op_9080_4_ff; +extern cpuop_func op_9088_4_nf; +extern cpuop_func op_9088_4_ff; +extern cpuop_func op_9090_4_nf; +extern cpuop_func op_9090_4_ff; +extern cpuop_func op_9098_4_nf; +extern cpuop_func op_9098_4_ff; +extern cpuop_func op_90a0_4_nf; +extern cpuop_func op_90a0_4_ff; +extern cpuop_func op_90a8_4_nf; +extern cpuop_func op_90a8_4_ff; +extern cpuop_func op_90b0_4_nf; +extern cpuop_func op_90b0_4_ff; +extern cpuop_func op_90b8_4_nf; +extern cpuop_func op_90b8_4_ff; +extern cpuop_func op_90b9_4_nf; +extern cpuop_func op_90b9_4_ff; +extern cpuop_func op_90ba_4_nf; +extern cpuop_func op_90ba_4_ff; +extern cpuop_func op_90bb_4_nf; +extern cpuop_func op_90bb_4_ff; +extern cpuop_func op_90bc_4_nf; +extern cpuop_func op_90bc_4_ff; +extern cpuop_func op_90c0_4_nf; +extern cpuop_func op_90c0_4_ff; +extern cpuop_func op_90c8_4_nf; +extern cpuop_func op_90c8_4_ff; +extern cpuop_func op_90d0_4_nf; +extern cpuop_func op_90d0_4_ff; +extern cpuop_func op_90d8_4_nf; +extern cpuop_func op_90d8_4_ff; +extern cpuop_func op_90e0_4_nf; +extern cpuop_func op_90e0_4_ff; +extern cpuop_func op_90e8_4_nf; +extern cpuop_func op_90e8_4_ff; +extern cpuop_func op_90f0_4_nf; +extern cpuop_func op_90f0_4_ff; +extern cpuop_func op_90f8_4_nf; +extern cpuop_func op_90f8_4_ff; +extern cpuop_func op_90f9_4_nf; +extern cpuop_func op_90f9_4_ff; +extern cpuop_func op_90fa_4_nf; +extern cpuop_func op_90fa_4_ff; +extern cpuop_func op_90fb_4_nf; +extern cpuop_func op_90fb_4_ff; +extern cpuop_func op_90fc_4_nf; +extern cpuop_func op_90fc_4_ff; +extern cpuop_func op_9100_4_nf; +extern cpuop_func op_9100_4_ff; +extern cpuop_func op_9108_4_nf; +extern cpuop_func op_9108_4_ff; +extern cpuop_func op_9110_4_nf; +extern cpuop_func op_9110_4_ff; +extern cpuop_func op_9118_4_nf; +extern cpuop_func op_9118_4_ff; +extern cpuop_func op_9120_4_nf; +extern cpuop_func op_9120_4_ff; +extern cpuop_func op_9128_4_nf; +extern cpuop_func op_9128_4_ff; +extern cpuop_func op_9130_4_nf; +extern cpuop_func op_9130_4_ff; +extern cpuop_func op_9138_4_nf; +extern cpuop_func op_9138_4_ff; +extern cpuop_func op_9139_4_nf; +extern cpuop_func op_9139_4_ff; +extern cpuop_func op_9140_4_nf; +extern cpuop_func op_9140_4_ff; +extern cpuop_func op_9148_4_nf; +extern cpuop_func op_9148_4_ff; +extern cpuop_func op_9150_4_nf; +extern cpuop_func op_9150_4_ff; +extern cpuop_func op_9158_4_nf; +extern cpuop_func op_9158_4_ff; +extern cpuop_func op_9160_4_nf; +extern cpuop_func op_9160_4_ff; +extern cpuop_func op_9168_4_nf; +extern cpuop_func op_9168_4_ff; +extern cpuop_func op_9170_4_nf; +extern cpuop_func op_9170_4_ff; +extern cpuop_func op_9178_4_nf; +extern cpuop_func op_9178_4_ff; +extern cpuop_func op_9179_4_nf; +extern cpuop_func op_9179_4_ff; +extern cpuop_func op_9180_4_nf; +extern cpuop_func op_9180_4_ff; +extern cpuop_func op_9188_4_nf; +extern cpuop_func op_9188_4_ff; +extern cpuop_func op_9190_4_nf; +extern cpuop_func op_9190_4_ff; +extern cpuop_func op_9198_4_nf; +extern cpuop_func op_9198_4_ff; +extern cpuop_func op_91a0_4_nf; +extern cpuop_func op_91a0_4_ff; +extern cpuop_func op_91a8_4_nf; +extern cpuop_func op_91a8_4_ff; +extern cpuop_func op_91b0_4_nf; +extern cpuop_func op_91b0_4_ff; +extern cpuop_func op_91b8_4_nf; +extern cpuop_func op_91b8_4_ff; +extern cpuop_func op_91b9_4_nf; +extern cpuop_func op_91b9_4_ff; +extern cpuop_func op_91c0_4_nf; +extern cpuop_func op_91c0_4_ff; +extern cpuop_func op_91c8_4_nf; +extern cpuop_func op_91c8_4_ff; +extern cpuop_func op_91d0_4_nf; +extern cpuop_func op_91d0_4_ff; +extern cpuop_func op_91d8_4_nf; +extern cpuop_func op_91d8_4_ff; +extern cpuop_func op_91e0_4_nf; +extern cpuop_func op_91e0_4_ff; +extern cpuop_func op_91e8_4_nf; +extern cpuop_func op_91e8_4_ff; +extern cpuop_func op_91f0_4_nf; +extern cpuop_func op_91f0_4_ff; +extern cpuop_func op_91f8_4_nf; +extern cpuop_func op_91f8_4_ff; +extern cpuop_func op_91f9_4_nf; +extern cpuop_func op_91f9_4_ff; +extern cpuop_func op_91fa_4_nf; +extern cpuop_func op_91fa_4_ff; +extern cpuop_func op_91fb_4_nf; +extern cpuop_func op_91fb_4_ff; +extern cpuop_func op_91fc_4_nf; +extern cpuop_func op_91fc_4_ff; +extern cpuop_func op_b000_4_nf; +extern cpuop_func op_b000_4_ff; +extern cpuop_func op_b010_4_nf; +extern cpuop_func op_b010_4_ff; +extern cpuop_func op_b018_4_nf; +extern cpuop_func op_b018_4_ff; +extern cpuop_func op_b020_4_nf; +extern cpuop_func op_b020_4_ff; +extern cpuop_func op_b028_4_nf; +extern cpuop_func op_b028_4_ff; +extern cpuop_func op_b030_4_nf; +extern cpuop_func op_b030_4_ff; +extern cpuop_func op_b038_4_nf; +extern cpuop_func op_b038_4_ff; +extern cpuop_func op_b039_4_nf; +extern cpuop_func op_b039_4_ff; +extern cpuop_func op_b03a_4_nf; +extern cpuop_func op_b03a_4_ff; +extern cpuop_func op_b03b_4_nf; +extern cpuop_func op_b03b_4_ff; +extern cpuop_func op_b03c_4_nf; +extern cpuop_func op_b03c_4_ff; +extern cpuop_func op_b040_4_nf; +extern cpuop_func op_b040_4_ff; +extern cpuop_func op_b048_4_nf; +extern cpuop_func op_b048_4_ff; +extern cpuop_func op_b050_4_nf; +extern cpuop_func op_b050_4_ff; +extern cpuop_func op_b058_4_nf; +extern cpuop_func op_b058_4_ff; +extern cpuop_func op_b060_4_nf; +extern cpuop_func op_b060_4_ff; +extern cpuop_func op_b068_4_nf; +extern cpuop_func op_b068_4_ff; +extern cpuop_func op_b070_4_nf; +extern cpuop_func op_b070_4_ff; +extern cpuop_func op_b078_4_nf; +extern cpuop_func op_b078_4_ff; +extern cpuop_func op_b079_4_nf; +extern cpuop_func op_b079_4_ff; +extern cpuop_func op_b07a_4_nf; +extern cpuop_func op_b07a_4_ff; +extern cpuop_func op_b07b_4_nf; +extern cpuop_func op_b07b_4_ff; +extern cpuop_func op_b07c_4_nf; +extern cpuop_func op_b07c_4_ff; +extern cpuop_func op_b080_4_nf; +extern cpuop_func op_b080_4_ff; +extern cpuop_func op_b088_4_nf; +extern cpuop_func op_b088_4_ff; +extern cpuop_func op_b090_4_nf; +extern cpuop_func op_b090_4_ff; +extern cpuop_func op_b098_4_nf; +extern cpuop_func op_b098_4_ff; +extern cpuop_func op_b0a0_4_nf; +extern cpuop_func op_b0a0_4_ff; +extern cpuop_func op_b0a8_4_nf; +extern cpuop_func op_b0a8_4_ff; +extern cpuop_func op_b0b0_4_nf; +extern cpuop_func op_b0b0_4_ff; +extern cpuop_func op_b0b8_4_nf; +extern cpuop_func op_b0b8_4_ff; +extern cpuop_func op_b0b9_4_nf; +extern cpuop_func op_b0b9_4_ff; +extern cpuop_func op_b0ba_4_nf; +extern cpuop_func op_b0ba_4_ff; +extern cpuop_func op_b0bb_4_nf; +extern cpuop_func op_b0bb_4_ff; +extern cpuop_func op_b0bc_4_nf; +extern cpuop_func op_b0bc_4_ff; +extern cpuop_func op_b0c0_4_nf; +extern cpuop_func op_b0c0_4_ff; +extern cpuop_func op_b0c8_4_nf; +extern cpuop_func op_b0c8_4_ff; +extern cpuop_func op_b0d0_4_nf; +extern cpuop_func op_b0d0_4_ff; +extern cpuop_func op_b0d8_4_nf; +extern cpuop_func op_b0d8_4_ff; +extern cpuop_func op_b0e0_4_nf; +extern cpuop_func op_b0e0_4_ff; +extern cpuop_func op_b0e8_4_nf; +extern cpuop_func op_b0e8_4_ff; +extern cpuop_func op_b0f0_4_nf; +extern cpuop_func op_b0f0_4_ff; +extern cpuop_func op_b0f8_4_nf; +extern cpuop_func op_b0f8_4_ff; +extern cpuop_func op_b0f9_4_nf; +extern cpuop_func op_b0f9_4_ff; +extern cpuop_func op_b0fa_4_nf; +extern cpuop_func op_b0fa_4_ff; +extern cpuop_func op_b0fb_4_nf; +extern cpuop_func op_b0fb_4_ff; +extern cpuop_func op_b0fc_4_nf; +extern cpuop_func op_b0fc_4_ff; +extern cpuop_func op_b100_4_nf; +extern cpuop_func op_b100_4_ff; +extern cpuop_func op_b108_4_nf; +extern cpuop_func op_b108_4_ff; +extern cpuop_func op_b110_4_nf; +extern cpuop_func op_b110_4_ff; +extern cpuop_func op_b118_4_nf; +extern cpuop_func op_b118_4_ff; +extern cpuop_func op_b120_4_nf; +extern cpuop_func op_b120_4_ff; +extern cpuop_func op_b128_4_nf; +extern cpuop_func op_b128_4_ff; +extern cpuop_func op_b130_4_nf; +extern cpuop_func op_b130_4_ff; +extern cpuop_func op_b138_4_nf; +extern cpuop_func op_b138_4_ff; +extern cpuop_func op_b139_4_nf; +extern cpuop_func op_b139_4_ff; +extern cpuop_func op_b140_4_nf; +extern cpuop_func op_b140_4_ff; +extern cpuop_func op_b148_4_nf; +extern cpuop_func op_b148_4_ff; +extern cpuop_func op_b150_4_nf; +extern cpuop_func op_b150_4_ff; +extern cpuop_func op_b158_4_nf; +extern cpuop_func op_b158_4_ff; +extern cpuop_func op_b160_4_nf; +extern cpuop_func op_b160_4_ff; +extern cpuop_func op_b168_4_nf; +extern cpuop_func op_b168_4_ff; +extern cpuop_func op_b170_4_nf; +extern cpuop_func op_b170_4_ff; +extern cpuop_func op_b178_4_nf; +extern cpuop_func op_b178_4_ff; +extern cpuop_func op_b179_4_nf; +extern cpuop_func op_b179_4_ff; +extern cpuop_func op_b180_4_nf; +extern cpuop_func op_b180_4_ff; +extern cpuop_func op_b188_4_nf; +extern cpuop_func op_b188_4_ff; +extern cpuop_func op_b190_4_nf; +extern cpuop_func op_b190_4_ff; +extern cpuop_func op_b198_4_nf; +extern cpuop_func op_b198_4_ff; +extern cpuop_func op_b1a0_4_nf; +extern cpuop_func op_b1a0_4_ff; +extern cpuop_func op_b1a8_4_nf; +extern cpuop_func op_b1a8_4_ff; +extern cpuop_func op_b1b0_4_nf; +extern cpuop_func op_b1b0_4_ff; +extern cpuop_func op_b1b8_4_nf; +extern cpuop_func op_b1b8_4_ff; +extern cpuop_func op_b1b9_4_nf; +extern cpuop_func op_b1b9_4_ff; +extern cpuop_func op_b1c0_4_nf; +extern cpuop_func op_b1c0_4_ff; +extern cpuop_func op_b1c8_4_nf; +extern cpuop_func op_b1c8_4_ff; +extern cpuop_func op_b1d0_4_nf; +extern cpuop_func op_b1d0_4_ff; +extern cpuop_func op_b1d8_4_nf; +extern cpuop_func op_b1d8_4_ff; +extern cpuop_func op_b1e0_4_nf; +extern cpuop_func op_b1e0_4_ff; +extern cpuop_func op_b1e8_4_nf; +extern cpuop_func op_b1e8_4_ff; +extern cpuop_func op_b1f0_4_nf; +extern cpuop_func op_b1f0_4_ff; +extern cpuop_func op_b1f8_4_nf; +extern cpuop_func op_b1f8_4_ff; +extern cpuop_func op_b1f9_4_nf; +extern cpuop_func op_b1f9_4_ff; +extern cpuop_func op_b1fa_4_nf; +extern cpuop_func op_b1fa_4_ff; +extern cpuop_func op_b1fb_4_nf; +extern cpuop_func op_b1fb_4_ff; +extern cpuop_func op_b1fc_4_nf; +extern cpuop_func op_b1fc_4_ff; +extern cpuop_func op_c000_4_nf; +extern cpuop_func op_c000_4_ff; +extern cpuop_func op_c010_4_nf; +extern cpuop_func op_c010_4_ff; +extern cpuop_func op_c018_4_nf; +extern cpuop_func op_c018_4_ff; +extern cpuop_func op_c020_4_nf; +extern cpuop_func op_c020_4_ff; +extern cpuop_func op_c028_4_nf; +extern cpuop_func op_c028_4_ff; +extern cpuop_func op_c030_4_nf; +extern cpuop_func op_c030_4_ff; +extern cpuop_func op_c038_4_nf; +extern cpuop_func op_c038_4_ff; +extern cpuop_func op_c039_4_nf; +extern cpuop_func op_c039_4_ff; +extern cpuop_func op_c03a_4_nf; +extern cpuop_func op_c03a_4_ff; +extern cpuop_func op_c03b_4_nf; +extern cpuop_func op_c03b_4_ff; +extern cpuop_func op_c03c_4_nf; +extern cpuop_func op_c03c_4_ff; +extern cpuop_func op_c040_4_nf; +extern cpuop_func op_c040_4_ff; +extern cpuop_func op_c050_4_nf; +extern cpuop_func op_c050_4_ff; +extern cpuop_func op_c058_4_nf; +extern cpuop_func op_c058_4_ff; +extern cpuop_func op_c060_4_nf; +extern cpuop_func op_c060_4_ff; +extern cpuop_func op_c068_4_nf; +extern cpuop_func op_c068_4_ff; +extern cpuop_func op_c070_4_nf; +extern cpuop_func op_c070_4_ff; +extern cpuop_func op_c078_4_nf; +extern cpuop_func op_c078_4_ff; +extern cpuop_func op_c079_4_nf; +extern cpuop_func op_c079_4_ff; +extern cpuop_func op_c07a_4_nf; +extern cpuop_func op_c07a_4_ff; +extern cpuop_func op_c07b_4_nf; +extern cpuop_func op_c07b_4_ff; +extern cpuop_func op_c07c_4_nf; +extern cpuop_func op_c07c_4_ff; +extern cpuop_func op_c080_4_nf; +extern cpuop_func op_c080_4_ff; +extern cpuop_func op_c090_4_nf; +extern cpuop_func op_c090_4_ff; +extern cpuop_func op_c098_4_nf; +extern cpuop_func op_c098_4_ff; +extern cpuop_func op_c0a0_4_nf; +extern cpuop_func op_c0a0_4_ff; +extern cpuop_func op_c0a8_4_nf; +extern cpuop_func op_c0a8_4_ff; +extern cpuop_func op_c0b0_4_nf; +extern cpuop_func op_c0b0_4_ff; +extern cpuop_func op_c0b8_4_nf; +extern cpuop_func op_c0b8_4_ff; +extern cpuop_func op_c0b9_4_nf; +extern cpuop_func op_c0b9_4_ff; +extern cpuop_func op_c0ba_4_nf; +extern cpuop_func op_c0ba_4_ff; +extern cpuop_func op_c0bb_4_nf; +extern cpuop_func op_c0bb_4_ff; +extern cpuop_func op_c0bc_4_nf; +extern cpuop_func op_c0bc_4_ff; +extern cpuop_func op_c0c0_4_nf; +extern cpuop_func op_c0c0_4_ff; +extern cpuop_func op_c0d0_4_nf; +extern cpuop_func op_c0d0_4_ff; +extern cpuop_func op_c0d8_4_nf; +extern cpuop_func op_c0d8_4_ff; +extern cpuop_func op_c0e0_4_nf; +extern cpuop_func op_c0e0_4_ff; +extern cpuop_func op_c0e8_4_nf; +extern cpuop_func op_c0e8_4_ff; +extern cpuop_func op_c0f0_4_nf; +extern cpuop_func op_c0f0_4_ff; +extern cpuop_func op_c0f8_4_nf; +extern cpuop_func op_c0f8_4_ff; +extern cpuop_func op_c0f9_4_nf; +extern cpuop_func op_c0f9_4_ff; +extern cpuop_func op_c0fa_4_nf; +extern cpuop_func op_c0fa_4_ff; +extern cpuop_func op_c0fb_4_nf; +extern cpuop_func op_c0fb_4_ff; +extern cpuop_func op_c0fc_4_nf; +extern cpuop_func op_c0fc_4_ff; +extern cpuop_func op_c100_4_nf; +extern cpuop_func op_c100_4_ff; +extern cpuop_func op_c108_4_nf; +extern cpuop_func op_c108_4_ff; +extern cpuop_func op_c110_4_nf; +extern cpuop_func op_c110_4_ff; +extern cpuop_func op_c118_4_nf; +extern cpuop_func op_c118_4_ff; +extern cpuop_func op_c120_4_nf; +extern cpuop_func op_c120_4_ff; +extern cpuop_func op_c128_4_nf; +extern cpuop_func op_c128_4_ff; +extern cpuop_func op_c130_4_nf; +extern cpuop_func op_c130_4_ff; +extern cpuop_func op_c138_4_nf; +extern cpuop_func op_c138_4_ff; +extern cpuop_func op_c139_4_nf; +extern cpuop_func op_c139_4_ff; +extern cpuop_func op_c140_4_nf; +extern cpuop_func op_c140_4_ff; +extern cpuop_func op_c148_4_nf; +extern cpuop_func op_c148_4_ff; +extern cpuop_func op_c150_4_nf; +extern cpuop_func op_c150_4_ff; +extern cpuop_func op_c158_4_nf; +extern cpuop_func op_c158_4_ff; +extern cpuop_func op_c160_4_nf; +extern cpuop_func op_c160_4_ff; +extern cpuop_func op_c168_4_nf; +extern cpuop_func op_c168_4_ff; +extern cpuop_func op_c170_4_nf; +extern cpuop_func op_c170_4_ff; +extern cpuop_func op_c178_4_nf; +extern cpuop_func op_c178_4_ff; +extern cpuop_func op_c179_4_nf; +extern cpuop_func op_c179_4_ff; +extern cpuop_func op_c188_4_nf; +extern cpuop_func op_c188_4_ff; +extern cpuop_func op_c190_4_nf; +extern cpuop_func op_c190_4_ff; +extern cpuop_func op_c198_4_nf; +extern cpuop_func op_c198_4_ff; +extern cpuop_func op_c1a0_4_nf; +extern cpuop_func op_c1a0_4_ff; +extern cpuop_func op_c1a8_4_nf; +extern cpuop_func op_c1a8_4_ff; +extern cpuop_func op_c1b0_4_nf; +extern cpuop_func op_c1b0_4_ff; +extern cpuop_func op_c1b8_4_nf; +extern cpuop_func op_c1b8_4_ff; +extern cpuop_func op_c1b9_4_nf; +extern cpuop_func op_c1b9_4_ff; +extern cpuop_func op_c1c0_4_nf; +extern cpuop_func op_c1c0_4_ff; +extern cpuop_func op_c1d0_4_nf; +extern cpuop_func op_c1d0_4_ff; +extern cpuop_func op_c1d8_4_nf; +extern cpuop_func op_c1d8_4_ff; +extern cpuop_func op_c1e0_4_nf; +extern cpuop_func op_c1e0_4_ff; +extern cpuop_func op_c1e8_4_nf; +extern cpuop_func op_c1e8_4_ff; +extern cpuop_func op_c1f0_4_nf; +extern cpuop_func op_c1f0_4_ff; +extern cpuop_func op_c1f8_4_nf; +extern cpuop_func op_c1f8_4_ff; +extern cpuop_func op_c1f9_4_nf; +extern cpuop_func op_c1f9_4_ff; +extern cpuop_func op_c1fa_4_nf; +extern cpuop_func op_c1fa_4_ff; +extern cpuop_func op_c1fb_4_nf; +extern cpuop_func op_c1fb_4_ff; +extern cpuop_func op_c1fc_4_nf; +extern cpuop_func op_c1fc_4_ff; +extern cpuop_func op_d000_4_nf; +extern cpuop_func op_d000_4_ff; +extern cpuop_func op_d010_4_nf; +extern cpuop_func op_d010_4_ff; +extern cpuop_func op_d018_4_nf; +extern cpuop_func op_d018_4_ff; +extern cpuop_func op_d020_4_nf; +extern cpuop_func op_d020_4_ff; +extern cpuop_func op_d028_4_nf; +extern cpuop_func op_d028_4_ff; +extern cpuop_func op_d030_4_nf; +extern cpuop_func op_d030_4_ff; +extern cpuop_func op_d038_4_nf; +extern cpuop_func op_d038_4_ff; +extern cpuop_func op_d039_4_nf; +extern cpuop_func op_d039_4_ff; +extern cpuop_func op_d03a_4_nf; +extern cpuop_func op_d03a_4_ff; +extern cpuop_func op_d03b_4_nf; +extern cpuop_func op_d03b_4_ff; +extern cpuop_func op_d03c_4_nf; +extern cpuop_func op_d03c_4_ff; +extern cpuop_func op_d040_4_nf; +extern cpuop_func op_d040_4_ff; +extern cpuop_func op_d048_4_nf; +extern cpuop_func op_d048_4_ff; +extern cpuop_func op_d050_4_nf; +extern cpuop_func op_d050_4_ff; +extern cpuop_func op_d058_4_nf; +extern cpuop_func op_d058_4_ff; +extern cpuop_func op_d060_4_nf; +extern cpuop_func op_d060_4_ff; +extern cpuop_func op_d068_4_nf; +extern cpuop_func op_d068_4_ff; +extern cpuop_func op_d070_4_nf; +extern cpuop_func op_d070_4_ff; +extern cpuop_func op_d078_4_nf; +extern cpuop_func op_d078_4_ff; +extern cpuop_func op_d079_4_nf; +extern cpuop_func op_d079_4_ff; +extern cpuop_func op_d07a_4_nf; +extern cpuop_func op_d07a_4_ff; +extern cpuop_func op_d07b_4_nf; +extern cpuop_func op_d07b_4_ff; +extern cpuop_func op_d07c_4_nf; +extern cpuop_func op_d07c_4_ff; +extern cpuop_func op_d080_4_nf; +extern cpuop_func op_d080_4_ff; +extern cpuop_func op_d088_4_nf; +extern cpuop_func op_d088_4_ff; +extern cpuop_func op_d090_4_nf; +extern cpuop_func op_d090_4_ff; +extern cpuop_func op_d098_4_nf; +extern cpuop_func op_d098_4_ff; +extern cpuop_func op_d0a0_4_nf; +extern cpuop_func op_d0a0_4_ff; +extern cpuop_func op_d0a8_4_nf; +extern cpuop_func op_d0a8_4_ff; +extern cpuop_func op_d0b0_4_nf; +extern cpuop_func op_d0b0_4_ff; +extern cpuop_func op_d0b8_4_nf; +extern cpuop_func op_d0b8_4_ff; +extern cpuop_func op_d0b9_4_nf; +extern cpuop_func op_d0b9_4_ff; +extern cpuop_func op_d0ba_4_nf; +extern cpuop_func op_d0ba_4_ff; +extern cpuop_func op_d0bb_4_nf; +extern cpuop_func op_d0bb_4_ff; +extern cpuop_func op_d0bc_4_nf; +extern cpuop_func op_d0bc_4_ff; +extern cpuop_func op_d0c0_4_nf; +extern cpuop_func op_d0c0_4_ff; +extern cpuop_func op_d0c8_4_nf; +extern cpuop_func op_d0c8_4_ff; +extern cpuop_func op_d0d0_4_nf; +extern cpuop_func op_d0d0_4_ff; +extern cpuop_func op_d0d8_4_nf; +extern cpuop_func op_d0d8_4_ff; +extern cpuop_func op_d0e0_4_nf; +extern cpuop_func op_d0e0_4_ff; +extern cpuop_func op_d0e8_4_nf; +extern cpuop_func op_d0e8_4_ff; +extern cpuop_func op_d0f0_4_nf; +extern cpuop_func op_d0f0_4_ff; +extern cpuop_func op_d0f8_4_nf; +extern cpuop_func op_d0f8_4_ff; +extern cpuop_func op_d0f9_4_nf; +extern cpuop_func op_d0f9_4_ff; +extern cpuop_func op_d0fa_4_nf; +extern cpuop_func op_d0fa_4_ff; +extern cpuop_func op_d0fb_4_nf; +extern cpuop_func op_d0fb_4_ff; +extern cpuop_func op_d0fc_4_nf; +extern cpuop_func op_d0fc_4_ff; +extern cpuop_func op_d100_4_nf; +extern cpuop_func op_d100_4_ff; +extern cpuop_func op_d108_4_nf; +extern cpuop_func op_d108_4_ff; +extern cpuop_func op_d110_4_nf; +extern cpuop_func op_d110_4_ff; +extern cpuop_func op_d118_4_nf; +extern cpuop_func op_d118_4_ff; +extern cpuop_func op_d120_4_nf; +extern cpuop_func op_d120_4_ff; +extern cpuop_func op_d128_4_nf; +extern cpuop_func op_d128_4_ff; +extern cpuop_func op_d130_4_nf; +extern cpuop_func op_d130_4_ff; +extern cpuop_func op_d138_4_nf; +extern cpuop_func op_d138_4_ff; +extern cpuop_func op_d139_4_nf; +extern cpuop_func op_d139_4_ff; +extern cpuop_func op_d140_4_nf; +extern cpuop_func op_d140_4_ff; +extern cpuop_func op_d148_4_nf; +extern cpuop_func op_d148_4_ff; +extern cpuop_func op_d150_4_nf; +extern cpuop_func op_d150_4_ff; +extern cpuop_func op_d158_4_nf; +extern cpuop_func op_d158_4_ff; +extern cpuop_func op_d160_4_nf; +extern cpuop_func op_d160_4_ff; +extern cpuop_func op_d168_4_nf; +extern cpuop_func op_d168_4_ff; +extern cpuop_func op_d170_4_nf; +extern cpuop_func op_d170_4_ff; +extern cpuop_func op_d178_4_nf; +extern cpuop_func op_d178_4_ff; +extern cpuop_func op_d179_4_nf; +extern cpuop_func op_d179_4_ff; +extern cpuop_func op_d180_4_nf; +extern cpuop_func op_d180_4_ff; +extern cpuop_func op_d188_4_nf; +extern cpuop_func op_d188_4_ff; +extern cpuop_func op_d190_4_nf; +extern cpuop_func op_d190_4_ff; +extern cpuop_func op_d198_4_nf; +extern cpuop_func op_d198_4_ff; +extern cpuop_func op_d1a0_4_nf; +extern cpuop_func op_d1a0_4_ff; +extern cpuop_func op_d1a8_4_nf; +extern cpuop_func op_d1a8_4_ff; +extern cpuop_func op_d1b0_4_nf; +extern cpuop_func op_d1b0_4_ff; +extern cpuop_func op_d1b8_4_nf; +extern cpuop_func op_d1b8_4_ff; +extern cpuop_func op_d1b9_4_nf; +extern cpuop_func op_d1b9_4_ff; +extern cpuop_func op_d1c0_4_nf; +extern cpuop_func op_d1c0_4_ff; +extern cpuop_func op_d1c8_4_nf; +extern cpuop_func op_d1c8_4_ff; +extern cpuop_func op_d1d0_4_nf; +extern cpuop_func op_d1d0_4_ff; +extern cpuop_func op_d1d8_4_nf; +extern cpuop_func op_d1d8_4_ff; +extern cpuop_func op_d1e0_4_nf; +extern cpuop_func op_d1e0_4_ff; +extern cpuop_func op_d1e8_4_nf; +extern cpuop_func op_d1e8_4_ff; +extern cpuop_func op_d1f0_4_nf; +extern cpuop_func op_d1f0_4_ff; +extern cpuop_func op_d1f8_4_nf; +extern cpuop_func op_d1f8_4_ff; +extern cpuop_func op_d1f9_4_nf; +extern cpuop_func op_d1f9_4_ff; +extern cpuop_func op_d1fa_4_nf; +extern cpuop_func op_d1fa_4_ff; +extern cpuop_func op_d1fb_4_nf; +extern cpuop_func op_d1fb_4_ff; +extern cpuop_func op_d1fc_4_nf; +extern cpuop_func op_d1fc_4_ff; +extern cpuop_func op_e000_4_nf; +extern cpuop_func op_e000_4_ff; +extern cpuop_func op_e008_4_nf; +extern cpuop_func op_e008_4_ff; +extern cpuop_func op_e010_4_nf; +extern cpuop_func op_e010_4_ff; +extern cpuop_func op_e018_4_nf; +extern cpuop_func op_e018_4_ff; +extern cpuop_func op_e020_4_nf; +extern cpuop_func op_e020_4_ff; +extern cpuop_func op_e028_4_nf; +extern cpuop_func op_e028_4_ff; +extern cpuop_func op_e030_4_nf; +extern cpuop_func op_e030_4_ff; +extern cpuop_func op_e038_4_nf; +extern cpuop_func op_e038_4_ff; +extern cpuop_func op_e040_4_nf; +extern cpuop_func op_e040_4_ff; +extern cpuop_func op_e048_4_nf; +extern cpuop_func op_e048_4_ff; +extern cpuop_func op_e050_4_nf; +extern cpuop_func op_e050_4_ff; +extern cpuop_func op_e058_4_nf; +extern cpuop_func op_e058_4_ff; +extern cpuop_func op_e060_4_nf; +extern cpuop_func op_e060_4_ff; +extern cpuop_func op_e068_4_nf; +extern cpuop_func op_e068_4_ff; +extern cpuop_func op_e070_4_nf; +extern cpuop_func op_e070_4_ff; +extern cpuop_func op_e078_4_nf; +extern cpuop_func op_e078_4_ff; +extern cpuop_func op_e080_4_nf; +extern cpuop_func op_e080_4_ff; +extern cpuop_func op_e088_4_nf; +extern cpuop_func op_e088_4_ff; +extern cpuop_func op_e090_4_nf; +extern cpuop_func op_e090_4_ff; +extern cpuop_func op_e098_4_nf; +extern cpuop_func op_e098_4_ff; +extern cpuop_func op_e0a0_4_nf; +extern cpuop_func op_e0a0_4_ff; +extern cpuop_func op_e0a8_4_nf; +extern cpuop_func op_e0a8_4_ff; +extern cpuop_func op_e0b0_4_nf; +extern cpuop_func op_e0b0_4_ff; +extern cpuop_func op_e0b8_4_nf; +extern cpuop_func op_e0b8_4_ff; +extern cpuop_func op_e0d0_4_nf; +extern cpuop_func op_e0d0_4_ff; +extern cpuop_func op_e0d8_4_nf; +extern cpuop_func op_e0d8_4_ff; +extern cpuop_func op_e0e0_4_nf; +extern cpuop_func op_e0e0_4_ff; +extern cpuop_func op_e0e8_4_nf; +extern cpuop_func op_e0e8_4_ff; +extern cpuop_func op_e0f0_4_nf; +extern cpuop_func op_e0f0_4_ff; +extern cpuop_func op_e0f8_4_nf; +extern cpuop_func op_e0f8_4_ff; +extern cpuop_func op_e0f9_4_nf; +extern cpuop_func op_e0f9_4_ff; +extern cpuop_func op_e100_4_nf; +extern cpuop_func op_e100_4_ff; +extern cpuop_func op_e108_4_nf; +extern cpuop_func op_e108_4_ff; +extern cpuop_func op_e110_4_nf; +extern cpuop_func op_e110_4_ff; +extern cpuop_func op_e118_4_nf; +extern cpuop_func op_e118_4_ff; +extern cpuop_func op_e120_4_nf; +extern cpuop_func op_e120_4_ff; +extern cpuop_func op_e128_4_nf; +extern cpuop_func op_e128_4_ff; +extern cpuop_func op_e130_4_nf; +extern cpuop_func op_e130_4_ff; +extern cpuop_func op_e138_4_nf; +extern cpuop_func op_e138_4_ff; +extern cpuop_func op_e140_4_nf; +extern cpuop_func op_e140_4_ff; +extern cpuop_func op_e148_4_nf; +extern cpuop_func op_e148_4_ff; +extern cpuop_func op_e150_4_nf; +extern cpuop_func op_e150_4_ff; +extern cpuop_func op_e158_4_nf; +extern cpuop_func op_e158_4_ff; +extern cpuop_func op_e160_4_nf; +extern cpuop_func op_e160_4_ff; +extern cpuop_func op_e168_4_nf; +extern cpuop_func op_e168_4_ff; +extern cpuop_func op_e170_4_nf; +extern cpuop_func op_e170_4_ff; +extern cpuop_func op_e178_4_nf; +extern cpuop_func op_e178_4_ff; +extern cpuop_func op_e180_4_nf; +extern cpuop_func op_e180_4_ff; +extern cpuop_func op_e188_4_nf; +extern cpuop_func op_e188_4_ff; +extern cpuop_func op_e190_4_nf; +extern cpuop_func op_e190_4_ff; +extern cpuop_func op_e198_4_nf; +extern cpuop_func op_e198_4_ff; +extern cpuop_func op_e1a0_4_nf; +extern cpuop_func op_e1a0_4_ff; +extern cpuop_func op_e1a8_4_nf; +extern cpuop_func op_e1a8_4_ff; +extern cpuop_func op_e1b0_4_nf; +extern cpuop_func op_e1b0_4_ff; +extern cpuop_func op_e1b8_4_nf; +extern cpuop_func op_e1b8_4_ff; +extern cpuop_func op_e1d0_4_nf; +extern cpuop_func op_e1d0_4_ff; +extern cpuop_func op_e1d8_4_nf; +extern cpuop_func op_e1d8_4_ff; +extern cpuop_func op_e1e0_4_nf; +extern cpuop_func op_e1e0_4_ff; +extern cpuop_func op_e1e8_4_nf; +extern cpuop_func op_e1e8_4_ff; +extern cpuop_func op_e1f0_4_nf; +extern cpuop_func op_e1f0_4_ff; +extern cpuop_func op_e1f8_4_nf; +extern cpuop_func op_e1f8_4_ff; +extern cpuop_func op_e1f9_4_nf; +extern cpuop_func op_e1f9_4_ff; +extern cpuop_func op_e2d0_4_nf; +extern cpuop_func op_e2d0_4_ff; +extern cpuop_func op_e2d8_4_nf; +extern cpuop_func op_e2d8_4_ff; +extern cpuop_func op_e2e0_4_nf; +extern cpuop_func op_e2e0_4_ff; +extern cpuop_func op_e2e8_4_nf; +extern cpuop_func op_e2e8_4_ff; +extern cpuop_func op_e2f0_4_nf; +extern cpuop_func op_e2f0_4_ff; +extern cpuop_func op_e2f8_4_nf; +extern cpuop_func op_e2f8_4_ff; +extern cpuop_func op_e2f9_4_nf; +extern cpuop_func op_e2f9_4_ff; +extern cpuop_func op_e3d0_4_nf; +extern cpuop_func op_e3d0_4_ff; +extern cpuop_func op_e3d8_4_nf; +extern cpuop_func op_e3d8_4_ff; +extern cpuop_func op_e3e0_4_nf; +extern cpuop_func op_e3e0_4_ff; +extern cpuop_func op_e3e8_4_nf; +extern cpuop_func op_e3e8_4_ff; +extern cpuop_func op_e3f0_4_nf; +extern cpuop_func op_e3f0_4_ff; +extern cpuop_func op_e3f8_4_nf; +extern cpuop_func op_e3f8_4_ff; +extern cpuop_func op_e3f9_4_nf; +extern cpuop_func op_e3f9_4_ff; +extern cpuop_func op_e4d0_4_nf; +extern cpuop_func op_e4d0_4_ff; +extern cpuop_func op_e4d8_4_nf; +extern cpuop_func op_e4d8_4_ff; +extern cpuop_func op_e4e0_4_nf; +extern cpuop_func op_e4e0_4_ff; +extern cpuop_func op_e4e8_4_nf; +extern cpuop_func op_e4e8_4_ff; +extern cpuop_func op_e4f0_4_nf; +extern cpuop_func op_e4f0_4_ff; +extern cpuop_func op_e4f8_4_nf; +extern cpuop_func op_e4f8_4_ff; +extern cpuop_func op_e4f9_4_nf; +extern cpuop_func op_e4f9_4_ff; +extern cpuop_func op_e5d0_4_nf; +extern cpuop_func op_e5d0_4_ff; +extern cpuop_func op_e5d8_4_nf; +extern cpuop_func op_e5d8_4_ff; +extern cpuop_func op_e5e0_4_nf; +extern cpuop_func op_e5e0_4_ff; +extern cpuop_func op_e5e8_4_nf; +extern cpuop_func op_e5e8_4_ff; +extern cpuop_func op_e5f0_4_nf; +extern cpuop_func op_e5f0_4_ff; +extern cpuop_func op_e5f8_4_nf; +extern cpuop_func op_e5f8_4_ff; +extern cpuop_func op_e5f9_4_nf; +extern cpuop_func op_e5f9_4_ff; +extern cpuop_func op_e6d0_4_nf; +extern cpuop_func op_e6d0_4_ff; +extern cpuop_func op_e6d8_4_nf; +extern cpuop_func op_e6d8_4_ff; +extern cpuop_func op_e6e0_4_nf; +extern cpuop_func op_e6e0_4_ff; +extern cpuop_func op_e6e8_4_nf; +extern cpuop_func op_e6e8_4_ff; +extern cpuop_func op_e6f0_4_nf; +extern cpuop_func op_e6f0_4_ff; +extern cpuop_func op_e6f8_4_nf; +extern cpuop_func op_e6f8_4_ff; +extern cpuop_func op_e6f9_4_nf; +extern cpuop_func op_e6f9_4_ff; +extern cpuop_func op_e7d0_4_nf; +extern cpuop_func op_e7d0_4_ff; +extern cpuop_func op_e7d8_4_nf; +extern cpuop_func op_e7d8_4_ff; +extern cpuop_func op_e7e0_4_nf; +extern cpuop_func op_e7e0_4_ff; +extern cpuop_func op_e7e8_4_nf; +extern cpuop_func op_e7e8_4_ff; +extern cpuop_func op_e7f0_4_nf; +extern cpuop_func op_e7f0_4_ff; +extern cpuop_func op_e7f8_4_nf; +extern cpuop_func op_e7f8_4_ff; +extern cpuop_func op_e7f9_4_nf; +extern cpuop_func op_e7f9_4_ff; +extern cpuop_func op_0_5_nf; +extern cpuop_func op_0_5_ff; +extern cpuop_func op_10_5_nf; +extern cpuop_func op_10_5_ff; +extern cpuop_func op_18_5_nf; +extern cpuop_func op_18_5_ff; +extern cpuop_func op_20_5_nf; +extern cpuop_func op_20_5_ff; +extern cpuop_func op_28_5_nf; +extern cpuop_func op_28_5_ff; +extern cpuop_func op_30_5_nf; +extern cpuop_func op_30_5_ff; +extern cpuop_func op_38_5_nf; +extern cpuop_func op_38_5_ff; +extern cpuop_func op_39_5_nf; +extern cpuop_func op_39_5_ff; +extern cpuop_func op_3c_5_nf; +extern cpuop_func op_3c_5_ff; +extern cpuop_func op_40_5_nf; +extern cpuop_func op_40_5_ff; +extern cpuop_func op_50_5_nf; +extern cpuop_func op_50_5_ff; +extern cpuop_func op_58_5_nf; +extern cpuop_func op_58_5_ff; +extern cpuop_func op_60_5_nf; +extern cpuop_func op_60_5_ff; +extern cpuop_func op_68_5_nf; +extern cpuop_func op_68_5_ff; +extern cpuop_func op_70_5_nf; +extern cpuop_func op_70_5_ff; +extern cpuop_func op_78_5_nf; +extern cpuop_func op_78_5_ff; +extern cpuop_func op_79_5_nf; +extern cpuop_func op_79_5_ff; +extern cpuop_func op_7c_5_nf; +extern cpuop_func op_7c_5_ff; +extern cpuop_func op_80_5_nf; +extern cpuop_func op_80_5_ff; +extern cpuop_func op_90_5_nf; +extern cpuop_func op_90_5_ff; +extern cpuop_func op_98_5_nf; +extern cpuop_func op_98_5_ff; +extern cpuop_func op_a0_5_nf; +extern cpuop_func op_a0_5_ff; +extern cpuop_func op_a8_5_nf; +extern cpuop_func op_a8_5_ff; +extern cpuop_func op_b0_5_nf; +extern cpuop_func op_b0_5_ff; +extern cpuop_func op_b8_5_nf; +extern cpuop_func op_b8_5_ff; +extern cpuop_func op_b9_5_nf; +extern cpuop_func op_b9_5_ff; +extern cpuop_func op_100_5_nf; +extern cpuop_func op_100_5_ff; +extern cpuop_func op_108_5_nf; +extern cpuop_func op_108_5_ff; +extern cpuop_func op_110_5_nf; +extern cpuop_func op_110_5_ff; +extern cpuop_func op_118_5_nf; +extern cpuop_func op_118_5_ff; +extern cpuop_func op_120_5_nf; +extern cpuop_func op_120_5_ff; +extern cpuop_func op_128_5_nf; +extern cpuop_func op_128_5_ff; +extern cpuop_func op_130_5_nf; +extern cpuop_func op_130_5_ff; +extern cpuop_func op_138_5_nf; +extern cpuop_func op_138_5_ff; +extern cpuop_func op_139_5_nf; +extern cpuop_func op_139_5_ff; +extern cpuop_func op_13a_5_nf; +extern cpuop_func op_13a_5_ff; +extern cpuop_func op_13b_5_nf; +extern cpuop_func op_13b_5_ff; +extern cpuop_func op_13c_5_nf; +extern cpuop_func op_13c_5_ff; +extern cpuop_func op_140_5_nf; +extern cpuop_func op_140_5_ff; +extern cpuop_func op_148_5_nf; +extern cpuop_func op_148_5_ff; +extern cpuop_func op_150_5_nf; +extern cpuop_func op_150_5_ff; +extern cpuop_func op_158_5_nf; +extern cpuop_func op_158_5_ff; +extern cpuop_func op_160_5_nf; +extern cpuop_func op_160_5_ff; +extern cpuop_func op_168_5_nf; +extern cpuop_func op_168_5_ff; +extern cpuop_func op_170_5_nf; +extern cpuop_func op_170_5_ff; +extern cpuop_func op_178_5_nf; +extern cpuop_func op_178_5_ff; +extern cpuop_func op_179_5_nf; +extern cpuop_func op_179_5_ff; +extern cpuop_func op_17a_5_nf; +extern cpuop_func op_17a_5_ff; +extern cpuop_func op_17b_5_nf; +extern cpuop_func op_17b_5_ff; +extern cpuop_func op_180_5_nf; +extern cpuop_func op_180_5_ff; +extern cpuop_func op_188_5_nf; +extern cpuop_func op_188_5_ff; +extern cpuop_func op_190_5_nf; +extern cpuop_func op_190_5_ff; +extern cpuop_func op_198_5_nf; +extern cpuop_func op_198_5_ff; +extern cpuop_func op_1a0_5_nf; +extern cpuop_func op_1a0_5_ff; +extern cpuop_func op_1a8_5_nf; +extern cpuop_func op_1a8_5_ff; +extern cpuop_func op_1b0_5_nf; +extern cpuop_func op_1b0_5_ff; +extern cpuop_func op_1b8_5_nf; +extern cpuop_func op_1b8_5_ff; +extern cpuop_func op_1b9_5_nf; +extern cpuop_func op_1b9_5_ff; +extern cpuop_func op_1ba_5_nf; +extern cpuop_func op_1ba_5_ff; +extern cpuop_func op_1bb_5_nf; +extern cpuop_func op_1bb_5_ff; +extern cpuop_func op_1c0_5_nf; +extern cpuop_func op_1c0_5_ff; +extern cpuop_func op_1c8_5_nf; +extern cpuop_func op_1c8_5_ff; +extern cpuop_func op_1d0_5_nf; +extern cpuop_func op_1d0_5_ff; +extern cpuop_func op_1d8_5_nf; +extern cpuop_func op_1d8_5_ff; +extern cpuop_func op_1e0_5_nf; +extern cpuop_func op_1e0_5_ff; +extern cpuop_func op_1e8_5_nf; +extern cpuop_func op_1e8_5_ff; +extern cpuop_func op_1f0_5_nf; +extern cpuop_func op_1f0_5_ff; +extern cpuop_func op_1f8_5_nf; +extern cpuop_func op_1f8_5_ff; +extern cpuop_func op_1f9_5_nf; +extern cpuop_func op_1f9_5_ff; +extern cpuop_func op_1fa_5_nf; +extern cpuop_func op_1fa_5_ff; +extern cpuop_func op_1fb_5_nf; +extern cpuop_func op_1fb_5_ff; +extern cpuop_func op_200_5_nf; +extern cpuop_func op_200_5_ff; +extern cpuop_func op_210_5_nf; +extern cpuop_func op_210_5_ff; +extern cpuop_func op_218_5_nf; +extern cpuop_func op_218_5_ff; +extern cpuop_func op_220_5_nf; +extern cpuop_func op_220_5_ff; +extern cpuop_func op_228_5_nf; +extern cpuop_func op_228_5_ff; +extern cpuop_func op_230_5_nf; +extern cpuop_func op_230_5_ff; +extern cpuop_func op_238_5_nf; +extern cpuop_func op_238_5_ff; +extern cpuop_func op_239_5_nf; +extern cpuop_func op_239_5_ff; +extern cpuop_func op_23c_5_nf; +extern cpuop_func op_23c_5_ff; +extern cpuop_func op_240_5_nf; +extern cpuop_func op_240_5_ff; +extern cpuop_func op_250_5_nf; +extern cpuop_func op_250_5_ff; +extern cpuop_func op_258_5_nf; +extern cpuop_func op_258_5_ff; +extern cpuop_func op_260_5_nf; +extern cpuop_func op_260_5_ff; +extern cpuop_func op_268_5_nf; +extern cpuop_func op_268_5_ff; +extern cpuop_func op_270_5_nf; +extern cpuop_func op_270_5_ff; +extern cpuop_func op_278_5_nf; +extern cpuop_func op_278_5_ff; +extern cpuop_func op_279_5_nf; +extern cpuop_func op_279_5_ff; +extern cpuop_func op_27c_5_nf; +extern cpuop_func op_27c_5_ff; +extern cpuop_func op_280_5_nf; +extern cpuop_func op_280_5_ff; +extern cpuop_func op_290_5_nf; +extern cpuop_func op_290_5_ff; +extern cpuop_func op_298_5_nf; +extern cpuop_func op_298_5_ff; +extern cpuop_func op_2a0_5_nf; +extern cpuop_func op_2a0_5_ff; +extern cpuop_func op_2a8_5_nf; +extern cpuop_func op_2a8_5_ff; +extern cpuop_func op_2b0_5_nf; +extern cpuop_func op_2b0_5_ff; +extern cpuop_func op_2b8_5_nf; +extern cpuop_func op_2b8_5_ff; +extern cpuop_func op_2b9_5_nf; +extern cpuop_func op_2b9_5_ff; +extern cpuop_func op_400_5_nf; +extern cpuop_func op_400_5_ff; +extern cpuop_func op_410_5_nf; +extern cpuop_func op_410_5_ff; +extern cpuop_func op_418_5_nf; +extern cpuop_func op_418_5_ff; +extern cpuop_func op_420_5_nf; +extern cpuop_func op_420_5_ff; +extern cpuop_func op_428_5_nf; +extern cpuop_func op_428_5_ff; +extern cpuop_func op_430_5_nf; +extern cpuop_func op_430_5_ff; +extern cpuop_func op_438_5_nf; +extern cpuop_func op_438_5_ff; +extern cpuop_func op_439_5_nf; +extern cpuop_func op_439_5_ff; +extern cpuop_func op_440_5_nf; +extern cpuop_func op_440_5_ff; +extern cpuop_func op_450_5_nf; +extern cpuop_func op_450_5_ff; +extern cpuop_func op_458_5_nf; +extern cpuop_func op_458_5_ff; +extern cpuop_func op_460_5_nf; +extern cpuop_func op_460_5_ff; +extern cpuop_func op_468_5_nf; +extern cpuop_func op_468_5_ff; +extern cpuop_func op_470_5_nf; +extern cpuop_func op_470_5_ff; +extern cpuop_func op_478_5_nf; +extern cpuop_func op_478_5_ff; +extern cpuop_func op_479_5_nf; +extern cpuop_func op_479_5_ff; +extern cpuop_func op_480_5_nf; +extern cpuop_func op_480_5_ff; +extern cpuop_func op_490_5_nf; +extern cpuop_func op_490_5_ff; +extern cpuop_func op_498_5_nf; +extern cpuop_func op_498_5_ff; +extern cpuop_func op_4a0_5_nf; +extern cpuop_func op_4a0_5_ff; +extern cpuop_func op_4a8_5_nf; +extern cpuop_func op_4a8_5_ff; +extern cpuop_func op_4b0_5_nf; +extern cpuop_func op_4b0_5_ff; +extern cpuop_func op_4b8_5_nf; +extern cpuop_func op_4b8_5_ff; +extern cpuop_func op_4b9_5_nf; +extern cpuop_func op_4b9_5_ff; +extern cpuop_func op_600_5_nf; +extern cpuop_func op_600_5_ff; +extern cpuop_func op_610_5_nf; +extern cpuop_func op_610_5_ff; +extern cpuop_func op_618_5_nf; +extern cpuop_func op_618_5_ff; +extern cpuop_func op_620_5_nf; +extern cpuop_func op_620_5_ff; +extern cpuop_func op_628_5_nf; +extern cpuop_func op_628_5_ff; +extern cpuop_func op_630_5_nf; +extern cpuop_func op_630_5_ff; +extern cpuop_func op_638_5_nf; +extern cpuop_func op_638_5_ff; +extern cpuop_func op_639_5_nf; +extern cpuop_func op_639_5_ff; +extern cpuop_func op_640_5_nf; +extern cpuop_func op_640_5_ff; +extern cpuop_func op_650_5_nf; +extern cpuop_func op_650_5_ff; +extern cpuop_func op_658_5_nf; +extern cpuop_func op_658_5_ff; +extern cpuop_func op_660_5_nf; +extern cpuop_func op_660_5_ff; +extern cpuop_func op_668_5_nf; +extern cpuop_func op_668_5_ff; +extern cpuop_func op_670_5_nf; +extern cpuop_func op_670_5_ff; +extern cpuop_func op_678_5_nf; +extern cpuop_func op_678_5_ff; +extern cpuop_func op_679_5_nf; +extern cpuop_func op_679_5_ff; +extern cpuop_func op_680_5_nf; +extern cpuop_func op_680_5_ff; +extern cpuop_func op_690_5_nf; +extern cpuop_func op_690_5_ff; +extern cpuop_func op_698_5_nf; +extern cpuop_func op_698_5_ff; +extern cpuop_func op_6a0_5_nf; +extern cpuop_func op_6a0_5_ff; +extern cpuop_func op_6a8_5_nf; +extern cpuop_func op_6a8_5_ff; +extern cpuop_func op_6b0_5_nf; +extern cpuop_func op_6b0_5_ff; +extern cpuop_func op_6b8_5_nf; +extern cpuop_func op_6b8_5_ff; +extern cpuop_func op_6b9_5_nf; +extern cpuop_func op_6b9_5_ff; +extern cpuop_func op_800_5_nf; +extern cpuop_func op_800_5_ff; +extern cpuop_func op_810_5_nf; +extern cpuop_func op_810_5_ff; +extern cpuop_func op_818_5_nf; +extern cpuop_func op_818_5_ff; +extern cpuop_func op_820_5_nf; +extern cpuop_func op_820_5_ff; +extern cpuop_func op_828_5_nf; +extern cpuop_func op_828_5_ff; +extern cpuop_func op_830_5_nf; +extern cpuop_func op_830_5_ff; +extern cpuop_func op_838_5_nf; +extern cpuop_func op_838_5_ff; +extern cpuop_func op_839_5_nf; +extern cpuop_func op_839_5_ff; +extern cpuop_func op_83a_5_nf; +extern cpuop_func op_83a_5_ff; +extern cpuop_func op_83b_5_nf; +extern cpuop_func op_83b_5_ff; +extern cpuop_func op_83c_5_nf; +extern cpuop_func op_83c_5_ff; +extern cpuop_func op_840_5_nf; +extern cpuop_func op_840_5_ff; +extern cpuop_func op_850_5_nf; +extern cpuop_func op_850_5_ff; +extern cpuop_func op_858_5_nf; +extern cpuop_func op_858_5_ff; +extern cpuop_func op_860_5_nf; +extern cpuop_func op_860_5_ff; +extern cpuop_func op_868_5_nf; +extern cpuop_func op_868_5_ff; +extern cpuop_func op_870_5_nf; +extern cpuop_func op_870_5_ff; +extern cpuop_func op_878_5_nf; +extern cpuop_func op_878_5_ff; +extern cpuop_func op_879_5_nf; +extern cpuop_func op_879_5_ff; +extern cpuop_func op_87a_5_nf; +extern cpuop_func op_87a_5_ff; +extern cpuop_func op_87b_5_nf; +extern cpuop_func op_87b_5_ff; +extern cpuop_func op_880_5_nf; +extern cpuop_func op_880_5_ff; +extern cpuop_func op_890_5_nf; +extern cpuop_func op_890_5_ff; +extern cpuop_func op_898_5_nf; +extern cpuop_func op_898_5_ff; +extern cpuop_func op_8a0_5_nf; +extern cpuop_func op_8a0_5_ff; +extern cpuop_func op_8a8_5_nf; +extern cpuop_func op_8a8_5_ff; +extern cpuop_func op_8b0_5_nf; +extern cpuop_func op_8b0_5_ff; +extern cpuop_func op_8b8_5_nf; +extern cpuop_func op_8b8_5_ff; +extern cpuop_func op_8b9_5_nf; +extern cpuop_func op_8b9_5_ff; +extern cpuop_func op_8ba_5_nf; +extern cpuop_func op_8ba_5_ff; +extern cpuop_func op_8bb_5_nf; +extern cpuop_func op_8bb_5_ff; +extern cpuop_func op_8c0_5_nf; +extern cpuop_func op_8c0_5_ff; +extern cpuop_func op_8d0_5_nf; +extern cpuop_func op_8d0_5_ff; +extern cpuop_func op_8d8_5_nf; +extern cpuop_func op_8d8_5_ff; +extern cpuop_func op_8e0_5_nf; +extern cpuop_func op_8e0_5_ff; +extern cpuop_func op_8e8_5_nf; +extern cpuop_func op_8e8_5_ff; +extern cpuop_func op_8f0_5_nf; +extern cpuop_func op_8f0_5_ff; +extern cpuop_func op_8f8_5_nf; +extern cpuop_func op_8f8_5_ff; +extern cpuop_func op_8f9_5_nf; +extern cpuop_func op_8f9_5_ff; +extern cpuop_func op_8fa_5_nf; +extern cpuop_func op_8fa_5_ff; +extern cpuop_func op_8fb_5_nf; +extern cpuop_func op_8fb_5_ff; +extern cpuop_func op_a00_5_nf; +extern cpuop_func op_a00_5_ff; +extern cpuop_func op_a10_5_nf; +extern cpuop_func op_a10_5_ff; +extern cpuop_func op_a18_5_nf; +extern cpuop_func op_a18_5_ff; +extern cpuop_func op_a20_5_nf; +extern cpuop_func op_a20_5_ff; +extern cpuop_func op_a28_5_nf; +extern cpuop_func op_a28_5_ff; +extern cpuop_func op_a30_5_nf; +extern cpuop_func op_a30_5_ff; +extern cpuop_func op_a38_5_nf; +extern cpuop_func op_a38_5_ff; +extern cpuop_func op_a39_5_nf; +extern cpuop_func op_a39_5_ff; +extern cpuop_func op_a3c_5_nf; +extern cpuop_func op_a3c_5_ff; +extern cpuop_func op_a40_5_nf; +extern cpuop_func op_a40_5_ff; +extern cpuop_func op_a50_5_nf; +extern cpuop_func op_a50_5_ff; +extern cpuop_func op_a58_5_nf; +extern cpuop_func op_a58_5_ff; +extern cpuop_func op_a60_5_nf; +extern cpuop_func op_a60_5_ff; +extern cpuop_func op_a68_5_nf; +extern cpuop_func op_a68_5_ff; +extern cpuop_func op_a70_5_nf; +extern cpuop_func op_a70_5_ff; +extern cpuop_func op_a78_5_nf; +extern cpuop_func op_a78_5_ff; +extern cpuop_func op_a79_5_nf; +extern cpuop_func op_a79_5_ff; +extern cpuop_func op_a7c_5_nf; +extern cpuop_func op_a7c_5_ff; +extern cpuop_func op_a80_5_nf; +extern cpuop_func op_a80_5_ff; +extern cpuop_func op_a90_5_nf; +extern cpuop_func op_a90_5_ff; +extern cpuop_func op_a98_5_nf; +extern cpuop_func op_a98_5_ff; +extern cpuop_func op_aa0_5_nf; +extern cpuop_func op_aa0_5_ff; +extern cpuop_func op_aa8_5_nf; +extern cpuop_func op_aa8_5_ff; +extern cpuop_func op_ab0_5_nf; +extern cpuop_func op_ab0_5_ff; +extern cpuop_func op_ab8_5_nf; +extern cpuop_func op_ab8_5_ff; +extern cpuop_func op_ab9_5_nf; +extern cpuop_func op_ab9_5_ff; +extern cpuop_func op_c00_5_nf; +extern cpuop_func op_c00_5_ff; +extern cpuop_func op_c10_5_nf; +extern cpuop_func op_c10_5_ff; +extern cpuop_func op_c18_5_nf; +extern cpuop_func op_c18_5_ff; +extern cpuop_func op_c20_5_nf; +extern cpuop_func op_c20_5_ff; +extern cpuop_func op_c28_5_nf; +extern cpuop_func op_c28_5_ff; +extern cpuop_func op_c30_5_nf; +extern cpuop_func op_c30_5_ff; +extern cpuop_func op_c38_5_nf; +extern cpuop_func op_c38_5_ff; +extern cpuop_func op_c39_5_nf; +extern cpuop_func op_c39_5_ff; +extern cpuop_func op_c3a_5_nf; +extern cpuop_func op_c3a_5_ff; +extern cpuop_func op_c3b_5_nf; +extern cpuop_func op_c3b_5_ff; +extern cpuop_func op_c40_5_nf; +extern cpuop_func op_c40_5_ff; +extern cpuop_func op_c50_5_nf; +extern cpuop_func op_c50_5_ff; +extern cpuop_func op_c58_5_nf; +extern cpuop_func op_c58_5_ff; +extern cpuop_func op_c60_5_nf; +extern cpuop_func op_c60_5_ff; +extern cpuop_func op_c68_5_nf; +extern cpuop_func op_c68_5_ff; +extern cpuop_func op_c70_5_nf; +extern cpuop_func op_c70_5_ff; +extern cpuop_func op_c78_5_nf; +extern cpuop_func op_c78_5_ff; +extern cpuop_func op_c79_5_nf; +extern cpuop_func op_c79_5_ff; +extern cpuop_func op_c7a_5_nf; +extern cpuop_func op_c7a_5_ff; +extern cpuop_func op_c7b_5_nf; +extern cpuop_func op_c7b_5_ff; +extern cpuop_func op_c80_5_nf; +extern cpuop_func op_c80_5_ff; +extern cpuop_func op_c90_5_nf; +extern cpuop_func op_c90_5_ff; +extern cpuop_func op_c98_5_nf; +extern cpuop_func op_c98_5_ff; +extern cpuop_func op_ca0_5_nf; +extern cpuop_func op_ca0_5_ff; +extern cpuop_func op_ca8_5_nf; +extern cpuop_func op_ca8_5_ff; +extern cpuop_func op_cb0_5_nf; +extern cpuop_func op_cb0_5_ff; +extern cpuop_func op_cb8_5_nf; +extern cpuop_func op_cb8_5_ff; +extern cpuop_func op_cb9_5_nf; +extern cpuop_func op_cb9_5_ff; +extern cpuop_func op_cba_5_nf; +extern cpuop_func op_cba_5_ff; +extern cpuop_func op_cbb_5_nf; +extern cpuop_func op_cbb_5_ff; +extern cpuop_func op_1000_5_nf; +extern cpuop_func op_1000_5_ff; +extern cpuop_func op_1008_5_nf; +extern cpuop_func op_1008_5_ff; +extern cpuop_func op_1010_5_nf; +extern cpuop_func op_1010_5_ff; +extern cpuop_func op_1018_5_nf; +extern cpuop_func op_1018_5_ff; +extern cpuop_func op_1020_5_nf; +extern cpuop_func op_1020_5_ff; +extern cpuop_func op_1028_5_nf; +extern cpuop_func op_1028_5_ff; +extern cpuop_func op_1030_5_nf; +extern cpuop_func op_1030_5_ff; +extern cpuop_func op_1038_5_nf; +extern cpuop_func op_1038_5_ff; +extern cpuop_func op_1039_5_nf; +extern cpuop_func op_1039_5_ff; +extern cpuop_func op_103a_5_nf; +extern cpuop_func op_103a_5_ff; +extern cpuop_func op_103b_5_nf; +extern cpuop_func op_103b_5_ff; +extern cpuop_func op_103c_5_nf; +extern cpuop_func op_103c_5_ff; +extern cpuop_func op_1080_5_nf; +extern cpuop_func op_1080_5_ff; +extern cpuop_func op_1088_5_nf; +extern cpuop_func op_1088_5_ff; +extern cpuop_func op_1090_5_nf; +extern cpuop_func op_1090_5_ff; +extern cpuop_func op_1098_5_nf; +extern cpuop_func op_1098_5_ff; +extern cpuop_func op_10a0_5_nf; +extern cpuop_func op_10a0_5_ff; +extern cpuop_func op_10a8_5_nf; +extern cpuop_func op_10a8_5_ff; +extern cpuop_func op_10b0_5_nf; +extern cpuop_func op_10b0_5_ff; +extern cpuop_func op_10b8_5_nf; +extern cpuop_func op_10b8_5_ff; +extern cpuop_func op_10b9_5_nf; +extern cpuop_func op_10b9_5_ff; +extern cpuop_func op_10ba_5_nf; +extern cpuop_func op_10ba_5_ff; +extern cpuop_func op_10bb_5_nf; +extern cpuop_func op_10bb_5_ff; +extern cpuop_func op_10bc_5_nf; +extern cpuop_func op_10bc_5_ff; +extern cpuop_func op_10c0_5_nf; +extern cpuop_func op_10c0_5_ff; +extern cpuop_func op_10c8_5_nf; +extern cpuop_func op_10c8_5_ff; +extern cpuop_func op_10d0_5_nf; +extern cpuop_func op_10d0_5_ff; +extern cpuop_func op_10d8_5_nf; +extern cpuop_func op_10d8_5_ff; +extern cpuop_func op_10e0_5_nf; +extern cpuop_func op_10e0_5_ff; +extern cpuop_func op_10e8_5_nf; +extern cpuop_func op_10e8_5_ff; +extern cpuop_func op_10f0_5_nf; +extern cpuop_func op_10f0_5_ff; +extern cpuop_func op_10f8_5_nf; +extern cpuop_func op_10f8_5_ff; +extern cpuop_func op_10f9_5_nf; +extern cpuop_func op_10f9_5_ff; +extern cpuop_func op_10fa_5_nf; +extern cpuop_func op_10fa_5_ff; +extern cpuop_func op_10fb_5_nf; +extern cpuop_func op_10fb_5_ff; +extern cpuop_func op_10fc_5_nf; +extern cpuop_func op_10fc_5_ff; +extern cpuop_func op_1100_5_nf; +extern cpuop_func op_1100_5_ff; +extern cpuop_func op_1108_5_nf; +extern cpuop_func op_1108_5_ff; +extern cpuop_func op_1110_5_nf; +extern cpuop_func op_1110_5_ff; +extern cpuop_func op_1118_5_nf; +extern cpuop_func op_1118_5_ff; +extern cpuop_func op_1120_5_nf; +extern cpuop_func op_1120_5_ff; +extern cpuop_func op_1128_5_nf; +extern cpuop_func op_1128_5_ff; +extern cpuop_func op_1130_5_nf; +extern cpuop_func op_1130_5_ff; +extern cpuop_func op_1138_5_nf; +extern cpuop_func op_1138_5_ff; +extern cpuop_func op_1139_5_nf; +extern cpuop_func op_1139_5_ff; +extern cpuop_func op_113a_5_nf; +extern cpuop_func op_113a_5_ff; +extern cpuop_func op_113b_5_nf; +extern cpuop_func op_113b_5_ff; +extern cpuop_func op_113c_5_nf; +extern cpuop_func op_113c_5_ff; +extern cpuop_func op_1140_5_nf; +extern cpuop_func op_1140_5_ff; +extern cpuop_func op_1148_5_nf; +extern cpuop_func op_1148_5_ff; +extern cpuop_func op_1150_5_nf; +extern cpuop_func op_1150_5_ff; +extern cpuop_func op_1158_5_nf; +extern cpuop_func op_1158_5_ff; +extern cpuop_func op_1160_5_nf; +extern cpuop_func op_1160_5_ff; +extern cpuop_func op_1168_5_nf; +extern cpuop_func op_1168_5_ff; +extern cpuop_func op_1170_5_nf; +extern cpuop_func op_1170_5_ff; +extern cpuop_func op_1178_5_nf; +extern cpuop_func op_1178_5_ff; +extern cpuop_func op_1179_5_nf; +extern cpuop_func op_1179_5_ff; +extern cpuop_func op_117a_5_nf; +extern cpuop_func op_117a_5_ff; +extern cpuop_func op_117b_5_nf; +extern cpuop_func op_117b_5_ff; +extern cpuop_func op_117c_5_nf; +extern cpuop_func op_117c_5_ff; +extern cpuop_func op_1180_5_nf; +extern cpuop_func op_1180_5_ff; +extern cpuop_func op_1188_5_nf; +extern cpuop_func op_1188_5_ff; +extern cpuop_func op_1190_5_nf; +extern cpuop_func op_1190_5_ff; +extern cpuop_func op_1198_5_nf; +extern cpuop_func op_1198_5_ff; +extern cpuop_func op_11a0_5_nf; +extern cpuop_func op_11a0_5_ff; +extern cpuop_func op_11a8_5_nf; +extern cpuop_func op_11a8_5_ff; +extern cpuop_func op_11b0_5_nf; +extern cpuop_func op_11b0_5_ff; +extern cpuop_func op_11b8_5_nf; +extern cpuop_func op_11b8_5_ff; +extern cpuop_func op_11b9_5_nf; +extern cpuop_func op_11b9_5_ff; +extern cpuop_func op_11ba_5_nf; +extern cpuop_func op_11ba_5_ff; +extern cpuop_func op_11bb_5_nf; +extern cpuop_func op_11bb_5_ff; +extern cpuop_func op_11bc_5_nf; +extern cpuop_func op_11bc_5_ff; +extern cpuop_func op_11c0_5_nf; +extern cpuop_func op_11c0_5_ff; +extern cpuop_func op_11c8_5_nf; +extern cpuop_func op_11c8_5_ff; +extern cpuop_func op_11d0_5_nf; +extern cpuop_func op_11d0_5_ff; +extern cpuop_func op_11d8_5_nf; +extern cpuop_func op_11d8_5_ff; +extern cpuop_func op_11e0_5_nf; +extern cpuop_func op_11e0_5_ff; +extern cpuop_func op_11e8_5_nf; +extern cpuop_func op_11e8_5_ff; +extern cpuop_func op_11f0_5_nf; +extern cpuop_func op_11f0_5_ff; +extern cpuop_func op_11f8_5_nf; +extern cpuop_func op_11f8_5_ff; +extern cpuop_func op_11f9_5_nf; +extern cpuop_func op_11f9_5_ff; +extern cpuop_func op_11fa_5_nf; +extern cpuop_func op_11fa_5_ff; +extern cpuop_func op_11fb_5_nf; +extern cpuop_func op_11fb_5_ff; +extern cpuop_func op_11fc_5_nf; +extern cpuop_func op_11fc_5_ff; +extern cpuop_func op_13c0_5_nf; +extern cpuop_func op_13c0_5_ff; +extern cpuop_func op_13c8_5_nf; +extern cpuop_func op_13c8_5_ff; +extern cpuop_func op_13d0_5_nf; +extern cpuop_func op_13d0_5_ff; +extern cpuop_func op_13d8_5_nf; +extern cpuop_func op_13d8_5_ff; +extern cpuop_func op_13e0_5_nf; +extern cpuop_func op_13e0_5_ff; +extern cpuop_func op_13e8_5_nf; +extern cpuop_func op_13e8_5_ff; +extern cpuop_func op_13f0_5_nf; +extern cpuop_func op_13f0_5_ff; +extern cpuop_func op_13f8_5_nf; +extern cpuop_func op_13f8_5_ff; +extern cpuop_func op_13f9_5_nf; +extern cpuop_func op_13f9_5_ff; +extern cpuop_func op_13fa_5_nf; +extern cpuop_func op_13fa_5_ff; +extern cpuop_func op_13fb_5_nf; +extern cpuop_func op_13fb_5_ff; +extern cpuop_func op_13fc_5_nf; +extern cpuop_func op_13fc_5_ff; +extern cpuop_func op_2000_5_nf; +extern cpuop_func op_2000_5_ff; +extern cpuop_func op_2008_5_nf; +extern cpuop_func op_2008_5_ff; +extern cpuop_func op_2010_5_nf; +extern cpuop_func op_2010_5_ff; +extern cpuop_func op_2018_5_nf; +extern cpuop_func op_2018_5_ff; +extern cpuop_func op_2020_5_nf; +extern cpuop_func op_2020_5_ff; +extern cpuop_func op_2028_5_nf; +extern cpuop_func op_2028_5_ff; +extern cpuop_func op_2030_5_nf; +extern cpuop_func op_2030_5_ff; +extern cpuop_func op_2038_5_nf; +extern cpuop_func op_2038_5_ff; +extern cpuop_func op_2039_5_nf; +extern cpuop_func op_2039_5_ff; +extern cpuop_func op_203a_5_nf; +extern cpuop_func op_203a_5_ff; +extern cpuop_func op_203b_5_nf; +extern cpuop_func op_203b_5_ff; +extern cpuop_func op_203c_5_nf; +extern cpuop_func op_203c_5_ff; +extern cpuop_func op_2040_5_nf; +extern cpuop_func op_2040_5_ff; +extern cpuop_func op_2048_5_nf; +extern cpuop_func op_2048_5_ff; +extern cpuop_func op_2050_5_nf; +extern cpuop_func op_2050_5_ff; +extern cpuop_func op_2058_5_nf; +extern cpuop_func op_2058_5_ff; +extern cpuop_func op_2060_5_nf; +extern cpuop_func op_2060_5_ff; +extern cpuop_func op_2068_5_nf; +extern cpuop_func op_2068_5_ff; +extern cpuop_func op_2070_5_nf; +extern cpuop_func op_2070_5_ff; +extern cpuop_func op_2078_5_nf; +extern cpuop_func op_2078_5_ff; +extern cpuop_func op_2079_5_nf; +extern cpuop_func op_2079_5_ff; +extern cpuop_func op_207a_5_nf; +extern cpuop_func op_207a_5_ff; +extern cpuop_func op_207b_5_nf; +extern cpuop_func op_207b_5_ff; +extern cpuop_func op_207c_5_nf; +extern cpuop_func op_207c_5_ff; +extern cpuop_func op_2080_5_nf; +extern cpuop_func op_2080_5_ff; +extern cpuop_func op_2088_5_nf; +extern cpuop_func op_2088_5_ff; +extern cpuop_func op_2090_5_nf; +extern cpuop_func op_2090_5_ff; +extern cpuop_func op_2098_5_nf; +extern cpuop_func op_2098_5_ff; +extern cpuop_func op_20a0_5_nf; +extern cpuop_func op_20a0_5_ff; +extern cpuop_func op_20a8_5_nf; +extern cpuop_func op_20a8_5_ff; +extern cpuop_func op_20b0_5_nf; +extern cpuop_func op_20b0_5_ff; +extern cpuop_func op_20b8_5_nf; +extern cpuop_func op_20b8_5_ff; +extern cpuop_func op_20b9_5_nf; +extern cpuop_func op_20b9_5_ff; +extern cpuop_func op_20ba_5_nf; +extern cpuop_func op_20ba_5_ff; +extern cpuop_func op_20bb_5_nf; +extern cpuop_func op_20bb_5_ff; +extern cpuop_func op_20bc_5_nf; +extern cpuop_func op_20bc_5_ff; +extern cpuop_func op_20c0_5_nf; +extern cpuop_func op_20c0_5_ff; +extern cpuop_func op_20c8_5_nf; +extern cpuop_func op_20c8_5_ff; +extern cpuop_func op_20d0_5_nf; +extern cpuop_func op_20d0_5_ff; +extern cpuop_func op_20d8_5_nf; +extern cpuop_func op_20d8_5_ff; +extern cpuop_func op_20e0_5_nf; +extern cpuop_func op_20e0_5_ff; +extern cpuop_func op_20e8_5_nf; +extern cpuop_func op_20e8_5_ff; +extern cpuop_func op_20f0_5_nf; +extern cpuop_func op_20f0_5_ff; +extern cpuop_func op_20f8_5_nf; +extern cpuop_func op_20f8_5_ff; +extern cpuop_func op_20f9_5_nf; +extern cpuop_func op_20f9_5_ff; +extern cpuop_func op_20fa_5_nf; +extern cpuop_func op_20fa_5_ff; +extern cpuop_func op_20fb_5_nf; +extern cpuop_func op_20fb_5_ff; +extern cpuop_func op_20fc_5_nf; +extern cpuop_func op_20fc_5_ff; +extern cpuop_func op_2100_5_nf; +extern cpuop_func op_2100_5_ff; +extern cpuop_func op_2108_5_nf; +extern cpuop_func op_2108_5_ff; +extern cpuop_func op_2110_5_nf; +extern cpuop_func op_2110_5_ff; +extern cpuop_func op_2118_5_nf; +extern cpuop_func op_2118_5_ff; +extern cpuop_func op_2120_5_nf; +extern cpuop_func op_2120_5_ff; +extern cpuop_func op_2128_5_nf; +extern cpuop_func op_2128_5_ff; +extern cpuop_func op_2130_5_nf; +extern cpuop_func op_2130_5_ff; +extern cpuop_func op_2138_5_nf; +extern cpuop_func op_2138_5_ff; +extern cpuop_func op_2139_5_nf; +extern cpuop_func op_2139_5_ff; +extern cpuop_func op_213a_5_nf; +extern cpuop_func op_213a_5_ff; +extern cpuop_func op_213b_5_nf; +extern cpuop_func op_213b_5_ff; +extern cpuop_func op_213c_5_nf; +extern cpuop_func op_213c_5_ff; +extern cpuop_func op_2140_5_nf; +extern cpuop_func op_2140_5_ff; +extern cpuop_func op_2148_5_nf; +extern cpuop_func op_2148_5_ff; +extern cpuop_func op_2150_5_nf; +extern cpuop_func op_2150_5_ff; +extern cpuop_func op_2158_5_nf; +extern cpuop_func op_2158_5_ff; +extern cpuop_func op_2160_5_nf; +extern cpuop_func op_2160_5_ff; +extern cpuop_func op_2168_5_nf; +extern cpuop_func op_2168_5_ff; +extern cpuop_func op_2170_5_nf; +extern cpuop_func op_2170_5_ff; +extern cpuop_func op_2178_5_nf; +extern cpuop_func op_2178_5_ff; +extern cpuop_func op_2179_5_nf; +extern cpuop_func op_2179_5_ff; +extern cpuop_func op_217a_5_nf; +extern cpuop_func op_217a_5_ff; +extern cpuop_func op_217b_5_nf; +extern cpuop_func op_217b_5_ff; +extern cpuop_func op_217c_5_nf; +extern cpuop_func op_217c_5_ff; +extern cpuop_func op_2180_5_nf; +extern cpuop_func op_2180_5_ff; +extern cpuop_func op_2188_5_nf; +extern cpuop_func op_2188_5_ff; +extern cpuop_func op_2190_5_nf; +extern cpuop_func op_2190_5_ff; +extern cpuop_func op_2198_5_nf; +extern cpuop_func op_2198_5_ff; +extern cpuop_func op_21a0_5_nf; +extern cpuop_func op_21a0_5_ff; +extern cpuop_func op_21a8_5_nf; +extern cpuop_func op_21a8_5_ff; +extern cpuop_func op_21b0_5_nf; +extern cpuop_func op_21b0_5_ff; +extern cpuop_func op_21b8_5_nf; +extern cpuop_func op_21b8_5_ff; +extern cpuop_func op_21b9_5_nf; +extern cpuop_func op_21b9_5_ff; +extern cpuop_func op_21ba_5_nf; +extern cpuop_func op_21ba_5_ff; +extern cpuop_func op_21bb_5_nf; +extern cpuop_func op_21bb_5_ff; +extern cpuop_func op_21bc_5_nf; +extern cpuop_func op_21bc_5_ff; +extern cpuop_func op_21c0_5_nf; +extern cpuop_func op_21c0_5_ff; +extern cpuop_func op_21c8_5_nf; +extern cpuop_func op_21c8_5_ff; +extern cpuop_func op_21d0_5_nf; +extern cpuop_func op_21d0_5_ff; +extern cpuop_func op_21d8_5_nf; +extern cpuop_func op_21d8_5_ff; +extern cpuop_func op_21e0_5_nf; +extern cpuop_func op_21e0_5_ff; +extern cpuop_func op_21e8_5_nf; +extern cpuop_func op_21e8_5_ff; +extern cpuop_func op_21f0_5_nf; +extern cpuop_func op_21f0_5_ff; +extern cpuop_func op_21f8_5_nf; +extern cpuop_func op_21f8_5_ff; +extern cpuop_func op_21f9_5_nf; +extern cpuop_func op_21f9_5_ff; +extern cpuop_func op_21fa_5_nf; +extern cpuop_func op_21fa_5_ff; +extern cpuop_func op_21fb_5_nf; +extern cpuop_func op_21fb_5_ff; +extern cpuop_func op_21fc_5_nf; +extern cpuop_func op_21fc_5_ff; +extern cpuop_func op_23c0_5_nf; +extern cpuop_func op_23c0_5_ff; +extern cpuop_func op_23c8_5_nf; +extern cpuop_func op_23c8_5_ff; +extern cpuop_func op_23d0_5_nf; +extern cpuop_func op_23d0_5_ff; +extern cpuop_func op_23d8_5_nf; +extern cpuop_func op_23d8_5_ff; +extern cpuop_func op_23e0_5_nf; +extern cpuop_func op_23e0_5_ff; +extern cpuop_func op_23e8_5_nf; +extern cpuop_func op_23e8_5_ff; +extern cpuop_func op_23f0_5_nf; +extern cpuop_func op_23f0_5_ff; +extern cpuop_func op_23f8_5_nf; +extern cpuop_func op_23f8_5_ff; +extern cpuop_func op_23f9_5_nf; +extern cpuop_func op_23f9_5_ff; +extern cpuop_func op_23fa_5_nf; +extern cpuop_func op_23fa_5_ff; +extern cpuop_func op_23fb_5_nf; +extern cpuop_func op_23fb_5_ff; +extern cpuop_func op_23fc_5_nf; +extern cpuop_func op_23fc_5_ff; +extern cpuop_func op_3000_5_nf; +extern cpuop_func op_3000_5_ff; +extern cpuop_func op_3008_5_nf; +extern cpuop_func op_3008_5_ff; +extern cpuop_func op_3010_5_nf; +extern cpuop_func op_3010_5_ff; +extern cpuop_func op_3018_5_nf; +extern cpuop_func op_3018_5_ff; +extern cpuop_func op_3020_5_nf; +extern cpuop_func op_3020_5_ff; +extern cpuop_func op_3028_5_nf; +extern cpuop_func op_3028_5_ff; +extern cpuop_func op_3030_5_nf; +extern cpuop_func op_3030_5_ff; +extern cpuop_func op_3038_5_nf; +extern cpuop_func op_3038_5_ff; +extern cpuop_func op_3039_5_nf; +extern cpuop_func op_3039_5_ff; +extern cpuop_func op_303a_5_nf; +extern cpuop_func op_303a_5_ff; +extern cpuop_func op_303b_5_nf; +extern cpuop_func op_303b_5_ff; +extern cpuop_func op_303c_5_nf; +extern cpuop_func op_303c_5_ff; +extern cpuop_func op_3040_5_nf; +extern cpuop_func op_3040_5_ff; +extern cpuop_func op_3048_5_nf; +extern cpuop_func op_3048_5_ff; +extern cpuop_func op_3050_5_nf; +extern cpuop_func op_3050_5_ff; +extern cpuop_func op_3058_5_nf; +extern cpuop_func op_3058_5_ff; +extern cpuop_func op_3060_5_nf; +extern cpuop_func op_3060_5_ff; +extern cpuop_func op_3068_5_nf; +extern cpuop_func op_3068_5_ff; +extern cpuop_func op_3070_5_nf; +extern cpuop_func op_3070_5_ff; +extern cpuop_func op_3078_5_nf; +extern cpuop_func op_3078_5_ff; +extern cpuop_func op_3079_5_nf; +extern cpuop_func op_3079_5_ff; +extern cpuop_func op_307a_5_nf; +extern cpuop_func op_307a_5_ff; +extern cpuop_func op_307b_5_nf; +extern cpuop_func op_307b_5_ff; +extern cpuop_func op_307c_5_nf; +extern cpuop_func op_307c_5_ff; +extern cpuop_func op_3080_5_nf; +extern cpuop_func op_3080_5_ff; +extern cpuop_func op_3088_5_nf; +extern cpuop_func op_3088_5_ff; +extern cpuop_func op_3090_5_nf; +extern cpuop_func op_3090_5_ff; +extern cpuop_func op_3098_5_nf; +extern cpuop_func op_3098_5_ff; +extern cpuop_func op_30a0_5_nf; +extern cpuop_func op_30a0_5_ff; +extern cpuop_func op_30a8_5_nf; +extern cpuop_func op_30a8_5_ff; +extern cpuop_func op_30b0_5_nf; +extern cpuop_func op_30b0_5_ff; +extern cpuop_func op_30b8_5_nf; +extern cpuop_func op_30b8_5_ff; +extern cpuop_func op_30b9_5_nf; +extern cpuop_func op_30b9_5_ff; +extern cpuop_func op_30ba_5_nf; +extern cpuop_func op_30ba_5_ff; +extern cpuop_func op_30bb_5_nf; +extern cpuop_func op_30bb_5_ff; +extern cpuop_func op_30bc_5_nf; +extern cpuop_func op_30bc_5_ff; +extern cpuop_func op_30c0_5_nf; +extern cpuop_func op_30c0_5_ff; +extern cpuop_func op_30c8_5_nf; +extern cpuop_func op_30c8_5_ff; +extern cpuop_func op_30d0_5_nf; +extern cpuop_func op_30d0_5_ff; +extern cpuop_func op_30d8_5_nf; +extern cpuop_func op_30d8_5_ff; +extern cpuop_func op_30e0_5_nf; +extern cpuop_func op_30e0_5_ff; +extern cpuop_func op_30e8_5_nf; +extern cpuop_func op_30e8_5_ff; +extern cpuop_func op_30f0_5_nf; +extern cpuop_func op_30f0_5_ff; +extern cpuop_func op_30f8_5_nf; +extern cpuop_func op_30f8_5_ff; +extern cpuop_func op_30f9_5_nf; +extern cpuop_func op_30f9_5_ff; +extern cpuop_func op_30fa_5_nf; +extern cpuop_func op_30fa_5_ff; +extern cpuop_func op_30fb_5_nf; +extern cpuop_func op_30fb_5_ff; +extern cpuop_func op_30fc_5_nf; +extern cpuop_func op_30fc_5_ff; +extern cpuop_func op_3100_5_nf; +extern cpuop_func op_3100_5_ff; +extern cpuop_func op_3108_5_nf; +extern cpuop_func op_3108_5_ff; +extern cpuop_func op_3110_5_nf; +extern cpuop_func op_3110_5_ff; +extern cpuop_func op_3118_5_nf; +extern cpuop_func op_3118_5_ff; +extern cpuop_func op_3120_5_nf; +extern cpuop_func op_3120_5_ff; +extern cpuop_func op_3128_5_nf; +extern cpuop_func op_3128_5_ff; +extern cpuop_func op_3130_5_nf; +extern cpuop_func op_3130_5_ff; +extern cpuop_func op_3138_5_nf; +extern cpuop_func op_3138_5_ff; +extern cpuop_func op_3139_5_nf; +extern cpuop_func op_3139_5_ff; +extern cpuop_func op_313a_5_nf; +extern cpuop_func op_313a_5_ff; +extern cpuop_func op_313b_5_nf; +extern cpuop_func op_313b_5_ff; +extern cpuop_func op_313c_5_nf; +extern cpuop_func op_313c_5_ff; +extern cpuop_func op_3140_5_nf; +extern cpuop_func op_3140_5_ff; +extern cpuop_func op_3148_5_nf; +extern cpuop_func op_3148_5_ff; +extern cpuop_func op_3150_5_nf; +extern cpuop_func op_3150_5_ff; +extern cpuop_func op_3158_5_nf; +extern cpuop_func op_3158_5_ff; +extern cpuop_func op_3160_5_nf; +extern cpuop_func op_3160_5_ff; +extern cpuop_func op_3168_5_nf; +extern cpuop_func op_3168_5_ff; +extern cpuop_func op_3170_5_nf; +extern cpuop_func op_3170_5_ff; +extern cpuop_func op_3178_5_nf; +extern cpuop_func op_3178_5_ff; +extern cpuop_func op_3179_5_nf; +extern cpuop_func op_3179_5_ff; +extern cpuop_func op_317a_5_nf; +extern cpuop_func op_317a_5_ff; +extern cpuop_func op_317b_5_nf; +extern cpuop_func op_317b_5_ff; +extern cpuop_func op_317c_5_nf; +extern cpuop_func op_317c_5_ff; +extern cpuop_func op_3180_5_nf; +extern cpuop_func op_3180_5_ff; +extern cpuop_func op_3188_5_nf; +extern cpuop_func op_3188_5_ff; +extern cpuop_func op_3190_5_nf; +extern cpuop_func op_3190_5_ff; +extern cpuop_func op_3198_5_nf; +extern cpuop_func op_3198_5_ff; +extern cpuop_func op_31a0_5_nf; +extern cpuop_func op_31a0_5_ff; +extern cpuop_func op_31a8_5_nf; +extern cpuop_func op_31a8_5_ff; +extern cpuop_func op_31b0_5_nf; +extern cpuop_func op_31b0_5_ff; +extern cpuop_func op_31b8_5_nf; +extern cpuop_func op_31b8_5_ff; +extern cpuop_func op_31b9_5_nf; +extern cpuop_func op_31b9_5_ff; +extern cpuop_func op_31ba_5_nf; +extern cpuop_func op_31ba_5_ff; +extern cpuop_func op_31bb_5_nf; +extern cpuop_func op_31bb_5_ff; +extern cpuop_func op_31bc_5_nf; +extern cpuop_func op_31bc_5_ff; +extern cpuop_func op_31c0_5_nf; +extern cpuop_func op_31c0_5_ff; +extern cpuop_func op_31c8_5_nf; +extern cpuop_func op_31c8_5_ff; +extern cpuop_func op_31d0_5_nf; +extern cpuop_func op_31d0_5_ff; +extern cpuop_func op_31d8_5_nf; +extern cpuop_func op_31d8_5_ff; +extern cpuop_func op_31e0_5_nf; +extern cpuop_func op_31e0_5_ff; +extern cpuop_func op_31e8_5_nf; +extern cpuop_func op_31e8_5_ff; +extern cpuop_func op_31f0_5_nf; +extern cpuop_func op_31f0_5_ff; +extern cpuop_func op_31f8_5_nf; +extern cpuop_func op_31f8_5_ff; +extern cpuop_func op_31f9_5_nf; +extern cpuop_func op_31f9_5_ff; +extern cpuop_func op_31fa_5_nf; +extern cpuop_func op_31fa_5_ff; +extern cpuop_func op_31fb_5_nf; +extern cpuop_func op_31fb_5_ff; +extern cpuop_func op_31fc_5_nf; +extern cpuop_func op_31fc_5_ff; +extern cpuop_func op_33c0_5_nf; +extern cpuop_func op_33c0_5_ff; +extern cpuop_func op_33c8_5_nf; +extern cpuop_func op_33c8_5_ff; +extern cpuop_func op_33d0_5_nf; +extern cpuop_func op_33d0_5_ff; +extern cpuop_func op_33d8_5_nf; +extern cpuop_func op_33d8_5_ff; +extern cpuop_func op_33e0_5_nf; +extern cpuop_func op_33e0_5_ff; +extern cpuop_func op_33e8_5_nf; +extern cpuop_func op_33e8_5_ff; +extern cpuop_func op_33f0_5_nf; +extern cpuop_func op_33f0_5_ff; +extern cpuop_func op_33f8_5_nf; +extern cpuop_func op_33f8_5_ff; +extern cpuop_func op_33f9_5_nf; +extern cpuop_func op_33f9_5_ff; +extern cpuop_func op_33fa_5_nf; +extern cpuop_func op_33fa_5_ff; +extern cpuop_func op_33fb_5_nf; +extern cpuop_func op_33fb_5_ff; +extern cpuop_func op_33fc_5_nf; +extern cpuop_func op_33fc_5_ff; +extern cpuop_func op_4000_5_nf; +extern cpuop_func op_4000_5_ff; +extern cpuop_func op_4010_5_nf; +extern cpuop_func op_4010_5_ff; +extern cpuop_func op_4018_5_nf; +extern cpuop_func op_4018_5_ff; +extern cpuop_func op_4020_5_nf; +extern cpuop_func op_4020_5_ff; +extern cpuop_func op_4028_5_nf; +extern cpuop_func op_4028_5_ff; +extern cpuop_func op_4030_5_nf; +extern cpuop_func op_4030_5_ff; +extern cpuop_func op_4038_5_nf; +extern cpuop_func op_4038_5_ff; +extern cpuop_func op_4039_5_nf; +extern cpuop_func op_4039_5_ff; +extern cpuop_func op_4040_5_nf; +extern cpuop_func op_4040_5_ff; +extern cpuop_func op_4050_5_nf; +extern cpuop_func op_4050_5_ff; +extern cpuop_func op_4058_5_nf; +extern cpuop_func op_4058_5_ff; +extern cpuop_func op_4060_5_nf; +extern cpuop_func op_4060_5_ff; +extern cpuop_func op_4068_5_nf; +extern cpuop_func op_4068_5_ff; +extern cpuop_func op_4070_5_nf; +extern cpuop_func op_4070_5_ff; +extern cpuop_func op_4078_5_nf; +extern cpuop_func op_4078_5_ff; +extern cpuop_func op_4079_5_nf; +extern cpuop_func op_4079_5_ff; +extern cpuop_func op_4080_5_nf; +extern cpuop_func op_4080_5_ff; +extern cpuop_func op_4090_5_nf; +extern cpuop_func op_4090_5_ff; +extern cpuop_func op_4098_5_nf; +extern cpuop_func op_4098_5_ff; +extern cpuop_func op_40a0_5_nf; +extern cpuop_func op_40a0_5_ff; +extern cpuop_func op_40a8_5_nf; +extern cpuop_func op_40a8_5_ff; +extern cpuop_func op_40b0_5_nf; +extern cpuop_func op_40b0_5_ff; +extern cpuop_func op_40b8_5_nf; +extern cpuop_func op_40b8_5_ff; +extern cpuop_func op_40b9_5_nf; +extern cpuop_func op_40b9_5_ff; +extern cpuop_func op_40c0_5_nf; +extern cpuop_func op_40c0_5_ff; +extern cpuop_func op_40d0_5_nf; +extern cpuop_func op_40d0_5_ff; +extern cpuop_func op_40d8_5_nf; +extern cpuop_func op_40d8_5_ff; +extern cpuop_func op_40e0_5_nf; +extern cpuop_func op_40e0_5_ff; +extern cpuop_func op_40e8_5_nf; +extern cpuop_func op_40e8_5_ff; +extern cpuop_func op_40f0_5_nf; +extern cpuop_func op_40f0_5_ff; +extern cpuop_func op_40f8_5_nf; +extern cpuop_func op_40f8_5_ff; +extern cpuop_func op_40f9_5_nf; +extern cpuop_func op_40f9_5_ff; +extern cpuop_func op_4180_5_nf; +extern cpuop_func op_4180_5_ff; +extern cpuop_func op_4190_5_nf; +extern cpuop_func op_4190_5_ff; +extern cpuop_func op_4198_5_nf; +extern cpuop_func op_4198_5_ff; +extern cpuop_func op_41a0_5_nf; +extern cpuop_func op_41a0_5_ff; +extern cpuop_func op_41a8_5_nf; +extern cpuop_func op_41a8_5_ff; +extern cpuop_func op_41b0_5_nf; +extern cpuop_func op_41b0_5_ff; +extern cpuop_func op_41b8_5_nf; +extern cpuop_func op_41b8_5_ff; +extern cpuop_func op_41b9_5_nf; +extern cpuop_func op_41b9_5_ff; +extern cpuop_func op_41ba_5_nf; +extern cpuop_func op_41ba_5_ff; +extern cpuop_func op_41bb_5_nf; +extern cpuop_func op_41bb_5_ff; +extern cpuop_func op_41bc_5_nf; +extern cpuop_func op_41bc_5_ff; +extern cpuop_func op_41d0_5_nf; +extern cpuop_func op_41d0_5_ff; +extern cpuop_func op_41e8_5_nf; +extern cpuop_func op_41e8_5_ff; +extern cpuop_func op_41f0_5_nf; +extern cpuop_func op_41f0_5_ff; +extern cpuop_func op_41f8_5_nf; +extern cpuop_func op_41f8_5_ff; +extern cpuop_func op_41f9_5_nf; +extern cpuop_func op_41f9_5_ff; +extern cpuop_func op_41fa_5_nf; +extern cpuop_func op_41fa_5_ff; +extern cpuop_func op_41fb_5_nf; +extern cpuop_func op_41fb_5_ff; +extern cpuop_func op_4200_5_nf; +extern cpuop_func op_4200_5_ff; +extern cpuop_func op_4210_5_nf; +extern cpuop_func op_4210_5_ff; +extern cpuop_func op_4218_5_nf; +extern cpuop_func op_4218_5_ff; +extern cpuop_func op_4220_5_nf; +extern cpuop_func op_4220_5_ff; +extern cpuop_func op_4228_5_nf; +extern cpuop_func op_4228_5_ff; +extern cpuop_func op_4230_5_nf; +extern cpuop_func op_4230_5_ff; +extern cpuop_func op_4238_5_nf; +extern cpuop_func op_4238_5_ff; +extern cpuop_func op_4239_5_nf; +extern cpuop_func op_4239_5_ff; +extern cpuop_func op_4240_5_nf; +extern cpuop_func op_4240_5_ff; +extern cpuop_func op_4250_5_nf; +extern cpuop_func op_4250_5_ff; +extern cpuop_func op_4258_5_nf; +extern cpuop_func op_4258_5_ff; +extern cpuop_func op_4260_5_nf; +extern cpuop_func op_4260_5_ff; +extern cpuop_func op_4268_5_nf; +extern cpuop_func op_4268_5_ff; +extern cpuop_func op_4270_5_nf; +extern cpuop_func op_4270_5_ff; +extern cpuop_func op_4278_5_nf; +extern cpuop_func op_4278_5_ff; +extern cpuop_func op_4279_5_nf; +extern cpuop_func op_4279_5_ff; +extern cpuop_func op_4280_5_nf; +extern cpuop_func op_4280_5_ff; +extern cpuop_func op_4290_5_nf; +extern cpuop_func op_4290_5_ff; +extern cpuop_func op_4298_5_nf; +extern cpuop_func op_4298_5_ff; +extern cpuop_func op_42a0_5_nf; +extern cpuop_func op_42a0_5_ff; +extern cpuop_func op_42a8_5_nf; +extern cpuop_func op_42a8_5_ff; +extern cpuop_func op_42b0_5_nf; +extern cpuop_func op_42b0_5_ff; +extern cpuop_func op_42b8_5_nf; +extern cpuop_func op_42b8_5_ff; +extern cpuop_func op_42b9_5_nf; +extern cpuop_func op_42b9_5_ff; +extern cpuop_func op_4400_5_nf; +extern cpuop_func op_4400_5_ff; +extern cpuop_func op_4410_5_nf; +extern cpuop_func op_4410_5_ff; +extern cpuop_func op_4418_5_nf; +extern cpuop_func op_4418_5_ff; +extern cpuop_func op_4420_5_nf; +extern cpuop_func op_4420_5_ff; +extern cpuop_func op_4428_5_nf; +extern cpuop_func op_4428_5_ff; +extern cpuop_func op_4430_5_nf; +extern cpuop_func op_4430_5_ff; +extern cpuop_func op_4438_5_nf; +extern cpuop_func op_4438_5_ff; +extern cpuop_func op_4439_5_nf; +extern cpuop_func op_4439_5_ff; +extern cpuop_func op_4440_5_nf; +extern cpuop_func op_4440_5_ff; +extern cpuop_func op_4450_5_nf; +extern cpuop_func op_4450_5_ff; +extern cpuop_func op_4458_5_nf; +extern cpuop_func op_4458_5_ff; +extern cpuop_func op_4460_5_nf; +extern cpuop_func op_4460_5_ff; +extern cpuop_func op_4468_5_nf; +extern cpuop_func op_4468_5_ff; +extern cpuop_func op_4470_5_nf; +extern cpuop_func op_4470_5_ff; +extern cpuop_func op_4478_5_nf; +extern cpuop_func op_4478_5_ff; +extern cpuop_func op_4479_5_nf; +extern cpuop_func op_4479_5_ff; +extern cpuop_func op_4480_5_nf; +extern cpuop_func op_4480_5_ff; +extern cpuop_func op_4490_5_nf; +extern cpuop_func op_4490_5_ff; +extern cpuop_func op_4498_5_nf; +extern cpuop_func op_4498_5_ff; +extern cpuop_func op_44a0_5_nf; +extern cpuop_func op_44a0_5_ff; +extern cpuop_func op_44a8_5_nf; +extern cpuop_func op_44a8_5_ff; +extern cpuop_func op_44b0_5_nf; +extern cpuop_func op_44b0_5_ff; +extern cpuop_func op_44b8_5_nf; +extern cpuop_func op_44b8_5_ff; +extern cpuop_func op_44b9_5_nf; +extern cpuop_func op_44b9_5_ff; +extern cpuop_func op_44c0_5_nf; +extern cpuop_func op_44c0_5_ff; +extern cpuop_func op_44d0_5_nf; +extern cpuop_func op_44d0_5_ff; +extern cpuop_func op_44d8_5_nf; +extern cpuop_func op_44d8_5_ff; +extern cpuop_func op_44e0_5_nf; +extern cpuop_func op_44e0_5_ff; +extern cpuop_func op_44e8_5_nf; +extern cpuop_func op_44e8_5_ff; +extern cpuop_func op_44f0_5_nf; +extern cpuop_func op_44f0_5_ff; +extern cpuop_func op_44f8_5_nf; +extern cpuop_func op_44f8_5_ff; +extern cpuop_func op_44f9_5_nf; +extern cpuop_func op_44f9_5_ff; +extern cpuop_func op_44fa_5_nf; +extern cpuop_func op_44fa_5_ff; +extern cpuop_func op_44fb_5_nf; +extern cpuop_func op_44fb_5_ff; +extern cpuop_func op_44fc_5_nf; +extern cpuop_func op_44fc_5_ff; +extern cpuop_func op_4600_5_nf; +extern cpuop_func op_4600_5_ff; +extern cpuop_func op_4610_5_nf; +extern cpuop_func op_4610_5_ff; +extern cpuop_func op_4618_5_nf; +extern cpuop_func op_4618_5_ff; +extern cpuop_func op_4620_5_nf; +extern cpuop_func op_4620_5_ff; +extern cpuop_func op_4628_5_nf; +extern cpuop_func op_4628_5_ff; +extern cpuop_func op_4630_5_nf; +extern cpuop_func op_4630_5_ff; +extern cpuop_func op_4638_5_nf; +extern cpuop_func op_4638_5_ff; +extern cpuop_func op_4639_5_nf; +extern cpuop_func op_4639_5_ff; +extern cpuop_func op_4640_5_nf; +extern cpuop_func op_4640_5_ff; +extern cpuop_func op_4650_5_nf; +extern cpuop_func op_4650_5_ff; +extern cpuop_func op_4658_5_nf; +extern cpuop_func op_4658_5_ff; +extern cpuop_func op_4660_5_nf; +extern cpuop_func op_4660_5_ff; +extern cpuop_func op_4668_5_nf; +extern cpuop_func op_4668_5_ff; +extern cpuop_func op_4670_5_nf; +extern cpuop_func op_4670_5_ff; +extern cpuop_func op_4678_5_nf; +extern cpuop_func op_4678_5_ff; +extern cpuop_func op_4679_5_nf; +extern cpuop_func op_4679_5_ff; +extern cpuop_func op_4680_5_nf; +extern cpuop_func op_4680_5_ff; +extern cpuop_func op_4690_5_nf; +extern cpuop_func op_4690_5_ff; +extern cpuop_func op_4698_5_nf; +extern cpuop_func op_4698_5_ff; +extern cpuop_func op_46a0_5_nf; +extern cpuop_func op_46a0_5_ff; +extern cpuop_func op_46a8_5_nf; +extern cpuop_func op_46a8_5_ff; +extern cpuop_func op_46b0_5_nf; +extern cpuop_func op_46b0_5_ff; +extern cpuop_func op_46b8_5_nf; +extern cpuop_func op_46b8_5_ff; +extern cpuop_func op_46b9_5_nf; +extern cpuop_func op_46b9_5_ff; +extern cpuop_func op_46c0_5_nf; +extern cpuop_func op_46c0_5_ff; +extern cpuop_func op_46d0_5_nf; +extern cpuop_func op_46d0_5_ff; +extern cpuop_func op_46d8_5_nf; +extern cpuop_func op_46d8_5_ff; +extern cpuop_func op_46e0_5_nf; +extern cpuop_func op_46e0_5_ff; +extern cpuop_func op_46e8_5_nf; +extern cpuop_func op_46e8_5_ff; +extern cpuop_func op_46f0_5_nf; +extern cpuop_func op_46f0_5_ff; +extern cpuop_func op_46f8_5_nf; +extern cpuop_func op_46f8_5_ff; +extern cpuop_func op_46f9_5_nf; +extern cpuop_func op_46f9_5_ff; +extern cpuop_func op_46fa_5_nf; +extern cpuop_func op_46fa_5_ff; +extern cpuop_func op_46fb_5_nf; +extern cpuop_func op_46fb_5_ff; +extern cpuop_func op_46fc_5_nf; +extern cpuop_func op_46fc_5_ff; +extern cpuop_func op_4800_5_nf; +extern cpuop_func op_4800_5_ff; +extern cpuop_func op_4810_5_nf; +extern cpuop_func op_4810_5_ff; +extern cpuop_func op_4818_5_nf; +extern cpuop_func op_4818_5_ff; +extern cpuop_func op_4820_5_nf; +extern cpuop_func op_4820_5_ff; +extern cpuop_func op_4828_5_nf; +extern cpuop_func op_4828_5_ff; +extern cpuop_func op_4830_5_nf; +extern cpuop_func op_4830_5_ff; +extern cpuop_func op_4838_5_nf; +extern cpuop_func op_4838_5_ff; +extern cpuop_func op_4839_5_nf; +extern cpuop_func op_4839_5_ff; +extern cpuop_func op_4840_5_nf; +extern cpuop_func op_4840_5_ff; +extern cpuop_func op_4850_5_nf; +extern cpuop_func op_4850_5_ff; +extern cpuop_func op_4868_5_nf; +extern cpuop_func op_4868_5_ff; +extern cpuop_func op_4870_5_nf; +extern cpuop_func op_4870_5_ff; +extern cpuop_func op_4878_5_nf; +extern cpuop_func op_4878_5_ff; +extern cpuop_func op_4879_5_nf; +extern cpuop_func op_4879_5_ff; +extern cpuop_func op_487a_5_nf; +extern cpuop_func op_487a_5_ff; +extern cpuop_func op_487b_5_nf; +extern cpuop_func op_487b_5_ff; +extern cpuop_func op_4880_5_nf; +extern cpuop_func op_4880_5_ff; +extern cpuop_func op_4890_5_nf; +extern cpuop_func op_4890_5_ff; +extern cpuop_func op_48a0_5_nf; +extern cpuop_func op_48a0_5_ff; +extern cpuop_func op_48a8_5_nf; +extern cpuop_func op_48a8_5_ff; +extern cpuop_func op_48b0_5_nf; +extern cpuop_func op_48b0_5_ff; +extern cpuop_func op_48b8_5_nf; +extern cpuop_func op_48b8_5_ff; +extern cpuop_func op_48b9_5_nf; +extern cpuop_func op_48b9_5_ff; +extern cpuop_func op_48c0_5_nf; +extern cpuop_func op_48c0_5_ff; +extern cpuop_func op_48d0_5_nf; +extern cpuop_func op_48d0_5_ff; +extern cpuop_func op_48e0_5_nf; +extern cpuop_func op_48e0_5_ff; +extern cpuop_func op_48e8_5_nf; +extern cpuop_func op_48e8_5_ff; +extern cpuop_func op_48f0_5_nf; +extern cpuop_func op_48f0_5_ff; +extern cpuop_func op_48f8_5_nf; +extern cpuop_func op_48f8_5_ff; +extern cpuop_func op_48f9_5_nf; +extern cpuop_func op_48f9_5_ff; +extern cpuop_func op_4a00_5_nf; +extern cpuop_func op_4a00_5_ff; +extern cpuop_func op_4a10_5_nf; +extern cpuop_func op_4a10_5_ff; +extern cpuop_func op_4a18_5_nf; +extern cpuop_func op_4a18_5_ff; +extern cpuop_func op_4a20_5_nf; +extern cpuop_func op_4a20_5_ff; +extern cpuop_func op_4a28_5_nf; +extern cpuop_func op_4a28_5_ff; +extern cpuop_func op_4a30_5_nf; +extern cpuop_func op_4a30_5_ff; +extern cpuop_func op_4a38_5_nf; +extern cpuop_func op_4a38_5_ff; +extern cpuop_func op_4a39_5_nf; +extern cpuop_func op_4a39_5_ff; +extern cpuop_func op_4a3a_5_nf; +extern cpuop_func op_4a3a_5_ff; +extern cpuop_func op_4a3b_5_nf; +extern cpuop_func op_4a3b_5_ff; +extern cpuop_func op_4a3c_5_nf; +extern cpuop_func op_4a3c_5_ff; +extern cpuop_func op_4a40_5_nf; +extern cpuop_func op_4a40_5_ff; +extern cpuop_func op_4a48_5_nf; +extern cpuop_func op_4a48_5_ff; +extern cpuop_func op_4a50_5_nf; +extern cpuop_func op_4a50_5_ff; +extern cpuop_func op_4a58_5_nf; +extern cpuop_func op_4a58_5_ff; +extern cpuop_func op_4a60_5_nf; +extern cpuop_func op_4a60_5_ff; +extern cpuop_func op_4a68_5_nf; +extern cpuop_func op_4a68_5_ff; +extern cpuop_func op_4a70_5_nf; +extern cpuop_func op_4a70_5_ff; +extern cpuop_func op_4a78_5_nf; +extern cpuop_func op_4a78_5_ff; +extern cpuop_func op_4a79_5_nf; +extern cpuop_func op_4a79_5_ff; +extern cpuop_func op_4a7a_5_nf; +extern cpuop_func op_4a7a_5_ff; +extern cpuop_func op_4a7b_5_nf; +extern cpuop_func op_4a7b_5_ff; +extern cpuop_func op_4a7c_5_nf; +extern cpuop_func op_4a7c_5_ff; +extern cpuop_func op_4a80_5_nf; +extern cpuop_func op_4a80_5_ff; +extern cpuop_func op_4a88_5_nf; +extern cpuop_func op_4a88_5_ff; +extern cpuop_func op_4a90_5_nf; +extern cpuop_func op_4a90_5_ff; +extern cpuop_func op_4a98_5_nf; +extern cpuop_func op_4a98_5_ff; +extern cpuop_func op_4aa0_5_nf; +extern cpuop_func op_4aa0_5_ff; +extern cpuop_func op_4aa8_5_nf; +extern cpuop_func op_4aa8_5_ff; +extern cpuop_func op_4ab0_5_nf; +extern cpuop_func op_4ab0_5_ff; +extern cpuop_func op_4ab8_5_nf; +extern cpuop_func op_4ab8_5_ff; +extern cpuop_func op_4ab9_5_nf; +extern cpuop_func op_4ab9_5_ff; +extern cpuop_func op_4aba_5_nf; +extern cpuop_func op_4aba_5_ff; +extern cpuop_func op_4abb_5_nf; +extern cpuop_func op_4abb_5_ff; +extern cpuop_func op_4abc_5_nf; +extern cpuop_func op_4abc_5_ff; +extern cpuop_func op_4ac0_5_nf; +extern cpuop_func op_4ac0_5_ff; +extern cpuop_func op_4ad0_5_nf; +extern cpuop_func op_4ad0_5_ff; +extern cpuop_func op_4ad8_5_nf; +extern cpuop_func op_4ad8_5_ff; +extern cpuop_func op_4ae0_5_nf; +extern cpuop_func op_4ae0_5_ff; +extern cpuop_func op_4ae8_5_nf; +extern cpuop_func op_4ae8_5_ff; +extern cpuop_func op_4af0_5_nf; +extern cpuop_func op_4af0_5_ff; +extern cpuop_func op_4af8_5_nf; +extern cpuop_func op_4af8_5_ff; +extern cpuop_func op_4af9_5_nf; +extern cpuop_func op_4af9_5_ff; +extern cpuop_func op_4c90_5_nf; +extern cpuop_func op_4c90_5_ff; +extern cpuop_func op_4c98_5_nf; +extern cpuop_func op_4c98_5_ff; +extern cpuop_func op_4ca8_5_nf; +extern cpuop_func op_4ca8_5_ff; +extern cpuop_func op_4cb0_5_nf; +extern cpuop_func op_4cb0_5_ff; +extern cpuop_func op_4cb8_5_nf; +extern cpuop_func op_4cb8_5_ff; +extern cpuop_func op_4cb9_5_nf; +extern cpuop_func op_4cb9_5_ff; +extern cpuop_func op_4cba_5_nf; +extern cpuop_func op_4cba_5_ff; +extern cpuop_func op_4cbb_5_nf; +extern cpuop_func op_4cbb_5_ff; +extern cpuop_func op_4cd0_5_nf; +extern cpuop_func op_4cd0_5_ff; +extern cpuop_func op_4cd8_5_nf; +extern cpuop_func op_4cd8_5_ff; +extern cpuop_func op_4ce8_5_nf; +extern cpuop_func op_4ce8_5_ff; +extern cpuop_func op_4cf0_5_nf; +extern cpuop_func op_4cf0_5_ff; +extern cpuop_func op_4cf8_5_nf; +extern cpuop_func op_4cf8_5_ff; +extern cpuop_func op_4cf9_5_nf; +extern cpuop_func op_4cf9_5_ff; +extern cpuop_func op_4cfa_5_nf; +extern cpuop_func op_4cfa_5_ff; +extern cpuop_func op_4cfb_5_nf; +extern cpuop_func op_4cfb_5_ff; +extern cpuop_func op_4e40_5_nf; +extern cpuop_func op_4e40_5_ff; +extern cpuop_func op_4e50_5_nf; +extern cpuop_func op_4e50_5_ff; +extern cpuop_func op_4e58_5_nf; +extern cpuop_func op_4e58_5_ff; +extern cpuop_func op_4e60_5_nf; +extern cpuop_func op_4e60_5_ff; +extern cpuop_func op_4e68_5_nf; +extern cpuop_func op_4e68_5_ff; +extern cpuop_func op_4e70_5_nf; +extern cpuop_func op_4e70_5_ff; +extern cpuop_func op_4e71_5_nf; +extern cpuop_func op_4e71_5_ff; +extern cpuop_func op_4e72_5_nf; +extern cpuop_func op_4e72_5_ff; +extern cpuop_func op_4e73_5_nf; +extern cpuop_func op_4e73_5_ff; +extern cpuop_func op_4e74_5_nf; +extern cpuop_func op_4e74_5_ff; +extern cpuop_func op_4e75_5_nf; +extern cpuop_func op_4e75_5_ff; +extern cpuop_func op_4e76_5_nf; +extern cpuop_func op_4e76_5_ff; +extern cpuop_func op_4e77_5_nf; +extern cpuop_func op_4e77_5_ff; +extern cpuop_func op_4e90_5_nf; +extern cpuop_func op_4e90_5_ff; +extern cpuop_func op_4ea8_5_nf; +extern cpuop_func op_4ea8_5_ff; +extern cpuop_func op_4eb0_5_nf; +extern cpuop_func op_4eb0_5_ff; +extern cpuop_func op_4eb8_5_nf; +extern cpuop_func op_4eb8_5_ff; +extern cpuop_func op_4eb9_5_nf; +extern cpuop_func op_4eb9_5_ff; +extern cpuop_func op_4eba_5_nf; +extern cpuop_func op_4eba_5_ff; +extern cpuop_func op_4ebb_5_nf; +extern cpuop_func op_4ebb_5_ff; +extern cpuop_func op_4ed0_5_nf; +extern cpuop_func op_4ed0_5_ff; +extern cpuop_func op_4ee8_5_nf; +extern cpuop_func op_4ee8_5_ff; +extern cpuop_func op_4ef0_5_nf; +extern cpuop_func op_4ef0_5_ff; +extern cpuop_func op_4ef8_5_nf; +extern cpuop_func op_4ef8_5_ff; +extern cpuop_func op_4ef9_5_nf; +extern cpuop_func op_4ef9_5_ff; +extern cpuop_func op_4efa_5_nf; +extern cpuop_func op_4efa_5_ff; +extern cpuop_func op_4efb_5_nf; +extern cpuop_func op_4efb_5_ff; +extern cpuop_func op_5000_5_nf; +extern cpuop_func op_5000_5_ff; +extern cpuop_func op_5010_5_nf; +extern cpuop_func op_5010_5_ff; +extern cpuop_func op_5018_5_nf; +extern cpuop_func op_5018_5_ff; +extern cpuop_func op_5020_5_nf; +extern cpuop_func op_5020_5_ff; +extern cpuop_func op_5028_5_nf; +extern cpuop_func op_5028_5_ff; +extern cpuop_func op_5030_5_nf; +extern cpuop_func op_5030_5_ff; +extern cpuop_func op_5038_5_nf; +extern cpuop_func op_5038_5_ff; +extern cpuop_func op_5039_5_nf; +extern cpuop_func op_5039_5_ff; +extern cpuop_func op_5040_5_nf; +extern cpuop_func op_5040_5_ff; +extern cpuop_func op_5048_5_nf; +extern cpuop_func op_5048_5_ff; +extern cpuop_func op_5050_5_nf; +extern cpuop_func op_5050_5_ff; +extern cpuop_func op_5058_5_nf; +extern cpuop_func op_5058_5_ff; +extern cpuop_func op_5060_5_nf; +extern cpuop_func op_5060_5_ff; +extern cpuop_func op_5068_5_nf; +extern cpuop_func op_5068_5_ff; +extern cpuop_func op_5070_5_nf; +extern cpuop_func op_5070_5_ff; +extern cpuop_func op_5078_5_nf; +extern cpuop_func op_5078_5_ff; +extern cpuop_func op_5079_5_nf; +extern cpuop_func op_5079_5_ff; +extern cpuop_func op_5080_5_nf; +extern cpuop_func op_5080_5_ff; +extern cpuop_func op_5088_5_nf; +extern cpuop_func op_5088_5_ff; +extern cpuop_func op_5090_5_nf; +extern cpuop_func op_5090_5_ff; +extern cpuop_func op_5098_5_nf; +extern cpuop_func op_5098_5_ff; +extern cpuop_func op_50a0_5_nf; +extern cpuop_func op_50a0_5_ff; +extern cpuop_func op_50a8_5_nf; +extern cpuop_func op_50a8_5_ff; +extern cpuop_func op_50b0_5_nf; +extern cpuop_func op_50b0_5_ff; +extern cpuop_func op_50b8_5_nf; +extern cpuop_func op_50b8_5_ff; +extern cpuop_func op_50b9_5_nf; +extern cpuop_func op_50b9_5_ff; +extern cpuop_func op_50c0_5_nf; +extern cpuop_func op_50c0_5_ff; +extern cpuop_func op_50c8_5_nf; +extern cpuop_func op_50c8_5_ff; +extern cpuop_func op_50d0_5_nf; +extern cpuop_func op_50d0_5_ff; +extern cpuop_func op_50d8_5_nf; +extern cpuop_func op_50d8_5_ff; +extern cpuop_func op_50e0_5_nf; +extern cpuop_func op_50e0_5_ff; +extern cpuop_func op_50e8_5_nf; +extern cpuop_func op_50e8_5_ff; +extern cpuop_func op_50f0_5_nf; +extern cpuop_func op_50f0_5_ff; +extern cpuop_func op_50f8_5_nf; +extern cpuop_func op_50f8_5_ff; +extern cpuop_func op_50f9_5_nf; +extern cpuop_func op_50f9_5_ff; +extern cpuop_func op_5100_5_nf; +extern cpuop_func op_5100_5_ff; +extern cpuop_func op_5110_5_nf; +extern cpuop_func op_5110_5_ff; +extern cpuop_func op_5118_5_nf; +extern cpuop_func op_5118_5_ff; +extern cpuop_func op_5120_5_nf; +extern cpuop_func op_5120_5_ff; +extern cpuop_func op_5128_5_nf; +extern cpuop_func op_5128_5_ff; +extern cpuop_func op_5130_5_nf; +extern cpuop_func op_5130_5_ff; +extern cpuop_func op_5138_5_nf; +extern cpuop_func op_5138_5_ff; +extern cpuop_func op_5139_5_nf; +extern cpuop_func op_5139_5_ff; +extern cpuop_func op_5140_5_nf; +extern cpuop_func op_5140_5_ff; +extern cpuop_func op_5148_5_nf; +extern cpuop_func op_5148_5_ff; +extern cpuop_func op_5150_5_nf; +extern cpuop_func op_5150_5_ff; +extern cpuop_func op_5158_5_nf; +extern cpuop_func op_5158_5_ff; +extern cpuop_func op_5160_5_nf; +extern cpuop_func op_5160_5_ff; +extern cpuop_func op_5168_5_nf; +extern cpuop_func op_5168_5_ff; +extern cpuop_func op_5170_5_nf; +extern cpuop_func op_5170_5_ff; +extern cpuop_func op_5178_5_nf; +extern cpuop_func op_5178_5_ff; +extern cpuop_func op_5179_5_nf; +extern cpuop_func op_5179_5_ff; +extern cpuop_func op_5180_5_nf; +extern cpuop_func op_5180_5_ff; +extern cpuop_func op_5188_5_nf; +extern cpuop_func op_5188_5_ff; +extern cpuop_func op_5190_5_nf; +extern cpuop_func op_5190_5_ff; +extern cpuop_func op_5198_5_nf; +extern cpuop_func op_5198_5_ff; +extern cpuop_func op_51a0_5_nf; +extern cpuop_func op_51a0_5_ff; +extern cpuop_func op_51a8_5_nf; +extern cpuop_func op_51a8_5_ff; +extern cpuop_func op_51b0_5_nf; +extern cpuop_func op_51b0_5_ff; +extern cpuop_func op_51b8_5_nf; +extern cpuop_func op_51b8_5_ff; +extern cpuop_func op_51b9_5_nf; +extern cpuop_func op_51b9_5_ff; +extern cpuop_func op_51c0_5_nf; +extern cpuop_func op_51c0_5_ff; +extern cpuop_func op_51c8_5_nf; +extern cpuop_func op_51c8_5_ff; +extern cpuop_func op_51d0_5_nf; +extern cpuop_func op_51d0_5_ff; +extern cpuop_func op_51d8_5_nf; +extern cpuop_func op_51d8_5_ff; +extern cpuop_func op_51e0_5_nf; +extern cpuop_func op_51e0_5_ff; +extern cpuop_func op_51e8_5_nf; +extern cpuop_func op_51e8_5_ff; +extern cpuop_func op_51f0_5_nf; +extern cpuop_func op_51f0_5_ff; +extern cpuop_func op_51f8_5_nf; +extern cpuop_func op_51f8_5_ff; +extern cpuop_func op_51f9_5_nf; +extern cpuop_func op_51f9_5_ff; +extern cpuop_func op_52c0_5_nf; +extern cpuop_func op_52c0_5_ff; +extern cpuop_func op_52c8_5_nf; +extern cpuop_func op_52c8_5_ff; +extern cpuop_func op_52d0_5_nf; +extern cpuop_func op_52d0_5_ff; +extern cpuop_func op_52d8_5_nf; +extern cpuop_func op_52d8_5_ff; +extern cpuop_func op_52e0_5_nf; +extern cpuop_func op_52e0_5_ff; +extern cpuop_func op_52e8_5_nf; +extern cpuop_func op_52e8_5_ff; +extern cpuop_func op_52f0_5_nf; +extern cpuop_func op_52f0_5_ff; +extern cpuop_func op_52f8_5_nf; +extern cpuop_func op_52f8_5_ff; +extern cpuop_func op_52f9_5_nf; +extern cpuop_func op_52f9_5_ff; +extern cpuop_func op_53c0_5_nf; +extern cpuop_func op_53c0_5_ff; +extern cpuop_func op_53c8_5_nf; +extern cpuop_func op_53c8_5_ff; +extern cpuop_func op_53d0_5_nf; +extern cpuop_func op_53d0_5_ff; +extern cpuop_func op_53d8_5_nf; +extern cpuop_func op_53d8_5_ff; +extern cpuop_func op_53e0_5_nf; +extern cpuop_func op_53e0_5_ff; +extern cpuop_func op_53e8_5_nf; +extern cpuop_func op_53e8_5_ff; +extern cpuop_func op_53f0_5_nf; +extern cpuop_func op_53f0_5_ff; +extern cpuop_func op_53f8_5_nf; +extern cpuop_func op_53f8_5_ff; +extern cpuop_func op_53f9_5_nf; +extern cpuop_func op_53f9_5_ff; +extern cpuop_func op_54c0_5_nf; +extern cpuop_func op_54c0_5_ff; +extern cpuop_func op_54c8_5_nf; +extern cpuop_func op_54c8_5_ff; +extern cpuop_func op_54d0_5_nf; +extern cpuop_func op_54d0_5_ff; +extern cpuop_func op_54d8_5_nf; +extern cpuop_func op_54d8_5_ff; +extern cpuop_func op_54e0_5_nf; +extern cpuop_func op_54e0_5_ff; +extern cpuop_func op_54e8_5_nf; +extern cpuop_func op_54e8_5_ff; +extern cpuop_func op_54f0_5_nf; +extern cpuop_func op_54f0_5_ff; +extern cpuop_func op_54f8_5_nf; +extern cpuop_func op_54f8_5_ff; +extern cpuop_func op_54f9_5_nf; +extern cpuop_func op_54f9_5_ff; +extern cpuop_func op_55c0_5_nf; +extern cpuop_func op_55c0_5_ff; +extern cpuop_func op_55c8_5_nf; +extern cpuop_func op_55c8_5_ff; +extern cpuop_func op_55d0_5_nf; +extern cpuop_func op_55d0_5_ff; +extern cpuop_func op_55d8_5_nf; +extern cpuop_func op_55d8_5_ff; +extern cpuop_func op_55e0_5_nf; +extern cpuop_func op_55e0_5_ff; +extern cpuop_func op_55e8_5_nf; +extern cpuop_func op_55e8_5_ff; +extern cpuop_func op_55f0_5_nf; +extern cpuop_func op_55f0_5_ff; +extern cpuop_func op_55f8_5_nf; +extern cpuop_func op_55f8_5_ff; +extern cpuop_func op_55f9_5_nf; +extern cpuop_func op_55f9_5_ff; +extern cpuop_func op_56c0_5_nf; +extern cpuop_func op_56c0_5_ff; +extern cpuop_func op_56c8_5_nf; +extern cpuop_func op_56c8_5_ff; +extern cpuop_func op_56d0_5_nf; +extern cpuop_func op_56d0_5_ff; +extern cpuop_func op_56d8_5_nf; +extern cpuop_func op_56d8_5_ff; +extern cpuop_func op_56e0_5_nf; +extern cpuop_func op_56e0_5_ff; +extern cpuop_func op_56e8_5_nf; +extern cpuop_func op_56e8_5_ff; +extern cpuop_func op_56f0_5_nf; +extern cpuop_func op_56f0_5_ff; +extern cpuop_func op_56f8_5_nf; +extern cpuop_func op_56f8_5_ff; +extern cpuop_func op_56f9_5_nf; +extern cpuop_func op_56f9_5_ff; +extern cpuop_func op_57c0_5_nf; +extern cpuop_func op_57c0_5_ff; +extern cpuop_func op_57c8_5_nf; +extern cpuop_func op_57c8_5_ff; +extern cpuop_func op_57d0_5_nf; +extern cpuop_func op_57d0_5_ff; +extern cpuop_func op_57d8_5_nf; +extern cpuop_func op_57d8_5_ff; +extern cpuop_func op_57e0_5_nf; +extern cpuop_func op_57e0_5_ff; +extern cpuop_func op_57e8_5_nf; +extern cpuop_func op_57e8_5_ff; +extern cpuop_func op_57f0_5_nf; +extern cpuop_func op_57f0_5_ff; +extern cpuop_func op_57f8_5_nf; +extern cpuop_func op_57f8_5_ff; +extern cpuop_func op_57f9_5_nf; +extern cpuop_func op_57f9_5_ff; +extern cpuop_func op_58c0_5_nf; +extern cpuop_func op_58c0_5_ff; +extern cpuop_func op_58c8_5_nf; +extern cpuop_func op_58c8_5_ff; +extern cpuop_func op_58d0_5_nf; +extern cpuop_func op_58d0_5_ff; +extern cpuop_func op_58d8_5_nf; +extern cpuop_func op_58d8_5_ff; +extern cpuop_func op_58e0_5_nf; +extern cpuop_func op_58e0_5_ff; +extern cpuop_func op_58e8_5_nf; +extern cpuop_func op_58e8_5_ff; +extern cpuop_func op_58f0_5_nf; +extern cpuop_func op_58f0_5_ff; +extern cpuop_func op_58f8_5_nf; +extern cpuop_func op_58f8_5_ff; +extern cpuop_func op_58f9_5_nf; +extern cpuop_func op_58f9_5_ff; +extern cpuop_func op_59c0_5_nf; +extern cpuop_func op_59c0_5_ff; +extern cpuop_func op_59c8_5_nf; +extern cpuop_func op_59c8_5_ff; +extern cpuop_func op_59d0_5_nf; +extern cpuop_func op_59d0_5_ff; +extern cpuop_func op_59d8_5_nf; +extern cpuop_func op_59d8_5_ff; +extern cpuop_func op_59e0_5_nf; +extern cpuop_func op_59e0_5_ff; +extern cpuop_func op_59e8_5_nf; +extern cpuop_func op_59e8_5_ff; +extern cpuop_func op_59f0_5_nf; +extern cpuop_func op_59f0_5_ff; +extern cpuop_func op_59f8_5_nf; +extern cpuop_func op_59f8_5_ff; +extern cpuop_func op_59f9_5_nf; +extern cpuop_func op_59f9_5_ff; +extern cpuop_func op_5ac0_5_nf; +extern cpuop_func op_5ac0_5_ff; +extern cpuop_func op_5ac8_5_nf; +extern cpuop_func op_5ac8_5_ff; +extern cpuop_func op_5ad0_5_nf; +extern cpuop_func op_5ad0_5_ff; +extern cpuop_func op_5ad8_5_nf; +extern cpuop_func op_5ad8_5_ff; +extern cpuop_func op_5ae0_5_nf; +extern cpuop_func op_5ae0_5_ff; +extern cpuop_func op_5ae8_5_nf; +extern cpuop_func op_5ae8_5_ff; +extern cpuop_func op_5af0_5_nf; +extern cpuop_func op_5af0_5_ff; +extern cpuop_func op_5af8_5_nf; +extern cpuop_func op_5af8_5_ff; +extern cpuop_func op_5af9_5_nf; +extern cpuop_func op_5af9_5_ff; +extern cpuop_func op_5bc0_5_nf; +extern cpuop_func op_5bc0_5_ff; +extern cpuop_func op_5bc8_5_nf; +extern cpuop_func op_5bc8_5_ff; +extern cpuop_func op_5bd0_5_nf; +extern cpuop_func op_5bd0_5_ff; +extern cpuop_func op_5bd8_5_nf; +extern cpuop_func op_5bd8_5_ff; +extern cpuop_func op_5be0_5_nf; +extern cpuop_func op_5be0_5_ff; +extern cpuop_func op_5be8_5_nf; +extern cpuop_func op_5be8_5_ff; +extern cpuop_func op_5bf0_5_nf; +extern cpuop_func op_5bf0_5_ff; +extern cpuop_func op_5bf8_5_nf; +extern cpuop_func op_5bf8_5_ff; +extern cpuop_func op_5bf9_5_nf; +extern cpuop_func op_5bf9_5_ff; +extern cpuop_func op_5cc0_5_nf; +extern cpuop_func op_5cc0_5_ff; +extern cpuop_func op_5cc8_5_nf; +extern cpuop_func op_5cc8_5_ff; +extern cpuop_func op_5cd0_5_nf; +extern cpuop_func op_5cd0_5_ff; +extern cpuop_func op_5cd8_5_nf; +extern cpuop_func op_5cd8_5_ff; +extern cpuop_func op_5ce0_5_nf; +extern cpuop_func op_5ce0_5_ff; +extern cpuop_func op_5ce8_5_nf; +extern cpuop_func op_5ce8_5_ff; +extern cpuop_func op_5cf0_5_nf; +extern cpuop_func op_5cf0_5_ff; +extern cpuop_func op_5cf8_5_nf; +extern cpuop_func op_5cf8_5_ff; +extern cpuop_func op_5cf9_5_nf; +extern cpuop_func op_5cf9_5_ff; +extern cpuop_func op_5dc0_5_nf; +extern cpuop_func op_5dc0_5_ff; +extern cpuop_func op_5dc8_5_nf; +extern cpuop_func op_5dc8_5_ff; +extern cpuop_func op_5dd0_5_nf; +extern cpuop_func op_5dd0_5_ff; +extern cpuop_func op_5dd8_5_nf; +extern cpuop_func op_5dd8_5_ff; +extern cpuop_func op_5de0_5_nf; +extern cpuop_func op_5de0_5_ff; +extern cpuop_func op_5de8_5_nf; +extern cpuop_func op_5de8_5_ff; +extern cpuop_func op_5df0_5_nf; +extern cpuop_func op_5df0_5_ff; +extern cpuop_func op_5df8_5_nf; +extern cpuop_func op_5df8_5_ff; +extern cpuop_func op_5df9_5_nf; +extern cpuop_func op_5df9_5_ff; +extern cpuop_func op_5ec0_5_nf; +extern cpuop_func op_5ec0_5_ff; +extern cpuop_func op_5ec8_5_nf; +extern cpuop_func op_5ec8_5_ff; +extern cpuop_func op_5ed0_5_nf; +extern cpuop_func op_5ed0_5_ff; +extern cpuop_func op_5ed8_5_nf; +extern cpuop_func op_5ed8_5_ff; +extern cpuop_func op_5ee0_5_nf; +extern cpuop_func op_5ee0_5_ff; +extern cpuop_func op_5ee8_5_nf; +extern cpuop_func op_5ee8_5_ff; +extern cpuop_func op_5ef0_5_nf; +extern cpuop_func op_5ef0_5_ff; +extern cpuop_func op_5ef8_5_nf; +extern cpuop_func op_5ef8_5_ff; +extern cpuop_func op_5ef9_5_nf; +extern cpuop_func op_5ef9_5_ff; +extern cpuop_func op_5fc0_5_nf; +extern cpuop_func op_5fc0_5_ff; +extern cpuop_func op_5fc8_5_nf; +extern cpuop_func op_5fc8_5_ff; +extern cpuop_func op_5fd0_5_nf; +extern cpuop_func op_5fd0_5_ff; +extern cpuop_func op_5fd8_5_nf; +extern cpuop_func op_5fd8_5_ff; +extern cpuop_func op_5fe0_5_nf; +extern cpuop_func op_5fe0_5_ff; +extern cpuop_func op_5fe8_5_nf; +extern cpuop_func op_5fe8_5_ff; +extern cpuop_func op_5ff0_5_nf; +extern cpuop_func op_5ff0_5_ff; +extern cpuop_func op_5ff8_5_nf; +extern cpuop_func op_5ff8_5_ff; +extern cpuop_func op_5ff9_5_nf; +extern cpuop_func op_5ff9_5_ff; +extern cpuop_func op_6000_5_nf; +extern cpuop_func op_6000_5_ff; +extern cpuop_func op_6001_5_nf; +extern cpuop_func op_6001_5_ff; +extern cpuop_func op_60ff_5_nf; +extern cpuop_func op_60ff_5_ff; +extern cpuop_func op_6100_5_nf; +extern cpuop_func op_6100_5_ff; +extern cpuop_func op_6101_5_nf; +extern cpuop_func op_6101_5_ff; +extern cpuop_func op_61ff_5_nf; +extern cpuop_func op_61ff_5_ff; +extern cpuop_func op_6200_5_nf; +extern cpuop_func op_6200_5_ff; +extern cpuop_func op_6201_5_nf; +extern cpuop_func op_6201_5_ff; +extern cpuop_func op_62ff_5_nf; +extern cpuop_func op_62ff_5_ff; +extern cpuop_func op_6300_5_nf; +extern cpuop_func op_6300_5_ff; +extern cpuop_func op_6301_5_nf; +extern cpuop_func op_6301_5_ff; +extern cpuop_func op_63ff_5_nf; +extern cpuop_func op_63ff_5_ff; +extern cpuop_func op_6400_5_nf; +extern cpuop_func op_6400_5_ff; +extern cpuop_func op_6401_5_nf; +extern cpuop_func op_6401_5_ff; +extern cpuop_func op_64ff_5_nf; +extern cpuop_func op_64ff_5_ff; +extern cpuop_func op_6500_5_nf; +extern cpuop_func op_6500_5_ff; +extern cpuop_func op_6501_5_nf; +extern cpuop_func op_6501_5_ff; +extern cpuop_func op_65ff_5_nf; +extern cpuop_func op_65ff_5_ff; +extern cpuop_func op_6600_5_nf; +extern cpuop_func op_6600_5_ff; +extern cpuop_func op_6601_5_nf; +extern cpuop_func op_6601_5_ff; +extern cpuop_func op_66ff_5_nf; +extern cpuop_func op_66ff_5_ff; +extern cpuop_func op_6700_5_nf; +extern cpuop_func op_6700_5_ff; +extern cpuop_func op_6701_5_nf; +extern cpuop_func op_6701_5_ff; +extern cpuop_func op_67ff_5_nf; +extern cpuop_func op_67ff_5_ff; +extern cpuop_func op_6800_5_nf; +extern cpuop_func op_6800_5_ff; +extern cpuop_func op_6801_5_nf; +extern cpuop_func op_6801_5_ff; +extern cpuop_func op_68ff_5_nf; +extern cpuop_func op_68ff_5_ff; +extern cpuop_func op_6900_5_nf; +extern cpuop_func op_6900_5_ff; +extern cpuop_func op_6901_5_nf; +extern cpuop_func op_6901_5_ff; +extern cpuop_func op_69ff_5_nf; +extern cpuop_func op_69ff_5_ff; +extern cpuop_func op_6a00_5_nf; +extern cpuop_func op_6a00_5_ff; +extern cpuop_func op_6a01_5_nf; +extern cpuop_func op_6a01_5_ff; +extern cpuop_func op_6aff_5_nf; +extern cpuop_func op_6aff_5_ff; +extern cpuop_func op_6b00_5_nf; +extern cpuop_func op_6b00_5_ff; +extern cpuop_func op_6b01_5_nf; +extern cpuop_func op_6b01_5_ff; +extern cpuop_func op_6bff_5_nf; +extern cpuop_func op_6bff_5_ff; +extern cpuop_func op_6c00_5_nf; +extern cpuop_func op_6c00_5_ff; +extern cpuop_func op_6c01_5_nf; +extern cpuop_func op_6c01_5_ff; +extern cpuop_func op_6cff_5_nf; +extern cpuop_func op_6cff_5_ff; +extern cpuop_func op_6d00_5_nf; +extern cpuop_func op_6d00_5_ff; +extern cpuop_func op_6d01_5_nf; +extern cpuop_func op_6d01_5_ff; +extern cpuop_func op_6dff_5_nf; +extern cpuop_func op_6dff_5_ff; +extern cpuop_func op_6e00_5_nf; +extern cpuop_func op_6e00_5_ff; +extern cpuop_func op_6e01_5_nf; +extern cpuop_func op_6e01_5_ff; +extern cpuop_func op_6eff_5_nf; +extern cpuop_func op_6eff_5_ff; +extern cpuop_func op_6f00_5_nf; +extern cpuop_func op_6f00_5_ff; +extern cpuop_func op_6f01_5_nf; +extern cpuop_func op_6f01_5_ff; +extern cpuop_func op_6fff_5_nf; +extern cpuop_func op_6fff_5_ff; +extern cpuop_func op_7000_5_nf; +extern cpuop_func op_7000_5_ff; +extern cpuop_func op_8000_5_nf; +extern cpuop_func op_8000_5_ff; +extern cpuop_func op_8010_5_nf; +extern cpuop_func op_8010_5_ff; +extern cpuop_func op_8018_5_nf; +extern cpuop_func op_8018_5_ff; +extern cpuop_func op_8020_5_nf; +extern cpuop_func op_8020_5_ff; +extern cpuop_func op_8028_5_nf; +extern cpuop_func op_8028_5_ff; +extern cpuop_func op_8030_5_nf; +extern cpuop_func op_8030_5_ff; +extern cpuop_func op_8038_5_nf; +extern cpuop_func op_8038_5_ff; +extern cpuop_func op_8039_5_nf; +extern cpuop_func op_8039_5_ff; +extern cpuop_func op_803a_5_nf; +extern cpuop_func op_803a_5_ff; +extern cpuop_func op_803b_5_nf; +extern cpuop_func op_803b_5_ff; +extern cpuop_func op_803c_5_nf; +extern cpuop_func op_803c_5_ff; +extern cpuop_func op_8040_5_nf; +extern cpuop_func op_8040_5_ff; +extern cpuop_func op_8050_5_nf; +extern cpuop_func op_8050_5_ff; +extern cpuop_func op_8058_5_nf; +extern cpuop_func op_8058_5_ff; +extern cpuop_func op_8060_5_nf; +extern cpuop_func op_8060_5_ff; +extern cpuop_func op_8068_5_nf; +extern cpuop_func op_8068_5_ff; +extern cpuop_func op_8070_5_nf; +extern cpuop_func op_8070_5_ff; +extern cpuop_func op_8078_5_nf; +extern cpuop_func op_8078_5_ff; +extern cpuop_func op_8079_5_nf; +extern cpuop_func op_8079_5_ff; +extern cpuop_func op_807a_5_nf; +extern cpuop_func op_807a_5_ff; +extern cpuop_func op_807b_5_nf; +extern cpuop_func op_807b_5_ff; +extern cpuop_func op_807c_5_nf; +extern cpuop_func op_807c_5_ff; +extern cpuop_func op_8080_5_nf; +extern cpuop_func op_8080_5_ff; +extern cpuop_func op_8090_5_nf; +extern cpuop_func op_8090_5_ff; +extern cpuop_func op_8098_5_nf; +extern cpuop_func op_8098_5_ff; +extern cpuop_func op_80a0_5_nf; +extern cpuop_func op_80a0_5_ff; +extern cpuop_func op_80a8_5_nf; +extern cpuop_func op_80a8_5_ff; +extern cpuop_func op_80b0_5_nf; +extern cpuop_func op_80b0_5_ff; +extern cpuop_func op_80b8_5_nf; +extern cpuop_func op_80b8_5_ff; +extern cpuop_func op_80b9_5_nf; +extern cpuop_func op_80b9_5_ff; +extern cpuop_func op_80ba_5_nf; +extern cpuop_func op_80ba_5_ff; +extern cpuop_func op_80bb_5_nf; +extern cpuop_func op_80bb_5_ff; +extern cpuop_func op_80bc_5_nf; +extern cpuop_func op_80bc_5_ff; +extern cpuop_func op_80c0_5_nf; +extern cpuop_func op_80c0_5_ff; +extern cpuop_func op_80d0_5_nf; +extern cpuop_func op_80d0_5_ff; +extern cpuop_func op_80d8_5_nf; +extern cpuop_func op_80d8_5_ff; +extern cpuop_func op_80e0_5_nf; +extern cpuop_func op_80e0_5_ff; +extern cpuop_func op_80e8_5_nf; +extern cpuop_func op_80e8_5_ff; +extern cpuop_func op_80f0_5_nf; +extern cpuop_func op_80f0_5_ff; +extern cpuop_func op_80f8_5_nf; +extern cpuop_func op_80f8_5_ff; +extern cpuop_func op_80f9_5_nf; +extern cpuop_func op_80f9_5_ff; +extern cpuop_func op_80fa_5_nf; +extern cpuop_func op_80fa_5_ff; +extern cpuop_func op_80fb_5_nf; +extern cpuop_func op_80fb_5_ff; +extern cpuop_func op_80fc_5_nf; +extern cpuop_func op_80fc_5_ff; +extern cpuop_func op_8100_5_nf; +extern cpuop_func op_8100_5_ff; +extern cpuop_func op_8108_5_nf; +extern cpuop_func op_8108_5_ff; +extern cpuop_func op_8110_5_nf; +extern cpuop_func op_8110_5_ff; +extern cpuop_func op_8118_5_nf; +extern cpuop_func op_8118_5_ff; +extern cpuop_func op_8120_5_nf; +extern cpuop_func op_8120_5_ff; +extern cpuop_func op_8128_5_nf; +extern cpuop_func op_8128_5_ff; +extern cpuop_func op_8130_5_nf; +extern cpuop_func op_8130_5_ff; +extern cpuop_func op_8138_5_nf; +extern cpuop_func op_8138_5_ff; +extern cpuop_func op_8139_5_nf; +extern cpuop_func op_8139_5_ff; +extern cpuop_func op_8150_5_nf; +extern cpuop_func op_8150_5_ff; +extern cpuop_func op_8158_5_nf; +extern cpuop_func op_8158_5_ff; +extern cpuop_func op_8160_5_nf; +extern cpuop_func op_8160_5_ff; +extern cpuop_func op_8168_5_nf; +extern cpuop_func op_8168_5_ff; +extern cpuop_func op_8170_5_nf; +extern cpuop_func op_8170_5_ff; +extern cpuop_func op_8178_5_nf; +extern cpuop_func op_8178_5_ff; +extern cpuop_func op_8179_5_nf; +extern cpuop_func op_8179_5_ff; +extern cpuop_func op_8190_5_nf; +extern cpuop_func op_8190_5_ff; +extern cpuop_func op_8198_5_nf; +extern cpuop_func op_8198_5_ff; +extern cpuop_func op_81a0_5_nf; +extern cpuop_func op_81a0_5_ff; +extern cpuop_func op_81a8_5_nf; +extern cpuop_func op_81a8_5_ff; +extern cpuop_func op_81b0_5_nf; +extern cpuop_func op_81b0_5_ff; +extern cpuop_func op_81b8_5_nf; +extern cpuop_func op_81b8_5_ff; +extern cpuop_func op_81b9_5_nf; +extern cpuop_func op_81b9_5_ff; +extern cpuop_func op_81c0_5_nf; +extern cpuop_func op_81c0_5_ff; +extern cpuop_func op_81d0_5_nf; +extern cpuop_func op_81d0_5_ff; +extern cpuop_func op_81d8_5_nf; +extern cpuop_func op_81d8_5_ff; +extern cpuop_func op_81e0_5_nf; +extern cpuop_func op_81e0_5_ff; +extern cpuop_func op_81e8_5_nf; +extern cpuop_func op_81e8_5_ff; +extern cpuop_func op_81f0_5_nf; +extern cpuop_func op_81f0_5_ff; +extern cpuop_func op_81f8_5_nf; +extern cpuop_func op_81f8_5_ff; +extern cpuop_func op_81f9_5_nf; +extern cpuop_func op_81f9_5_ff; +extern cpuop_func op_81fa_5_nf; +extern cpuop_func op_81fa_5_ff; +extern cpuop_func op_81fb_5_nf; +extern cpuop_func op_81fb_5_ff; +extern cpuop_func op_81fc_5_nf; +extern cpuop_func op_81fc_5_ff; +extern cpuop_func op_9000_5_nf; +extern cpuop_func op_9000_5_ff; +extern cpuop_func op_9010_5_nf; +extern cpuop_func op_9010_5_ff; +extern cpuop_func op_9018_5_nf; +extern cpuop_func op_9018_5_ff; +extern cpuop_func op_9020_5_nf; +extern cpuop_func op_9020_5_ff; +extern cpuop_func op_9028_5_nf; +extern cpuop_func op_9028_5_ff; +extern cpuop_func op_9030_5_nf; +extern cpuop_func op_9030_5_ff; +extern cpuop_func op_9038_5_nf; +extern cpuop_func op_9038_5_ff; +extern cpuop_func op_9039_5_nf; +extern cpuop_func op_9039_5_ff; +extern cpuop_func op_903a_5_nf; +extern cpuop_func op_903a_5_ff; +extern cpuop_func op_903b_5_nf; +extern cpuop_func op_903b_5_ff; +extern cpuop_func op_903c_5_nf; +extern cpuop_func op_903c_5_ff; +extern cpuop_func op_9040_5_nf; +extern cpuop_func op_9040_5_ff; +extern cpuop_func op_9048_5_nf; +extern cpuop_func op_9048_5_ff; +extern cpuop_func op_9050_5_nf; +extern cpuop_func op_9050_5_ff; +extern cpuop_func op_9058_5_nf; +extern cpuop_func op_9058_5_ff; +extern cpuop_func op_9060_5_nf; +extern cpuop_func op_9060_5_ff; +extern cpuop_func op_9068_5_nf; +extern cpuop_func op_9068_5_ff; +extern cpuop_func op_9070_5_nf; +extern cpuop_func op_9070_5_ff; +extern cpuop_func op_9078_5_nf; +extern cpuop_func op_9078_5_ff; +extern cpuop_func op_9079_5_nf; +extern cpuop_func op_9079_5_ff; +extern cpuop_func op_907a_5_nf; +extern cpuop_func op_907a_5_ff; +extern cpuop_func op_907b_5_nf; +extern cpuop_func op_907b_5_ff; +extern cpuop_func op_907c_5_nf; +extern cpuop_func op_907c_5_ff; +extern cpuop_func op_9080_5_nf; +extern cpuop_func op_9080_5_ff; +extern cpuop_func op_9088_5_nf; +extern cpuop_func op_9088_5_ff; +extern cpuop_func op_9090_5_nf; +extern cpuop_func op_9090_5_ff; +extern cpuop_func op_9098_5_nf; +extern cpuop_func op_9098_5_ff; +extern cpuop_func op_90a0_5_nf; +extern cpuop_func op_90a0_5_ff; +extern cpuop_func op_90a8_5_nf; +extern cpuop_func op_90a8_5_ff; +extern cpuop_func op_90b0_5_nf; +extern cpuop_func op_90b0_5_ff; +extern cpuop_func op_90b8_5_nf; +extern cpuop_func op_90b8_5_ff; +extern cpuop_func op_90b9_5_nf; +extern cpuop_func op_90b9_5_ff; +extern cpuop_func op_90ba_5_nf; +extern cpuop_func op_90ba_5_ff; +extern cpuop_func op_90bb_5_nf; +extern cpuop_func op_90bb_5_ff; +extern cpuop_func op_90bc_5_nf; +extern cpuop_func op_90bc_5_ff; +extern cpuop_func op_90c0_5_nf; +extern cpuop_func op_90c0_5_ff; +extern cpuop_func op_90c8_5_nf; +extern cpuop_func op_90c8_5_ff; +extern cpuop_func op_90d0_5_nf; +extern cpuop_func op_90d0_5_ff; +extern cpuop_func op_90d8_5_nf; +extern cpuop_func op_90d8_5_ff; +extern cpuop_func op_90e0_5_nf; +extern cpuop_func op_90e0_5_ff; +extern cpuop_func op_90e8_5_nf; +extern cpuop_func op_90e8_5_ff; +extern cpuop_func op_90f0_5_nf; +extern cpuop_func op_90f0_5_ff; +extern cpuop_func op_90f8_5_nf; +extern cpuop_func op_90f8_5_ff; +extern cpuop_func op_90f9_5_nf; +extern cpuop_func op_90f9_5_ff; +extern cpuop_func op_90fa_5_nf; +extern cpuop_func op_90fa_5_ff; +extern cpuop_func op_90fb_5_nf; +extern cpuop_func op_90fb_5_ff; +extern cpuop_func op_90fc_5_nf; +extern cpuop_func op_90fc_5_ff; +extern cpuop_func op_9100_5_nf; +extern cpuop_func op_9100_5_ff; +extern cpuop_func op_9108_5_nf; +extern cpuop_func op_9108_5_ff; +extern cpuop_func op_9110_5_nf; +extern cpuop_func op_9110_5_ff; +extern cpuop_func op_9118_5_nf; +extern cpuop_func op_9118_5_ff; +extern cpuop_func op_9120_5_nf; +extern cpuop_func op_9120_5_ff; +extern cpuop_func op_9128_5_nf; +extern cpuop_func op_9128_5_ff; +extern cpuop_func op_9130_5_nf; +extern cpuop_func op_9130_5_ff; +extern cpuop_func op_9138_5_nf; +extern cpuop_func op_9138_5_ff; +extern cpuop_func op_9139_5_nf; +extern cpuop_func op_9139_5_ff; +extern cpuop_func op_9140_5_nf; +extern cpuop_func op_9140_5_ff; +extern cpuop_func op_9148_5_nf; +extern cpuop_func op_9148_5_ff; +extern cpuop_func op_9150_5_nf; +extern cpuop_func op_9150_5_ff; +extern cpuop_func op_9158_5_nf; +extern cpuop_func op_9158_5_ff; +extern cpuop_func op_9160_5_nf; +extern cpuop_func op_9160_5_ff; +extern cpuop_func op_9168_5_nf; +extern cpuop_func op_9168_5_ff; +extern cpuop_func op_9170_5_nf; +extern cpuop_func op_9170_5_ff; +extern cpuop_func op_9178_5_nf; +extern cpuop_func op_9178_5_ff; +extern cpuop_func op_9179_5_nf; +extern cpuop_func op_9179_5_ff; +extern cpuop_func op_9180_5_nf; +extern cpuop_func op_9180_5_ff; +extern cpuop_func op_9188_5_nf; +extern cpuop_func op_9188_5_ff; +extern cpuop_func op_9190_5_nf; +extern cpuop_func op_9190_5_ff; +extern cpuop_func op_9198_5_nf; +extern cpuop_func op_9198_5_ff; +extern cpuop_func op_91a0_5_nf; +extern cpuop_func op_91a0_5_ff; +extern cpuop_func op_91a8_5_nf; +extern cpuop_func op_91a8_5_ff; +extern cpuop_func op_91b0_5_nf; +extern cpuop_func op_91b0_5_ff; +extern cpuop_func op_91b8_5_nf; +extern cpuop_func op_91b8_5_ff; +extern cpuop_func op_91b9_5_nf; +extern cpuop_func op_91b9_5_ff; +extern cpuop_func op_91c0_5_nf; +extern cpuop_func op_91c0_5_ff; +extern cpuop_func op_91c8_5_nf; +extern cpuop_func op_91c8_5_ff; +extern cpuop_func op_91d0_5_nf; +extern cpuop_func op_91d0_5_ff; +extern cpuop_func op_91d8_5_nf; +extern cpuop_func op_91d8_5_ff; +extern cpuop_func op_91e0_5_nf; +extern cpuop_func op_91e0_5_ff; +extern cpuop_func op_91e8_5_nf; +extern cpuop_func op_91e8_5_ff; +extern cpuop_func op_91f0_5_nf; +extern cpuop_func op_91f0_5_ff; +extern cpuop_func op_91f8_5_nf; +extern cpuop_func op_91f8_5_ff; +extern cpuop_func op_91f9_5_nf; +extern cpuop_func op_91f9_5_ff; +extern cpuop_func op_91fa_5_nf; +extern cpuop_func op_91fa_5_ff; +extern cpuop_func op_91fb_5_nf; +extern cpuop_func op_91fb_5_ff; +extern cpuop_func op_91fc_5_nf; +extern cpuop_func op_91fc_5_ff; +extern cpuop_func op_b000_5_nf; +extern cpuop_func op_b000_5_ff; +extern cpuop_func op_b010_5_nf; +extern cpuop_func op_b010_5_ff; +extern cpuop_func op_b018_5_nf; +extern cpuop_func op_b018_5_ff; +extern cpuop_func op_b020_5_nf; +extern cpuop_func op_b020_5_ff; +extern cpuop_func op_b028_5_nf; +extern cpuop_func op_b028_5_ff; +extern cpuop_func op_b030_5_nf; +extern cpuop_func op_b030_5_ff; +extern cpuop_func op_b038_5_nf; +extern cpuop_func op_b038_5_ff; +extern cpuop_func op_b039_5_nf; +extern cpuop_func op_b039_5_ff; +extern cpuop_func op_b03a_5_nf; +extern cpuop_func op_b03a_5_ff; +extern cpuop_func op_b03b_5_nf; +extern cpuop_func op_b03b_5_ff; +extern cpuop_func op_b03c_5_nf; +extern cpuop_func op_b03c_5_ff; +extern cpuop_func op_b040_5_nf; +extern cpuop_func op_b040_5_ff; +extern cpuop_func op_b048_5_nf; +extern cpuop_func op_b048_5_ff; +extern cpuop_func op_b050_5_nf; +extern cpuop_func op_b050_5_ff; +extern cpuop_func op_b058_5_nf; +extern cpuop_func op_b058_5_ff; +extern cpuop_func op_b060_5_nf; +extern cpuop_func op_b060_5_ff; +extern cpuop_func op_b068_5_nf; +extern cpuop_func op_b068_5_ff; +extern cpuop_func op_b070_5_nf; +extern cpuop_func op_b070_5_ff; +extern cpuop_func op_b078_5_nf; +extern cpuop_func op_b078_5_ff; +extern cpuop_func op_b079_5_nf; +extern cpuop_func op_b079_5_ff; +extern cpuop_func op_b07a_5_nf; +extern cpuop_func op_b07a_5_ff; +extern cpuop_func op_b07b_5_nf; +extern cpuop_func op_b07b_5_ff; +extern cpuop_func op_b07c_5_nf; +extern cpuop_func op_b07c_5_ff; +extern cpuop_func op_b080_5_nf; +extern cpuop_func op_b080_5_ff; +extern cpuop_func op_b088_5_nf; +extern cpuop_func op_b088_5_ff; +extern cpuop_func op_b090_5_nf; +extern cpuop_func op_b090_5_ff; +extern cpuop_func op_b098_5_nf; +extern cpuop_func op_b098_5_ff; +extern cpuop_func op_b0a0_5_nf; +extern cpuop_func op_b0a0_5_ff; +extern cpuop_func op_b0a8_5_nf; +extern cpuop_func op_b0a8_5_ff; +extern cpuop_func op_b0b0_5_nf; +extern cpuop_func op_b0b0_5_ff; +extern cpuop_func op_b0b8_5_nf; +extern cpuop_func op_b0b8_5_ff; +extern cpuop_func op_b0b9_5_nf; +extern cpuop_func op_b0b9_5_ff; +extern cpuop_func op_b0ba_5_nf; +extern cpuop_func op_b0ba_5_ff; +extern cpuop_func op_b0bb_5_nf; +extern cpuop_func op_b0bb_5_ff; +extern cpuop_func op_b0bc_5_nf; +extern cpuop_func op_b0bc_5_ff; +extern cpuop_func op_b0c0_5_nf; +extern cpuop_func op_b0c0_5_ff; +extern cpuop_func op_b0c8_5_nf; +extern cpuop_func op_b0c8_5_ff; +extern cpuop_func op_b0d0_5_nf; +extern cpuop_func op_b0d0_5_ff; +extern cpuop_func op_b0d8_5_nf; +extern cpuop_func op_b0d8_5_ff; +extern cpuop_func op_b0e0_5_nf; +extern cpuop_func op_b0e0_5_ff; +extern cpuop_func op_b0e8_5_nf; +extern cpuop_func op_b0e8_5_ff; +extern cpuop_func op_b0f0_5_nf; +extern cpuop_func op_b0f0_5_ff; +extern cpuop_func op_b0f8_5_nf; +extern cpuop_func op_b0f8_5_ff; +extern cpuop_func op_b0f9_5_nf; +extern cpuop_func op_b0f9_5_ff; +extern cpuop_func op_b0fa_5_nf; +extern cpuop_func op_b0fa_5_ff; +extern cpuop_func op_b0fb_5_nf; +extern cpuop_func op_b0fb_5_ff; +extern cpuop_func op_b0fc_5_nf; +extern cpuop_func op_b0fc_5_ff; +extern cpuop_func op_b100_5_nf; +extern cpuop_func op_b100_5_ff; +extern cpuop_func op_b108_5_nf; +extern cpuop_func op_b108_5_ff; +extern cpuop_func op_b110_5_nf; +extern cpuop_func op_b110_5_ff; +extern cpuop_func op_b118_5_nf; +extern cpuop_func op_b118_5_ff; +extern cpuop_func op_b120_5_nf; +extern cpuop_func op_b120_5_ff; +extern cpuop_func op_b128_5_nf; +extern cpuop_func op_b128_5_ff; +extern cpuop_func op_b130_5_nf; +extern cpuop_func op_b130_5_ff; +extern cpuop_func op_b138_5_nf; +extern cpuop_func op_b138_5_ff; +extern cpuop_func op_b139_5_nf; +extern cpuop_func op_b139_5_ff; +extern cpuop_func op_b140_5_nf; +extern cpuop_func op_b140_5_ff; +extern cpuop_func op_b148_5_nf; +extern cpuop_func op_b148_5_ff; +extern cpuop_func op_b150_5_nf; +extern cpuop_func op_b150_5_ff; +extern cpuop_func op_b158_5_nf; +extern cpuop_func op_b158_5_ff; +extern cpuop_func op_b160_5_nf; +extern cpuop_func op_b160_5_ff; +extern cpuop_func op_b168_5_nf; +extern cpuop_func op_b168_5_ff; +extern cpuop_func op_b170_5_nf; +extern cpuop_func op_b170_5_ff; +extern cpuop_func op_b178_5_nf; +extern cpuop_func op_b178_5_ff; +extern cpuop_func op_b179_5_nf; +extern cpuop_func op_b179_5_ff; +extern cpuop_func op_b180_5_nf; +extern cpuop_func op_b180_5_ff; +extern cpuop_func op_b188_5_nf; +extern cpuop_func op_b188_5_ff; +extern cpuop_func op_b190_5_nf; +extern cpuop_func op_b190_5_ff; +extern cpuop_func op_b198_5_nf; +extern cpuop_func op_b198_5_ff; +extern cpuop_func op_b1a0_5_nf; +extern cpuop_func op_b1a0_5_ff; +extern cpuop_func op_b1a8_5_nf; +extern cpuop_func op_b1a8_5_ff; +extern cpuop_func op_b1b0_5_nf; +extern cpuop_func op_b1b0_5_ff; +extern cpuop_func op_b1b8_5_nf; +extern cpuop_func op_b1b8_5_ff; +extern cpuop_func op_b1b9_5_nf; +extern cpuop_func op_b1b9_5_ff; +extern cpuop_func op_b1c0_5_nf; +extern cpuop_func op_b1c0_5_ff; +extern cpuop_func op_b1c8_5_nf; +extern cpuop_func op_b1c8_5_ff; +extern cpuop_func op_b1d0_5_nf; +extern cpuop_func op_b1d0_5_ff; +extern cpuop_func op_b1d8_5_nf; +extern cpuop_func op_b1d8_5_ff; +extern cpuop_func op_b1e0_5_nf; +extern cpuop_func op_b1e0_5_ff; +extern cpuop_func op_b1e8_5_nf; +extern cpuop_func op_b1e8_5_ff; +extern cpuop_func op_b1f0_5_nf; +extern cpuop_func op_b1f0_5_ff; +extern cpuop_func op_b1f8_5_nf; +extern cpuop_func op_b1f8_5_ff; +extern cpuop_func op_b1f9_5_nf; +extern cpuop_func op_b1f9_5_ff; +extern cpuop_func op_b1fa_5_nf; +extern cpuop_func op_b1fa_5_ff; +extern cpuop_func op_b1fb_5_nf; +extern cpuop_func op_b1fb_5_ff; +extern cpuop_func op_b1fc_5_nf; +extern cpuop_func op_b1fc_5_ff; +extern cpuop_func op_c000_5_nf; +extern cpuop_func op_c000_5_ff; +extern cpuop_func op_c010_5_nf; +extern cpuop_func op_c010_5_ff; +extern cpuop_func op_c018_5_nf; +extern cpuop_func op_c018_5_ff; +extern cpuop_func op_c020_5_nf; +extern cpuop_func op_c020_5_ff; +extern cpuop_func op_c028_5_nf; +extern cpuop_func op_c028_5_ff; +extern cpuop_func op_c030_5_nf; +extern cpuop_func op_c030_5_ff; +extern cpuop_func op_c038_5_nf; +extern cpuop_func op_c038_5_ff; +extern cpuop_func op_c039_5_nf; +extern cpuop_func op_c039_5_ff; +extern cpuop_func op_c03a_5_nf; +extern cpuop_func op_c03a_5_ff; +extern cpuop_func op_c03b_5_nf; +extern cpuop_func op_c03b_5_ff; +extern cpuop_func op_c03c_5_nf; +extern cpuop_func op_c03c_5_ff; +extern cpuop_func op_c040_5_nf; +extern cpuop_func op_c040_5_ff; +extern cpuop_func op_c050_5_nf; +extern cpuop_func op_c050_5_ff; +extern cpuop_func op_c058_5_nf; +extern cpuop_func op_c058_5_ff; +extern cpuop_func op_c060_5_nf; +extern cpuop_func op_c060_5_ff; +extern cpuop_func op_c068_5_nf; +extern cpuop_func op_c068_5_ff; +extern cpuop_func op_c070_5_nf; +extern cpuop_func op_c070_5_ff; +extern cpuop_func op_c078_5_nf; +extern cpuop_func op_c078_5_ff; +extern cpuop_func op_c079_5_nf; +extern cpuop_func op_c079_5_ff; +extern cpuop_func op_c07a_5_nf; +extern cpuop_func op_c07a_5_ff; +extern cpuop_func op_c07b_5_nf; +extern cpuop_func op_c07b_5_ff; +extern cpuop_func op_c07c_5_nf; +extern cpuop_func op_c07c_5_ff; +extern cpuop_func op_c080_5_nf; +extern cpuop_func op_c080_5_ff; +extern cpuop_func op_c090_5_nf; +extern cpuop_func op_c090_5_ff; +extern cpuop_func op_c098_5_nf; +extern cpuop_func op_c098_5_ff; +extern cpuop_func op_c0a0_5_nf; +extern cpuop_func op_c0a0_5_ff; +extern cpuop_func op_c0a8_5_nf; +extern cpuop_func op_c0a8_5_ff; +extern cpuop_func op_c0b0_5_nf; +extern cpuop_func op_c0b0_5_ff; +extern cpuop_func op_c0b8_5_nf; +extern cpuop_func op_c0b8_5_ff; +extern cpuop_func op_c0b9_5_nf; +extern cpuop_func op_c0b9_5_ff; +extern cpuop_func op_c0ba_5_nf; +extern cpuop_func op_c0ba_5_ff; +extern cpuop_func op_c0bb_5_nf; +extern cpuop_func op_c0bb_5_ff; +extern cpuop_func op_c0bc_5_nf; +extern cpuop_func op_c0bc_5_ff; +extern cpuop_func op_c0c0_5_nf; +extern cpuop_func op_c0c0_5_ff; +extern cpuop_func op_c0d0_5_nf; +extern cpuop_func op_c0d0_5_ff; +extern cpuop_func op_c0d8_5_nf; +extern cpuop_func op_c0d8_5_ff; +extern cpuop_func op_c0e0_5_nf; +extern cpuop_func op_c0e0_5_ff; +extern cpuop_func op_c0e8_5_nf; +extern cpuop_func op_c0e8_5_ff; +extern cpuop_func op_c0f0_5_nf; +extern cpuop_func op_c0f0_5_ff; +extern cpuop_func op_c0f8_5_nf; +extern cpuop_func op_c0f8_5_ff; +extern cpuop_func op_c0f9_5_nf; +extern cpuop_func op_c0f9_5_ff; +extern cpuop_func op_c0fa_5_nf; +extern cpuop_func op_c0fa_5_ff; +extern cpuop_func op_c0fb_5_nf; +extern cpuop_func op_c0fb_5_ff; +extern cpuop_func op_c0fc_5_nf; +extern cpuop_func op_c0fc_5_ff; +extern cpuop_func op_c100_5_nf; +extern cpuop_func op_c100_5_ff; +extern cpuop_func op_c108_5_nf; +extern cpuop_func op_c108_5_ff; +extern cpuop_func op_c110_5_nf; +extern cpuop_func op_c110_5_ff; +extern cpuop_func op_c118_5_nf; +extern cpuop_func op_c118_5_ff; +extern cpuop_func op_c120_5_nf; +extern cpuop_func op_c120_5_ff; +extern cpuop_func op_c128_5_nf; +extern cpuop_func op_c128_5_ff; +extern cpuop_func op_c130_5_nf; +extern cpuop_func op_c130_5_ff; +extern cpuop_func op_c138_5_nf; +extern cpuop_func op_c138_5_ff; +extern cpuop_func op_c139_5_nf; +extern cpuop_func op_c139_5_ff; +extern cpuop_func op_c140_5_nf; +extern cpuop_func op_c140_5_ff; +extern cpuop_func op_c148_5_nf; +extern cpuop_func op_c148_5_ff; +extern cpuop_func op_c150_5_nf; +extern cpuop_func op_c150_5_ff; +extern cpuop_func op_c158_5_nf; +extern cpuop_func op_c158_5_ff; +extern cpuop_func op_c160_5_nf; +extern cpuop_func op_c160_5_ff; +extern cpuop_func op_c168_5_nf; +extern cpuop_func op_c168_5_ff; +extern cpuop_func op_c170_5_nf; +extern cpuop_func op_c170_5_ff; +extern cpuop_func op_c178_5_nf; +extern cpuop_func op_c178_5_ff; +extern cpuop_func op_c179_5_nf; +extern cpuop_func op_c179_5_ff; +extern cpuop_func op_c188_5_nf; +extern cpuop_func op_c188_5_ff; +extern cpuop_func op_c190_5_nf; +extern cpuop_func op_c190_5_ff; +extern cpuop_func op_c198_5_nf; +extern cpuop_func op_c198_5_ff; +extern cpuop_func op_c1a0_5_nf; +extern cpuop_func op_c1a0_5_ff; +extern cpuop_func op_c1a8_5_nf; +extern cpuop_func op_c1a8_5_ff; +extern cpuop_func op_c1b0_5_nf; +extern cpuop_func op_c1b0_5_ff; +extern cpuop_func op_c1b8_5_nf; +extern cpuop_func op_c1b8_5_ff; +extern cpuop_func op_c1b9_5_nf; +extern cpuop_func op_c1b9_5_ff; +extern cpuop_func op_c1c0_5_nf; +extern cpuop_func op_c1c0_5_ff; +extern cpuop_func op_c1d0_5_nf; +extern cpuop_func op_c1d0_5_ff; +extern cpuop_func op_c1d8_5_nf; +extern cpuop_func op_c1d8_5_ff; +extern cpuop_func op_c1e0_5_nf; +extern cpuop_func op_c1e0_5_ff; +extern cpuop_func op_c1e8_5_nf; +extern cpuop_func op_c1e8_5_ff; +extern cpuop_func op_c1f0_5_nf; +extern cpuop_func op_c1f0_5_ff; +extern cpuop_func op_c1f8_5_nf; +extern cpuop_func op_c1f8_5_ff; +extern cpuop_func op_c1f9_5_nf; +extern cpuop_func op_c1f9_5_ff; +extern cpuop_func op_c1fa_5_nf; +extern cpuop_func op_c1fa_5_ff; +extern cpuop_func op_c1fb_5_nf; +extern cpuop_func op_c1fb_5_ff; +extern cpuop_func op_c1fc_5_nf; +extern cpuop_func op_c1fc_5_ff; +extern cpuop_func op_d000_5_nf; +extern cpuop_func op_d000_5_ff; +extern cpuop_func op_d010_5_nf; +extern cpuop_func op_d010_5_ff; +extern cpuop_func op_d018_5_nf; +extern cpuop_func op_d018_5_ff; +extern cpuop_func op_d020_5_nf; +extern cpuop_func op_d020_5_ff; +extern cpuop_func op_d028_5_nf; +extern cpuop_func op_d028_5_ff; +extern cpuop_func op_d030_5_nf; +extern cpuop_func op_d030_5_ff; +extern cpuop_func op_d038_5_nf; +extern cpuop_func op_d038_5_ff; +extern cpuop_func op_d039_5_nf; +extern cpuop_func op_d039_5_ff; +extern cpuop_func op_d03a_5_nf; +extern cpuop_func op_d03a_5_ff; +extern cpuop_func op_d03b_5_nf; +extern cpuop_func op_d03b_5_ff; +extern cpuop_func op_d03c_5_nf; +extern cpuop_func op_d03c_5_ff; +extern cpuop_func op_d040_5_nf; +extern cpuop_func op_d040_5_ff; +extern cpuop_func op_d048_5_nf; +extern cpuop_func op_d048_5_ff; +extern cpuop_func op_d050_5_nf; +extern cpuop_func op_d050_5_ff; +extern cpuop_func op_d058_5_nf; +extern cpuop_func op_d058_5_ff; +extern cpuop_func op_d060_5_nf; +extern cpuop_func op_d060_5_ff; +extern cpuop_func op_d068_5_nf; +extern cpuop_func op_d068_5_ff; +extern cpuop_func op_d070_5_nf; +extern cpuop_func op_d070_5_ff; +extern cpuop_func op_d078_5_nf; +extern cpuop_func op_d078_5_ff; +extern cpuop_func op_d079_5_nf; +extern cpuop_func op_d079_5_ff; +extern cpuop_func op_d07a_5_nf; +extern cpuop_func op_d07a_5_ff; +extern cpuop_func op_d07b_5_nf; +extern cpuop_func op_d07b_5_ff; +extern cpuop_func op_d07c_5_nf; +extern cpuop_func op_d07c_5_ff; +extern cpuop_func op_d080_5_nf; +extern cpuop_func op_d080_5_ff; +extern cpuop_func op_d088_5_nf; +extern cpuop_func op_d088_5_ff; +extern cpuop_func op_d090_5_nf; +extern cpuop_func op_d090_5_ff; +extern cpuop_func op_d098_5_nf; +extern cpuop_func op_d098_5_ff; +extern cpuop_func op_d0a0_5_nf; +extern cpuop_func op_d0a0_5_ff; +extern cpuop_func op_d0a8_5_nf; +extern cpuop_func op_d0a8_5_ff; +extern cpuop_func op_d0b0_5_nf; +extern cpuop_func op_d0b0_5_ff; +extern cpuop_func op_d0b8_5_nf; +extern cpuop_func op_d0b8_5_ff; +extern cpuop_func op_d0b9_5_nf; +extern cpuop_func op_d0b9_5_ff; +extern cpuop_func op_d0ba_5_nf; +extern cpuop_func op_d0ba_5_ff; +extern cpuop_func op_d0bb_5_nf; +extern cpuop_func op_d0bb_5_ff; +extern cpuop_func op_d0bc_5_nf; +extern cpuop_func op_d0bc_5_ff; +extern cpuop_func op_d0c0_5_nf; +extern cpuop_func op_d0c0_5_ff; +extern cpuop_func op_d0c8_5_nf; +extern cpuop_func op_d0c8_5_ff; +extern cpuop_func op_d0d0_5_nf; +extern cpuop_func op_d0d0_5_ff; +extern cpuop_func op_d0d8_5_nf; +extern cpuop_func op_d0d8_5_ff; +extern cpuop_func op_d0e0_5_nf; +extern cpuop_func op_d0e0_5_ff; +extern cpuop_func op_d0e8_5_nf; +extern cpuop_func op_d0e8_5_ff; +extern cpuop_func op_d0f0_5_nf; +extern cpuop_func op_d0f0_5_ff; +extern cpuop_func op_d0f8_5_nf; +extern cpuop_func op_d0f8_5_ff; +extern cpuop_func op_d0f9_5_nf; +extern cpuop_func op_d0f9_5_ff; +extern cpuop_func op_d0fa_5_nf; +extern cpuop_func op_d0fa_5_ff; +extern cpuop_func op_d0fb_5_nf; +extern cpuop_func op_d0fb_5_ff; +extern cpuop_func op_d0fc_5_nf; +extern cpuop_func op_d0fc_5_ff; +extern cpuop_func op_d100_5_nf; +extern cpuop_func op_d100_5_ff; +extern cpuop_func op_d108_5_nf; +extern cpuop_func op_d108_5_ff; +extern cpuop_func op_d110_5_nf; +extern cpuop_func op_d110_5_ff; +extern cpuop_func op_d118_5_nf; +extern cpuop_func op_d118_5_ff; +extern cpuop_func op_d120_5_nf; +extern cpuop_func op_d120_5_ff; +extern cpuop_func op_d128_5_nf; +extern cpuop_func op_d128_5_ff; +extern cpuop_func op_d130_5_nf; +extern cpuop_func op_d130_5_ff; +extern cpuop_func op_d138_5_nf; +extern cpuop_func op_d138_5_ff; +extern cpuop_func op_d139_5_nf; +extern cpuop_func op_d139_5_ff; +extern cpuop_func op_d140_5_nf; +extern cpuop_func op_d140_5_ff; +extern cpuop_func op_d148_5_nf; +extern cpuop_func op_d148_5_ff; +extern cpuop_func op_d150_5_nf; +extern cpuop_func op_d150_5_ff; +extern cpuop_func op_d158_5_nf; +extern cpuop_func op_d158_5_ff; +extern cpuop_func op_d160_5_nf; +extern cpuop_func op_d160_5_ff; +extern cpuop_func op_d168_5_nf; +extern cpuop_func op_d168_5_ff; +extern cpuop_func op_d170_5_nf; +extern cpuop_func op_d170_5_ff; +extern cpuop_func op_d178_5_nf; +extern cpuop_func op_d178_5_ff; +extern cpuop_func op_d179_5_nf; +extern cpuop_func op_d179_5_ff; +extern cpuop_func op_d180_5_nf; +extern cpuop_func op_d180_5_ff; +extern cpuop_func op_d188_5_nf; +extern cpuop_func op_d188_5_ff; +extern cpuop_func op_d190_5_nf; +extern cpuop_func op_d190_5_ff; +extern cpuop_func op_d198_5_nf; +extern cpuop_func op_d198_5_ff; +extern cpuop_func op_d1a0_5_nf; +extern cpuop_func op_d1a0_5_ff; +extern cpuop_func op_d1a8_5_nf; +extern cpuop_func op_d1a8_5_ff; +extern cpuop_func op_d1b0_5_nf; +extern cpuop_func op_d1b0_5_ff; +extern cpuop_func op_d1b8_5_nf; +extern cpuop_func op_d1b8_5_ff; +extern cpuop_func op_d1b9_5_nf; +extern cpuop_func op_d1b9_5_ff; +extern cpuop_func op_d1c0_5_nf; +extern cpuop_func op_d1c0_5_ff; +extern cpuop_func op_d1c8_5_nf; +extern cpuop_func op_d1c8_5_ff; +extern cpuop_func op_d1d0_5_nf; +extern cpuop_func op_d1d0_5_ff; +extern cpuop_func op_d1d8_5_nf; +extern cpuop_func op_d1d8_5_ff; +extern cpuop_func op_d1e0_5_nf; +extern cpuop_func op_d1e0_5_ff; +extern cpuop_func op_d1e8_5_nf; +extern cpuop_func op_d1e8_5_ff; +extern cpuop_func op_d1f0_5_nf; +extern cpuop_func op_d1f0_5_ff; +extern cpuop_func op_d1f8_5_nf; +extern cpuop_func op_d1f8_5_ff; +extern cpuop_func op_d1f9_5_nf; +extern cpuop_func op_d1f9_5_ff; +extern cpuop_func op_d1fa_5_nf; +extern cpuop_func op_d1fa_5_ff; +extern cpuop_func op_d1fb_5_nf; +extern cpuop_func op_d1fb_5_ff; +extern cpuop_func op_d1fc_5_nf; +extern cpuop_func op_d1fc_5_ff; +extern cpuop_func op_e000_5_nf; +extern cpuop_func op_e000_5_ff; +extern cpuop_func op_e008_5_nf; +extern cpuop_func op_e008_5_ff; +extern cpuop_func op_e010_5_nf; +extern cpuop_func op_e010_5_ff; +extern cpuop_func op_e018_5_nf; +extern cpuop_func op_e018_5_ff; +extern cpuop_func op_e020_5_nf; +extern cpuop_func op_e020_5_ff; +extern cpuop_func op_e028_5_nf; +extern cpuop_func op_e028_5_ff; +extern cpuop_func op_e030_5_nf; +extern cpuop_func op_e030_5_ff; +extern cpuop_func op_e038_5_nf; +extern cpuop_func op_e038_5_ff; +extern cpuop_func op_e040_5_nf; +extern cpuop_func op_e040_5_ff; +extern cpuop_func op_e048_5_nf; +extern cpuop_func op_e048_5_ff; +extern cpuop_func op_e050_5_nf; +extern cpuop_func op_e050_5_ff; +extern cpuop_func op_e058_5_nf; +extern cpuop_func op_e058_5_ff; +extern cpuop_func op_e060_5_nf; +extern cpuop_func op_e060_5_ff; +extern cpuop_func op_e068_5_nf; +extern cpuop_func op_e068_5_ff; +extern cpuop_func op_e070_5_nf; +extern cpuop_func op_e070_5_ff; +extern cpuop_func op_e078_5_nf; +extern cpuop_func op_e078_5_ff; +extern cpuop_func op_e080_5_nf; +extern cpuop_func op_e080_5_ff; +extern cpuop_func op_e088_5_nf; +extern cpuop_func op_e088_5_ff; +extern cpuop_func op_e090_5_nf; +extern cpuop_func op_e090_5_ff; +extern cpuop_func op_e098_5_nf; +extern cpuop_func op_e098_5_ff; +extern cpuop_func op_e0a0_5_nf; +extern cpuop_func op_e0a0_5_ff; +extern cpuop_func op_e0a8_5_nf; +extern cpuop_func op_e0a8_5_ff; +extern cpuop_func op_e0b0_5_nf; +extern cpuop_func op_e0b0_5_ff; +extern cpuop_func op_e0b8_5_nf; +extern cpuop_func op_e0b8_5_ff; +extern cpuop_func op_e0d0_5_nf; +extern cpuop_func op_e0d0_5_ff; +extern cpuop_func op_e0d8_5_nf; +extern cpuop_func op_e0d8_5_ff; +extern cpuop_func op_e0e0_5_nf; +extern cpuop_func op_e0e0_5_ff; +extern cpuop_func op_e0e8_5_nf; +extern cpuop_func op_e0e8_5_ff; +extern cpuop_func op_e0f0_5_nf; +extern cpuop_func op_e0f0_5_ff; +extern cpuop_func op_e0f8_5_nf; +extern cpuop_func op_e0f8_5_ff; +extern cpuop_func op_e0f9_5_nf; +extern cpuop_func op_e0f9_5_ff; +extern cpuop_func op_e100_5_nf; +extern cpuop_func op_e100_5_ff; +extern cpuop_func op_e108_5_nf; +extern cpuop_func op_e108_5_ff; +extern cpuop_func op_e110_5_nf; +extern cpuop_func op_e110_5_ff; +extern cpuop_func op_e118_5_nf; +extern cpuop_func op_e118_5_ff; +extern cpuop_func op_e120_5_nf; +extern cpuop_func op_e120_5_ff; +extern cpuop_func op_e128_5_nf; +extern cpuop_func op_e128_5_ff; +extern cpuop_func op_e130_5_nf; +extern cpuop_func op_e130_5_ff; +extern cpuop_func op_e138_5_nf; +extern cpuop_func op_e138_5_ff; +extern cpuop_func op_e140_5_nf; +extern cpuop_func op_e140_5_ff; +extern cpuop_func op_e148_5_nf; +extern cpuop_func op_e148_5_ff; +extern cpuop_func op_e150_5_nf; +extern cpuop_func op_e150_5_ff; +extern cpuop_func op_e158_5_nf; +extern cpuop_func op_e158_5_ff; +extern cpuop_func op_e160_5_nf; +extern cpuop_func op_e160_5_ff; +extern cpuop_func op_e168_5_nf; +extern cpuop_func op_e168_5_ff; +extern cpuop_func op_e170_5_nf; +extern cpuop_func op_e170_5_ff; +extern cpuop_func op_e178_5_nf; +extern cpuop_func op_e178_5_ff; +extern cpuop_func op_e180_5_nf; +extern cpuop_func op_e180_5_ff; +extern cpuop_func op_e188_5_nf; +extern cpuop_func op_e188_5_ff; +extern cpuop_func op_e190_5_nf; +extern cpuop_func op_e190_5_ff; +extern cpuop_func op_e198_5_nf; +extern cpuop_func op_e198_5_ff; +extern cpuop_func op_e1a0_5_nf; +extern cpuop_func op_e1a0_5_ff; +extern cpuop_func op_e1a8_5_nf; +extern cpuop_func op_e1a8_5_ff; +extern cpuop_func op_e1b0_5_nf; +extern cpuop_func op_e1b0_5_ff; +extern cpuop_func op_e1b8_5_nf; +extern cpuop_func op_e1b8_5_ff; +extern cpuop_func op_e1d0_5_nf; +extern cpuop_func op_e1d0_5_ff; +extern cpuop_func op_e1d8_5_nf; +extern cpuop_func op_e1d8_5_ff; +extern cpuop_func op_e1e0_5_nf; +extern cpuop_func op_e1e0_5_ff; +extern cpuop_func op_e1e8_5_nf; +extern cpuop_func op_e1e8_5_ff; +extern cpuop_func op_e1f0_5_nf; +extern cpuop_func op_e1f0_5_ff; +extern cpuop_func op_e1f8_5_nf; +extern cpuop_func op_e1f8_5_ff; +extern cpuop_func op_e1f9_5_nf; +extern cpuop_func op_e1f9_5_ff; +extern cpuop_func op_e2d0_5_nf; +extern cpuop_func op_e2d0_5_ff; +extern cpuop_func op_e2d8_5_nf; +extern cpuop_func op_e2d8_5_ff; +extern cpuop_func op_e2e0_5_nf; +extern cpuop_func op_e2e0_5_ff; +extern cpuop_func op_e2e8_5_nf; +extern cpuop_func op_e2e8_5_ff; +extern cpuop_func op_e2f0_5_nf; +extern cpuop_func op_e2f0_5_ff; +extern cpuop_func op_e2f8_5_nf; +extern cpuop_func op_e2f8_5_ff; +extern cpuop_func op_e2f9_5_nf; +extern cpuop_func op_e2f9_5_ff; +extern cpuop_func op_e3d0_5_nf; +extern cpuop_func op_e3d0_5_ff; +extern cpuop_func op_e3d8_5_nf; +extern cpuop_func op_e3d8_5_ff; +extern cpuop_func op_e3e0_5_nf; +extern cpuop_func op_e3e0_5_ff; +extern cpuop_func op_e3e8_5_nf; +extern cpuop_func op_e3e8_5_ff; +extern cpuop_func op_e3f0_5_nf; +extern cpuop_func op_e3f0_5_ff; +extern cpuop_func op_e3f8_5_nf; +extern cpuop_func op_e3f8_5_ff; +extern cpuop_func op_e3f9_5_nf; +extern cpuop_func op_e3f9_5_ff; +extern cpuop_func op_e4d0_5_nf; +extern cpuop_func op_e4d0_5_ff; +extern cpuop_func op_e4d8_5_nf; +extern cpuop_func op_e4d8_5_ff; +extern cpuop_func op_e4e0_5_nf; +extern cpuop_func op_e4e0_5_ff; +extern cpuop_func op_e4e8_5_nf; +extern cpuop_func op_e4e8_5_ff; +extern cpuop_func op_e4f0_5_nf; +extern cpuop_func op_e4f0_5_ff; +extern cpuop_func op_e4f8_5_nf; +extern cpuop_func op_e4f8_5_ff; +extern cpuop_func op_e4f9_5_nf; +extern cpuop_func op_e4f9_5_ff; +extern cpuop_func op_e5d0_5_nf; +extern cpuop_func op_e5d0_5_ff; +extern cpuop_func op_e5d8_5_nf; +extern cpuop_func op_e5d8_5_ff; +extern cpuop_func op_e5e0_5_nf; +extern cpuop_func op_e5e0_5_ff; +extern cpuop_func op_e5e8_5_nf; +extern cpuop_func op_e5e8_5_ff; +extern cpuop_func op_e5f0_5_nf; +extern cpuop_func op_e5f0_5_ff; +extern cpuop_func op_e5f8_5_nf; +extern cpuop_func op_e5f8_5_ff; +extern cpuop_func op_e5f9_5_nf; +extern cpuop_func op_e5f9_5_ff; +extern cpuop_func op_e6d0_5_nf; +extern cpuop_func op_e6d0_5_ff; +extern cpuop_func op_e6d8_5_nf; +extern cpuop_func op_e6d8_5_ff; +extern cpuop_func op_e6e0_5_nf; +extern cpuop_func op_e6e0_5_ff; +extern cpuop_func op_e6e8_5_nf; +extern cpuop_func op_e6e8_5_ff; +extern cpuop_func op_e6f0_5_nf; +extern cpuop_func op_e6f0_5_ff; +extern cpuop_func op_e6f8_5_nf; +extern cpuop_func op_e6f8_5_ff; +extern cpuop_func op_e6f9_5_nf; +extern cpuop_func op_e6f9_5_ff; +extern cpuop_func op_e7d0_5_nf; +extern cpuop_func op_e7d0_5_ff; +extern cpuop_func op_e7d8_5_nf; +extern cpuop_func op_e7d8_5_ff; +extern cpuop_func op_e7e0_5_nf; +extern cpuop_func op_e7e0_5_ff; +extern cpuop_func op_e7e8_5_nf; +extern cpuop_func op_e7e8_5_ff; +extern cpuop_func op_e7f0_5_nf; +extern cpuop_func op_e7f0_5_ff; +extern cpuop_func op_e7f8_5_nf; +extern cpuop_func op_e7f8_5_ff; +extern cpuop_func op_e7f9_5_nf; +extern cpuop_func op_e7f9_5_ff; diff --git a/waterbox/virtualjaguar/src/m68000/gencpu.c b/waterbox/virtualjaguar/src/m68000/gencpu.c new file mode 100644 index 0000000000..88f121ba1b --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/gencpu.c @@ -0,0 +1,2818 @@ +/* + * UAE - The Un*x Amiga Emulator - CPU core + * + * MC68000 emulation generator + * + * This is a fairly stupid program that generates a lot of case labels that + * can be #included in a switch statement. + * As an alternative, it can generate functions that handle specific + * MC68000 instructions, plus a prototype header file and a function pointer + * array to look up the function for an opcode. + * Error checking is bad, an illegal table68k file will cause the program to + * call abort(). + * The generated code is sometimes sub-optimal, an optimizing compiler should + * take care of this. + * + * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992. + * + * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt + * + * Adaptation to Hatari and better cpu timings by Thomas Huth + * Adaptation to Virtual Jaguar by James Hammons + * + * This file is distributed under the GNU Public License, version 3 or at + * your option any later version. Read the file GPLv3 for details. + * + */ + + +/* 2007/03/xx [NP] Use add_cycles.pl to set 'CurrentInstrCycles' in each opcode. */ +/* 2007/04/09 [NP] Correct CLR : on 68000, CLR reads the memory before clearing it (but we should */ +/* not add cycles for reading). This means CLR can give 2 wait states (one for */ +/* read and one for right) (clr.b $fa1b.w in Decade's Demo Main Menu). */ +/* 2007/04/14 [NP] - Although dest -(an) normally takes 2 cycles, this is not the case for move : */ +/* move dest (an), (an)+ and -(an) all take the same time (curi->dmode == Apdi) */ +/* (Syntax Terror Demo Reset). */ +/* - Scc takes 6 cycles instead of 4 if the result is true (Ventura Demo Loader). */ +/* - Store the family of the current opcode into OpcodeFamily : used to check */ +/* instruction pairing on ST into m68000.c */ +/* 2007/04/17 [NP] Add support for cycle accurate MULU (No Cooper Greeting Screen). */ +/* 2007/04/24 [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 (ULM Demo Menu). */ +/* 2007/04/25 [NP] On ST, d8(An,Xn) and d8(PC,Xn) take 2 cycles more than the official 68000's */ +/* table (ULM Demo Menu). */ +/* 2007/11/12 [NP] Add refill_prefetch for i_ADD to fix Transbeauce 2 demo self modified code. */ +/* Ugly hack, we need better prefetch emulation (switch to winuae gencpu.c) */ +/* 2007/11/25 [NP] In i_DBcc, in case of address error, last_addr_for_exception_3 should be */ +/* pc+4, not pc+2 (Transbeauce 2 demo) (e.g. 'dbf d0,#$fff5'). */ +/* This means the value pushed on the frame stack should be the address of the */ +/* instruction following the one generating the address error. */ +/* FIXME : this should be the case for i_BSR and i_BCC too (need to check on */ +/* a real 68000). */ +/* 2007/11/28 [NP] Backport DIVS/DIVU cycles exact routines from WinUAE (original work by Jorge */ +/* Cwik, pasti@fxatari.com). */ +/* 2007/12/08 [NP] In case of CHK/CHK2 exception, PC stored on the stack wasn't pointing to the */ +/* next instruction but to the current CHK/CHK2 instruction (Transbeauce 2 demo). */ +/* We need to call 'sync_m68k_pc' before calling 'Exception'. */ +/* 2007/12/09 [NP] CHK.L (e.g. $4700) doesn't exist on 68000 and should be considered as an illegal*/ +/* instruction (Transbeauce 2 demo) -> change in table68k. */ +/* 2008/01/24 [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 (Fullshade in Anomaly Demos). */ +/* 2008/01/26 [NP] On ST, d8(An,Xn) takes 2 cycles more when used with ADDA/SUBA (ULM Demo Menu) */ +/* but not when used with MOVE (e.g. 'move.l 0(a5,d1),(a4)' takes 26 cycles and so */ +/* can pair with a lsr) (Anomaly Demo Intro). */ +/* 2008/04/26 [NP] Handle sz_byte for Areg in genamode, as 'move.b a1,(a0)' ($1089) is possible */ +/* on ST (fix Blood Money on Superior 65) */ +/* 2010/04/05 [NP] On ST, d8(An,Xn) takes 2 cycles more (which can generate pairing). */ +/* Use BusCyclePenalty to properly handle the 2/4 cycles added in that case when */ +/* addressing mode is Ad8r or PC8r (ULM Demo Menu, Anomaly Demo Intro, DHS */ +/* Sommarhack 2010) (see m68000.h) */ + + +//const char GenCpu_fileid[] = "Hatari gencpu.c : " __DATE__ " " __TIME__; + +#include +#include + +#include "sysdeps.h" +#include "readcpu.h" + +#define BOOL_TYPE "int" + +static FILE *headerfile; +static FILE *stblfile; + +static int using_prefetch; +static int using_exception_3; +static int cpu_level; + +char exactCpuCycles[256]; /* Space to store return string for exact cpu cycles */ + +long nCurInstrCycPos; /* Stores where we have to patch in the current cycles value */ + +/* For the current opcode, the next lower level that will have different code. + * Initialized to -1 for each opcode. If it remains unchanged, indicates we + * are done with that opcode. */ +static int next_cpu_level; +static int *opcode_map; +static int *opcode_next_clev; +static int *opcode_last_postfix; +static unsigned long *counts; + + +static void read_counts (void) +{ + FILE *file; + unsigned long opcode, count, total; + char name[20]; + int nr = 0; + memset (counts, 0, 65536 * sizeof *counts); + + file = fopen ("frequent.68k", "r"); + if (file) { + if (fscanf (file, "Total: %lu\n", &total) == EOF) { + perror("read_counts"); + } + while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) { + opcode_next_clev[nr] = 4; + opcode_last_postfix[nr] = -1; + opcode_map[nr++] = opcode; + counts[opcode] = count; + } + fclose (file); + } + if (nr == nr_cpuop_funcs) + return; + for (opcode = 0; opcode < 0x10000; opcode++) { + if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG + && counts[opcode] == 0) + { + opcode_next_clev[nr] = 4; + opcode_last_postfix[nr] = -1; + opcode_map[nr++] = opcode; + counts[opcode] = count; + } + } + if (nr != nr_cpuop_funcs) + abort (); +} + +static char endlabelstr[80]; +static int endlabelno = 0; +static int need_endlabel; + +static int n_braces = 0; +static int m68k_pc_offset = 0; +static int insn_n_cycles; + +static void start_brace (void) +{ + n_braces++; + printf ("{"); +} + +static void close_brace (void) +{ + assert (n_braces > 0); + n_braces--; + printf ("}"); +} + +static void finish_braces (void) +{ + while (n_braces > 0) + close_brace (); +} + +static void pop_braces (int to) +{ + while (n_braces > to) + close_brace (); +} + +static int bit_size (int size) +{ + switch (size) { + case sz_byte: return 8; + case sz_word: return 16; + case sz_long: return 32; + default: abort (); + } + return 0; +} + +static const char *bit_mask (int size) +{ + switch (size) { + case sz_byte: return "0xff"; + case sz_word: return "0xffff"; + case sz_long: return "0xffffffff"; + default: abort (); + } + return 0; +} + +static const char *gen_nextilong (void) +{ + static char buffer[80]; + int r = m68k_pc_offset; + m68k_pc_offset += 4; + + insn_n_cycles += 8; + + if (using_prefetch) + sprintf (buffer, "get_ilong_prefetch(%d)", r); + else + sprintf (buffer, "get_ilong(%d)", r); + return buffer; +} + +static const char *gen_nextiword (void) +{ + static char buffer[80]; + int r = m68k_pc_offset; + m68k_pc_offset += 2; + + insn_n_cycles += 4; + + if (using_prefetch) + sprintf (buffer, "get_iword_prefetch(%d)", r); + else + sprintf (buffer, "get_iword(%d)", r); + return buffer; +} + +static const char *gen_nextibyte (void) +{ + static char buffer[80]; + int r = m68k_pc_offset; + m68k_pc_offset += 2; + + insn_n_cycles += 4; + + if (using_prefetch) + sprintf (buffer, "get_ibyte_prefetch(%d)", r); + else + sprintf (buffer, "get_ibyte(%d)", r); + return buffer; +} + +static void fill_prefetch_0 (void) +{ + if (using_prefetch) + printf ("fill_prefetch_0 ();\n"); +} + +static void fill_prefetch_2 (void) +{ + if (using_prefetch) + printf ("fill_prefetch_2 ();\n"); +} + +static void sync_m68k_pc(void) +{ + if (m68k_pc_offset == 0) + return; + + printf("m68k_incpc(%d);\n", m68k_pc_offset); + + switch (m68k_pc_offset) + { + case 0: + /*fprintf (stderr, "refilling prefetch at 0\n"); */ + break; + case 2: + fill_prefetch_2(); + break; + default: + fill_prefetch_0(); + break; + } + + m68k_pc_offset = 0; +} + +/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0, + * the calling routine handles Apdi and Aipi modes. + * gb-- movem == 2 means the same thing but for a MOVE16 instruction */ +static void genamode(amodes mode, const char * reg, wordsizes size, + const char * name, int getv, int movem) +{ + start_brace(); + switch (mode) + { + case Dreg: + if (movem) + abort (); + if (getv == 1) + switch (size) { + case sz_byte: + printf ("\tint8_t %s = m68k_dreg(regs, %s);\n", name, reg); + break; + case sz_word: + printf ("\tint16_t %s = m68k_dreg(regs, %s);\n", name, reg); + break; + case sz_long: + printf ("\tint32_t %s = m68k_dreg(regs, %s);\n", name, reg); + break; + default: + abort (); + } + return; + case Areg: + if (movem) + abort (); + if (getv == 1) + switch (size) { + case sz_byte: // [NP] Areg with .b is possible in MOVE source */ + printf ("\tint8_t %s = m68k_areg(regs, %s);\n", name, reg); + break; + case sz_word: + printf ("\tint16_t %s = m68k_areg(regs, %s);\n", name, reg); + break; + case sz_long: + printf ("\tint32_t %s = m68k_areg(regs, %s);\n", name, reg); + break; + default: + abort (); + } + return; + case Aind: + printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg); + break; + case Aipi: + printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg); + break; + case Apdi: + insn_n_cycles += 2; + switch (size) { + case sz_byte: + if (movem) + printf ("\tuint32_t %sa = m68k_areg(regs, %s);\n", name, reg); + else + printf ("\tuint32_t %sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg); + break; + case sz_word: + printf ("\tuint32_t %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2); + break; + case sz_long: + printf ("\tuint32_t %sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4); + break; + default: + abort (); + } + break; + case Ad16: + printf ("\tuint32_t %sa = m68k_areg(regs, %s) + (int32_t)(int16_t)%s;\n", name, reg, gen_nextiword ()); + break; + case Ad8r: + insn_n_cycles += 2; + if (cpu_level > 1) { + if (next_cpu_level < 1) + next_cpu_level = 1; + sync_m68k_pc (); + start_brace (); + /* This would ordinarily be done in gen_nextiword, which we bypass. */ + insn_n_cycles += 4; + printf ("\tuint32_t %sa = get_disp_ea_020(m68k_areg(regs, %s), next_iword());\n", name, reg); + } else { + printf ("\tuint32_t %sa = get_disp_ea_000(m68k_areg(regs, %s), %s);\n", name, reg, gen_nextiword ()); + } + printf ("\tBusCyclePenalty += 2;\n"); + + break; + case PC16: + printf ("\tuint32_t %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset); + printf ("\t%sa += (int32_t)(int16_t)%s;\n", name, gen_nextiword ()); + break; + case PC8r: + insn_n_cycles += 2; + if (cpu_level > 1) { + if (next_cpu_level < 1) + next_cpu_level = 1; + sync_m68k_pc (); + start_brace (); + /* This would ordinarily be done in gen_nextiword, which we bypass. */ + insn_n_cycles += 4; + printf ("\tuint32_t tmppc = m68k_getpc();\n"); + printf ("\tuint32_t %sa = get_disp_ea_020(tmppc, next_iword());\n", name); + } else { + printf ("\tuint32_t tmppc = m68k_getpc() + %d;\n", m68k_pc_offset); + printf ("\tuint32_t %sa = get_disp_ea_000(tmppc, %s);\n", name, gen_nextiword ()); + } + printf ("\tBusCyclePenalty += 2;\n"); + + break; + case absw: + printf ("\tuint32_t %sa = (int32_t)(int16_t)%s;\n", name, gen_nextiword ()); + break; + case absl: + printf ("\tuint32_t %sa = %s;\n", name, gen_nextilong ()); + break; + case imm: + if (getv != 1) + abort (); + switch (size) { + case sz_byte: + printf ("\tint8_t %s = %s;\n", name, gen_nextibyte ()); + break; + case sz_word: + printf ("\tint16_t %s = %s;\n", name, gen_nextiword ()); + break; + case sz_long: + printf ("\tint32_t %s = %s;\n", name, gen_nextilong ()); + break; + default: + abort (); + } + return; + case imm0: + if (getv != 1) + abort (); + printf ("\tint8_t %s = %s;\n", name, gen_nextibyte ()); + return; + case imm1: + if (getv != 1) + abort (); + printf ("\tint16_t %s = %s;\n", name, gen_nextiword ()); + return; + case imm2: + if (getv != 1) + abort (); + printf ("\tint32_t %s = %s;\n", name, gen_nextilong ()); + return; + case immi: + if (getv != 1) + abort (); + printf ("\tuint32_t %s = %s;\n", name, reg); + return; + default: + abort (); + } + + /* We get here for all non-reg non-immediate addressing modes to + * actually fetch the value. */ + + if (using_exception_3 && getv != 0 && size != sz_byte) { + printf ("\tif ((%sa & 1) != 0) {\n", name); + printf ("\t\tlast_fault_for_exception_3 = %sa;\n", name); + printf ("\t\tlast_op_for_exception_3 = opcode;\n"); + printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + %d;\n", m68k_pc_offset); + printf ("\t\tException(3, 0, M68000_EXC_SRC_CPU);\n"); + printf ("\t\tgoto %s;\n", endlabelstr); + printf ("\t}\n"); + need_endlabel = 1; + start_brace (); + } + + if (getv == 1) { + switch (size) { + case sz_byte: insn_n_cycles += 4; break; + case sz_word: insn_n_cycles += 4; break; + case sz_long: insn_n_cycles += 8; break; + default: abort (); + } + start_brace (); + switch (size) { + case sz_byte: printf ("\tint8_t %s = m68k_read_memory_8(%sa);\n", name, name); break; + case sz_word: printf ("\tint16_t %s = m68k_read_memory_16(%sa);\n", name, name); break; + case sz_long: printf ("\tint32_t %s = m68k_read_memory_32(%sa);\n", name, name); break; + default: abort (); + } + } + + /* We now might have to fix up the register for pre-dec or post-inc + * addressing modes. */ + if (!movem) + switch (mode) { + case Aipi: + switch (size) { + case sz_byte: + printf ("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg); + break; + case sz_word: + printf ("\tm68k_areg(regs, %s) += 2;\n", reg); + break; + case sz_long: + printf ("\tm68k_areg(regs, %s) += 4;\n", reg); + break; + default: + abort (); + } + break; + case Apdi: + printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name); + break; + default: + break; + } +} + +static void genastore (const char *from, amodes mode, const char *reg, + wordsizes size, const char *to) +{ + switch (mode) { + case Dreg: + switch (size) { + case sz_byte: + printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from); + break; + case sz_word: + printf ("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from); + break; + case sz_long: + printf ("\tm68k_dreg(regs, %s) = (%s);\n", reg, from); + break; + default: + abort (); + } + break; + case Areg: + switch (size) { + case sz_word: + fprintf (stderr, "Foo\n"); + printf ("\tm68k_areg(regs, %s) = (int32_t)(int16_t)(%s);\n", reg, from); + break; + case sz_long: + printf ("\tm68k_areg(regs, %s) = (%s);\n", reg, from); + break; + default: + abort (); + } + break; + case Aind: + case Aipi: + case Apdi: + case Ad16: + case Ad8r: + case absw: + case absl: + case PC16: + case PC8r: + if (using_prefetch) + sync_m68k_pc (); + switch (size) { + case sz_byte: + insn_n_cycles += 4; + printf ("\tm68k_write_memory_8(%sa,%s);\n", to, from); + break; + case sz_word: + insn_n_cycles += 4; + if (cpu_level < 2 && (mode == PC16 || mode == PC8r)) + abort (); + printf ("\tm68k_write_memory_16(%sa,%s);\n", to, from); + break; + case sz_long: + insn_n_cycles += 8; + if (cpu_level < 2 && (mode == PC16 || mode == PC8r)) + abort (); + printf ("\tm68k_write_memory_32(%sa,%s);\n", to, from); + break; + default: + abort (); + } + break; + case imm: + case imm0: + case imm1: + case imm2: + case immi: + abort (); + break; + default: + abort (); + } +} + + +static void genmovemel (uint16_t opcode) +{ + char getcode[100]; + int bMovemLong = (table68k[opcode].size == sz_long); + int size = bMovemLong ? 4 : 2; + + if (bMovemLong) { + strcpy (getcode, "m68k_read_memory_32(srca)"); + } else { + strcpy (getcode, "(int32_t)(int16_t)m68k_read_memory_16(srca)"); + } + + printf ("\tuint16_t mask = %s;\n", gen_nextiword ()); + printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n"); + printf ("\tretcycles = 0;\n"); + genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1); + start_brace (); + printf ("\twhile (dmask) { m68k_dreg(regs, movem_index1[dmask]) = %s;" + " srca += %d; dmask = movem_next[dmask]; retcycles+=%d; }\n", + getcode, size, (bMovemLong ? 8 : 4)); + printf ("\twhile (amask) { m68k_areg(regs, movem_index1[amask]) = %s;" + " srca += %d; amask = movem_next[amask]; retcycles+=%d; }\n", + getcode, size, (bMovemLong ? 8 : 4)); + + if (table68k[opcode].dmode == Aipi) + printf ("\tm68k_areg(regs, dstreg) = srca;\n"); + + /* Better cycles - experimental! (Thothy) */ + switch(table68k[opcode].dmode) + { + case Aind: insn_n_cycles=12; break; + case Aipi: insn_n_cycles=12; break; + case Ad16: insn_n_cycles=16; break; + case Ad8r: insn_n_cycles=18; break; + case absw: insn_n_cycles=16; break; + case absl: insn_n_cycles=20; break; + case PC16: insn_n_cycles=16; break; + case PC8r: insn_n_cycles=18; break; + } + sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles); +} + +static void genmovemle (uint16_t opcode) +{ + char putcode[100]; + int bMovemLong = (table68k[opcode].size == sz_long); + int size = bMovemLong ? 4 : 2; + + if (bMovemLong) { + strcpy (putcode, "m68k_write_memory_32(srca,"); + } else { + strcpy (putcode, "m68k_write_memory_16(srca,"); + } + + printf ("\tuint16_t mask = %s;\n", gen_nextiword ()); + printf ("\tretcycles = 0;\n"); + genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1); + if (using_prefetch) + sync_m68k_pc (); + + start_brace (); + if (table68k[opcode].dmode == Apdi) { + printf ("\tuint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n"); + printf ("\twhile (amask) { srca -= %d; %s m68k_areg(regs, movem_index2[amask]));" + " amask = movem_next[amask]; retcycles+=%d; }\n", + size, putcode, (bMovemLong ? 8 : 4)); + printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg(regs, movem_index2[dmask]));" + " dmask = movem_next[dmask]; retcycles+=%d; }\n", + size, putcode, (bMovemLong ? 8 : 4)); + printf ("\tm68k_areg(regs, dstreg) = srca;\n"); + } else { + printf ("\tuint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n"); + printf ("\twhile (dmask) { %s m68k_dreg(regs, movem_index1[dmask])); srca += %d;" + " dmask = movem_next[dmask]; retcycles+=%d; }\n", + putcode, size, (bMovemLong ? 8 : 4)); + printf ("\twhile (amask) { %s m68k_areg(regs, movem_index1[amask])); srca += %d;" + " amask = movem_next[amask]; retcycles+=%d; }\n", + putcode, size, (bMovemLong ? 8 : 4)); + } + + /* Better cycles - experimental! (Thothy) */ + switch(table68k[opcode].dmode) + { + case Aind: insn_n_cycles=8; break; + case Apdi: insn_n_cycles=8; break; + case Ad16: insn_n_cycles=12; break; + case Ad8r: insn_n_cycles=14; break; + case absw: insn_n_cycles=12; break; + case absl: insn_n_cycles=16; break; + } + sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles); +} + + +static void duplicate_carry (void) +{ + printf ("\tCOPY_CARRY;\n"); +} + +typedef enum +{ + flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn, + flag_av, flag_sv +} +flagtypes; + +static void genflags_normal (flagtypes type, wordsizes size, const char *value, + const char *src, const char *dst) +{ + char vstr[100], sstr[100], dstr[100]; + char usstr[100], udstr[100]; + char unsstr[100], undstr[100]; + + switch (size) { + case sz_byte: + strcpy (vstr, "((int8_t)("); + strcpy (usstr, "((uint8_t)("); + break; + case sz_word: + strcpy (vstr, "((int16_t)("); + strcpy (usstr, "((uint16_t)("); + break; + case sz_long: + strcpy (vstr, "((int32_t)("); + strcpy (usstr, "((uint32_t)("); + break; + default: + abort (); + } + strcpy (unsstr, usstr); + + strcpy (sstr, vstr); + strcpy (dstr, vstr); + strcat (vstr, value); + strcat (vstr, "))"); + strcat (dstr, dst); + strcat (dstr, "))"); + strcat (sstr, src); + strcat (sstr, "))"); + + strcpy (udstr, usstr); + strcat (udstr, dst); + strcat (udstr, "))"); + strcat (usstr, src); + strcat (usstr, "))"); + + strcpy (undstr, unsstr); + strcat (unsstr, "-"); + strcat (undstr, "~"); + strcat (undstr, dst); + strcat (undstr, "))"); + strcat (unsstr, src); + strcat (unsstr, "))"); + + switch (type) { + case flag_logical_noclobber: + case flag_logical: + case flag_zn: + case flag_av: + case flag_sv: + case flag_addx: + case flag_subx: + break; + + case flag_add: + start_brace (); + printf ("uint32_t %s = %s + %s;\n", value, dstr, sstr); + break; + case flag_sub: + case flag_cmp: + start_brace (); + printf ("uint32_t %s = %s - %s;\n", value, dstr, sstr); + break; + } + + switch (type) { + case flag_logical_noclobber: + case flag_logical: + case flag_zn: + break; + + case flag_add: + case flag_sub: + case flag_addx: + case flag_subx: + case flag_cmp: + case flag_av: + case flag_sv: + start_brace (); + printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr); + printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr); + printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr); + break; + } + + switch (type) { + case flag_logical: + printf ("\tCLEAR_CZNV;\n"); + printf ("\tSET_ZFLG (%s == 0);\n", vstr); + printf ("\tSET_NFLG (%s < 0);\n", vstr); + break; + case flag_logical_noclobber: + printf ("\tSET_ZFLG (%s == 0);\n", vstr); + printf ("\tSET_NFLG (%s < 0);\n", vstr); + break; + case flag_av: + printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); + break; + case flag_sv: + printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n"); + break; + case flag_zn: + printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr); + printf ("\tSET_NFLG (%s < 0);\n", vstr); + break; + case flag_add: + printf ("\tSET_ZFLG (%s == 0);\n", vstr); + printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); + printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr); + duplicate_carry (); + printf ("\tSET_NFLG (flgn != 0);\n"); + break; + case flag_sub: + printf ("\tSET_ZFLG (%s == 0);\n", vstr); + printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n"); + printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr); + duplicate_carry (); + printf ("\tSET_NFLG (flgn != 0);\n"); + break; + case flag_addx: + printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */ + printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */ + duplicate_carry (); + break; + case flag_subx: + printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */ + printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */ + duplicate_carry (); + break; + case flag_cmp: + printf ("\tSET_ZFLG (%s == 0);\n", vstr); + printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n"); + printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr); + printf ("\tSET_NFLG (flgn != 0);\n"); + break; + } +} + +static void genflags (flagtypes type, wordsizes size, const char *value, + const char *src, const char *dst) +{ + /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have + them in the appropriate m68k.h files and use just one copy of this + code here. The API can be changed if necessary. */ +#ifdef OPTIMIZED_FLAGS + switch (type) { + case flag_add: + case flag_sub: + start_brace (); + printf ("\tuint32_t %s;\n", value); + break; + + default: + break; + } + + /* At least some of those casts are fairly important! */ + switch (type) { + case flag_logical_noclobber: + printf ("\t{uint32_t oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n"); + if (strcmp (value, "0") == 0) { + printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n"); + } else { + switch (size) { + case sz_byte: printf ("\toptflag_testb ((int8_t)(%s));\n", value); break; + case sz_word: printf ("\toptflag_testw ((int16_t)(%s));\n", value); break; + case sz_long: printf ("\toptflag_testl ((int32_t)(%s));\n", value); break; + } + printf ("\tIOR_CZNV (oldcznv);\n"); + } + printf ("\t}\n"); + return; + case flag_logical: + if (strcmp (value, "0") == 0) { + printf ("\tSET_CZNV (FLAGVAL_Z);\n"); + } else { + switch (size) { + case sz_byte: printf ("\toptflag_testb ((int8_t)(%s));\n", value); break; + case sz_word: printf ("\toptflag_testw ((int16_t)(%s));\n", value); break; + case sz_long: printf ("\toptflag_testl ((int32_t)(%s));\n", value); break; + } + } + return; + + case flag_add: + switch (size) { + case sz_byte: printf ("\toptflag_addb (%s, (int8_t)(%s), (int8_t)(%s));\n", value, src, dst); break; + case sz_word: printf ("\toptflag_addw (%s, (int16_t)(%s), (int16_t)(%s));\n", value, src, dst); break; + case sz_long: printf ("\toptflag_addl (%s, (int32_t)(%s), (int32_t)(%s));\n", value, src, dst); break; + } + return; + + case flag_sub: + switch (size) { + case sz_byte: printf ("\toptflag_subb (%s, (int8_t)(%s), (int8_t)(%s));\n", value, src, dst); break; + case sz_word: printf ("\toptflag_subw (%s, (int16_t)(%s), (int16_t)(%s));\n", value, src, dst); break; + case sz_long: printf ("\toptflag_subl (%s, (int32_t)(%s), (int32_t)(%s));\n", value, src, dst); break; + } + return; + + case flag_cmp: + switch (size) { + case sz_byte: printf ("\toptflag_cmpb ((int8_t)(%s), (int8_t)(%s));\n", src, dst); break; + case sz_word: printf ("\toptflag_cmpw ((int16_t)(%s), (int16_t)(%s));\n", src, dst); break; + case sz_long: printf ("\toptflag_cmpl ((int32_t)(%s), (int32_t)(%s));\n", src, dst); break; + } + return; + + default: + break; + } +#endif + + genflags_normal (type, size, value, src, dst); +} + +static void force_range_for_rox (const char *var, wordsizes size) +{ + /* Could do a modulo operation here... which one is faster? */ + switch (size) { + case sz_long: + printf ("\tif (%s >= 33) %s -= 33;\n", var, var); + break; + case sz_word: + printf ("\tif (%s >= 34) %s -= 34;\n", var, var); + printf ("\tif (%s >= 17) %s -= 17;\n", var, var); + break; + case sz_byte: + printf ("\tif (%s >= 36) %s -= 36;\n", var, var); + printf ("\tif (%s >= 18) %s -= 18;\n", var, var); + printf ("\tif (%s >= 9) %s -= 9;\n", var, var); + break; + } +} + +static const char *cmask (wordsizes size) +{ + switch (size) { + case sz_byte: return "0x80"; + case sz_word: return "0x8000"; + case sz_long: return "0x80000000"; + default: abort (); + } +} + +static int source_is_imm1_8 (struct instr *i) +{ + return i->stype == 3; +} + + + +static void gen_opcode (unsigned long int opcode) +{ +#if 0 + char *amodenames[] = { "Dreg", "Areg", "Aind", "Aipi", "Apdi", "Ad16", "Ad8r", + "absw", "absl", "PC16", "PC8r", "imm", "imm0", "imm1", "imm2", "immi", "am_unknown", "am_illg"}; +#endif + + struct instr *curi = table68k + opcode; + insn_n_cycles = 4; + + /* Store the family of the instruction (used to check for pairing on ST) + * and leave some space for patching in the current cycles later */ + printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo); + nCurInstrCycPos = ftell(stdout) - 5; + + start_brace (); + m68k_pc_offset = 2; + + switch (curi->plev) { + case 0: /* not privileged */ + break; + case 1: /* unprivileged only on 68000 */ + if (cpu_level == 0) + break; + if (next_cpu_level < 0) + next_cpu_level = 0; + + /* fall through */ + case 2: /* priviledged */ + printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + need_endlabel = 1; + start_brace (); + break; + case 3: /* privileged if size == word */ + if (curi->size == sz_byte) + break; + printf ("if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + need_endlabel = 1; + start_brace (); + break; + } + + /* Build the opcodes: */ + switch (curi->mnemo) { + case i_OR: + case i_AND: + case i_EOR: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^'); + genflags (flag_logical, curi->size, "src", "", ""); + genastore ("src", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->size==sz_long && curi->dmode==Dreg) + { + insn_n_cycles += 2; + if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi)) + insn_n_cycles += 2; + } +#if 0 + /* Output the CPU cycles: */ + fprintf(stderr,"MOVE, size %i: ",curi->size); + fprintf(stderr," %s ->",amodenames[curi->smode]); + fprintf(stderr," %s ",amodenames[curi->dmode]); + fprintf(stderr," Cycles: %i\n",insn_n_cycles); +#endif + break; + case i_ORSR: + case i_EORSR: + printf ("\tMakeSR();\n"); + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + if (curi->size == sz_byte) { + printf ("\tsrc &= 0xFF;\n"); + } + printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|'); + printf ("\tMakeFromSR();\n"); + insn_n_cycles = 20; + break; + case i_ANDSR: + printf ("\tMakeSR();\n"); + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + if (curi->size == sz_byte) { + printf ("\tsrc |= 0xFF00;\n"); + } + printf ("\tregs.sr &= src;\n"); + printf ("\tMakeFromSR();\n"); + insn_n_cycles = 20; + break; + case i_SUB: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + genflags (flag_sub, curi->size, "newv", "src", "dst"); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->size==sz_long && curi->dmode==Dreg) + { + insn_n_cycles += 2; + if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi)) + insn_n_cycles += 2; + } + break; + case i_SUBA: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = dst - src;\n"); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi)) + insn_n_cycles += 2; + else + insn_n_cycles += 4; + break; + case i_SUBX: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = dst - src - (GET_XFLG ? 1 : 0);\n"); + genflags (flag_subx, curi->size, "newv", "src", "dst"); + genflags (flag_zn, curi->size, "newv", "", ""); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->smode==Dreg && curi->size==sz_long) + insn_n_cycles=8; + if(curi->smode==Apdi) + { + if(curi->size==sz_long) + insn_n_cycles=30; + else + insn_n_cycles=18; + } + break; + case i_SBCD: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf ("\tuint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuint16_t newv_hi = (dst & 0xF0) - (src & 0xF0);\n"); + printf ("\tuint16_t newv, tmp_newv;\n"); + printf ("\tint bcd = 0;\n"); + printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n"); + printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n"); + printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n"); + printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n"); + duplicate_carry (); + genflags (flag_zn, curi->size, "newv", "", ""); + printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n"); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->smode==Dreg) insn_n_cycles=6; + if(curi->smode==Apdi) insn_n_cycles=18; + break; + case i_ADD: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf("\trefill_prefetch (m68k_getpc(), 2);\n"); // FIXME [NP] For Transbeauce 2 demo, need better prefetch emulation + genflags (flag_add, curi->size, "newv", "src", "dst"); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->size==sz_long && curi->dmode==Dreg) + { + insn_n_cycles += 2; + if(curi->smode==Dreg || curi->smode==Areg || (curi->smode>=imm && curi->smode<=immi)) + insn_n_cycles += 2; + } + break; + case i_ADDA: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = dst + src;\n"); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + if(curi->size==sz_long && curi->smode!=Dreg && curi->smode!=Areg && !(curi->smode>=imm && curi->smode<=immi)) + insn_n_cycles += 2; + else + insn_n_cycles += 4; + break; + case i_ADDX: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = dst + src + (GET_XFLG ? 1 : 0);\n"); + genflags (flag_addx, curi->size, "newv", "src", "dst"); + genflags (flag_zn, curi->size, "newv", "", ""); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->smode==Dreg && curi->size==sz_long) + insn_n_cycles=8; + if(curi->smode==Apdi) + { + if(curi->size==sz_long) + insn_n_cycles=30; + else + insn_n_cycles=18; + } + break; + case i_ABCD: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf ("\tuint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n"); + printf ("\tuint16_t newv_hi = (src & 0xF0) + (dst & 0xF0);\n"); + printf ("\tuint16_t newv, tmp_newv;\n"); + printf ("\tint cflg;\n"); + printf ("\tnewv = tmp_newv = newv_hi + newv_lo;"); + printf ("\tif (newv_lo > 9) { newv += 6; }\n"); + printf ("\tcflg = (newv & 0x3F0) > 0x90;\n"); + printf ("\tif (cflg) newv += 0x60;\n"); + printf ("\tSET_CFLG (cflg);\n"); + duplicate_carry (); + genflags (flag_zn, curi->size, "newv", "", ""); + printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n"); + genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->smode==Dreg) insn_n_cycles=6; + if(curi->smode==Apdi) insn_n_cycles=18; + break; + case i_NEG: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + genflags (flag_sub, curi->size, "dst", "src", "0"); + genastore ("dst", curi->smode, "srcreg", curi->size, "src"); + if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2; + break; + case i_NEGX: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + printf ("\tuint32_t newv = 0 - src - (GET_XFLG ? 1 : 0);\n"); + genflags (flag_subx, curi->size, "newv", "src", "0"); + genflags (flag_zn, curi->size, "newv", "", ""); + genastore ("newv", curi->smode, "srcreg", curi->size, "src"); + if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2; + break; + case i_NBCD: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + printf ("\tuint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuint16_t newv_hi = - (src & 0xF0);\n"); + printf ("\tuint16_t newv;\n"); + printf ("\tint cflg;\n"); + printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n"); + printf ("\tnewv = newv_hi + newv_lo;"); + printf ("\tcflg = (newv & 0x1F0) > 0x90;\n"); + printf ("\tif (cflg) newv -= 0x60;\n"); + printf ("\tSET_CFLG (cflg);\n"); + duplicate_carry(); + genflags (flag_zn, curi->size, "newv", "", ""); + genastore ("newv", curi->smode, "srcreg", curi->size, "src"); + if(curi->smode==Dreg) insn_n_cycles += 2; + break; + case i_CLR: + genamode (curi->smode, "srcreg", curi->size, "src", 2, 0); + + /* [NP] CLR does a read before the write only on 68000 */ + /* but there's no cycle penalty for doing the read */ + if ( curi->smode != Dreg ) // only if destination is memory + { + if (curi->size==sz_byte) + printf ("\tint8_t src = m68k_read_memory_8(srca);\n"); + else if (curi->size==sz_word) + printf ("\tint16_t src = m68k_read_memory_16(srca);\n"); + else if (curi->size==sz_long) + printf ("\tint32_t src = m68k_read_memory_32(srca);\n"); + } + + genflags (flag_logical, curi->size, "0", "", ""); + genastore ("0", curi->smode, "srcreg", curi->size, "src"); + if(curi->size==sz_long) + { + if(curi->smode==Dreg) + insn_n_cycles += 2; + else + insn_n_cycles += 4; + } + if(curi->smode!=Dreg) + insn_n_cycles += 4; + break; + case i_NOT: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + printf ("\tuint32_t dst = ~src;\n"); + genflags (flag_logical, curi->size, "dst", "", ""); + genastore ("dst", curi->smode, "srcreg", curi->size, "src"); + if(curi->size==sz_long && curi->smode==Dreg) insn_n_cycles += 2; + break; + case i_TST: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genflags (flag_logical, curi->size, "src", "", ""); + break; + case i_BTST: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + if (curi->size == sz_byte) + printf ("\tsrc &= 7;\n"); + else + printf ("\tsrc &= 31;\n"); + printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n"); + if(curi->dmode==Dreg) insn_n_cycles += 2; + break; + case i_BCHG: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + if (curi->size == sz_byte) + printf ("\tsrc &= 7;\n"); + else + printf ("\tsrc &= 31;\n"); + printf ("\tdst ^= (1 << src);\n"); + printf ("\tSET_ZFLG (((uint32_t)dst & (1 << src)) >> src);\n"); + genastore ("dst", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->dmode==Dreg) insn_n_cycles += 4; + break; + case i_BCLR: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + if (curi->size == sz_byte) + printf ("\tsrc &= 7;\n"); + else + printf ("\tsrc &= 31;\n"); + printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n"); + printf ("\tdst &= ~(1 << src);\n"); + genastore ("dst", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->dmode==Dreg) insn_n_cycles += 6; + /* [NP] BCLR #n,Dx takes 12 cycles instead of 14 if n<16 */ + if((curi->smode==imm1) && (curi->dmode==Dreg)) + printf ("\tif ( src < 16 ) { m68k_incpc(4); return 12; }\n"); + /* [NP] BCLR Dy,Dx takes 8 cycles instead of 10 if Dy<16 */ + if((curi->smode==Dreg) && (curi->dmode==Dreg)) + printf ("\tif ( src < 16 ) { m68k_incpc(2); return 8; }\n"); + break; + case i_BSET: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + if (curi->size == sz_byte) + printf ("\tsrc &= 7;\n"); + else + printf ("\tsrc &= 31;\n"); + printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n"); + printf ("\tdst |= (1 << src);\n"); + genastore ("dst", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->dmode==Dreg) insn_n_cycles += 4; + break; + case i_CMPM: + case i_CMP: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + genflags (flag_cmp, curi->size, "newv", "src", "dst"); + if(curi->size==sz_long && curi->dmode==Dreg) + insn_n_cycles += 2; + break; + case i_CMPA: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0); + start_brace (); + genflags (flag_cmp, sz_long, "newv", "src", "dst"); + insn_n_cycles += 2; + break; + /* The next two are coded a little unconventional, but they are doing + * weird things... */ + case i_MVPRM: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + + printf ("\tuint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)%s;\n", gen_nextiword ()); + if (curi->size == sz_word) { + printf ("\tm68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src);\n"); + } else { + printf ("\tm68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16);\n"); + printf ("\tm68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src);\n"); + } + if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16; + break; + case i_MVPMR: + printf ("\tuint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)%s;\n", gen_nextiword ()); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + if (curi->size == sz_word) { + printf ("\tuint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2);\n"); + } else { + printf ("\tuint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16)\n"); + printf (" + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6);\n"); + } + genastore ("val", curi->dmode, "dstreg", curi->size, "dst"); + if(curi->size==sz_long) insn_n_cycles=24; else insn_n_cycles=16; + break; + case i_MOVE: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + + /* [NP] genamode counts 2 cycles if dest is -(An), this is wrong. */ + /* For move dest (An), (An)+ and -(An) take the same time */ + /* (for other instr, dest -(An) really takes 2 cycles more) */ + if ( curi->dmode == Apdi ) + insn_n_cycles -= 2; /* correct the wrong cycle count for -(An) */ + + genflags (flag_logical, curi->size, "src", "", ""); + genastore ("src", curi->dmode, "dstreg", curi->size, "dst"); + break; + case i_MOVEA: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + if (curi->size == sz_word) { + printf ("\tuint32_t val = (int32_t)(int16_t)src;\n"); + } else { + printf ("\tuint32_t val = src;\n"); + } + genastore ("val", curi->dmode, "dstreg", sz_long, "dst"); + break; + case i_MVSR2: /* Move from SR */ + genamode (curi->smode, "srcreg", sz_word, "src", 2, 0); + printf ("\tMakeSR();\n"); + if (curi->size == sz_byte) + genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src"); + else + genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src"); + if (curi->smode==Dreg) insn_n_cycles += 2; else insn_n_cycles += 4; + break; + case i_MV2SR: /* Move to SR */ + genamode (curi->smode, "srcreg", sz_word, "src", 1, 0); + if (curi->size == sz_byte) + printf ("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n"); + else { + printf ("\tregs.sr = src;\n"); + } + printf ("\tMakeFromSR();\n"); + insn_n_cycles += 8; + break; + case i_SWAP: + genamode (curi->smode, "srcreg", sz_long, "src", 1, 0); + start_brace (); + printf ("\tuint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n"); + genflags (flag_logical, sz_long, "dst", "", ""); + genastore ("dst", curi->smode, "srcreg", sz_long, "src"); + break; + case i_EXG: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + genastore ("dst", curi->smode, "srcreg", curi->size, "src"); + genastore ("src", curi->dmode, "dstreg", curi->size, "dst"); + insn_n_cycles = 6; + break; + case i_EXT: + genamode (curi->smode, "srcreg", sz_long, "src", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t dst = (int32_t)(int8_t)src;\n"); break; + case sz_word: printf ("\tuint16_t dst = (int16_t)(int8_t)src;\n"); break; + case sz_long: printf ("\tuint32_t dst = (int32_t)(int16_t)src;\n"); break; + default: abort (); + } + genflags (flag_logical, + curi->size == sz_word ? sz_word : sz_long, "dst", "", ""); + genastore ("dst", curi->smode, "srcreg", + curi->size == sz_word ? sz_word : sz_long, "src"); + break; + case i_MVMEL: + genmovemel (opcode); + break; + case i_MVMLE: + genmovemle (opcode); + break; + case i_TRAP: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + sync_m68k_pc (); + printf ("\tException(src+32,0,M68000_EXC_SRC_CPU);\n"); + m68k_pc_offset = 0; + break; + case i_MVR2USP: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + printf ("\tregs.usp = src;\n"); + break; + case i_MVUSP2R: + genamode (curi->smode, "srcreg", curi->size, "src", 2, 0); + genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src"); + break; + case i_RESET: +//JLH:Not needed printf ("\tcustomreset();\n"); + insn_n_cycles = 132; /* I am not so sure about this!? - Thothy */ + break; + case i_NOP: + break; + case i_STOP: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + printf ("\tregs.sr = src;\n"); + printf ("\tMakeFromSR();\n"); + printf ("\tm68k_setstopped(1);\n"); + insn_n_cycles = 4; + break; + case i_RTE: + if (cpu_level == 0) { + genamode (Aipi, "7", sz_word, "sr", 1, 0); + genamode (Aipi, "7", sz_long, "pc", 1, 0); + printf ("\tregs.sr = sr; m68k_setpc_rte(pc);\n"); + fill_prefetch_0 (); + printf ("\tMakeFromSR();\n"); + } else { + int old_brace_level = n_braces; + if (next_cpu_level < 0) + next_cpu_level = 0; + printf ("\tuint16_t newsr; uint32_t newpc; for (;;) {\n"); + genamode (Aipi, "7", sz_word, "sr", 1, 0); + genamode (Aipi, "7", sz_long, "pc", 1, 0); + genamode (Aipi, "7", sz_word, "format", 1, 0); + printf ("\tnewsr = sr; newpc = pc;\n"); + printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n"); + printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n"); + printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n"); + printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n"); + printf ("\telse if ((format & 0xF000) == 0x9000) { m68k_areg(regs, 7) += 12; break; }\n"); + printf ("\telse if ((format & 0xF000) == 0xa000) { m68k_areg(regs, 7) += 24; break; }\n"); + printf ("\telse if ((format & 0xF000) == 0xb000) { m68k_areg(regs, 7) += 84; break; }\n"); + printf ("\telse { Exception(14,0,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + printf ("\tregs.sr = newsr; MakeFromSR();\n}\n"); + pop_braces (old_brace_level); + printf ("\tregs.sr = newsr; MakeFromSR();\n"); + printf ("\tm68k_setpc_rte(newpc);\n"); + fill_prefetch_0 (); + need_endlabel = 1; + } + /* PC is set and prefetch filled. */ + m68k_pc_offset = 0; + insn_n_cycles = 20; + break; + case i_RTD: + genamode (Aipi, "7", sz_long, "pc", 1, 0); + genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0); + printf ("\tm68k_areg(regs, 7) += offs;\n"); + printf ("\tm68k_setpc_rte(pc);\n"); + fill_prefetch_0 (); + /* PC is set and prefetch filled. */ + m68k_pc_offset = 0; + break; + case i_LINK: + genamode (Apdi, "7", sz_long, "old", 2, 0); + genamode (curi->smode, "srcreg", sz_long, "src", 1, 0); + genastore ("src", Apdi, "7", sz_long, "old"); + genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src"); + genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0); + printf ("\tm68k_areg(regs, 7) += offs;\n"); + break; + case i_UNLK: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + printf ("\tm68k_areg(regs, 7) = src;\n"); + genamode (Aipi, "7", sz_long, "old", 1, 0); + genastore ("old", curi->smode, "srcreg", curi->size, "src"); + break; + case i_RTS: + printf ("\tm68k_do_rts();\n"); + fill_prefetch_0 (); + m68k_pc_offset = 0; + insn_n_cycles = 16; + break; + case i_TRAPV: + sync_m68k_pc (); + printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + need_endlabel = 1; + break; + case i_RTR: + printf ("\tMakeSR();\n"); + genamode (Aipi, "7", sz_word, "sr", 1, 0); + genamode (Aipi, "7", sz_long, "pc", 1, 0); + printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n"); + printf ("\tregs.sr |= sr; m68k_setpc(pc);\n"); + fill_prefetch_0 (); + printf ("\tMakeFromSR();\n"); + m68k_pc_offset = 0; + insn_n_cycles = 20; + break; + case i_JSR: + genamode (curi->smode, "srcreg", curi->size, "src", 0, 0); + printf ("\tuint32_t oldpc = m68k_getpc () + %d;\n", m68k_pc_offset); + if (using_exception_3) { + printf ("\tif (srca & 1) {\n"); + printf ("\t\tlast_addr_for_exception_3 = oldpc;\n"); + printf ("\t\tlast_fault_for_exception_3 = srca;\n"); + printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + printf ("\t}\n"); + need_endlabel = 1; + } + printf ("\tm68k_do_jsr(m68k_getpc() + %d, srca);\n", m68k_pc_offset); + fill_prefetch_0 (); + m68k_pc_offset = 0; + switch(curi->smode) + { + case Aind: insn_n_cycles=16; break; + case Ad16: insn_n_cycles=18; break; + case Ad8r: insn_n_cycles=22; break; + case absw: insn_n_cycles=18; break; + case absl: insn_n_cycles=20; break; + case PC16: insn_n_cycles=18; break; + case PC8r: insn_n_cycles=22; break; + } + break; + case i_JMP: + genamode (curi->smode, "srcreg", curi->size, "src", 0, 0); + if (using_exception_3) { + printf ("\tif (srca & 1) {\n"); + printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 6;\n"); + printf ("\t\tlast_fault_for_exception_3 = srca;\n"); + printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + printf ("\t}\n"); + need_endlabel = 1; + } + printf ("\tm68k_setpc(srca);\n"); + fill_prefetch_0 (); + m68k_pc_offset = 0; + switch(curi->smode) + { + case Aind: insn_n_cycles=8; break; + case Ad16: insn_n_cycles=10; break; + case Ad8r: insn_n_cycles=14; break; + case absw: insn_n_cycles=10; break; + case absl: insn_n_cycles=12; break; + case PC16: insn_n_cycles=10; break; + case PC8r: insn_n_cycles=14; break; + } + break; + case i_BSR: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + printf ("\tint32_t s = (int32_t)src + 2;\n"); + if (using_exception_3) { + printf ("\tif (src & 1) {\n"); + printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ? + printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + s;\n"); + printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + printf ("\t}\n"); + need_endlabel = 1; + } + printf ("\tm68k_do_bsr(m68k_getpc() + %d, s);\n", m68k_pc_offset); + fill_prefetch_0 (); + m68k_pc_offset = 0; + insn_n_cycles = 18; + break; + case i_Bcc: + if (curi->size == sz_long) { + if (cpu_level < 2) { + printf ("\tm68k_incpc(2);\n"); + printf ("\tif (!cctrue(%d)) goto %s;\n", curi->cc, endlabelstr); + printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); + printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 1;\n"); + printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + need_endlabel = 1; + } else { + if (next_cpu_level < 1) + next_cpu_level = 1; + } + } + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + printf ("\tif (!cctrue(%d)) goto didnt_jump;\n", curi->cc); + if (using_exception_3) { + printf ("\tif (src & 1) {\n"); + printf ("\t\tlast_addr_for_exception_3 = m68k_getpc() + 2;\n"); // [NP] FIXME should be +4, not +2 (same as DBcc) ? + printf ("\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src;\n"); + printf ("\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + printf ("\t}\n"); + need_endlabel = 1; + } + printf ("\tm68k_incpc ((int32_t)src + 2);\n"); + fill_prefetch_0 (); + printf ("\treturn 10;\n"); + printf ("didnt_jump:;\n"); + need_endlabel = 1; + insn_n_cycles = (curi->size == sz_byte) ? 8 : 12; + break; + case i_LEA: + genamode (curi->smode, "srcreg", curi->size, "src", 0, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + genastore ("srca", curi->dmode, "dstreg", curi->size, "dst"); + /* Set correct cycles: According to the M68K User Manual, LEA takes 12 + * cycles in Ad8r and PC8r mode, but it takes 14 (or 16) cycles on a real ST: */ + if (curi->smode == Ad8r || curi->smode == PC8r) + insn_n_cycles = 14; + break; + case i_PEA: + genamode (curi->smode, "srcreg", curi->size, "src", 0, 0); + genamode (Apdi, "7", sz_long, "dst", 2, 0); + genastore ("srca", Apdi, "7", sz_long, "dst"); + /* Set correct cycles: */ + switch(curi->smode) + { + case Aind: insn_n_cycles=12; break; + case Ad16: insn_n_cycles=16; break; + /* Note: according to the M68K User Manual, PEA takes 20 cycles for + * the Ad8r mode, but on a real ST, it takes 22 (or 24) cycles! */ + case Ad8r: insn_n_cycles=22; break; + case absw: insn_n_cycles=16; break; + case absl: insn_n_cycles=20; break; + case PC16: insn_n_cycles=16; break; + /* Note: PEA with PC8r takes 20 cycles according to the User Manual, + * but it takes 22 (or 24) cycles on a real ST: */ + case PC8r: insn_n_cycles=22; break; + } + break; + case i_DBcc: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0); + + printf ("\tif (!cctrue(%d)) {\n\t", curi->cc); + genastore ("(src-1)", curi->smode, "srcreg", curi->size, "src"); + + printf ("\t\tif (src) {\n"); + if (using_exception_3) { + printf ("\t\t\tif (offs & 1) {\n"); + printf ("\t\t\tlast_addr_for_exception_3 = m68k_getpc() + 2 + 2;\n"); // [NP] last_addr is pc+4, not pc+2 + printf ("\t\t\tlast_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2;\n"); + printf ("\t\t\tlast_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto %s;\n", endlabelstr); + printf ("\t\t}\n"); + need_endlabel = 1; + } + printf ("\t\t\tm68k_incpc((int32_t)offs + 2);\n"); + fill_prefetch_0 (); + printf ("\t\t\treturn 10;\n"); + printf ("\t\t} else {\n\t\t\t"); + { + int tmp_offset = m68k_pc_offset; + sync_m68k_pc(); /* not so nice to call it here... */ + m68k_pc_offset = tmp_offset; + } + printf ("\t\t\treturn 14;\n"); + printf ("\t\t}\n"); + printf ("\t}\n"); + insn_n_cycles = 12; + need_endlabel = 1; + break; + case i_Scc: + genamode (curi->smode, "srcreg", curi->size, "src", 2, 0); + start_brace (); + printf ("\tint val = cctrue(%d) ? 0xff : 0;\n", curi->cc); + genastore ("val", curi->smode, "srcreg", curi->size, "src"); + if (curi->smode!=Dreg) insn_n_cycles += 4; + else + { /* [NP] if result is TRUE, we return 6 instead of 4 */ + printf ("\tif (val) { m68k_incpc(2) ; return 4+2; }\n"); + } + break; + case i_DIVU: + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + genamode (curi->smode, "srcreg", sz_word, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0); + sync_m68k_pc (); + /* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends + * on this (actually, it's doing a DIVS). */ + printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr); + printf ("\tuint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src;\n"); + printf ("\tuint32_t rem = (uint32_t)dst %% (uint32_t)(uint16_t)src;\n"); + /* The N flag appears to be set each time there is an overflow. + * Weird. */ + printf ("\tif (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n"); + genflags (flag_logical, sz_word, "newv", "", ""); + printf ("\tnewv = (newv & 0xffff) | ((uint32_t)rem << 16);\n"); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + printf ("\t}\n"); + printf ("\t}\n"); +// insn_n_cycles += 136; + printf ("\tretcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src);\n"); + sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles); + need_endlabel = 1; + break; + case i_DIVS: + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + genamode (curi->smode, "srcreg", sz_word, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0); + sync_m68k_pc (); + printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto %s; } else {\n", endlabelstr); + printf ("\tint32_t newv = (int32_t)dst / (int32_t)(int16_t)src;\n"); + printf ("\tuint16_t rem = (int32_t)dst %% (int32_t)(int16_t)src;\n"); + printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n"); + printf ("\tif (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem;\n"); + genflags (flag_logical, sz_word, "newv", "", ""); + printf ("\tnewv = (newv & 0xffff) | ((uint32_t)rem << 16);\n"); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + printf ("\t}\n"); + printf ("\t}\n"); +// insn_n_cycles += 154; + printf ("\tretcycles = getDivs68kCycles((int32_t)dst, (int16_t)src);\n"); + sprintf(exactCpuCycles," return (%i+retcycles);", insn_n_cycles); + need_endlabel = 1; + break; + case i_MULU: + genamode (curi->smode, "srcreg", sz_word, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src;\n"); + genflags (flag_logical, sz_long, "newv", "", ""); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 1 bits in src */ + insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */ + printf ("\twhile (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; }\n"); + sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles); + break; + case i_MULS: + genamode (curi->smode, "srcreg", sz_word, "src", 1, 0); + genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0); + start_brace (); + printf ("\tuint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src;\n"); + printf ("\tuint32_t src2;\n"); + genflags (flag_logical, sz_long, "newv", "", ""); + genastore ("newv", curi->dmode, "dstreg", sz_long, "dst"); + /* [NP] number of cycles is 38 + 2n + ea time ; n is the number of 01 or 10 patterns in src expanded to 17 bits */ + insn_n_cycles += 38-4; /* insn_n_cycles is already initialized to 4 instead of 0 */ + printf ("\tsrc2 = ((uint32_t)src) << 1;\n"); + printf ("\twhile (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; }\n"); + sprintf(exactCpuCycles," return (%i+retcycles*2);", insn_n_cycles); + break; + case i_CHK: + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + sync_m68k_pc (); + printf ("\tif ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + printf ("\telse if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr); + need_endlabel = 1; + insn_n_cycles += 6; + break; + + case i_CHK2: + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + printf ("\t{int32_t upper,lower,reg = regs.regs[(extra >> 12) & 15];\n"); + switch (curi->size) { + case sz_byte: + printf ("\tlower=(int32_t)(int8_t)m68k_read_memory_8(dsta); upper = (int32_t)(int8_t)m68k_read_memory_8(dsta+1);\n"); + printf ("\tif ((extra & 0x8000) == 0) reg = (int32_t)(int8_t)reg;\n"); + break; + case sz_word: + printf ("\tlower=(int32_t)(int16_t)m68k_read_memory_16(dsta); upper = (int32_t)(int16_t)m68k_read_memory_16(dsta+2);\n"); + printf ("\tif ((extra & 0x8000) == 0) reg = (int32_t)(int16_t)reg;\n"); + break; + case sz_long: + printf ("\tlower=m68k_read_memory_32(dsta); upper = m68k_read_memory_32(dsta+4);\n"); + break; + default: + abort (); + } + printf ("\tSET_ZFLG (upper == reg || lower == reg);\n"); + printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n"); + sync_m68k_pc (); + printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc,M68000_EXC_SRC_CPU); goto %s; }\n}\n", endlabelstr); + need_endlabel = 1; + break; + + case i_ASR: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1); + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); + printf ("\t\tval = %s & (uint32_t)-sign;\n", bit_mask (curi->size)); + printf ("\t\tSET_CFLG (sign);\n"); + duplicate_carry (); + if (source_is_imm1_8 (curi)) + printf ("\t} else {\n"); + else + printf ("\t} else if (cnt > 0) {\n"); + printf ("\t\tval >>= cnt - 1;\n"); + printf ("\t\tSET_CFLG (val & 1);\n"); + duplicate_carry (); + printf ("\t\tval >>= 1;\n"); + printf ("\t\tval |= (%s << (%d - cnt)) & (uint32_t)-sign;\n", + bit_mask (curi->size), + bit_size (curi->size)); + printf ("\t\tval &= %s;\n", bit_mask (curi->size)); + printf ("\t}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ASL: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); + printf ("\t\tSET_VFLG (val != 0);\n"); + printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", + bit_size (curi->size)); + duplicate_carry (); + printf ("\t\tval = 0;\n"); + if (source_is_imm1_8 (curi)) + printf ("\t} else {\n"); + else + printf ("\t} else if (cnt > 0) {\n"); + printf ("\t\tuint32_t mask = (%s << (%d - cnt)) & %s;\n", + bit_mask (curi->size), + bit_size (curi->size) - 1, + bit_mask (curi->size)); + printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n"); + printf ("\t\tval <<= cnt - 1;\n"); + printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1); + duplicate_carry (); + printf ("\t\tval <<= 1;\n"); + printf ("\t\tval &= %s;\n", bit_mask (curi->size)); + printf ("\t}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_LSR: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); + printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n", + bit_size (curi->size), bit_size (curi->size) - 1); + duplicate_carry (); + printf ("\t\tval = 0;\n"); + if (source_is_imm1_8 (curi)) + printf ("\t} else {\n"); + else + printf ("\t} else if (cnt > 0) {\n"); + printf ("\t\tval >>= cnt - 1;\n"); + printf ("\t\tSET_CFLG (val & 1);\n"); + duplicate_carry (); + printf ("\t\tval >>= 1;\n"); + printf ("\t}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_LSL: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); + printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", + bit_size (curi->size)); + duplicate_carry (); + printf ("\t\tval = 0;\n"); + if (source_is_imm1_8 (curi)) + printf ("\t} else {\n"); + else + printf ("\t} else if (cnt > 0) {\n"); + printf ("\t\tval <<= (cnt - 1);\n"); + printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1); + duplicate_carry (); + printf ("\t\tval <<= 1;\n"); + printf ("\tval &= %s;\n", bit_mask (curi->size)); + printf ("\t}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ROL: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + if (source_is_imm1_8 (curi)) + printf ("{"); + else + printf ("\tif (cnt > 0) {\n"); + printf ("\tuint32_t loval;\n"); + printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1); + printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size)); + printf ("\tval <<= cnt;\n"); + printf ("\tval |= loval;\n"); + printf ("\tval &= %s;\n", bit_mask (curi->size)); + printf ("\tSET_CFLG (val & 1);\n"); + printf ("}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ROR: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + if (source_is_imm1_8 (curi)) + printf ("{"); + else + printf ("\tif (cnt > 0) {"); + printf ("\tuint32_t hival;\n"); + printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1); + printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size)); + printf ("\tval >>= cnt;\n"); + printf ("\tval |= hival;\n"); + printf ("\tval &= %s;\n", bit_mask (curi->size)); + printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1); + printf ("\t}\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ROXL: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + if (source_is_imm1_8 (curi)) + printf ("{"); + else { + force_range_for_rox ("cnt", curi->size); + printf ("\tif (cnt > 0) {\n"); + } + printf ("\tcnt--;\n"); + printf ("\t{\n\tuint32_t carry;\n"); + printf ("\tuint32_t loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1); + printf ("\tcarry = loval & 1;\n"); + printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n"); + printf ("\tSET_XFLG (carry);\n"); + printf ("\tval &= %s;\n", bit_mask (curi->size)); + printf ("\t} }\n"); + printf ("\tSET_CFLG (GET_XFLG);\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ROXR: + genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tcnt &= 63;\n"); + printf ("\tretcycles = cnt;\n"); + printf ("\tCLEAR_CZNV;\n"); + if (source_is_imm1_8 (curi)) + printf ("{"); + else { + force_range_for_rox ("cnt", curi->size); + printf ("\tif (cnt > 0) {\n"); + } + printf ("\tcnt--;\n"); + printf ("\t{\n\tuint32_t carry;\n"); + printf ("\tuint32_t hival = (val << 1) | GET_XFLG;\n"); + printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1); + printf ("\tval >>= cnt;\n"); + printf ("\tcarry = val & 1;\n"); + printf ("\tval >>= 1;\n"); + printf ("\tval |= hival;\n"); + printf ("\tSET_XFLG (carry);\n"); + printf ("\tval &= %s;\n", bit_mask (curi->size)); + printf ("\t} }\n"); + printf ("\tSET_CFLG (GET_XFLG);\n"); + genflags (flag_logical_noclobber, curi->size, "val", "", ""); + genastore ("val", curi->dmode, "dstreg", curi->size, "data"); + if(curi->size==sz_long) + strcpy(exactCpuCycles," return (8+retcycles*2);"); + else + strcpy(exactCpuCycles," return (6+retcycles*2);"); + break; + case i_ASRW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t sign = %s & val;\n", cmask (curi->size)); + printf ("\tuint32_t cflg = val & 1;\n"); + printf ("\tval = (val >> 1) | sign;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("\tSET_CFLG (cflg);\n"); + duplicate_carry (); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_ASLW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t sign = %s & val;\n", cmask (curi->size)); + printf ("\tuint32_t sign2;\n"); + printf ("\tval <<= 1;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("\tsign2 = %s & val;\n", cmask (curi->size)); + printf ("\tSET_CFLG (sign != 0);\n"); + duplicate_carry (); + + printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n"); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_LSRW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint32_t val = (uint8_t)data;\n"); break; + case sz_word: printf ("\tuint32_t val = (uint16_t)data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & 1;\n"); + printf ("\tval >>= 1;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry);\n"); + duplicate_carry (); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_LSLW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint8_t val = data;\n"); break; + case sz_word: printf ("\tuint16_t val = data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size)); + printf ("\tval <<= 1;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1); + duplicate_carry (); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_ROLW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint8_t val = data;\n"); break; + case sz_word: printf ("\tuint16_t val = data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size)); + printf ("\tval <<= 1;\n"); + printf ("\tif (carry) val |= 1;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_RORW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint8_t val = data;\n"); break; + case sz_word: printf ("\tuint16_t val = data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & 1;\n"); + printf ("\tval >>= 1;\n"); + printf ("\tif (carry) val |= %s;\n", cmask (curi->size)); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry);\n"); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_ROXLW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint8_t val = data;\n"); break; + case sz_word: printf ("\tuint16_t val = data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & %s;\n", cmask (curi->size)); + printf ("\tval <<= 1;\n"); + printf ("\tif (GET_XFLG) val |= 1;\n"); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1); + duplicate_carry (); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_ROXRW: + genamode (curi->smode, "srcreg", curi->size, "data", 1, 0); + start_brace (); + switch (curi->size) { + case sz_byte: printf ("\tuint8_t val = data;\n"); break; + case sz_word: printf ("\tuint16_t val = data;\n"); break; + case sz_long: printf ("\tuint32_t val = data;\n"); break; + default: abort (); + } + printf ("\tuint32_t carry = val & 1;\n"); + printf ("\tval >>= 1;\n"); + printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size)); + genflags (flag_logical, curi->size, "val", "", ""); + printf ("SET_CFLG (carry);\n"); + duplicate_carry (); + genastore ("val", curi->smode, "srcreg", curi->size, "data"); + break; + case i_MOVEC2: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + printf ("\tint regno = (src >> 12) & 15;\n"); + printf ("\tuint32_t *regp = regs.regs + regno;\n"); + printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr); + break; + case i_MOVE2C: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + start_brace (); + printf ("\tint regno = (src >> 12) & 15;\n"); + printf ("\tuint32_t *regp = regs.regs + regno;\n"); + printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr); + break; + case i_CAS: + { + int old_brace_level; + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + start_brace (); + printf ("\tint ru = (src >> 6) & 7;\n"); + printf ("\tint rc = src & 7;\n"); + genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst"); + printf ("\tif (GET_ZFLG)"); + old_brace_level = n_braces; + start_brace (); + genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst"); + pop_braces (old_brace_level); + printf ("else"); + start_brace (); + printf ("m68k_dreg(regs, rc) = dst;\n"); + pop_braces (old_brace_level); + } + break; + case i_CAS2: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + printf ("\tuint32_t rn1 = regs.regs[(extra >> 28) & 15];\n"); + printf ("\tuint32_t rn2 = regs.regs[(extra >> 12) & 15];\n"); + if (curi->size == sz_word) { + int old_brace_level = n_braces; + printf ("\tuint16_t dst1 = m68k_read_memory_16(rn1), dst2 = m68k_read_memory_16(rn2);\n"); + genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1"); + printf ("\tif (GET_ZFLG) {\n"); + genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2"); + printf ("\tif (GET_ZFLG) {\n"); + printf ("\tm68k_write_memory_16(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n"); + printf ("\tm68k_write_memory_16(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n"); + printf ("\t}}\n"); + pop_braces (old_brace_level); + printf ("\tif (! GET_ZFLG) {\n"); + printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n"); + printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n"); + printf ("\t}\n"); + } else { + int old_brace_level = n_braces; + printf ("\tuint32_t dst1 = m68k_read_memory_32(rn1), dst2 = m68k_read_memory_32(rn2);\n"); + genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1"); + printf ("\tif (GET_ZFLG) {\n"); + genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2"); + printf ("\tif (GET_ZFLG) {\n"); + printf ("\tm68k_write_memory_32(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n"); + printf ("\tm68k_write_memory_32(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n"); + printf ("\t}}\n"); + pop_braces (old_brace_level); + printf ("\tif (! GET_ZFLG) {\n"); + printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n"); + printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n"); + printf ("\t}\n"); + } + break; + case i_MOVES: /* ignore DFC and SFC because we have no MMU */ + { + int old_brace_level; + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + printf ("\tif (extra & 0x800)\n"); + old_brace_level = n_braces; + start_brace (); + printf ("\tuint32_t src = regs.regs[(extra >> 12) & 15];\n"); + genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0); + genastore ("src", curi->dmode, "dstreg", curi->size, "dst"); + pop_braces (old_brace_level); + printf ("else"); + start_brace (); + genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0); + printf ("\tif (extra & 0x8000) {\n"); + switch (curi->size) { + case sz_byte: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (int32_t)(int8_t)src;\n"); break; + case sz_word: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = (int32_t)(int16_t)src;\n"); break; + case sz_long: printf ("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break; + default: abort (); + } + printf ("\t} else {\n"); + genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, ""); + printf ("\t}\n"); + pop_braces (old_brace_level); + } + break; + case i_BKPT: /* only needed for hardware emulators */ + sync_m68k_pc (); + printf ("\top_illg(opcode);\n"); + break; + case i_CALLM: /* not present in 68030 */ + sync_m68k_pc (); + printf ("\top_illg(opcode);\n"); + break; + case i_RTM: /* not present in 68030 */ + sync_m68k_pc (); + printf ("\top_illg(opcode);\n"); + break; + case i_TRAPcc: + if (curi->smode != am_unknown && curi->smode != am_illg) + genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0); + printf ("\tif (cctrue(%d)) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr); + need_endlabel = 1; + break; + case i_DIVL: + sync_m68k_pc (); + start_brace (); + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + sync_m68k_pc (); + printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n"); + break; + case i_MULL: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); + sync_m68k_pc (); + printf ("\tm68k_mull(opcode, dst, extra);\n"); + break; + case i_BFTST: + case i_BFEXTU: + case i_BFCHG: + case i_BFEXTS: + case i_BFCLR: + case i_BFFFO: + case i_BFSET: + case i_BFINS: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0); + start_brace (); + printf ("\tint32_t offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n"); + printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n"); + if (curi->dmode == Dreg) { + printf ("\tuint32_t tmp = m68k_dreg(regs, dstreg) << (offset & 0x1f);\n"); + } else { + printf ("\tuint32_t tmp,bf0,bf1;\n"); + printf ("\tdsta += (offset >> 3) | (offset & 0x80000000 ? ~0x1fffffff : 0);\n"); + printf ("\tbf0 = m68k_read_memory_32(dsta);bf1 = m68k_read_memory_8(dsta+4) & 0xff;\n"); + printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n"); + } + printf ("\ttmp >>= (32 - width);\n"); + printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n"); + printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n"); + switch (curi->mnemo) { + case i_BFTST: + break; + case i_BFEXTU: + printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n"); + break; + case i_BFCHG: + printf ("\ttmp = ~tmp;\n"); + break; + case i_BFEXTS: + printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n"); + printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n"); + break; + case i_BFCLR: + printf ("\ttmp = 0;\n"); + break; + case i_BFFFO: + printf ("\t{ uint32_t mask = 1 << (width-1);\n"); + printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n"); + printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = offset;\n"); + break; + case i_BFSET: + printf ("\ttmp = 0xffffffff;\n"); + break; + case i_BFINS: + printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n"); + printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n"); + printf ("\tSET_ZFLG (tmp == 0);\n"); + break; + default: + break; + } + if (curi->mnemo == i_BFCHG + || curi->mnemo == i_BFCLR + || curi->mnemo == i_BFSET + || curi->mnemo == i_BFINS) + { + printf ("\ttmp <<= (32 - width);\n"); + if (curi->dmode == Dreg) { + printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ((offset & 0x1f) == 0 ? 0 :\n"); + printf ("\t\t(0xffffffff << (32 - (offset & 0x1f))))) |\n"); + printf ("\t\t(tmp >> (offset & 0x1f)) |\n"); + printf ("\t\t(((offset & 0x1f) + width) >= 32 ? 0 :\n"); + printf (" (m68k_dreg(regs, dstreg) & ((uint32_t)0xffffffff >> ((offset & 0x1f) + width))));\n"); + } else { + printf ("\tbf0 = (bf0 & (0xff000000 << (8 - (offset & 7)))) |\n"); + printf ("\t\t(tmp >> (offset & 7)) |\n"); + printf ("\t\t(((offset & 7) + width) >= 32 ? 0 :\n"); + printf ("\t\t (bf0 & ((uint32_t)0xffffffff >> ((offset & 7) + width))));\n"); + printf ("\tm68k_write_memory_32(dsta,bf0 );\n"); + printf ("\tif (((offset & 7) + width) > 32) {\n"); + printf ("\t\tbf1 = (bf1 & (0xff >> (width - 32 + (offset & 7)))) |\n"); + printf ("\t\t\t(tmp << (8 - (offset & 7)));\n"); + printf ("\t\tm68k_write_memory_8(dsta+4,bf1);\n"); + printf ("\t}\n"); + } + } + break; + case i_PACK: + if (curi->smode == Dreg) { + printf ("\tuint16_t val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword ()); + printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n"); + } else { + printf ("\tuint16_t val;\n"); + printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n"); + printf ("\tval = (uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg));\n"); + printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n"); + printf ("\tval = (val | ((uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg)) << 8)) + %s;\n", gen_nextiword ()); + printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n"); + printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n"); + } + break; + case i_UNPK: + if (curi->smode == Dreg) { + printf ("\tuint16_t val = m68k_dreg(regs, srcreg);\n"); + printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ()); + printf ("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n"); + } else { + printf ("\tuint16_t val;\n"); + printf ("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n"); + printf ("\tval = (uint16_t)m68k_read_memory_8(m68k_areg(regs, srcreg));\n"); + printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword ()); + printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n"); + printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),val);\n"); + printf ("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n"); + printf ("\tm68k_write_memory_8(m68k_areg(regs, dstreg),val >> 8);\n"); + } + break; + case i_TAS: + genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); + genflags (flag_logical, curi->size, "src", "", ""); + printf ("\tsrc |= 0x80;\n"); + genastore ("src", curi->smode, "srcreg", curi->size, "src"); + if( curi->smode!=Dreg ) insn_n_cycles += 2; + break; + case i_FPP: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + sync_m68k_pc (); + printf ("\tfpp_opp(opcode,extra);\n"); + break; + case i_FDBcc: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + sync_m68k_pc (); + printf ("\tfdbcc_opp(opcode,extra);\n"); + break; + case i_FScc: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + sync_m68k_pc (); + printf ("\tfscc_opp(opcode,extra);\n"); + break; + case i_FTRAPcc: + sync_m68k_pc (); + start_brace (); + printf ("\tuint32_t oldpc = m68k_getpc();\n"); + if (curi->smode != am_unknown && curi->smode != am_illg) + genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0); + sync_m68k_pc (); + printf ("\tftrapcc_opp(opcode,oldpc);\n"); + break; + case i_FBcc: + sync_m68k_pc (); + start_brace (); + printf ("\tuint32_t pc = m68k_getpc();\n"); + genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0); + sync_m68k_pc (); + printf ("\tfbcc_opp(opcode,pc,extra);\n"); + break; + case i_FSAVE: + sync_m68k_pc (); + printf ("\tfsave_opp(opcode);\n"); + break; + case i_FRESTORE: + sync_m68k_pc (); + printf ("\tfrestore_opp(opcode);\n"); + break; + + case i_CINVL: + case i_CINVP: + case i_CINVA: + case i_CPUSHL: + case i_CPUSHP: + case i_CPUSHA: + break; + case i_MOVE16: + if ((opcode & 0xfff8) == 0xf620) { + /* MOVE16 (Ax)+,(Ay)+ */ + printf ("\tuint32_t mems = m68k_areg(regs, srcreg) & ~15, memd;\n"); + printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword()); + printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n"); + printf ("\tm68k_write_memory_32(memd, m68k_read_memory_32(mems));\n"); + printf ("\tm68k_write_memory_32(memd+4, m68k_read_memory_32(mems+4));\n"); + printf ("\tm68k_write_memory_32(memd+8, m68k_read_memory_32(mems+8));\n"); + printf ("\tm68k_write_memory_32(memd+12, m68k_read_memory_32(mems+12));\n"); + printf ("\tif (srcreg != dstreg)\n"); + printf ("\tm68k_areg(regs, srcreg) += 16;\n"); + printf ("\tm68k_areg(regs, dstreg) += 16;\n"); + } else { + /* Other variants */ + genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2); + genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2); + printf ("\tmemsa &= ~15;\n"); + printf ("\tmemda &= ~15;\n"); + printf ("\tm68k_write_memory_32(memda, m68k_read_memory_32(memsa));\n"); + printf ("\tm68k_write_memory_32(memda+4, m68k_read_memory_32(memsa+4));\n"); + printf ("\tm68k_write_memory_32(memda+8, m68k_read_memory_32(memsa+8));\n"); + printf ("\tm68k_write_memory_32(memda+12, m68k_read_memory_32(memsa+12));\n"); + if ((opcode & 0xfff8) == 0xf600) + printf ("\tm68k_areg(regs, srcreg) += 16;\n"); + else if ((opcode & 0xfff8) == 0xf608) + printf ("\tm68k_areg(regs, dstreg) += 16;\n"); + } + break; + + case i_MMUOP: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0); + sync_m68k_pc (); + printf ("\tmmu_op(opcode,extra);\n"); + break; + default: + abort (); + break; + } + finish_braces (); + sync_m68k_pc (); +} + +static void generate_includes(FILE * f) +{ +//JLH:no fprintf(f, "#include \"sysdeps.h\"\n"); +//JLH:no fprintf(f, "#include \"hatari-glue.h\"\n"); +//JLH:no fprintf(f, "#include \"maccess.h\"\n"); +//JLH:no fprintf(f, "#include \"memory.h\"\n"); +//JLH:no fprintf(f, "#include \"newcpu.h\"\n"); + fprintf(f, "#include \"cpudefs.h\"\n"); + fprintf(f, "#include \"cpuextra.h\"\n"); + fprintf(f, "#include \"inlines.h\"\n"); + fprintf(f, "#include \"cputbl.h\"\n"); + fprintf(f, "#define CPUFUNC(x) x##_ff\n" + "#ifdef NOFLAGS\n" + "#include \"noflags.h\"\n" + "#endif\n"); +} + +// JLH: Since this is stuff that should be generated in a file that creates +// constants, it's in here now. :-P +static void GenerateTables(FILE * f) +{ + int i, j; + + fprintf(f, "\nconst int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };\n"); + fprintf(f, "const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 };\n\n"); + fprintf(f, "const int movem_index1[256] = {\n"); + + for(i=0; i<256; i++) + { + for(j=0; j<8; j++) + if (i & (1 << j)) + break; + + fprintf(f, "0x%02X, ", j); + + if ((i % 16) == 15) + fprintf(f, "\n"); + } + + fprintf(f, "};\n\n"); + fprintf(f, "const int movem_index2[256] = {\n"); + + for(i=0; i<256; i++) + { + for(j=0; j<8; j++) + if (i & (1 << j)) + break; + + fprintf(f, "0x%02X, ", 7 - j); + + if ((i % 16) == 15) + fprintf(f, "\n"); + } + + fprintf(f, "};\n\n"); + fprintf(f, "const int movem_next[256] = {\n"); + + for(i=0; i<256; i++) + { + for(j=0; j<8; j++) + if (i & (1 << j)) + break; + + fprintf(f, "0x%02X, ", i & (~(1 << j))); + + if ((i % 16) == 15) + fprintf(f, "\n"); + } + + fprintf(f, "};\n\n"); +} + +static int postfix; + +static void generate_one_opcode (int rp) +{ + int i; + uint16_t smsk, dmsk; + long int opcode = opcode_map[rp]; + + exactCpuCycles[0] = 0; /* Default: not used */ + + if (table68k[opcode].mnemo == i_ILLG + || table68k[opcode].clev > cpu_level) + return; + + for (i = 0; lookuptab[i].name[0]; i++) { + if (table68k[opcode].mnemo == lookuptab[i].mnemo) + break; + } + + if (table68k[opcode].handler != -1) + return; + + if (opcode_next_clev[rp] != cpu_level) { + fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp], + opcode, lookuptab[i].name); + return; + } + fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name); + fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix); + fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix); + printf ("unsigned long CPUFUNC(op_%lx_%d)(uint32_t opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name); + + switch (table68k[opcode].stype) { + case 0: smsk = 7; break; + case 1: smsk = 255; break; + case 2: smsk = 15; break; + case 3: smsk = 7; break; + case 4: smsk = 7; break; + case 5: smsk = 63; break; + case 7: smsk = 3; break; + default: abort (); + } + dmsk = 7; + + next_cpu_level = -1; + if (table68k[opcode].suse + && table68k[opcode].smode != imm && table68k[opcode].smode != imm0 + && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2 + && table68k[opcode].smode != absw && table68k[opcode].smode != absl + && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16) + { + if (table68k[opcode].spos == -1) { + if (((int) table68k[opcode].sreg) >= 128) + printf ("\tuint32_t srcreg = (int32_t)(int8_t)%d;\n", (int) table68k[opcode].sreg); + else + printf ("\tuint32_t srcreg = %d;\n", (int) table68k[opcode].sreg); + } else { + char source[100]; + int pos = table68k[opcode].spos; + + if (pos) + sprintf (source, "((opcode >> %d) & %d)", pos, smsk); + else + sprintf (source, "(opcode & %d)", smsk); + + if (table68k[opcode].stype == 3) + printf ("\tuint32_t srcreg = imm8_table[%s];\n", source); + else if (table68k[opcode].stype == 1) + printf ("\tuint32_t srcreg = (int32_t)(int8_t)%s;\n", source); + else + printf ("\tuint32_t srcreg = %s;\n", source); + } + } + if (table68k[opcode].duse + /* Yes, the dmode can be imm, in case of LINK or DBcc */ + && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0 + && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2 + && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl) + { + if (table68k[opcode].dpos == -1) { + if (((int) table68k[opcode].dreg) >= 128) + printf ("\tuint32_t dstreg = (int32_t)(int8_t)%d;\n", (int) table68k[opcode].dreg); + else + printf ("\tuint32_t dstreg = %d;\n", (int) table68k[opcode].dreg); + } else { + int pos = table68k[opcode].dpos; +#if 0 + /* Check that we can do the little endian optimization safely. */ + if (pos < 8 && (dmsk >> (8 - pos)) != 0) + abort (); +#endif + if (pos) + printf ("\tuint32_t dstreg = (opcode >> %d) & %d;\n", + pos, dmsk); + else + printf ("\tuint32_t dstreg = opcode & %d;\n", dmsk); + } + } + need_endlabel = 0; + endlabelno++; + sprintf (endlabelstr, "endlabel%d", endlabelno); + if(table68k[opcode].mnemo==i_ASR || table68k[opcode].mnemo==i_ASL || table68k[opcode].mnemo==i_LSR || table68k[opcode].mnemo==i_LSL + || table68k[opcode].mnemo==i_ROL || table68k[opcode].mnemo==i_ROR || table68k[opcode].mnemo==i_ROXL || table68k[opcode].mnemo==i_ROXR + || table68k[opcode].mnemo==i_MVMEL || table68k[opcode].mnemo==i_MVMLE + || table68k[opcode].mnemo==i_MULU || table68k[opcode].mnemo==i_MULS + || table68k[opcode].mnemo==i_DIVU || table68k[opcode].mnemo==i_DIVS ) + printf("\tunsigned int retcycles = 0;\n"); + gen_opcode (opcode); + if (need_endlabel) + printf ("%s: ;\n", endlabelstr); + + if (strlen(exactCpuCycles) > 0) + printf("%s\n",exactCpuCycles); + else + printf ("return %d;\n", insn_n_cycles); + /* Now patch in the instruction cycles at the beginning of the function: */ + fseek(stdout, nCurInstrCycPos, SEEK_SET); + printf("%d;", insn_n_cycles); + fseek(stdout, 0, SEEK_END); + + printf ("}\n"); + opcode_next_clev[rp] = next_cpu_level; + opcode_last_postfix[rp] = postfix; +} + +static void generate_func(void) +{ + int i, j, rp; + + using_prefetch = 0; + using_exception_3 = 0; +//JLH: +// for(i=0; i<6; i++) +//For some reason, this doesn't work properly. Seems something is making a bad +//assumption somewhere. +//and it's probably in opcode_next_clev[rp]... + for(i=4; i<6; i++) + { + cpu_level = 4 - i; + + //JLH + for(rp=0; rp68000 cpus, so this is bogus. +#if 0 + /* A traced STOP instruction drops through immediately without + actually stopping. */ + if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0) + regs.spcflags |= SPCFLAG_STOP; +#endif +} + +STATIC_INLINE void m68k_do_rts(void) +{ + m68k_setpc(m68k_read_memory_32(m68k_areg(regs, 7))); + m68k_areg(regs, 7) += 4; +} + +STATIC_INLINE void m68k_do_bsr(uint32_t oldpc, int32_t offset) +{ + m68k_areg(regs, 7) -= 4; + m68k_write_memory_32(m68k_areg(regs, 7), oldpc); + m68k_incpc(offset); +} + +STATIC_INLINE void m68k_do_jsr(uint32_t oldpc, uint32_t dest) +{ + m68k_areg(regs, 7) -= 4; + m68k_write_memory_32(m68k_areg(regs, 7), oldpc); + m68k_setpc(dest); +} + +#if 0 +//These do_get_mem_* functions are only used in newcpu... +//What it does is use a pointer to make instruction fetching quicker, +//though it probably leads to more problems than it solves. Something to +//decide using a profiler... +#define get_ibyte(o) do_get_mem_byte(regs.pc_p + (o) + 1) +#define get_iword(o) do_get_mem_word(regs.pc_p + (o)) +#define get_ilong(o) do_get_mem_long(regs.pc_p + (o)) +#else +// For now, we'll punt this crap... +// (Also, notice that the byte read is at address + 1...) +#define get_ibyte(o) m68k_read_memory_8(regs.pc + (o) + 1) +#define get_iword(o) m68k_read_memory_16(regs.pc + (o)) +#define get_ilong(o) m68k_read_memory_32(regs.pc + (o)) +#endif + +// We don't use this crap, so let's comment out for now... +STATIC_INLINE void refill_prefetch(uint32_t currpc, uint32_t offs) +{ +#if 0 + uint32_t t = (currpc + offs) & ~1; + int32_t pc_p_offs = t - currpc; + uint8_t * ptr = regs.pc_p + pc_p_offs; + uint32_t r; + +#ifdef UNALIGNED_PROFITABLE + r = *(uint32_t *)ptr; + regs.prefetch = r; +#else + r = do_get_mem_long(ptr); + do_put_mem_long(®s.prefetch, r); +#endif + /* printf ("PC %lx T %lx PCPOFFS %d R %lx\n", currpc, t, pc_p_offs, r); */ + regs.prefetch_pc = t; +#endif +} + +STATIC_INLINE uint32_t get_ibyte_prefetch(int32_t o) +{ +#if 0 + uint32_t currpc = m68k_getpc(); + uint32_t addr = currpc + o + 1; + uint32_t offs = addr - regs.prefetch_pc; + + if (offs > 3) + { + refill_prefetch(currpc, o + 1); + offs = addr - regs.prefetch_pc; + } + + uint32_t v = do_get_mem_byte(((uint8_t *)®s.prefetch) + offs); + + if (offs >= 2) + refill_prefetch(currpc, 2); + + /* printf ("get_ibyte PC %lx ADDR %lx OFFS %lx V %lx\n", currpc, addr, offs, v); */ + return v; +#else + return get_ibyte(o); +#endif +} + +STATIC_INLINE uint32_t get_iword_prefetch(int32_t o) +{ +#if 0 + uint32_t currpc = m68k_getpc(); + uint32_t addr = currpc + o; + uint32_t offs = addr - regs.prefetch_pc; + + if (offs > 3) + { + refill_prefetch(currpc, o); + offs = addr - regs.prefetch_pc; + } + + uint32_t v = do_get_mem_word(((uint8_t *)®s.prefetch) + offs); + + if (offs >= 2) + refill_prefetch(currpc, 2); + +/* printf ("get_iword PC %lx ADDR %lx OFFS %lx V %lx\n", currpc, addr, offs, v); */ + return v; +#else + return get_iword(o); +#endif +} + +STATIC_INLINE uint32_t get_ilong_prefetch(int32_t o) +{ +#if 0 + uint32_t v = get_iword_prefetch(o); + v <<= 16; + v |= get_iword_prefetch(o + 2); + return v; +#else + return get_ilong(o); +#endif +} + +STATIC_INLINE void fill_prefetch_0(void) +{ +} + +#define fill_prefetch_2 fill_prefetch_0 + +#endif // __INLINES_H__ diff --git a/waterbox/virtualjaguar/src/m68000/m68kdasm.c b/waterbox/virtualjaguar/src/m68000/m68kdasm.c new file mode 100644 index 0000000000..ab31cdb7bb --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/m68kdasm.c @@ -0,0 +1,421 @@ +// +// m68kdasm.c: 68000 instruction disassembly +// +// Originally part of the UAE 68000 cpu core +// by Bernd Schmidt +// +// Adapted to Virtual Jaguar by James Hammons +// +// This file is distributed under the GNU Public License, version 3 or at your +// option any later version. Read the file GPLv3 for details. +// + +#include +#include "cpudefs.h" +#include "cpuextra.h" +#include "inlines.h" +#include "readcpu.h" + + +// Stuff from m68kinterface.c +extern unsigned long IllegalOpcode(uint32_t opcode); +extern cpuop_func * cpuFunctionTable[65536]; + +// Prototypes +void HandleMovem(char * output, uint16_t data, int direction); + +// Local "global" variables +static long int m68kpc_offset; + +#if 0 +#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) +#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) +#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) +#else +#define get_ibyte_1(o) m68k_read_memory_8(regs.pc + (o) + 1) +#define get_iword_1(o) m68k_read_memory_16(regs.pc + (o)) +#define get_ilong_1(o) m68k_read_memory_32(regs.pc + (o)) +#endif + + +//int32_t ShowEA(FILE * f, int reg, amodes mode, wordsizes size, char * buf) +int32_t ShowEA(int mnemonic, int reg, amodes mode, wordsizes size, char * buf) +{ + uint16_t dp; + int8_t disp8; + int16_t disp16; + int r; + uint32_t dispreg; + uint32_t addr; + int32_t offset = 0; + char buffer[80]; + + switch (mode) + { + case Dreg: + sprintf(buffer,"D%d", reg); + break; + case Areg: + sprintf(buffer,"A%d", reg); + break; + case Aind: + sprintf(buffer,"(A%d)", reg); + break; + case Aipi: + sprintf(buffer,"(A%d)+", reg); + break; + case Apdi: + sprintf(buffer,"-(A%d)", reg); + break; + case Ad16: + disp16 = get_iword_1(m68kpc_offset); m68kpc_offset += 2; + addr = m68k_areg(regs,reg) + (int16_t)disp16; + sprintf(buffer,"(A%d,$%X) == $%lX", reg, disp16 & 0xFFFF, + (unsigned long)addr); + break; + case Ad8r: + dp = get_iword_1(m68kpc_offset); m68kpc_offset += 2; + disp8 = dp & 0xFF; + r = (dp & 0x7000) >> 12; + dispreg = (dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r)); + + if (!(dp & 0x800)) + dispreg = (int32_t)(int16_t)(dispreg); + + dispreg <<= (dp >> 9) & 3; + + if (dp & 0x100) + { + int32_t outer = 0, disp = 0; + int32_t base = m68k_areg(regs,reg); + char name[10]; + sprintf (name,"A%d, ",reg); + if (dp & 0x80) { base = 0; name[0] = 0; } + if (dp & 0x40) dispreg = 0; + if ((dp & 0x30) == 0x20) { disp = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; } + if ((dp & 0x30) == 0x30) { disp = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; } + base += disp; + + if ((dp & 0x3) == 0x2) { outer = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; } + if ((dp & 0x3) == 0x3) { outer = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; } + + if (!(dp & 4)) base += dispreg; + if (dp & 3) base = m68k_read_memory_32(base); + if (dp & 4) base += dispreg; + + addr = base + outer; + sprintf(buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%lX", name, + dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', + 1 << ((dp >> 9) & 3), + (long)disp, (long)outer, (unsigned long)addr); + } + else + { + addr = m68k_areg(regs,reg) + (int32_t)((int8_t)disp8) + dispreg; + sprintf (buffer,"(A%d, %c%d.%c*%d, $%X) == $%lX", reg, + dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', + 1 << ((dp >> 9) & 3), disp8, (unsigned long)addr); + } + break; + case PC16: + addr = m68k_getpc() + m68kpc_offset; + disp16 = get_iword_1(m68kpc_offset); m68kpc_offset += 2; + addr += (int16_t)disp16; + sprintf(buffer,"(PC, $%X) == $%lX", disp16 & 0xFFFF, (unsigned long)addr); + break; + case PC8r: + addr = m68k_getpc() + m68kpc_offset; + dp = get_iword_1(m68kpc_offset); m68kpc_offset += 2; + disp8 = dp & 0xFF; + r = (dp & 0x7000) >> 12; + dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r); + + if (!(dp & 0x800)) + dispreg = (int32_t)(int16_t)(dispreg); + + dispreg <<= (dp >> 9) & 3; + + if (dp & 0x100) + { + int32_t outer = 0,disp = 0; + int32_t base = addr; + char name[10]; + sprintf (name,"PC, "); + if (dp & 0x80) { base = 0; name[0] = 0; } + if (dp & 0x40) dispreg = 0; + if ((dp & 0x30) == 0x20) { disp = (int32_t)(int16_t)get_iword_1(m68kpc_offset); m68kpc_offset += 2; } + if ((dp & 0x30) == 0x30) { disp = get_ilong_1(m68kpc_offset); m68kpc_offset += 4; } + base += disp; + + if ((dp & 0x3) == 0x2) + { + outer = (int32_t)(int16_t)get_iword_1(m68kpc_offset); + m68kpc_offset += 2; + } + + if ((dp & 0x3) == 0x3) + { + outer = get_ilong_1(m68kpc_offset); + m68kpc_offset += 4; + } + + if (!(dp & 4)) base += dispreg; + if (dp & 3) base = m68k_read_memory_32(base); + if (dp & 4) base += dispreg; + + addr = base + outer; + sprintf(buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%lX", name, + dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', + 1 << ((dp >> 9) & 3), (long)disp, (long)outer, (unsigned long)addr); + } + else + { + addr += (int32_t)((int8_t)disp8) + dispreg; + sprintf(buffer,"(PC, %c%d.%c*%d, $%X) == $%lX", dp & 0x8000 ? 'A' : 'D', + (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), + disp8, (unsigned long)addr); + } + break; + case absw: + sprintf(buffer,"$%lX", (unsigned long)(int32_t)(int16_t)get_iword_1(m68kpc_offset)); + m68kpc_offset += 2; + break; + case absl: + sprintf(buffer,"$%lX", (unsigned long)get_ilong_1(m68kpc_offset)); + m68kpc_offset += 4; + break; + case imm: + switch (size) + { + case sz_byte: + sprintf(buffer,"#$%X", (unsigned int)(get_iword_1(m68kpc_offset) & 0xFF)); + m68kpc_offset += 2; + break; + case sz_word: + sprintf(buffer,"#$%X", (unsigned int)(get_iword_1(m68kpc_offset) & 0xFFFF)); + m68kpc_offset += 2; + break; + case sz_long: + sprintf(buffer,"#$%lX", (unsigned long)(get_ilong_1(m68kpc_offset))); + m68kpc_offset += 4; + break; + default: + break; + } + break; + case imm0: + offset = (int32_t)(int8_t)get_iword_1(m68kpc_offset); + m68kpc_offset += 2; + sprintf(buffer,"#$%X", (unsigned int)(offset & 0xFF)); + break; + case imm1: + offset = (int32_t)(int16_t)get_iword_1(m68kpc_offset); + m68kpc_offset += 2; + + if (mnemonic == i_MVMEL) + HandleMovem(buffer, offset, 0); + else if (mnemonic == i_MVMLE) + HandleMovem(buffer, offset, 1); + else + sprintf(buffer,"#$%X", (unsigned int)(offset & 0xFFFF)); + + break; + case imm2: + offset = (int32_t)get_ilong_1(m68kpc_offset); + m68kpc_offset += 4; + sprintf(buffer,"#$%lX", (unsigned long)(offset & 0xFFFFFFFF)); + break; + case immi: + offset = (int32_t)(int8_t)(reg & 0xFF); + sprintf(buffer,"#$%lX", (unsigned long)(offset & 0xFFFFFFFF)); + break; + default: + break; + } + +// if (buf == 0) +// fprintf(f, "%s", buffer); +// else + strcat(buf, buffer); + + return offset; +} + + +void HandleMovem(char * output, uint16_t data, int direction) +{ + uint16_t ascending[16] = { + 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 }; + uint16_t descending[16] = { + 0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100, + 0x0080, 0x0040, 0x0020, 0x0010, 0x0008, 0x0004, 0x0002, 0x0001 }; + + int i, j, first, runLength, firstPrint = 1; + char buf[16]; + uint16_t * bitMask; + + bitMask = (direction ? descending : ascending); + output[0] = 0; + + // Handle D0-D7... + for(i=0; i<8; i++) + { + if (data & bitMask[i]) + { + first = i; + runLength = 0; + + for(j=i+1; j<8 && (data & bitMask[j]); j++) + runLength++; + + i += runLength; + + if (firstPrint) + firstPrint = 0; + else + strcat(output, "/"); + + sprintf(buf, "D%d", first); + strcat(output, buf); + + if (runLength > 0) + { + sprintf(buf, "-D%d", first + runLength); + strcat(output, buf); + } + } + } + + // Handle A0-A7... + for(i=0; i<8; i++) + { + if (data & bitMask[i + 8]) + { + first = i; + runLength = 0; + + for(j=i+1; j<8 && (data & bitMask[j+8]); j++) + runLength++; + + i += runLength; + + if (firstPrint) + firstPrint = 0; + else + strcat(output, "/"); + + sprintf(buf, "A%d", first); + strcat(output, buf); + + if (runLength > 0) + { + sprintf(buf, "-A%d", first + runLength); + strcat(output, buf); + } + } + } +} + + +unsigned int M68KDisassemble(char * output, uint32_t addr) +{ + char f[256], str[256]; + char src[256], dst[256]; + static const char * const ccnames[] = + { "RA","RN","HI","LS","CC","CS","NE","EQ", + "VC","VS","PL","MI","GE","LT","GT","LE" }; + + str[0] = 0; + output[0] = 0; + uint32_t newpc = 0; + m68kpc_offset = addr - m68k_getpc(); + long int pcOffsetSave = m68kpc_offset; + int opwords; + char instrname[20]; + const struct mnemolookup * lookup; + + uint32_t opcode = get_iword_1(m68kpc_offset); + m68kpc_offset += 2; + + if (cpuFunctionTable[opcode] == IllegalOpcode) + opcode = 0x4AFC; + + struct instr * dp = table68k + opcode; + + for(lookup=lookuptab; lookup->mnemo!=dp->mnemo; lookup++) + ; + + strcpy(instrname, lookup->name); + char * ccpt = strstr(instrname, "cc"); + + if (ccpt) + strncpy(ccpt, ccnames[dp->cc], 2); + + sprintf(f, "%s", instrname); + strcat(str, f); + + switch (dp->size) + { + case sz_byte: strcat(str, ".B\t"); break; + case sz_word: strcat(str, ".W\t"); break; + case sz_long: strcat(str, ".L\t"); break; + default: strcat(str, "\t"); break; + } + + // Get source and destination operands (if any) + src[0] = dst[0] = f[0] = 0; + + if (dp->suse) + newpc = m68k_getpc() + m68kpc_offset + + ShowEA(dp->mnemo, dp->sreg, dp->smode, dp->size, src); + + if (dp->duse) + newpc = m68k_getpc() + m68kpc_offset + + ShowEA(dp->mnemo, dp->dreg, dp->dmode, dp->size, dst); + + // Handle execptions to the standard rules + if (dp->mnemo == i_BSR || dp->mnemo == i_Bcc) + sprintf(f, "$%lX", (long)newpc); + else if (dp->mnemo == i_DBcc) + sprintf(f, "%s, $%lX", src, (long)newpc); + else if (dp->mnemo == i_MVMEL) + sprintf(f, "%s, %s", dst, src); + else + sprintf(f, "%s%s%s", src, (dp->suse && dp->duse ? ", " : ""), dst); + + strcat(str, f); + + if (ccpt) + { + sprintf(f, " (%s)", (cctrue(dp->cc) ? "true" : "false")); + strcat(str, f); + } + + // Add byte(s) display to front of disassembly + long int numberOfBytes = m68kpc_offset - pcOffsetSave; + + for(opwords=0; opwords<5; opwords++) + { + if (((opwords + 1) * 2) <= numberOfBytes) + sprintf(f, "%04X ", get_iword_1(pcOffsetSave + opwords * 2)); + else + sprintf(f, " "); + + strcat(output, f); + } + + strcat(output, str); + + return numberOfBytes; +} + + +// +// Disassemble one instruction at pc and store in str_buff +// +unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type) +{ + return M68KDisassemble(str_buff, pc); +} + diff --git a/waterbox/virtualjaguar/src/m68000/m68kinterface.c b/waterbox/virtualjaguar/src/m68000/m68kinterface.c new file mode 100644 index 0000000000..d896cdfe10 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/m68kinterface.c @@ -0,0 +1,763 @@ +// +// m68kinterface.c: Code interface to the UAE 68000 core and support code +// +// by James Hammons +// (C) 2011 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 10/28/2011 Created this file ;-) +// + +#include "m68kinterface.h" +//#include +#include "cpudefs.h" +#include "inlines.h" +#include "cpuextra.h" +#include "readcpu.h" + +// Exception Vectors handled by emulation +#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */ +#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */ +#define EXCEPTION_ILLEGAL_INSTRUCTION 4 +#define EXCEPTION_ZERO_DIVIDE 5 +#define EXCEPTION_CHK 6 +#define EXCEPTION_TRAPV 7 +#define EXCEPTION_PRIVILEGE_VIOLATION 8 +#define EXCEPTION_TRACE 9 +#define EXCEPTION_1010 10 +#define EXCEPTION_1111 11 +#define EXCEPTION_FORMAT_ERROR 14 +#define EXCEPTION_UNINITIALIZED_INTERRUPT 15 +#define EXCEPTION_SPURIOUS_INTERRUPT 24 +#define EXCEPTION_INTERRUPT_AUTOVECTOR 24 +#define EXCEPTION_TRAP_BASE 32 + +// These are found in obj/cpustbl.c (generated by gencpu) + +//extern const struct cputbl op_smalltbl_0_ff[]; /* 68040 */ +//extern const struct cputbl op_smalltbl_1_ff[]; /* 68020 + 68881 */ +//extern const struct cputbl op_smalltbl_2_ff[]; /* 68020 */ +//extern const struct cputbl op_smalltbl_3_ff[]; /* 68010 */ +extern const struct cputbl op_smalltbl_4_ff[]; /* 68000 */ +extern const struct cputbl op_smalltbl_5_ff[]; /* 68000 slow but compatible. */ + +// Externs, supplied by the user... +//extern int irq_ack_handler(int); + +// Function prototypes... +STATIC_INLINE void m68ki_check_interrupts(void); +void m68ki_exception_interrupt(uint32_t intLevel); +STATIC_INLINE uint32_t m68ki_init_exception(void); +STATIC_INLINE void m68ki_stack_frame_3word(uint32_t pc, uint32_t sr); +unsigned long IllegalOpcode(uint32_t opcode); +void BuildCPUFunctionTable(void); +void m68k_set_irq2(unsigned int intLevel); + +// Local "Global" vars +static int32_t initialCycles; +cpuop_func * cpuFunctionTable[65536]; + +// By virtue of the fact that m68k_set_irq() can be called asychronously by +// another thread, we need something along the lines of this: +static int checkForIRQToHandle = 0; +//static pthread_mutex_t executionLock = PTHREAD_MUTEX_INITIALIZER; +static int IRQLevelToHandle = 0; + +#if 0 +#define ADD_CYCLES(A) m68ki_remaining_cycles += (A) +#define USE_CYCLES(A) m68ki_remaining_cycles -= (A) +#define SET_CYCLES(A) m68ki_remaining_cycles = A +#define GET_CYCLES() m68ki_remaining_cycles +#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0 + +#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */ +#define CPU_INT_CYCLES m68ki_cpu.int_cycles /* ASG */ +#define CPU_STOPPED m68ki_cpu.stopped +#define CPU_PREF_ADDR m68ki_cpu.pref_addr +#define CPU_PREF_DATA m68ki_cpu.pref_data +#define CPU_ADDRESS_MASK m68ki_cpu.address_mask +#define CPU_SR_MASK m68ki_cpu.sr_mask +#endif + +#define CPU_DEBUG + + +void Dasm(uint32_t offset, uint32_t qt) +{ +#ifdef CPU_DEBUG +// back up a few instructions... +//offset -= 100; + static char buffer[2048];//, mem[64]; + int pc = offset, oldpc; + uint32_t i; + + for(i=0; i 0); + +#if 0 + /* set previous PC to current PC for the next entry into the loop */ + REG_PPC = REG_PC; + + /* ASG: update cycles */ + USE_CYCLES(CPU_INT_CYCLES); + CPU_INT_CYCLES = 0; + + /* return how many clocks we used */ + return m68ki_initial_cycles - GET_CYCLES(); +#else + regs.remainingCycles -= regs.interruptCycles; + regs.interruptCycles = 0; + + // Return # of clock cycles used + return initialCycles - regs.remainingCycles; +#endif +} + + +void m68k_set_irq(unsigned int intLevel) +{ + // We need to check for stopped state as well... + if (regs.stopped) + { + m68k_set_irq2(intLevel); + return; + } + + // Since this can be called asynchronously, we need to fix it so that it + // doesn't fuck up the main execution loop. + IRQLevelToHandle = intLevel; + checkForIRQToHandle = 1; +} + + +/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */ +void m68k_set_irq2(unsigned int intLevel) +{ +// pthread_mutex_lock(&executionLock); +// printf("m68k_set_irq: Could not get the lock!!!\n"); + + int oldLevel = regs.intLevel; + regs.intLevel = intLevel; + + // A transition from < 7 to 7 always interrupts (NMI) + // Note: Level 7 can also level trigger like a normal IRQ + if (oldLevel != 0x07 && regs.intLevel == 0x07) + m68ki_exception_interrupt(7); // Edge triggered level 7 (NMI) + else + m68ki_check_interrupts(); // Level triggered (IRQ) + +// pthread_mutex_unlock(&executionLock); +} + + +// Check for interrupts +STATIC_INLINE void m68ki_check_interrupts(void) +{ +#if 0 + if(CPU_INT_LEVEL > FLAG_INT_MASK) + m68ki_exception_interrupt(CPU_INT_LEVEL>>8); +#else + if (regs.intLevel > regs.intmask) + m68ki_exception_interrupt(regs.intLevel); +#endif +} + + +// Service an interrupt request and start exception processing +void m68ki_exception_interrupt(uint32_t intLevel) +{ +#if 0 + uint vector; + uint sr; + uint new_pc; + + /* Turn off the stopped state */ + CPU_STOPPED &= ~STOP_LEVEL_STOP; + + /* If we are halted, don't do anything */ + if(CPU_STOPPED) + return; + + /* Acknowledge the interrupt */ + vector = m68ki_int_ack(int_level); + + /* Get the interrupt vector */ + if(vector == M68K_INT_ACK_AUTOVECTOR) + /* Use the autovectors. This is the most commonly used implementation */ + vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level; + else if(vector == M68K_INT_ACK_SPURIOUS) + /* Called if no devices respond to the interrupt acknowledge */ + vector = EXCEPTION_SPURIOUS_INTERRUPT; + else if(vector > 255) + { + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); + return; + } + + /* Start exception processing */ + sr = m68ki_init_exception(); + + /* Set the interrupt mask to the level of the one being serviced */ + FLAG_INT_MASK = int_level<<8; + + /* Get the new PC */ + new_pc = m68ki_read_data_32((vector<<2) + REG_VBR); + + /* If vector is uninitialized, call the uninitialized interrupt vector */ + if(new_pc == 0) + new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR); + + /* Generate a stack frame */ + m68ki_stack_frame_0000(REG_PC, sr, vector); + + if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Create throwaway frame */ + m68ki_set_sm_flag(FLAG_S); /* clear M */ + sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */ + m68ki_stack_frame_0001(REG_PC, sr, vector); + } + + m68ki_jump(new_pc); + + /* Defer cycle counting until later */ + CPU_INT_CYCLES += CYC_EXCEPTION[vector]; + +#if !M68K_EMULATE_INT_ACK + /* Automatically clear IRQ if we are not using an acknowledge scheme */ + CPU_INT_LEVEL = 0; +#endif /* M68K_EMULATE_INT_ACK */ +#else + // Turn off the stopped state (N.B.: normal 68K behavior!) + regs.stopped = 0; + +//JLH: need to add halt state? +// prolly, for debugging/alpine mode... :-/ +// but then again, this should be handled already by the main execution loop :-P + // If we are halted, don't do anything +// if (regs.halted) +// return; + + // Acknowledge the interrupt (NOTE: This is a user supplied function!) + uint32_t vector = irq_ack_handler(intLevel); + + // Get the interrupt vector + if (vector == M68K_INT_ACK_AUTOVECTOR) + // Use the autovectors. This is the most commonly used implementation + vector = EXCEPTION_INTERRUPT_AUTOVECTOR + intLevel; + else if (vector == M68K_INT_ACK_SPURIOUS) + // Called if no devices respond to the interrupt acknowledge + vector = EXCEPTION_SPURIOUS_INTERRUPT; + else if (vector > 255) + { +// M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", +// m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); + return; + } + + // Start exception processing + uint32_t sr = m68ki_init_exception(); + + // Set the interrupt mask to the level of the one being serviced + regs.intmask = intLevel; + +#if 0 +extern int startM68KTracing; +if (startM68KTracing) +{ + printf("IRQ: old PC=%06X, ", regs.pc); +} +#endif + + // Get the new PC + uint32_t newPC = m68k_read_memory_32(vector << 2); + +#if 0 +if (startM68KTracing) +{ + printf("new PC=%06X, vector=%u, ", newPC, vector); +} +#endif + + // If vector is uninitialized, call the uninitialized interrupt vector + if (newPC == 0) + newPC = m68k_read_memory_32(EXCEPTION_UNINITIALIZED_INTERRUPT << 2); + + // Generate a stack frame + m68ki_stack_frame_3word(regs.pc, sr); + + m68k_setpc(newPC); +#if 0 +if (startM68KTracing) +{ + printf("(PC=%06X)\n", regs.pc); +} +#endif + + // Defer cycle counting until later + regs.interruptCycles += 56; // NOT ACCURATE-- !!! FIX !!! +// CPU_INT_CYCLES += CYC_EXCEPTION[vector]; +#endif +} + + +// Initiate exception processing +STATIC_INLINE uint32_t m68ki_init_exception(void) +{ +#if 0 + /* Save the old status register */ + uint sr = m68ki_get_sr(); + + /* Turn off trace flag, clear pending traces */ + FLAG_T1 = FLAG_T0 = 0; + m68ki_clear_trace(); + /* Enter supervisor mode */ + m68ki_set_s_flag(SFLAG_SET); + + return sr; +#else + MakeSR(); + uint32_t sr = regs.sr; // Save old status register + regs.s = 1; // Set supervisor mode + + return sr; +#endif +} + + +// 3 word stack frame (68000 only) +STATIC_INLINE void m68ki_stack_frame_3word(uint32_t pc, uint32_t sr) +{ +#if 0 + m68ki_push_32(pc); + m68ki_push_16(sr); +#else + // Push PC on stack: + m68k_areg(regs, 7) -= 4; + m68k_write_memory_32(m68k_areg(regs, 7), pc); + // Push SR on stack: + m68k_areg(regs, 7) -= 2; + m68k_write_memory_16(m68k_areg(regs, 7), sr); +#endif +} + + +unsigned int m68k_get_reg(void * context, m68k_register_t reg) +{ + if (reg <= M68K_REG_A7) + return regs.regs[reg]; + else if (reg == M68K_REG_PC) + return regs.pc; + else if (reg == M68K_REG_SR) + { + MakeSR(); + return regs.sr; + } + else if (reg == M68K_REG_SP) + return regs.regs[15]; + + return 0; +} + + +void m68k_set_reg(m68k_register_t reg, unsigned int value) +{ + if (reg <= M68K_REG_A7) + regs.regs[reg] = value; + else if (reg == M68K_REG_PC) + regs.pc = value; + else if (reg == M68K_REG_SR) + { + regs.sr = value; + MakeFromSR(); + } + else if (reg == M68K_REG_SP) + regs.regs[15] = value; +} + + +// +// Check if the instruction is a valid one +// +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type) +{ + instruction &= 0xFFFF; + + if (cpuFunctionTable[instruction] == IllegalOpcode) + return 0; + + return 1; +} + + +// Dummy functions, for now, until we prove the concept here. :-) + +// Temp, while we're using the Musashi disassembler... +#if 0 +unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type) +{ + return 0; +} +#endif + +int m68k_cycles_run(void) {} /* Number of cycles run so far */ +int m68k_cycles_remaining(void) {} /* Number of cycles left */ +//void m68k_modify_timeslice(int cycles) {} /* Modify cycles left */ +//void m68k_end_timeslice(void) {} /* End timeslice now */ + + +void m68k_modify_timeslice(int cycles) +{ + regs.remainingCycles = cycles; +} + + +void m68k_end_timeslice(void) +{ +#if 0 + m68ki_initial_cycles = GET_CYCLES(); + SET_CYCLES(0); +#else + initialCycles = regs.remainingCycles; + regs.remainingCycles = 0; +#endif +} + + +unsigned long IllegalOpcode(uint32_t opcode) +{ +#if 0 + uint32_t pc = m68k_getpc (); +#endif + if ((opcode & 0xF000) == 0xF000) + { + Exception(0x0B, 0, M68000_EXC_SRC_CPU); // LineF exception... + return 4; + } + else if ((opcode & 0xF000) == 0xA000) + { + Exception(0x0A, 0, M68000_EXC_SRC_CPU); // LineA exception... + return 4; + } + +#if 0 + write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc); +#endif + + Exception(0x04, 0, M68000_EXC_SRC_CPU); // Illegal opcode exception... + return 4; +} + + +void BuildCPUFunctionTable(void) +{ + int i; + unsigned long opcode; + + // We're only using the "fast" 68000 emulation here, not the "compatible" + // ("fast" doesn't throw exceptions, so we're using "compatible" now :-P) +#if 0 + const struct cputbl * tbl = (currprefs.cpu_compatible + ? op_smalltbl_5_ff : op_smalltbl_4_ff); +#else +//let's try "compatible" and see what happens here... +// const struct cputbl * tbl = op_smalltbl_4_ff; + const struct cputbl * tbl = op_smalltbl_5_ff; +#endif + +// Log_Printf(LOG_DEBUG, "Building CPU function table (%d %d %d).\n", +// currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24); + + // Set all instructions to Illegal... + for(opcode=0; opcode<65536; opcode++) + cpuFunctionTable[opcode] = IllegalOpcode; + + // Move functions from compact table into our full function table... + for(i=0; tbl[i].handler!=NULL; i++) + cpuFunctionTable[tbl[i].opcode] = tbl[i].handler; + +//JLH: According to readcpu.c, handler is set to -1 and never changes. +// Actually, it does read this crap in readcpu.c, do_merges() does it... :-P +// Again, seems like a build time thing could be done here... +#if 1 + for(opcode=0; opcode<65536; opcode++) + { +// if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level) + if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > 0) + continue; + + if (table68k[opcode].handler != -1) + { +//printf("Relocate: $%04X->$%04X\n", table68k[opcode].handler, opcode); + cpuop_func * f = cpuFunctionTable[table68k[opcode].handler]; + + if (f == IllegalOpcode) + abort(); + + cpuFunctionTable[opcode] = f; + } + } +#endif +} diff --git a/waterbox/virtualjaguar/src/m68000/m68kinterface.h b/waterbox/virtualjaguar/src/m68000/m68kinterface.h new file mode 100644 index 0000000000..84c87af9f3 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/m68kinterface.h @@ -0,0 +1,137 @@ +// +// C interface to the UAE core +// +// by James Hammons +// (C) 2011 Underground Software +// +// Most of these functions are in place to help make it easy to replace the +// Musashi core with my bastardized UAE one. :-) +// + +#ifndef __M68KINTERFACE_H__ +#define __M68KINTERFACE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Registers used by m68k_get_reg() and m68k_set_reg() */ +typedef enum +{ + /* Real registers */ + M68K_REG_D0, /* Data registers */ + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, /* Address registers */ + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_PC, /* Program Counter */ + M68K_REG_SR, /* Status Register */ + M68K_REG_SP, /* The current Stack Pointer (located in A7) */ + M68K_REG_USP, /* User Stack Pointer */ + + /* Assumed registers */ + /* These are cheat registers which emulate the 1-longword prefetch + * present in the 68000 and 68010. + */ + M68K_REG_PREF_ADDR, /* Last prefetch address */ + M68K_REG_PREF_DATA, /* Last prefetch data */ + + /* Convenience registers */ + M68K_REG_PPC, /* Previous value in the program counter */ + M68K_REG_IR, /* Instruction register */ +} m68k_register_t; + +/* Special interrupt acknowledge values. + * Use these as special returns from the interrupt acknowledge callback + * (specified later in this header). + */ + +/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. + * This happens in a real 68K if VPA or AVEC is asserted during an interrupt + * acknowledge cycle instead of DTACK. + */ +#define M68K_INT_ACK_AUTOVECTOR 0xFFFFFFFF + +/* Causes the spurious interrupt vector (0x18) to be taken + * This happens in a real 68K if BERR is asserted during the interrupt + * acknowledge cycle (i.e. no devices responded to the acknowledge). + */ +#define M68K_INT_ACK_SPURIOUS 0xFFFFFFFE + +void m68k_set_cpu_type(unsigned int); +void m68k_pulse_reset(void); +int m68k_execute(int num_cycles); +void m68k_set_irq(unsigned int int_level); + +// Functions that MUST be implemented by the user: + +// Read from anywhere +unsigned int m68k_read_memory_8(unsigned int address); +unsigned int m68k_read_memory_16(unsigned int address); +unsigned int m68k_read_memory_32(unsigned int address); + +// Write to anywhere +void m68k_write_memory_8(unsigned int address, unsigned int value); +void m68k_write_memory_16(unsigned int address, unsigned int value); +void m68k_write_memory_32(unsigned int address, unsigned int value); + +int irq_ack_handler(int); + +// Convenience functions + +// Uncomment this to have the emulated CPU call a hook function after every instruction +// NB: This must be implemented by the user! +#define M68K_HOOK_FUNCTION +#ifdef M68K_HOOK_FUNCTION +void M68KInstructionHook(void); +#endif + +// Functions to allow debugging +void M68KDebugHalt(void); +void M68KDebugResume(void); + +/* Peek at the internals of a CPU context. This can either be a context + * retrieved using m68k_get_context() or the currently running context. + * If context is NULL, the currently running CPU context will be used. + */ +unsigned int m68k_get_reg(void * context, m68k_register_t reg); + +/* Poke values into the internals of the currently running CPU context */ +void m68k_set_reg(m68k_register_t reg, unsigned int value); + +// Dummy functions, for now... + +/* Check if an instruction is valid for the specified CPU type */ +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); + +/* Disassemble 1 instruction using the epecified CPU type at pc. Stores + * disassembly in str_buff and returns the size of the instruction in bytes. + */ +unsigned int m68k_disassemble(char * str_buff, unsigned int pc, unsigned int cpu_type); + +/* These functions let you read/write/modify the number of cycles left to run + * while m68k_execute() is running. + * These are useful if the 68k accesses a memory-mapped port on another device + * that requires immediate processing by another CPU. + */ +int m68k_cycles_run(void); // Number of cycles run so far +int m68k_cycles_remaining(void); // Number of cycles left +void m68k_modify_timeslice(int cycles); // Modify cycles left +void m68k_end_timeslice(void); // End timeslice now + +#ifdef __cplusplus +} +#endif + +#endif // __M68KINTERFACE_H__ diff --git a/waterbox/virtualjaguar/src/m68000/readcpu.c b/waterbox/virtualjaguar/src/m68000/readcpu.c new file mode 100644 index 0000000000..4fcb100926 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/readcpu.c @@ -0,0 +1,1123 @@ +/* + * UAE - The Un*x Amiga Emulator - CPU core + * + * Read 68000 CPU specs from file "table68k" + * + * Copyright 1995,1996 Bernd Schmidt + * + * Adaptation to Hatari by Thomas Huth + * Adaptation to Virtual Jaguar by James Hammons + * + * This file is distributed under the GNU Public License, version 3 or at + * your option any later version. Read the file GPLv3 for details. + */ + + +/* 2008/04/26 [NP] Handle sz_byte for Areg as a valid srcmode if current instruction is a MOVE */ +/* (e.g. move.b a1,(a0) ($1089)) (fix Blood Money on Superior 65) */ + + +//const char ReadCpu_fileid[] = "Hatari readcpu.c : " __DATE__ " " __TIME__; + +#include +#include + +#include "readcpu.h" + +int nr_cpuop_funcs; + +const struct mnemolookup lookuptab[] = { + { i_ILLG, "ILLEGAL" }, + { i_OR, "OR" }, + { i_CHK, "CHK" }, + { i_CHK2, "CHK2" }, + { i_AND, "AND" }, + { i_EOR, "EOR" }, + { i_ORSR, "ORSR" }, + { i_ANDSR, "ANDSR" }, + { i_EORSR, "EORSR" }, + { i_SUB, "SUB" }, + { i_SUBA, "SUBA" }, + { i_SUBX, "SUBX" }, + { i_SBCD, "SBCD" }, + { i_ADD, "ADD" }, + { i_ADDA, "ADDA" }, + { i_ADDX, "ADDX" }, + { i_ABCD, "ABCD" }, + { i_NEG, "NEG" }, + { i_NEGX, "NEGX" }, + { i_NBCD, "NBCD" }, + { i_CLR, "CLR" }, + { i_NOT, "NOT" }, + { i_TST, "TST" }, + { i_BTST, "BTST" }, + { i_BCHG, "BCHG" }, + { i_BCLR, "BCLR" }, + { i_BSET, "BSET" }, + { i_CMP, "CMP" }, + { i_CMPM, "CMPM" }, + { i_CMPA, "CMPA" }, + { i_MVPRM, "MVPRM" }, + { i_MVPMR, "MVPMR" }, + { i_MOVE, "MOVE" }, + { i_MOVEA, "MOVEA" }, + { i_MVSR2, "MVSR2" }, + { i_MV2SR, "MV2SR" }, + { i_SWAP, "SWAP" }, + { i_EXG, "EXG" }, + { i_EXT, "EXT" }, + { i_MVMEL, "MVMEL" }, + { i_MVMLE, "MVMLE" }, + { i_TRAP, "TRAP" }, + { i_MVR2USP, "MVR2USP" }, + { i_MVUSP2R, "MVUSP2R" }, + { i_NOP, "NOP" }, + { i_RESET, "RESET" }, + { i_RTE, "RTE" }, + { i_RTD, "RTD" }, + { i_LINK, "LINK" }, + { i_UNLK, "UNLK" }, + { i_RTS, "RTS" }, + { i_STOP, "STOP" }, + { i_TRAPV, "TRAPV" }, + { i_RTR, "RTR" }, + { i_JSR, "JSR" }, + { i_JMP, "JMP" }, + { i_BSR, "BSR" }, + { i_Bcc, "Bcc" }, + { i_LEA, "LEA" }, + { i_PEA, "PEA" }, + { i_DBcc, "DBcc" }, + { i_Scc, "Scc" }, + { i_DIVU, "DIVU" }, + { i_DIVS, "DIVS" }, + { i_MULU, "MULU" }, + { i_MULS, "MULS" }, + { i_ASR, "ASR" }, + { i_ASL, "ASL" }, + { i_LSR, "LSR" }, + { i_LSL, "LSL" }, + { i_ROL, "ROL" }, + { i_ROR, "ROR" }, + { i_ROXL, "ROXL" }, + { i_ROXR, "ROXR" }, + { i_ASRW, "ASRW" }, + { i_ASLW, "ASLW" }, + { i_LSRW, "LSRW" }, + { i_LSLW, "LSLW" }, + { i_ROLW, "ROLW" }, + { i_RORW, "RORW" }, + { i_ROXLW, "ROXLW" }, + { i_ROXRW, "ROXRW" }, + + { i_MOVE2C, "MOVE2C" }, + { i_MOVEC2, "MOVEC2" }, + { i_CAS, "CAS" }, + { i_CAS2, "CAS2" }, + { i_MULL, "MULL" }, + { i_DIVL, "DIVL" }, + { i_BFTST, "BFTST" }, + { i_BFEXTU, "BFEXTU" }, + { i_BFCHG, "BFCHG" }, + { i_BFEXTS, "BFEXTS" }, + { i_BFCLR, "BFCLR" }, + { i_BFFFO, "BFFFO" }, + { i_BFSET, "BFSET" }, + { i_BFINS, "BFINS" }, + { i_PACK, "PACK" }, + { i_UNPK, "UNPK" }, + { i_TAS, "TAS" }, + { i_BKPT, "BKPT" }, + { i_CALLM, "CALLM" }, + { i_RTM, "RTM" }, + { i_TRAPcc, "TRAPcc" }, + { i_MOVES, "MOVES" }, + { i_FPP, "FPP" }, + { i_FDBcc, "FDBcc" }, + { i_FScc, "FScc" }, + { i_FTRAPcc, "FTRAPcc" }, + { i_FBcc, "FBcc" }, + { i_FBcc, "FBcc" }, + { i_FSAVE, "FSAVE" }, + { i_FRESTORE, "FRESTORE" }, + + { i_CINVL, "CINVL" }, + { i_CINVP, "CINVP" }, + { i_CINVA, "CINVA" }, + { i_CPUSHL, "CPUSHL" }, + { i_CPUSHP, "CPUSHP" }, + { i_CPUSHA, "CPUSHA" }, + { i_MOVE16, "MOVE16" }, + + { i_MMUOP, "MMUOP" }, + { i_ILLG, "" }, +}; + + +struct instr * table68k; + + +STATIC_INLINE amodes mode_from_str(const char * str) +{ + if (strncmp (str, "Dreg", 4) == 0) return Dreg; + if (strncmp (str, "Areg", 4) == 0) return Areg; + if (strncmp (str, "Aind", 4) == 0) return Aind; + if (strncmp (str, "Apdi", 4) == 0) return Apdi; + if (strncmp (str, "Aipi", 4) == 0) return Aipi; + if (strncmp (str, "Ad16", 4) == 0) return Ad16; + if (strncmp (str, "Ad8r", 4) == 0) return Ad8r; + if (strncmp (str, "absw", 4) == 0) return absw; + if (strncmp (str, "absl", 4) == 0) return absl; + if (strncmp (str, "PC16", 4) == 0) return PC16; + if (strncmp (str, "PC8r", 4) == 0) return PC8r; + if (strncmp (str, "Immd", 4) == 0) return imm; + + abort(); + return 0; +} + + +STATIC_INLINE amodes mode_from_mr(int mode, int reg) +{ + switch (mode) + { + case 0: return Dreg; + case 1: return Areg; + case 2: return Aind; + case 3: return Aipi; + case 4: return Apdi; + case 5: return Ad16; + case 6: return Ad8r; + case 7: + switch (reg) + { + case 0: return absw; + case 1: return absl; + case 2: return PC16; + case 3: return PC8r; + case 4: return imm; + case 5: + case 6: + case 7: return am_illg; + } + } + + abort(); + return 0; +} + + +static void build_insn(int insn) +{ + int find = -1; + int variants; + int isjmp = 0; + struct instr_def id; + const char * opcstr; + int j; + + int flaglive = 0, flagdead = 0; + id = defs68k[insn]; + + /* Note: We treat anything with unknown flags as a jump. That + is overkill, but "the programmer" was lazy quite often, and + *this* programmer can't be bothered to work out what can and + can't trap. Usually, this will be overwritten with the gencomp + based information, anyway. */ + + for(j=0; j<5; j++) + { + switch (id.flaginfo[j].flagset) + { + case fa_unset: break; + case fa_isjmp: isjmp = 1; break; + case fa_isbranch: isjmp = 1; break; + case fa_zero: flagdead |= 1 << j; break; + case fa_one: flagdead |= 1 << j; break; + case fa_dontcare: flagdead |= 1 << j; break; + case fa_unknown: isjmp = 1; flagdead = -1; goto out1; + case fa_set: flagdead |= 1 << j; break; + } + } + +out1: + for(j=0; j<5; j++) + { + switch (id.flaginfo[j].flaguse) + { + case fu_unused: break; + case fu_isjmp: isjmp = 1; flaglive |= 1 << j; break; + case fu_maybecc: isjmp = 1; flaglive |= 1 << j; break; + case fu_unknown: isjmp = 1; flaglive |= 1 << j; break; + case fu_used: flaglive |= 1 << j; break; + } + } + + opcstr = id.opcstr; + + for(variants=0; variants<(1 << id.n_variable); variants++) + { + int bitcnt[lastbit]; + int bitval[lastbit]; + int bitpos[lastbit]; + int i; + uint16_t opc = id.bits; + uint16_t msk, vmsk; + int pos = 0; + int mnp = 0; + int bitno = 0; + char mnemonic[10]; + + wordsizes sz = sz_long; + int srcgather = 0, dstgather = 0; + int usesrc = 0, usedst = 0; + int srctype = 0; + int srcpos = -1, dstpos = -1; + + amodes srcmode = am_unknown, destmode = am_unknown; + int srcreg = -1, destreg = -1; + + for(i=0; i>= 1) + { + if (!(msk & id.mask)) + { + int currbit = id.bitpos[bitno++]; + int bit_set; + vmsk >>= 1; + bit_set = (variants & vmsk ? 1 : 0); + + if (bit_set) + opc |= msk; + + bitpos[currbit] = 15 - i; + bitcnt[currbit]++; + bitval[currbit] <<= 1; + bitval[currbit] |= bit_set; + } + } + + if (bitval[bitj] == 0) + bitval[bitj] = 8; + + /* first check whether this one does not match after all */ + if (bitval[bitz] == 3 || bitval[bitC] == 1) + continue; + + if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff)) + continue; + + /* bitI and bitC get copied to biti and bitc */ + if (bitcnt[bitI]) + { + bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI]; + } + + if (bitcnt[bitC]) + bitval[bitc] = bitval[bitC]; + + pos = 0; + while (opcstr[pos] && !isspace((unsigned)opcstr[pos])) + { + if (opcstr[pos] == '.') + { + pos++; + + switch (opcstr[pos]) + { + case 'B': sz = sz_byte; break; + case 'W': sz = sz_word; break; + case 'L': sz = sz_long; break; + case 'z': + switch (bitval[bitz]) + { + case 0: sz = sz_byte; break; + case 1: sz = sz_word; break; + case 2: sz = sz_long; break; + default: abort(); + } + break; + default: abort(); + } + } + else + { + mnemonic[mnp] = opcstr[pos]; + + if (mnemonic[mnp] == 'f') + { + find = -1; + switch (bitval[bitf]) + { + case 0: mnemonic[mnp] = 'R'; break; + case 1: mnemonic[mnp] = 'L'; break; + default: abort(); + } + } + + mnp++; + } + + pos++; + } + + mnemonic[mnp] = 0; + + /* now, we have read the mnemonic and the size */ + while (opcstr[pos] && isspace((unsigned)opcstr[pos])) + pos++; + + /* A goto a day keeps the D******a away. */ + if (opcstr[pos] == 0) + goto endofline; + + /* parse the source address */ + usesrc = 1; + switch (opcstr[pos++]) + { + case 'D': + srcmode = Dreg; + + switch (opcstr[pos++]) + { + case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; + case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; + default: abort(); + } + + break; + case 'A': + srcmode = Areg; + + switch (opcstr[pos++]) + { + case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; + case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; + default: abort(); + } + + switch (opcstr[pos]) + { + case 'p': srcmode = Apdi; pos++; break; + case 'P': srcmode = Aipi; pos++; break; + } + break; + + case 'L': + srcmode = absl; + break; + case '#': + switch (opcstr[pos++]) + { + case 'z': srcmode = imm; break; + case '0': srcmode = imm0; break; + case '1': srcmode = imm1; break; + case '2': srcmode = imm2; break; + case 'i': + srcmode = immi; srcreg = (int32_t)(int8_t)bitval[biti]; + + if (CPU_EMU_SIZE < 4) + { + /* Used for branch instructions */ + srctype = 1; + srcgather = 1; + srcpos = bitpos[biti]; + } + + break; + case 'j': + srcmode = immi; srcreg = bitval[bitj]; + + if (CPU_EMU_SIZE < 3) + { + /* 1..8 for ADDQ/SUBQ and rotshi insns */ + srcgather = 1; + srctype = 3; + srcpos = bitpos[bitj]; + } + + break; + case 'J': + srcmode = immi; srcreg = bitval[bitJ]; + + if (CPU_EMU_SIZE < 5) + { + /* 0..15 */ + srcgather = 1; + srctype = 2; + srcpos = bitpos[bitJ]; + } + + break; + case 'k': + srcmode = immi; srcreg = bitval[bitk]; + + if (CPU_EMU_SIZE < 3) + { + srcgather = 1; + srctype = 4; + srcpos = bitpos[bitk]; + } + + break; + case 'K': + srcmode = immi; srcreg = bitval[bitK]; + + if (CPU_EMU_SIZE < 5) + { + /* 0..15 */ + srcgather = 1; + srctype = 5; + srcpos = bitpos[bitK]; + } + + break; + case 'p': + srcmode = immi; srcreg = bitval[bitK]; + + if (CPU_EMU_SIZE < 5) + { + /* 0..3 */ + srcgather = 1; + srctype = 7; + srcpos = bitpos[bitp]; + } + + break; + default: abort(); + } + + break; + case 'd': + srcreg = bitval[bitD]; + srcmode = mode_from_mr(bitval[bitd],bitval[bitD]); + + if (srcmode == am_illg) + continue; + + if (CPU_EMU_SIZE < 2 + && (srcmode == Areg || srcmode == Dreg || srcmode == Aind + || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi + || srcmode == Apdi)) + { + srcgather = 1; + srcpos = bitpos[bitD]; + } + + if (opcstr[pos] == '[') + { + pos++; + + if (opcstr[pos] == '!') + { + /* exclusion */ + do + { + pos++; + + if (mode_from_str(opcstr + pos) == srcmode) + goto nomatch; + + pos += 4; + } + while (opcstr[pos] == ','); + + pos++; + } + else + { + if (opcstr[pos + 4] == '-') + { + /* replacement */ + if (mode_from_str(opcstr + pos) == srcmode) + srcmode = mode_from_str(opcstr + pos + 5); + else + goto nomatch; + + pos += 10; + } + else + { + /* normal */ + while(mode_from_str(opcstr + pos) != srcmode) + { + pos += 4; + + if (opcstr[pos] == ']') + goto nomatch; + + pos++; + } + + while(opcstr[pos] != ']') + pos++; + + pos++; + break; + } + } + } + + /* Some addressing modes are invalid as destination */ + if (srcmode == imm || srcmode == PC16 || srcmode == PC8r) + goto nomatch; + + break; + case 's': + srcreg = bitval[bitS]; + srcmode = mode_from_mr(bitval[bits],bitval[bitS]); + + if (srcmode == am_illg) + continue; + + if (CPU_EMU_SIZE < 2 + && (srcmode == Areg || srcmode == Dreg || srcmode == Aind + || srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi + || srcmode == Apdi)) + { + srcgather = 1; + srcpos = bitpos[bitS]; + } + + if (opcstr[pos] == '[') + { + pos++; + + if (opcstr[pos] == '!') + { + /* exclusion */ + do + { + pos++; + + if (mode_from_str(opcstr + pos) == srcmode) + goto nomatch; + + pos += 4; + } + while (opcstr[pos] == ','); + + pos++; + } + else + { + if (opcstr[pos + 4] == '-') + { + /* replacement */ + if (mode_from_str(opcstr + pos) == srcmode) + srcmode = mode_from_str(opcstr + pos + 5); + else + goto nomatch; + + pos += 10; + } + else + { + /* normal */ + while(mode_from_str(opcstr+pos) != srcmode) + { + pos += 4; + + if (opcstr[pos] == ']') + goto nomatch; + + pos++; + } + + while(opcstr[pos] != ']') + pos++; + + pos++; + } + } + } + break; + default: abort(); + } + + /* safety check - might have changed */ + if (srcmode != Areg && srcmode != Dreg && srcmode != Aind + && srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi + && srcmode != Apdi && srcmode != immi) + { + srcgather = 0; + } + +// if (srcmode == Areg && sz == sz_byte) + if (srcmode == Areg && sz == sz_byte && strcmp(mnemonic, "MOVE") != 0 ) // [NP] move.b is valid on 68000 + goto nomatch; + + if (opcstr[pos] != ',') + goto endofline; + + pos++; + + /* parse the destination address */ + usedst = 1; + + switch (opcstr[pos++]) + { + case 'D': + destmode = Dreg; + + switch (opcstr[pos++]) + { + case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; + case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; + default: abort(); + } + + if (dstpos < 0 || dstpos >= 32) + abort(); + + break; + case 'A': + destmode = Areg; + + switch (opcstr[pos++]) + { + case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; + case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; + case 'x': destreg = 0; dstgather = 0; dstpos = 0; break; + default: abort(); + } + + if (dstpos < 0 || dstpos >= 32) + abort(); + + switch (opcstr[pos]) + { + case 'p': destmode = Apdi; pos++; break; + case 'P': destmode = Aipi; pos++; break; + } + + break; + case 'L': + destmode = absl; + break; + case '#': + switch (opcstr[pos++]) + { + case 'z': destmode = imm; break; + case '0': destmode = imm0; break; + case '1': destmode = imm1; break; + case '2': destmode = imm2; break; + case 'i': destmode = immi; destreg = (int32_t)(int8_t)bitval[biti]; break; + case 'j': destmode = immi; destreg = bitval[bitj]; break; + case 'J': destmode = immi; destreg = bitval[bitJ]; break; + case 'k': destmode = immi; destreg = bitval[bitk]; break; + case 'K': destmode = immi; destreg = bitval[bitK]; break; + default: abort(); + } + break; + case 'd': + destreg = bitval[bitD]; + destmode = mode_from_mr(bitval[bitd],bitval[bitD]); + + if (destmode == am_illg) + continue; + + if (CPU_EMU_SIZE < 1 + && (destmode == Areg || destmode == Dreg || destmode == Aind + || destmode == Ad16 || destmode == Ad8r || destmode == Aipi + || destmode == Apdi)) + { + dstgather = 1; + dstpos = bitpos[bitD]; + } + + if (opcstr[pos] == '[') + { + pos++; + + if (opcstr[pos] == '!') + { + /* exclusion */ + do + { + pos++; + + if (mode_from_str(opcstr + pos) == destmode) + goto nomatch; + + pos += 4; + } + while (opcstr[pos] == ','); + + pos++; + } + else + { + if (opcstr[pos+4] == '-') + { + /* replacement */ + if (mode_from_str(opcstr + pos) == destmode) + destmode = mode_from_str(opcstr + pos + 5); + else + goto nomatch; + + pos += 10; + } + else + { + /* normal */ + while(mode_from_str(opcstr + pos) != destmode) + { + pos += 4; + + if (opcstr[pos] == ']') + goto nomatch; + + pos++; + } + + while(opcstr[pos] != ']') + pos++; + + pos++; + break; + } + } + } + + /* Some addressing modes are invalid as destination */ + if (destmode == imm || destmode == PC16 || destmode == PC8r) + goto nomatch; + + break; + case 's': + destreg = bitval[bitS]; + destmode = mode_from_mr(bitval[bits], bitval[bitS]); + + if (destmode == am_illg) + continue; + if (CPU_EMU_SIZE < 1 + && (destmode == Areg || destmode == Dreg || destmode == Aind + || destmode == Ad16 || destmode == Ad8r || destmode == Aipi + || destmode == Apdi)) + { + dstgather = 1; + dstpos = bitpos[bitS]; + } + + if (opcstr[pos] == '[') + { + pos++; + + if (opcstr[pos] == '!') + { + /* exclusion */ + do + { + pos++; + + if (mode_from_str(opcstr + pos) == destmode) + goto nomatch; + + pos += 4; + } + while (opcstr[pos] == ','); + + pos++; + } + else + { + if (opcstr[pos+4] == '-') + { + /* replacement */ + if (mode_from_str(opcstr + pos) == destmode) + destmode = mode_from_str(opcstr + pos + 5); + else + goto nomatch; + + pos += 10; + } + else + { + /* normal */ + while (mode_from_str(opcstr + pos) != destmode) + { + pos += 4; + + if (opcstr[pos] == ']') + goto nomatch; + + pos++; + } + + while (opcstr[pos] != ']') + pos++; + + pos++; + } + } + } + break; + default: abort(); + } + + /* safety check - might have changed */ + if (destmode != Areg && destmode != Dreg && destmode != Aind + && destmode != Ad16 && destmode != Ad8r && destmode != Aipi + && destmode != Apdi) + { + dstgather = 0; + } + + if (destmode == Areg && sz == sz_byte) + goto nomatch; +#if 0 + if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) { + dstgather = 0; + } +#endif +endofline: + /* now, we have a match */ + if (table68k[opc].mnemo != i_ILLG) + fprintf(stderr, "Double match: %x: %s\n", opc, opcstr); + + if (find == -1) + { + for(find=0; ; find++) + { + if (strcmp(mnemonic, lookuptab[find].name) == 0) + { + table68k[opc].mnemo = lookuptab[find].mnemo; + break; + } + + if (strlen(lookuptab[find].name) == 0) + abort(); + } + } + else + { + table68k[opc].mnemo = lookuptab[find].mnemo; + } + + table68k[opc].cc = bitval[bitc]; + + if (table68k[opc].mnemo == i_BTST + || table68k[opc].mnemo == i_BSET + || table68k[opc].mnemo == i_BCLR + || table68k[opc].mnemo == i_BCHG) + { + sz = (destmode == Dreg ? sz_long : sz_byte); + } + + table68k[opc].size = sz; + table68k[opc].sreg = srcreg; + table68k[opc].dreg = destreg; + table68k[opc].smode = srcmode; + table68k[opc].dmode = destmode; + table68k[opc].spos = (srcgather ? srcpos : -1); + table68k[opc].dpos = (dstgather ? dstpos : -1); + table68k[opc].suse = usesrc; + table68k[opc].duse = usedst; + table68k[opc].stype = srctype; + table68k[opc].plev = id.plevel; + table68k[opc].clev = id.cpulevel; +#if 0 + for (i = 0; i < 5; i++) { + table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset; + table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse; + } +#endif + table68k[opc].flagdead = flagdead; + table68k[opc].flaglive = flaglive; + table68k[opc].isjmp = isjmp; + +nomatch: + /* FOO! */; + } +} + + +void read_table68k(void) +{ + int i; + table68k = (struct instr *)malloc(65536 * sizeof(struct instr)); + + for(i=0; i<65536; i++) + { + table68k[i].mnemo = i_ILLG; + table68k[i].handler = -1; + } + + for(i=0; i +//0011 0001 1100 0011 : DDD = 0, ddd = 7, sss = 0, SSS = 3 + + if (table68k[opcode].spos == -1) + { + sbitdst = 1; + smsk = 0; + } + else + { + switch (table68k[opcode].stype) + { + case 0: + smsk = 7; sbitdst = 8; break; + case 1: + smsk = 255; sbitdst = 256; break; + case 2: + smsk = 15; sbitdst = 16; break; + case 3: + smsk = 7; sbitdst = 8; break; + case 4: + smsk = 7; sbitdst = 8; break; + case 5: + smsk = 63; sbitdst = 64; break; + case 7: + smsk = 3; sbitdst = 4; break; + default: + smsk = 0; sbitdst = 0; + abort(); + break; + } + + smsk <<= table68k[opcode].spos; + } + + if (table68k[opcode].dpos == -1) + { + dmsk = 0; + dstend = 1; + } + else + { + dmsk = 7 << table68k[opcode].dpos; + dstend = 8; + } + + for(srcreg=0; srcreg$%04X)\n", (uint16_t)opcode, code); + printf(" handler: %08X\n", table68k[code].handler); + printf(" dreg: %i\n", table68k[code].dreg); + printf(" sreg: %i\n", table68k[code].sreg); + printf(" dpos: %i\n", table68k[code].dpos); + printf(" spos: %i\n", table68k[code].spos); + printf(" sduse: %i\n", table68k[code].sduse); + printf("flagdead: %i\n", table68k[code].flagdead); + printf("flaglive: %i\n", table68k[code].flaglive); +} +#endif +/* + long int handler; + unsigned char dreg; + unsigned char sreg; + signed char dpos; + signed char spos; + unsigned char sduse; + int flagdead:8, flaglive:8; + unsigned int mnemo:8; + unsigned int cc:4; + unsigned int plev:2; + unsigned int size:2; + unsigned int smode:5; + unsigned int stype:3; + unsigned int dmode:5; + unsigned int suse:1; + unsigned int duse:1; + unsigned int unused1:1; + unsigned int clev:3; + unsigned int isjmp:1; + unsigned int unused2:4; +*/ + } + } + } +} + + +// What this really does is expand the # of handlers, which is why the +// opcode has to be passed into the opcode handler... +// E.g., $F620 maps into $F621-F627 as well; this code does this expansion. +void do_merges(void) +{ + long int opcode; + int nr = 0; + mismatch = 0; + + for(opcode=0; opcode<65536; opcode++) + { + if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG) + continue; + + nr++; + handle_merges(opcode); + } + + nr_cpuop_funcs = nr; +} + + +int get_no_mismatches(void) +{ + return mismatch; +} + diff --git a/waterbox/virtualjaguar/src/m68000/readcpu.h b/waterbox/virtualjaguar/src/m68000/readcpu.h new file mode 100644 index 0000000000..5fe0d495b6 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/readcpu.h @@ -0,0 +1,119 @@ +/* + * readcpu.h - UAE CPU core + * + * This file is distributed under the GNU Public License, version 3 or at + * your option any later version. Read the file GPLv3 for details. + * + */ + +#ifndef UAE_READCPU_H +#define UAE_READCPU_H + +#include "sysdeps.h" + + +ENUMDECL { + Dreg, Areg, Aind, Aipi, Apdi, Ad16, Ad8r, + absw, absl, PC16, PC8r, imm, imm0, imm1, imm2, immi, am_unknown, am_illg +} ENUMNAME (amodes); + +ENUMDECL { + i_ILLG, + + i_OR, i_AND, i_EOR, i_ORSR, i_ANDSR, i_EORSR, + i_SUB, i_SUBA, i_SUBX, i_SBCD, + i_ADD, i_ADDA, i_ADDX, i_ABCD, + i_NEG, i_NEGX, i_NBCD, i_CLR, i_NOT, i_TST, + i_BTST, i_BCHG, i_BCLR, i_BSET, + i_CMP, i_CMPM, i_CMPA, + i_MVPRM, i_MVPMR, i_MOVE, i_MOVEA, i_MVSR2, i_MV2SR, + i_SWAP, i_EXG, i_EXT, i_MVMEL, i_MVMLE, + i_TRAP, i_MVR2USP, i_MVUSP2R, i_RESET, i_NOP, i_STOP, i_RTE, i_RTD, + i_LINK, i_UNLK, + i_RTS, i_TRAPV, i_RTR, + i_JSR, i_JMP, i_BSR, i_Bcc, + i_LEA, i_PEA, i_DBcc, i_Scc, + i_DIVU, i_DIVS, i_MULU, i_MULS, + i_ASR, i_ASL, i_LSR, i_LSL, i_ROL, i_ROR, i_ROXL, i_ROXR, + i_ASRW, i_ASLW, i_LSRW, i_LSLW, i_ROLW, i_RORW, i_ROXLW, i_ROXRW, + i_CHK,i_CHK2, + i_MOVEC2, i_MOVE2C, i_CAS, i_CAS2, i_DIVL, i_MULL, + i_BFTST,i_BFEXTU,i_BFCHG,i_BFEXTS,i_BFCLR,i_BFFFO,i_BFSET,i_BFINS, + i_PACK, i_UNPK, i_TAS, i_BKPT, i_CALLM, i_RTM, i_TRAPcc, i_MOVES, + i_FPP, i_FDBcc, i_FScc, i_FTRAPcc, i_FBcc, i_FSAVE, i_FRESTORE, + i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16, + i_MMUOP, + + MAX_OPCODE_FAMILY /* should always be last of the list */ +} ENUMNAME (instrmnem); + +extern const struct mnemolookup { + instrmnem mnemo; + const char *name; +} lookuptab[]; + +ENUMDECL { + sz_byte, sz_word, sz_long +} ENUMNAME (wordsizes); + +ENUMDECL { + fa_set, fa_unset, fa_zero, fa_one, fa_dontcare, fa_unknown, fa_isjmp, + fa_isbranch +} ENUMNAME (flagaffect); + +ENUMDECL { + fu_used, fu_unused, fu_maybecc, fu_unknown, fu_isjmp +} ENUMNAME (flaguse); + +ENUMDECL { + bit0, bit1, bitc, bitC, bitf, biti, bitI, bitj, bitJ, bitk, bitK, + bits, bitS, bitd, bitD, bitr, bitR, bitz, bitp, lastbit +} ENUMNAME (bitvals); + +struct instr_def { + unsigned int bits; + int n_variable; + char bitpos[16]; + unsigned int mask; + int cpulevel; + int plevel; + struct { + unsigned int flaguse:3; + unsigned int flagset:3; + } flaginfo[5]; + unsigned char sduse; + const char *opcstr; +}; + +extern const struct instr_def defs68k[]; +extern int n_defs68k; + +extern struct instr { + long int handler; + unsigned char dreg; + unsigned char sreg; + signed char dpos; + signed char spos; + unsigned char sduse; + int flagdead:8, flaglive:8; + unsigned int mnemo:8; + unsigned int cc:4; + unsigned int plev:2; + unsigned int size:2; + unsigned int smode:5; + unsigned int stype:3; + unsigned int dmode:5; + unsigned int suse:1; + unsigned int duse:1; + unsigned int unused1:1; + unsigned int clev:3; + unsigned int isjmp:1; + unsigned int unused2:4; +} *table68k; + +extern void read_table68k(void); +extern void do_merges(void); +extern int get_no_mismatches(void); +extern int nr_cpuop_funcs; + +#endif /* ifndef UAE_READCPU_H */ diff --git a/waterbox/virtualjaguar/src/m68000/sysdeps.h b/waterbox/virtualjaguar/src/m68000/sysdeps.h new file mode 100644 index 0000000000..d927b8dbaa --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/sysdeps.h @@ -0,0 +1,118 @@ +/* + * UAE - The Un*x Amiga Emulator - CPU core + * + * Try to include the right system headers and get other system-specific + * stuff right & other collected kludges. + * + * If you think about modifying this, think twice. Some systems rely on + * the exact order of the #include statements. That's also the reason + * why everything gets included unconditionally regardless of whether + * it's actually needed by the .c file. + * + * Copyright 1996, 1997 Bernd Schmidt + * + * Adaptation to Hatari by Thomas Huth + * Adaptation to Virtual Jagaur by James Hammons + * + * This file is distributed under the GNU Public License, version 3 or at + * your option any later version. Read the file GPLv3 for details. + * + */ + +#ifndef UAE_SYSDEPS_H +#define UAE_SYSDEPS_H + +#include +#include +#include +#include + +#ifndef __STDC__ +#error "Your compiler is not ANSI. Get a real one." +#endif + +#include +#include + + +#if EEXIST == ENOTEMPTY +#define BROKEN_OS_PROBABLY_AIX +#endif + +#ifdef __NeXT__ +#define S_IRUSR S_IREAD +#define S_IWUSR S_IWRITE +#define S_IXUSR S_IEXEC +#define S_ISDIR(val) (S_IFDIR & val) +struct utimbuf +{ + time_t actime; + time_t modtime; +}; +#endif + + +#if defined(WARPUP) +#include "devices/timer.h" +#include "osdep/posixemu.h" +#define RETSIGTYPE +#define USE_ZFILE +#define strcasecmp stricmp +#define memcpy q_memcpy +#define memset q_memset +#define strdup my_strdup +#define random rand +#define creat(x,y) open("T:creat",O_CREAT|O_RDWR|O_TRUNC,777) +extern void * q_memset(void *, int, size_t); +extern void * q_memcpy(void *, const void *, size_t); +#endif + + +/* Acorn specific stuff */ +#ifdef ACORN + +#define S_IRUSR S_IREAD +#define S_IWUSR S_IWRITE +#define S_IXUSR S_IEXEC + +#define strcasecmp stricmp + +#endif + +/* We can only rely on GNU C getting enums right. Mickeysoft VSC++ is known + * to have problems, and it's likely that other compilers choke too. */ +#ifdef __GNUC__ +#define ENUMDECL typedef enum +#define ENUMNAME(name) name +#else +#define ENUMDECL enum +#define ENUMNAME(name) ; typedef int name +#endif + +/* When using GNU C, make abort more useful. */ +#ifdef __GNUC__ +#define abort() \ + do { \ + fprintf(stderr, "Internal error; file %s, line %d\n", __FILE__, __LINE__); \ + (abort) (); \ +} while (0) +#endif + + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +#ifndef STATIC_INLINE +#define STATIC_INLINE static __inline__ +#endif + +/* + * You can specify numbers from 0 to 5 here. It is possible that higher + * numbers will make the CPU emulation slightly faster, but if the setting + * is too high, you will run out of memory while compiling. + * Best to leave this as it is. + */ +#define CPU_EMU_SIZE 0 + +#endif /* ifndef UAE_SYSDEPS_H */ diff --git a/waterbox/virtualjaguar/src/m68000/table68k b/waterbox/virtualjaguar/src/m68000/table68k new file mode 100644 index 0000000000..9605d6e3e2 --- /dev/null +++ b/waterbox/virtualjaguar/src/m68000/table68k @@ -0,0 +1,260 @@ +% 0: bit 0 +% 1: bit 1 +% c: condition code +% C: condition codes, except F +% f: direction +% i: immediate +% I: immediate, except 00 and ff +% j: immediate 1..8 +% J: immediate 0..15 +% k: immediate 0..7 +% K: immediate 0..63 +% p: immediate 0..3 (CINV and CPUSH: cache field) +% s: source mode +% S: source reg +% d: dest mode +% D: dest reg +% r: reg +% z: size +% +% Actually, a sssSSS may appear as a destination, and +% vice versa. The only difference between sssSSS and +% dddDDD are the valid addressing modes. There is +% no match for immediate and pc-rel. addressing modes +% in case of dddDDD. +% +% Arp: --> -(Ar) +% ArP: --> (Ar)+ +% L: (xxx.L) +% +% Fields on a line: +% 16 chars bitpattern : +% CPU level / privilege level : +% CPU level 0: 68000 +% 1: 68010 +% 2: 68020 +% privilege level 0: not privileged +% 1: unprivileged only on 68000 (check regs.s) +% 2: privileged (check regs.s) +% 3: privileged if size == word (check regs.s) +% Flags set by instruction: XNZVC : +% Flags used by instruction: XNZVC : +% - means flag unaffected / unused +% 0 means flag reset +% 1 means flag set +% ? means programmer was too lazy to check or instruction may trap +% + means instruction is conditional branch +% everything else means flag set/used +% / means instruction is unconditional branch/call +% x means flag is unknown and well-behaved programs shouldn't check it +% srcaddr status destaddr status : +% bitmasks of +% 1 means fetched +% 2 means stored +% 4 means jump offset +% 8 means jump address +% instruction +% + +0000 0000 0011 1100:00:XNZVC:XNZVC:10: ORSR.B #1 +0000 0000 0111 1100:02:?????:?????:10: ORSR.W #1 +0000 0zz0 11ss sSSS:20:?????:?????:11: CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd] +0000 0000 zzdd dDDD:00:-NZ00:-----:13: OR.z #z,d[!Areg] +0000 0010 0011 1100:00:XNZVC:XNZVC:10: ANDSR.B #1 +0000 0010 0111 1100:02:?????:?????:10: ANDSR.W #1 +0000 0010 zzdd dDDD:00:-NZ00:-----:13: AND.z #z,d[!Areg] +0000 0100 zzdd dDDD:00:XNZVC:-----:13: SUB.z #z,d[!Areg] +0000 0110 zzdd dDDD:00:XNZVC:-----:13: ADD.z #z,d[!Areg] +0000 0110 11ss sSSS:20:?????:?????:10: CALLM s[!Dreg,Areg,Aipi,Apdi,Immd] +0000 0110 11ss sSSS:20:?????:?????:10: RTM s[Dreg,Areg] +0000 1000 00ss sSSS:00:--Z--:-----:11: BTST #1,s[!Areg] +0000 1000 01ss sSSS:00:--Z--:-----:13: BCHG #1,s[!Areg,Immd] +0000 1000 10ss sSSS:00:--Z--:-----:13: BCLR #1,s[!Areg,Immd] +0000 1000 11ss sSSS:00:--Z--:-----:13: BSET #1,s[!Areg,Immd] +0000 1010 0011 1100:00:XNZVC:XNZVC:10: EORSR.B #1 +0000 1010 0111 1100:02:?????:?????:10: EORSR.W #1 +0000 1010 zzdd dDDD:00:-NZ00:-----:13: EOR.z #z,d[!Areg] +0000 1100 zzss sSSS:00:-NZVC:-----:11: CMP.z #z,s[!Areg,Immd] + +0000 1010 11ss sSSS:20:?????:?????:13: CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16] +0000 1100 11ss sSSS:20:?????:?????:13: CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16] +0000 1100 1111 1100:20:?????:?????:10: CAS2.W #2 +0000 1110 zzss sSSS:22:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16] +0000 1110 11ss sSSS:20:?????:?????:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16] +0000 1110 1111 1100:20:?????:?????:10: CAS2.L #2 + +0000 rrr1 00dd dDDD:00:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr +0000 rrr1 01dd dDDD:00:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr +0000 rrr1 10dd dDDD:00:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16] +0000 rrr1 11dd dDDD:00:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16] +0000 rrr1 00ss sSSS:00:--Z--:-----:11: BTST Dr,s[!Areg] +0000 rrr1 01ss sSSS:00:--Z--:-----:13: BCHG Dr,s[!Areg,Immd] +0000 rrr1 10ss sSSS:00:--Z--:-----:13: BCLR Dr,s[!Areg,Immd] +0000 rrr1 11ss sSSS:00:--Z--:-----:13: BSET Dr,s[!Areg,Immd] + +0001 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.B s,d[!Areg] +0010 DDDd ddss sSSS:00:-----:-----:12: MOVEA.L s,d[Areg] +0010 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.L s,d[!Areg] +0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg] +0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg] + +0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z d[!Areg] +0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg] +0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z d[!Areg] +0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg] +0100 0100 zzdd dDDD:00:XNZVC:-----:30: NEG.z d[!Areg] +0100 0100 11ss sSSS:00:XNZVC:-----:10: MV2SR.B s[!Areg] +0100 0110 zzdd dDDD:00:-NZ00:-----:30: NOT.z d[!Areg] +0100 0110 11ss sSSS:02:?????:?????:10: MV2SR.W s[!Areg] +0100 1000 0000 1rrr:20:-----:-----:31: LINK.L Ar,#2 +0100 1000 00dd dDDD:00:X?Z?C:X-Z--:30: NBCD.B d[!Areg] +0100 1000 0100 1kkk:20:?????:?????:10: BKPT #k +0100 1000 01ss sSSS:00:-NZ00:-----:30: SWAP.W s[Dreg] +0100 1000 01ss sSSS:00:-----:-----:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd] +0100 1000 10dd dDDD:00:-NZ00:-----:30: EXT.W d[Dreg] +0100 1000 10dd dDDD:00:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi] +0100 1000 11dd dDDD:00:-NZ00:-----:30: EXT.L d[Dreg] +0100 1000 11dd dDDD:00:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi] +0100 1001 11dd dDDD:20:-NZ00:-----:30: EXT.B d[Dreg] +0100 1010 zzss sSSS:00:-NZ00:-----:10: TST.z s +0100 1010 11dd dDDD:00:?????:?????:30: TAS.B d[!Areg] +0100 1010 1111 1100:00:?????:?????:00: ILLEGAL +0100 1100 00ss sSSS:20:-NZVC:-----:13: MULL.L #1,s[!Areg] +0100 1100 01ss sSSS:20:?????:?????:13: DIVL.L #1,s[!Areg] +0100 1100 10ss sSSS:00:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd] +0100 1100 11ss sSSS:00:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd] +0100 1110 0100 JJJJ:00:-----:XNZVC:10: TRAP #J +0100 1110 0101 0rrr:00:-----:-----:31: LINK.W Ar,#1 +0100 1110 0101 1rrr:00:-----:-----:30: UNLK.L Ar +0100 1110 0110 0rrr:02:-----:-----:10: MVR2USP.L Ar +0100 1110 0110 1rrr:02:-----:-----:20: MVUSP2R.L Ar +0100 1110 0111 0000:02:-----:-----:00: RESET +0100 1110 0111 0001:00:-----:-----:00: NOP +0100 1110 0111 0010:02:XNZVC:-----:10: STOP #1 +0100 1110 0111 0011:02:XNZVC:-----:00: RTE +0100 1110 0111 0100:00:?????:?????:10: RTD #1 +0100 1110 0111 0101:00:-----:-----:00: RTS +0100 1110 0111 0110:00:-----:XNZVC:00: TRAPV +0100 1110 0111 0111:00:XNZVC:-----:00: RTR +0100 1110 0111 1010:12:?????:?????:10: MOVEC2 #1 +0100 1110 0111 1011:12:?????:?????:10: MOVE2C #1 +0100 1110 10ss sSSS:00://///://///:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd] +0100 rrr1 00ss sSSS:20:?????:?????:11: CHK.L s[!Areg],Dr +0100 rrr1 10ss sSSS:00:?????:?????:11: CHK.W s[!Areg],Dr +0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd] +0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar + +0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg] +0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg] +0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg] +0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg] +0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg] +0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg] +0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1 +0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg] +0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1 +0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2 +0101 cccc 1111 1100:20:?????:?????:00: TRAPcc + +% Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal +% instruction exceptions when compiling a 68000 only emulation, which isn't +% what we want either. +0110 0001 0000 0000:00://///://///:40: BSR.W #1 +0110 0001 IIII IIII:00://///://///:40: BSR.B #i +0110 0001 1111 1111:00://///://///:40: BSR.L #2 +0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1 +0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i +0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2 + +0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr + +1000 rrr0 zzss sSSS:00:-NZ00:-----:13: OR.z s[!Areg],Dr +1000 rrr0 11ss sSSS:00:?????:?????:13: DIVU.W s[!Areg],Dr +1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Dreg],Dr +1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Areg-Apdi],Arp +1000 rrr1 zzdd dDDD:00:-NZ00:-----:13: OR.z Dr,d[!Areg,Dreg] +1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Dreg],Dr +1000 rrr1 01dd dDDD:20:?????:?????:12: PACK d[Areg-Apdi],Arp +1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Dreg],Dr +1000 rrr1 10dd dDDD:20:?????:?????:12: UNPK d[Areg-Apdi],Arp +1000 rrr1 11ss sSSS:00:?????:?????:13: DIVS.W s[!Areg],Dr + +1001 rrr0 zzss sSSS:00:XNZVC:-----:13: SUB.z s,Dr +1001 rrr0 11ss sSSS:00:-----:-----:13: SUBA.W s,Ar +1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Dreg],Dr +1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Areg-Apdi],Arp +1001 rrr1 zzdd dDDD:00:XNZVC:-----:13: SUB.z Dr,d[!Areg,Dreg] +1001 rrr1 11ss sSSS:00:-----:-----:13: SUBA.L s,Ar + +1011 rrr0 zzss sSSS:00:-NZVC:-----:11: CMP.z s,Dr +1011 rrr0 11ss sSSS:00:-NZVC:-----:11: CMPA.W s,Ar +1011 rrr1 11ss sSSS:00:-NZVC:-----:11: CMPA.L s,Ar +1011 rrr1 zzdd dDDD:00:-NZVC:-----:11: CMPM.z d[Areg-Aipi],ArP +1011 rrr1 zzdd dDDD:00:-NZ00:-----:13: EOR.z Dr,d[!Areg] + +1100 rrr0 zzss sSSS:00:-NZ00:-----:13: AND.z s[!Areg],Dr +1100 rrr0 11ss sSSS:00:-NZ00:-----:13: MULU.W s[!Areg],Dr +1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Dreg],Dr +1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Areg-Apdi],Arp +1100 rrr1 zzdd dDDD:00:-NZ00:-----:13: AND.z Dr,d[!Areg,Dreg] +1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Dr,d[Dreg] +1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Ar,d[Areg] +1100 rrr1 10dd dDDD:00:-----:-----:33: EXG.L Dr,d[Areg] +1100 rrr1 11ss sSSS:00:-NZ00:-----:13: MULS.W s[!Areg],Dr + +1101 rrr0 zzss sSSS:00:XNZVC:-----:13: ADD.z s,Dr +1101 rrr0 11ss sSSS:00:-----:-----:13: ADDA.W s,Ar +1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Dreg],Dr +1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Areg-Apdi],Arp +1101 rrr1 zzdd dDDD:00:XNZVC:-----:13: ADD.z Dr,d[!Areg,Dreg] +1101 rrr1 11ss sSSS:00:-----:-----:13: ADDA.L s,Ar + +1110 jjjf zz00 0RRR:00:XNZVC:-----:13: ASf.z #j,DR +1110 jjjf zz00 1RRR:00:XNZ0C:-----:13: LSf.z #j,DR +1110 jjjf zz01 0RRR:00:XNZ0C:X----:13: ROXf.z #j,DR +1110 jjjf zz01 1RRR:00:-NZ0C:-----:13: ROf.z #j,DR +1110 rrrf zz10 0RRR:00:XNZVC:X----:13: ASf.z Dr,DR +1110 rrrf zz10 1RRR:00:XNZ0C:X----:13: LSf.z Dr,DR +1110 rrrf zz11 0RRR:00:XNZ0C:X----:13: ROXf.z Dr,DR +1110 rrrf zz11 1RRR:00:-NZ0C:-----:13: ROf.z Dr,DR +1110 000f 11dd dDDD:00:XNZVC:-----:13: ASfW.W d[!Dreg,Areg] +1110 001f 11dd dDDD:00:XNZ0C:-----:13: LSfW.W d[!Dreg,Areg] +1110 010f 11dd dDDD:00:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg] +1110 011f 11dd dDDD:00:-NZ0C:-----:13: ROfW.W d[!Dreg,Areg] + +1110 1000 11ss sSSS:20:?????:?????:11: BFTST #1,s[!Areg,Apdi,Aipi,Immd] +1110 1001 11ss sSSS:20:?????:?????:11: BFEXTU #1,s[!Areg,Apdi,Aipi,Immd] +1110 1010 11ss sSSS:20:?????:?????:13: BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] +1110 1011 11ss sSSS:20:?????:?????:11: BFEXTS #1,s[!Areg,Apdi,Aipi,Immd] +1110 1100 11ss sSSS:20:?????:?????:13: BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] +1110 1101 11ss sSSS:20:?????:?????:11: BFFFO #1,s[!Areg,Apdi,Aipi,Immd] +1110 1110 11ss sSSS:20:?????:?????:13: BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] +1110 1111 11ss sSSS:20:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] + +% floating point co processor +1111 0010 00ss sSSS:30:?????:?????:11: FPP #1,s +1111 0010 01ss sSSS:30:?????:?????:11: FDBcc #1,s[Areg-Dreg] +1111 0010 01ss sSSS:30:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16] +1111 0010 0111 1010:30:?????:?????:10: FTRAPcc #1 +1111 0010 0111 1011:30:?????:?????:10: FTRAPcc #2 +1111 0010 0111 1100:30:?????:?????:00: FTRAPcc +1111 0010 10KK KKKK:30:?????:?????:11: FBcc #K,#1 +1111 0010 11KK KKKK:30:?????:?????:11: FBcc #K,#2 +1111 0011 00ss sSSS:32:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16] +1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] + +1111 0101 iiii iSSS:40:?????:?????:11: MMUOP #i,s + +% 68040 instructions +1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar +1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar +1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p +1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar +1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar +1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p +% destination register number is encoded in the following word +1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi] +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind] diff --git a/waterbox/virtualjaguar/src/memory.cpp b/waterbox/virtualjaguar/src/memory.cpp new file mode 100644 index 0000000000..f067c916ff --- /dev/null +++ b/waterbox/virtualjaguar/src/memory.cpp @@ -0,0 +1,268 @@ +// +// Jaguar memory and I/O physical (hosted!) memory +// +// by James Hammons +// +// JLH = James Hammons +// +// WHO WHEN WHAT +// --- ---------- ----------------------------------------------------------- +// JLH 12/10/2009 Repurposed this file. :-) +// + +/* +$FFFFFF => 16,777,215 +$A00000 => 10,485,760 + +Really, just six megabytes short of using the entire address space... +Why not? We could just allocate the entire space and then use the MMU code to do +things like call functions and whatnot... +In other words, read/write would just tuck the value into the host RAM space and +the I/O function would take care of any weird stuff... + +Actually: writes would tuck in the value, but reads would have to be handled +correctly since some registers do not fall on the same address as far as reading +goes... Still completely doable though. :-) + +N.B.: Jaguar RAM is only 2 megs. ROM is 6 megs max, IO is 128K +*/ + +#include "memory.h" + +uint8_t jagMemSpace[0xF20000]; // The entire memory space of the Jaguar...! + +uint8_t * jaguarMainRAM = &jagMemSpace[0x000000]; +uint8_t * jaguarMainROM = &jagMemSpace[0x800000]; +uint8_t * cdRAM = &jagMemSpace[0xDFFF00]; +uint8_t * gpuRAM = &jagMemSpace[0xF03000]; +uint8_t * dspRAM = &jagMemSpace[0xF1B000]; + +#if 0 +union Word +{ + uint16_t word; + struct { + // This changes depending on endianness... +#ifdef __BIG_ENDIAN__ + uint8_t hi, lo; // Big endian +#else + uint8_t lo, hi; // Little endian +#endif + }; +}; +#endif + +#if 0 +union DWord +{ + uint32_t dword; + struct + { +#ifdef __BIG_ENDIAN__ + uint16_t hiw, low; +#else + uint16_t low, hiw; +#endif + }; +}; +#endif + +#if 0 +static void test(void) +{ + Word reg; + reg.word = 0x1234; + reg.lo = 0xFF; + reg.hi = 0xEE; + + DWord reg2; + reg2.hiw = 0xFFFE; + reg2.low = 0x3322; + reg2.low.lo = 0x11; +} +#endif + +// OR, we could do like so: +#if 0 +#ifdef __BIG_ENDIAN__ +#define DWORD_BYTE_HWORD_H 1 +#define DWORD_BYTE_HWORD_L 2 +#define DWORD_BYTE_LWORD_H 3 +#define DWORD_BYTE_LWORD_L 4 +#else +#define DWORD_BYTE_HWORD_H 4 +#define DWORD_BYTE_HWORD_L 3 +#define DWORD_BYTE_LWORD_H 2 +#define DWORD_BYTE_LWORD_L 1 +#endif +// But this starts to get cumbersome after a while... Is union really better? + +//More union stuff... +unsigned long ByteSwap1 (unsigned long nLongNumber) +{ + union u {unsigned long vi; unsigned char c[sizeof(unsigned long)];}; + union v {unsigned long ni; unsigned char d[sizeof(unsigned long)];}; + union u un; + union v vn; + un.vi = nLongNumber; + vn.d[0]=un.c[3]; + vn.d[1]=un.c[2]; + vn.d[2]=un.c[1]; + vn.d[3]=un.c[0]; + return (vn.ni); +} +#endif + +//Not sure if this is a good approach yet... +//should be if we use proper aliasing, and htonl and friends... +#if 1 +uint32_t & butch = *((uint32_t *)&jagMemSpace[0xDFFF00]); // base of Butch == interrupt control register, R/W +uint32_t & dscntrl = *((uint32_t *)&jagMemSpace[0xDFFF04]); // DSA control register, R/W +uint16_t & ds_data = *((uint16_t *)&jagMemSpace[0xDFFF0A]); // DSA TX/RX data, R/W +uint32_t & i2cntrl = *((uint32_t *)&jagMemSpace[0xDFFF10]); // i2s bus control register, R/W +uint32_t & sbcntrl = *((uint32_t *)&jagMemSpace[0xDFFF14]); // CD subcode control register, R/W +uint32_t & subdata = *((uint32_t *)&jagMemSpace[0xDFFF18]); // Subcode data register A +uint32_t & subdatb = *((uint32_t *)&jagMemSpace[0xDFFF1C]); // Subcode data register B +uint32_t & sb_time = *((uint32_t *)&jagMemSpace[0xDFFF20]); // Subcode time and compare enable (D24) +uint32_t & fifo_data = *((uint32_t *)&jagMemSpace[0xDFFF24]); // i2s FIFO data +uint32_t & i2sdat2 = *((uint32_t *)&jagMemSpace[0xDFFF28]); // i2s FIFO data (old) +uint32_t & unknown = *((uint32_t *)&jagMemSpace[0xDFFF2C]); // Seems to be some sort of I2S interface +#else +uint32_t butch, dscntrl, ds_data, i2cntrl, sbcntrl, subdata, subdatb, sb_time, fifo_data, i2sdat2, unknown; +#endif + +//#warning "Need to separate out this stuff (or do we???)" +//if we use a contiguous memory space, we don't need this shit... +//err, maybe we do, let's not be so hasty now... :-) + +//#define ENDIANSAFE(x) htonl(x) + +// The nice thing about doing it this way is that on big endian machines, htons/l +// compile to nothing and on Intel machines, it compiles down to a single bswap instruction. +// So endianness issues go away nicely without a lot of drama. :-D + +#define BSWAP16(x) (htons(x)) +#define BSWAP32(x) (htonl(x)) +//this isn't endian safe... +#define BSWAP64(x) ((htonl(x & 0xFFFFFFFF) << 32) | htonl(x >> 32)) +// Actually, we use ESAFExx() macros instead of this, and we use GCC to check the endianness... +// Actually, considering that "byteswap.h" doesn't exist elsewhere, the above +// is probably our best bet here. Just need to rename them to ESAFExx(). + +// Look at and see if that header is portable or not. + +uint16_t & memcon1 = *((uint16_t *)&jagMemSpace[0xF00000]); +uint16_t & memcon2 = *((uint16_t *)&jagMemSpace[0xF00002]); +uint16_t & hc = *((uint16_t *)&jagMemSpace[0xF00004]); +uint16_t & vc = *((uint16_t *)&jagMemSpace[0xF00006]); +uint16_t & lph = *((uint16_t *)&jagMemSpace[0xF00008]); +uint16_t & lpv = *((uint16_t *)&jagMemSpace[0xF0000A]); +uint64_t & obData = *((uint64_t *)&jagMemSpace[0xF00010]); +uint32_t & olp = *((uint32_t *)&jagMemSpace[0xF00020]); +uint16_t & obf = *((uint16_t *)&jagMemSpace[0xF00026]); +uint16_t & vmode = *((uint16_t *)&jagMemSpace[0xF00028]); +uint16_t & bord1 = *((uint16_t *)&jagMemSpace[0xF0002A]); +uint16_t & bord2 = *((uint16_t *)&jagMemSpace[0xF0002C]); +uint16_t & hp = *((uint16_t *)&jagMemSpace[0xF0002E]); +uint16_t & hbb = *((uint16_t *)&jagMemSpace[0xF00030]); +uint16_t & hbe = *((uint16_t *)&jagMemSpace[0xF00032]); +uint16_t & hs = *((uint16_t *)&jagMemSpace[0xF00034]); +uint16_t & hvs = *((uint16_t *)&jagMemSpace[0xF00036]); +uint16_t & hdb1 = *((uint16_t *)&jagMemSpace[0xF00038]); +uint16_t & hdb2 = *((uint16_t *)&jagMemSpace[0xF0003A]); +uint16_t & hde = *((uint16_t *)&jagMemSpace[0xF0003C]); +uint16_t & vp = *((uint16_t *)&jagMemSpace[0xF0003E]); +uint16_t & vbb = *((uint16_t *)&jagMemSpace[0xF00040]); +uint16_t & vbe = *((uint16_t *)&jagMemSpace[0xF00042]); +uint16_t & vs = *((uint16_t *)&jagMemSpace[0xF00044]); +uint16_t & vdb = *((uint16_t *)&jagMemSpace[0xF00046]); +uint16_t & vde = *((uint16_t *)&jagMemSpace[0xF00048]); +uint16_t & veb = *((uint16_t *)&jagMemSpace[0xF0004A]); +uint16_t & vee = *((uint16_t *)&jagMemSpace[0xF0004C]); +uint16_t & vi = *((uint16_t *)&jagMemSpace[0xF0004E]); +uint16_t & pit0 = *((uint16_t *)&jagMemSpace[0xF00050]); +uint16_t & pit1 = *((uint16_t *)&jagMemSpace[0xF00052]); +uint16_t & heq = *((uint16_t *)&jagMemSpace[0xF00054]); +uint32_t & bg = *((uint32_t *)&jagMemSpace[0xF00058]); +uint16_t & int1 = *((uint16_t *)&jagMemSpace[0xF000E0]); +uint16_t & int2 = *((uint16_t *)&jagMemSpace[0xF000E2]); +uint8_t * clut = (uint8_t *) &jagMemSpace[0xF00400]; +uint8_t * lbuf = (uint8_t *) &jagMemSpace[0xF00800]; +uint32_t & g_flags = *((uint32_t *)&jagMemSpace[0xF02100]); +uint32_t & g_mtxc = *((uint32_t *)&jagMemSpace[0xF02104]); +uint32_t & g_mtxa = *((uint32_t *)&jagMemSpace[0xF02108]); +uint32_t & g_end = *((uint32_t *)&jagMemSpace[0xF0210C]); +uint32_t & g_pc = *((uint32_t *)&jagMemSpace[0xF02110]); +uint32_t & g_ctrl = *((uint32_t *)&jagMemSpace[0xF02114]); +uint32_t & g_hidata = *((uint32_t *)&jagMemSpace[0xF02118]); +uint32_t & g_divctrl = *((uint32_t *)&jagMemSpace[0xF0211C]); +uint32_t g_remain; // Dual register with $F0211C +uint32_t & a1_base = *((uint32_t *)&jagMemSpace[0xF02200]); +uint32_t & a1_flags = *((uint32_t *)&jagMemSpace[0xF02204]); +uint32_t & a1_clip = *((uint32_t *)&jagMemSpace[0xF02208]); +uint32_t & a1_pixel = *((uint32_t *)&jagMemSpace[0xF0220C]); +uint32_t & a1_step = *((uint32_t *)&jagMemSpace[0xF02210]); +uint32_t & a1_fstep = *((uint32_t *)&jagMemSpace[0xF02214]); +uint32_t & a1_fpixel = *((uint32_t *)&jagMemSpace[0xF02218]); +uint32_t & a1_inc = *((uint32_t *)&jagMemSpace[0xF0221C]); +uint32_t & a1_finc = *((uint32_t *)&jagMemSpace[0xF02220]); +uint32_t & a2_base = *((uint32_t *)&jagMemSpace[0xF02224]); +uint32_t & a2_flags = *((uint32_t *)&jagMemSpace[0xF02228]); +uint32_t & a2_mask = *((uint32_t *)&jagMemSpace[0xF0222C]); +uint32_t & a2_pixel = *((uint32_t *)&jagMemSpace[0xF02230]); +uint32_t & a2_step = *((uint32_t *)&jagMemSpace[0xF02234]); +uint32_t & b_cmd = *((uint32_t *)&jagMemSpace[0xF02238]); +uint32_t & b_count = *((uint32_t *)&jagMemSpace[0xF0223C]); +uint64_t & b_srcd = *((uint64_t *)&jagMemSpace[0xF02240]); +uint64_t & b_dstd = *((uint64_t *)&jagMemSpace[0xF02248]); +uint64_t & b_dstz = *((uint64_t *)&jagMemSpace[0xF02250]); +uint64_t & b_srcz1 = *((uint64_t *)&jagMemSpace[0xF02258]); +uint64_t & b_srcz2 = *((uint64_t *)&jagMemSpace[0xF02260]); +uint64_t & b_patd = *((uint64_t *)&jagMemSpace[0xF02268]); +uint32_t & b_iinc = *((uint32_t *)&jagMemSpace[0xF02270]); +uint32_t & b_zinc = *((uint32_t *)&jagMemSpace[0xF02274]); +uint32_t & b_stop = *((uint32_t *)&jagMemSpace[0xF02278]); +uint32_t & b_i3 = *((uint32_t *)&jagMemSpace[0xF0227C]); +uint32_t & b_i2 = *((uint32_t *)&jagMemSpace[0xF02280]); +uint32_t & b_i1 = *((uint32_t *)&jagMemSpace[0xF02284]); +uint32_t & b_i0 = *((uint32_t *)&jagMemSpace[0xF02288]); +uint32_t & b_z3 = *((uint32_t *)&jagMemSpace[0xF0228C]); +uint32_t & b_z2 = *((uint32_t *)&jagMemSpace[0xF02290]); +uint32_t & b_z1 = *((uint32_t *)&jagMemSpace[0xF02294]); +uint32_t & b_z0 = *((uint32_t *)&jagMemSpace[0xF02298]); +uint16_t & jpit1 = *((uint16_t *)&jagMemSpace[0xF10000]); +uint16_t & jpit2 = *((uint16_t *)&jagMemSpace[0xF10002]); +uint16_t & jpit3 = *((uint16_t *)&jagMemSpace[0xF10004]); +uint16_t & jpit4 = *((uint16_t *)&jagMemSpace[0xF10006]); +uint16_t & clk1 = *((uint16_t *)&jagMemSpace[0xF10010]); +uint16_t & clk2 = *((uint16_t *)&jagMemSpace[0xF10012]); +uint16_t & clk3 = *((uint16_t *)&jagMemSpace[0xF10014]); +uint16_t & j_int = *((uint16_t *)&jagMemSpace[0xF10020]); +uint16_t & asidata = *((uint16_t *)&jagMemSpace[0xF10030]); +uint16_t & asictrl = *((uint16_t *)&jagMemSpace[0xF10032]); +uint16_t asistat; // Dual register with $F10032 +uint16_t & asiclk = *((uint16_t *)&jagMemSpace[0xF10034]); +uint16_t & joystick = *((uint16_t *)&jagMemSpace[0xF14000]); +uint16_t & joybuts = *((uint16_t *)&jagMemSpace[0xF14002]); +uint32_t & d_flags = *((uint32_t *)&jagMemSpace[0xF1A100]); +uint32_t & d_mtxc = *((uint32_t *)&jagMemSpace[0xF1A104]); +uint32_t & d_mtxa = *((uint32_t *)&jagMemSpace[0xF1A108]); +uint32_t & d_end = *((uint32_t *)&jagMemSpace[0xF1A10C]); +uint32_t & d_pc = *((uint32_t *)&jagMemSpace[0xF1A110]); +uint32_t & d_ctrl = *((uint32_t *)&jagMemSpace[0xF1A114]); +uint32_t & d_mod = *((uint32_t *)&jagMemSpace[0xF1A118]); +uint32_t & d_divctrl = *((uint32_t *)&jagMemSpace[0xF1A11C]); +uint32_t d_remain; // Dual register with $F0211C +uint32_t & d_machi = *((uint32_t *)&jagMemSpace[0xF1A120]); +uint16_t & ltxd = *((uint16_t *)&jagMemSpace[0xF1A148]); +uint16_t lrxd; // Dual register with $F1A148 +uint16_t & rtxd = *((uint16_t *)&jagMemSpace[0xF1A14C]); +uint16_t rrxd; // Dual register with $F1A14C +uint8_t & sclk = *((uint8_t *) &jagMemSpace[0xF1A150]); +uint8_t sstat; // Dual register with $F1A150 +uint32_t & smode = *((uint32_t *)&jagMemSpace[0xF1A154]); + +// Memory debugging identifiers + +const char * whoName[10] = + { "Unknown", "Jaguar", "DSP", "GPU", "TOM", "JERRY", "M68K", "Blitter", "OP", "Debugger" }; diff --git a/waterbox/virtualjaguar/src/memory.h b/waterbox/virtualjaguar/src/memory.h new file mode 100644 index 0000000000..0f84b7afcd --- /dev/null +++ b/waterbox/virtualjaguar/src/memory.h @@ -0,0 +1,208 @@ +// +// MEMORY.H: Header file +// +// All Jaguar related memory and I/O locations are contained in this file +// + +#ifndef __MEMORY_H__ +#define __MEMORY_H__ + +#include + +extern uint8_t jagMemSpace[]; + +extern uint8_t * jaguarMainRAM; +extern uint8_t * jaguarMainROM; +extern uint8_t * gpuRAM; +extern uint8_t * dspRAM; + +#if 1 +extern uint32_t & butch, & dscntrl; +extern uint16_t & ds_data; +extern uint32_t & i2cntrl, & sbcntrl, & subdata, & subdatb, & sb_time, & fifo_data, & i2sdat2, & unknown; +#else +extern uint32_t butch, dscntrl, ds_data, i2cntrl, sbcntrl, subdata, subdatb, sb_time, fifo_data, i2sdat2, unknown; +#endif + +extern uint16_t & memcon1, & memcon2, & hc, & vc, & lph, & lpv; +extern uint64_t & obData; +extern uint32_t & olp; +extern uint16_t & obf, & vmode, & bord1, & bord2, & hp, & hbb, & hbe, & hs, + & hvs, & hdb1, & hdb2, & hde, & vp, & vbb, & vbe, & vs, & vdb, & vde, + & veb, & vee, & vi, & pit0, & pit1, & heq; +extern uint32_t & bg; +extern uint16_t & int1, & int2; +extern uint8_t * clut, * lbuf; +extern uint32_t & g_flags, & g_mtxc, & g_mtxa, & g_end, & g_pc, & g_ctrl, + & g_hidata, & g_divctrl; +extern uint32_t g_remain; +extern uint32_t & a1_base, & a1_flags, & a1_clip, & a1_pixel, & a1_step, + & a1_fstep, & a1_fpixel, & a1_inc, & a1_finc, & a2_base, & a2_flags, + & a2_mask, & a2_pixel, & a2_step, & b_cmd, & b_count; +extern uint64_t & b_srcd, & b_dstd, & b_dstz, & b_srcz1, & b_srcz2, & b_patd; +extern uint32_t & b_iinc, & b_zinc, & b_stop, & b_i3, & b_i2, & b_i1, & b_i0, & b_z3, + & b_z2, & b_z1, & b_z0; +extern uint16_t & jpit1, & jpit2, & jpit3, & jpit4, & clk1, & clk2, & clk3, & j_int, + & asidata, & asictrl; +extern uint16_t asistat; +extern uint16_t & asiclk, & joystick, & joybuts; +extern uint32_t & d_flags, & d_mtxc, & d_mtxa, & d_end, & d_pc, & d_ctrl, + & d_mod, & d_divctrl; +extern uint32_t d_remain; +extern uint32_t & d_machi; +extern uint16_t & ltxd, lrxd, & rtxd, rrxd; +extern uint8_t & sclk, sstat; +extern uint32_t & smode; +/* +uint16_t & ltxd = *((uint16_t *)&jagMemSpace[0xF1A148]); +uint16_t lrxd; // Dual register with $F1A148 +uint16_t & rtxd = *((uint16_t *)&jagMemSpace[0xF1A14C]); +uint16_t rrxd; // Dual register with $F1A14C +uint8_t & sclk = *((uint8_t *) &jagMemSpace[0xF1A150]); +uint8_t sstat; // Dual register with $F1A150 +uint32_t & smode = *((uint32_t *)&jagMemSpace[0xF1A154]); +*/ + +// Read/write tracing enumeration + +enum { UNKNOWN, JAGUAR, DSP, GPU, TOM, JERRY, M68K, BLITTER, OP, DEBUG }; +extern const char * whoName[10]; + +// BIOS identification enum + +//enum { BIOS_NORMAL=0x01, BIOS_CD=0x02, BIOS_STUB1=0x04, BIOS_STUB2=0x08, BIOS_DEV_CD=0x10 }; +//extern int biosAvailable; + +// Some handy macros to help converting native endian to big endian (jaguar native) +// & vice versa + +#define SET64(r, a, v) r[(a)] = ((v) & 0xFF00000000000000) >> 56, r[(a)+1] = ((v) & 0x00FF000000000000) >> 48, \ + r[(a)+2] = ((v) & 0x0000FF0000000000) >> 40, r[(a)+3] = ((v) & 0x000000FF00000000) >> 32, \ + r[(a)+4] = ((v) & 0xFF000000) >> 24, r[(a)+5] = ((v) & 0x00FF0000) >> 16, \ + r[(a)+6] = ((v) & 0x0000FF00) >> 8, r[(a)+7] = (v) & 0x000000FF +#define GET64(r, a) (((uint64_t)r[(a)] << 56) | ((uint64_t)r[(a)+1] << 48) | \ + ((uint64_t)r[(a)+2] << 40) | ((uint64_t)r[(a)+3] << 32) | \ + ((uint64_t)r[(a)+4] << 24) | ((uint64_t)r[(a)+5] << 16) | \ + ((uint64_t)r[(a)+6] << 8) | (uint64_t)r[(a)+7]) +#define SET32(r, a, v) r[(a)] = ((v) & 0xFF000000) >> 24, r[(a)+1] = ((v) & 0x00FF0000) >> 16, \ + r[(a)+2] = ((v) & 0x0000FF00) >> 8, r[(a)+3] = (v) & 0x000000FF +#define GET32(r, a) ((r[(a)] << 24) | (r[(a)+1] << 16) | (r[(a)+2] << 8) | r[(a)+3]) +#define SET16(r, a, v) r[(a)] = ((v) & 0xFF00) >> 8, r[(a)+1] = (v) & 0xFF +#define GET16(r, a) ((r[(a)] << 8) | r[(a)+1]) + +//This doesn't seem to work on OSX. So have to figure something else out. :-( +//byteswap.h doesn't exist on OSX. +#if 0 +// This is GCC specific, but we can fix that if we need to... +// Big plus of this approach is that these compile down to single instructions on little +// endian machines while one big endian machines we don't have any overhead. :-) + +#include +#include + +#if __BYTE_ORDER == __LITTLE_ENDIAN + #define ESAFE16(x) bswap_16(x) + #define ESAFE32(x) bswap_32(x) + #define ESAFE64(x) bswap_64(x) +#else + #define ESAFE16(x) (x) + #define ESAFE32(x) (x) + #define ESAFE64(x) (x) +#endif +#endif + +#if 0 +Stuff ripped out of Hatari, that may be useful: + +/* Can the actual CPU access unaligned memory? */ +#ifndef CPU_CAN_ACCESS_UNALIGNED +# if defined(__i386__) || defined(powerpc) || defined(__mc68020__) +# define CPU_CAN_ACCESS_UNALIGNED 1 +# else +# define CPU_CAN_ACCESS_UNALIGNED 0 +# endif +#endif + + +/* If the CPU can access unaligned memory, use these accelerated functions: */ +#if CPU_CAN_ACCESS_UNALIGNED + +#include + + +static inline uae_u32 do_get_mem_long(void *a) +{ + return SDL_SwapBE32(*(uae_u32 *)a); +} + +static inline uae_u16 do_get_mem_word(void *a) +{ + return SDL_SwapBE16(*(uae_u16 *)a); +} + + +static inline void do_put_mem_long(void *a, uae_u32 v) +{ + *(uae_u32 *)a = SDL_SwapBE32(v); +} + +static inline void do_put_mem_word(void *a, uae_u16 v) +{ + *(uae_u16 *)a = SDL_SwapBE16(v); +} + + +#else /* Cpu can not access unaligned memory: */ + + +static inline uae_u32 do_get_mem_long(void *a) +{ + uae_u8 *b = (uae_u8 *)a; + + return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; +} + +static inline uae_u16 do_get_mem_word(void *a) +{ + uae_u8 *b = (uae_u8 *)a; + + return (b[0] << 8) | b[1]; +} + + +static inline void do_put_mem_long(void *a, uae_u32 v) +{ + uae_u8 *b = (uae_u8 *)a; + + b[0] = v >> 24; + b[1] = v >> 16; + b[2] = v >> 8; + b[3] = v; +} + +static inline void do_put_mem_word(void *a, uae_u16 v) +{ + uae_u8 *b = (uae_u8 *)a; + + b[0] = v >> 8; + b[1] = v; +} + + +#endif /* CPU_CAN_ACCESS_UNALIGNED */ + + +/* These are same for all architectures: */ + +static inline uae_u8 do_get_mem_byte(uae_u8 *a) +{ + return *a; +} + +static inline void do_put_mem_byte(uae_u8 *a, uae_u8 v) +{ + *a = v; +} +#endif + +#endif // __MEMORY_H__ diff --git a/waterbox/virtualjaguar/src/memtrack.cpp b/waterbox/virtualjaguar/src/memtrack.cpp new file mode 100644 index 0000000000..cc9daabc63 --- /dev/null +++ b/waterbox/virtualjaguar/src/memtrack.cpp @@ -0,0 +1,225 @@ +// +// Memory Track cartridge emulation +// +// by James Hammons +// (C) 2016 Underground Software +// +// The Memory Track is just a large(-ish) EEPROM, holding 128K. We emulate the +// Atmel part, since it seems to be easier to deal with than the AMD part. The +// way it works is the 68K checks in its R/W functions to see if the MT is +// inserted, and, if so, call the R/W functions here. It also checks to see if +// the ROM width was changed to 32-bit; if not, then it reads the normal ROM in +// the ROM space like usual. +// +// The Atmel part reads/writes a single byte into a long space. So we have to +// adjust for that when reading from/writing to the NVRAM. +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ----------------------------------------------------------- +// JLH 06/12/2016 Created this file ;-) +// + +#include "memtrack.h" + +#include +#include +#include +#include + + +#define MEMTRACK_FILENAME "memtrack.eeprom" +//#define DEBUG_MEMTRACK + +enum { MT_NONE, MT_PROD_ID, MT_RESET, MT_WRITE_ENABLE }; +enum { MT_IDLE, MT_PHASE1, MT_PHASE2 }; + +uint8_t mtMem[0x20000]; +uint8_t mtCommand = MT_NONE; +uint8_t mtState = MT_IDLE; +bool haveMT = false; +char mtFilename[MAX_PATH]; + +// Private function prototypes +void MTWriteFile(void); +void MTStateMachine(uint8_t reg, uint16_t data); + + +void MTInit(void) +{ + sprintf(mtFilename, "%s%s", vjs.EEPROMPath, MEMTRACK_FILENAME); + FILE * fp = fopen(mtFilename, "rb"); + + if (fp) + { + size_t ignored = fread(mtMem, 1, 0x20000, fp); + fclose(fp); + WriteLog("MT: Loaded NVRAM from %s\n", mtFilename); + haveMT = true; + } + else + WriteLog("MT: Could not open file \"%s\"!\n", mtFilename); +} + + +void MTReset(void) +{ + if (!haveMT) + memset(mtMem, 0xFF, 0x20000); +} + + +void MTDone(void) +{ + MTWriteFile(); + WriteLog("MT: Done.\n"); +} + + +void MTWriteFile(void) +{ + if (!haveMT) + return; + + FILE * fp = fopen(mtFilename, "wb"); + + if (fp) + { + fwrite(mtMem, 1, 0x20000, fp); + fclose(fp); + } + else + WriteLog("MT: Could not create file \"%s\"!", mtFilename); +} + + +// +// This is crappy, there doesn't seem to be a word interface to the NVRAM. But +// we'll keep this as a placeholder for now. +// +uint16_t MTReadWord(uint32_t addr) +{ + uint32_t value = MTReadLong(addr); + + if ((addr & 0x03) == 0) + value >>= 16; + else if ((addr & 0x03) == 2) + value &= 0xFFFF; + +#ifdef DEBUG_MEMTRACK +WriteLog("MT: Reading word @ $%06X: $%04X\n", addr, value); +#endif + + return (uint16_t)value; +} + + +uint32_t MTReadLong(uint32_t addr) +{ + uint32_t value = 0; + + if (mtCommand == MT_PROD_ID) + { + if (addr == 0x800000) + value = 0x1F; + else if (addr == 0x800004) + value = 0xD5; + } + else + { + value = (uint32_t)mtMem[(addr & 0x7FFFC) >> 2]; + } + + // We do this because we're not sure how the real thing behaves; but it + // seems reasonable on its face to do it this way. :-P So we turn off write + // mode when reading the NVRAM. + if (mtCommand == MT_WRITE_ENABLE) + mtCommand = MT_NONE; + +#ifdef DEBUG_MEMTRACK +WriteLog("MT: Reading long @ $%06X: $%08X\n", addr, value << 16); +#endif + return value << 16; +} + + +void MTWriteWord(uint32_t addr, uint16_t data) +{ + // We don't care about writes to long offsets + 2 + if ((addr & 0x3) == 2) + return; + +#ifdef DEBUG_MEMTRACK +WriteLog("MT: Writing word @ $%06X: $%04X (Writing is %sabled)\n", addr, data, (mtCommand == MT_WRITE_ENABLE ? "en" : "dis")); +#endif + + // Write to the NVRAM if it's enabled... + if (mtCommand == MT_WRITE_ENABLE) + { + mtMem[(addr & 0x7FFFC) >> 2] = (uint8_t)(data & 0xFF); + return; + } + + switch (addr) + { + case (0x800000 + (4 * 0x5555)): // $815554 + MTStateMachine(0, data); + break; + case (0x800000 + (4 * 0x2AAA)): // $80AAA8 + MTStateMachine(1, data); + break; + } +} + + +void MTWriteLong(uint32_t addr, uint32_t data) +{ + // Strip off lower 3 bits of the passed in address + addr &= 0xFFFFFC; + + MTWriteWord(addr + 0, data & 0xFFFF); + MTWriteWord(addr + 2, data >> 16); +} + + +void MTStateMachine(uint8_t reg, uint16_t data) +{ +#ifdef DEBUG_MEMTRACK +WriteLog("MTStateMachine: reg = %u, data = $%02X, current state = %u\n", reg, data, mtState); +#endif + switch (mtState) + { + case MT_IDLE: + if ((reg == 0) && (data == 0xAA)) + mtState = MT_PHASE1; + + break; + case MT_PHASE1: + if ((reg == 1) && (data == 0x55)) + mtState = MT_PHASE2; + else + mtState = MT_IDLE; + + break; + case MT_PHASE2: + if (reg == 0) + { + if (data == 0x90) // Product ID + mtCommand = MT_PROD_ID; + else if (data == 0xF0) // Reset + mtCommand = MT_NONE; + else if (data == 0xA0) // Write enagle + mtCommand = MT_WRITE_ENABLE; + else + mtCommand = MT_NONE; + } + + mtState = MT_IDLE; + break; + } +#ifdef DEBUG_MEMTRACK +WriteLog(" state = %u, cmd = %u\n", mtState, mtCommand); +#endif +} + diff --git a/waterbox/virtualjaguar/src/memtrack.h b/waterbox/virtualjaguar/src/memtrack.h new file mode 100644 index 0000000000..d6eb036cdb --- /dev/null +++ b/waterbox/virtualjaguar/src/memtrack.h @@ -0,0 +1,15 @@ +// +// memtrack.h: Header file +// + +#include + +void MTInit(void); +void MTReset(void); +void MTDone(void); + +uint16_t MTReadWord(uint32_t addr); +uint32_t MTReadLong(uint32_t addr); +void MTWriteWord(uint32_t addr, uint16_t data); +void MTWriteLong(uint32_t addr, uint32_t data); + diff --git a/waterbox/virtualjaguar/src/mmu.cpp b/waterbox/virtualjaguar/src/mmu.cpp new file mode 100644 index 0000000000..a33f0b225f --- /dev/null +++ b/waterbox/virtualjaguar/src/mmu.cpp @@ -0,0 +1,608 @@ +// +// mmu.cpp +// +// Jaguar Memory Manager Unit +// +// by James Hammons +// +// JLH = James Hammons +// +// WHO WHEN WHAT +// --- ---------- ----------------------------------------------------------- +// JLH 11/25/2009 Created this file. :-) +// + +#include "mmu.h" + +#include // For NULL definition +#include "dac.h" +//#include "jaguar.h" +//#include "memory.h" +//#include "jagbios.h" +#include "wavetable.h" + +/* +Addresses to be handled: + +SYSTEM SETUP REGISTERS + +*MEMCON1 Memory Control Register 1 F00000 RW +*MEMCON2 Memory Control Register 2 F00002 RW +HC Horizontal Count F00004 RW +VC Vertical Count F00006 RW +LPH Light Pen Horizontal F00008 RO +LPV Light Pen Vertical F0000A RO +OB[0-3] Object Data Field F00010-16 RO +OLP Object List Pointer F00020-23 WO +OBF Object Flag F00026 WO +VMODE Video Mode F00028 WO +BORD1 Border Colour (Red & Green) F0002A WO +BORD2 Border Colour (Blue) F0002C WO +*HP Horizontal Period F0002E WO +*HBB Horizontal Blank Begin F00030 WO +*HBE Horizontal Blank End F00032 WO +*HS Horizontal Sync F00034 WO +*HVS Horizontal Vertical Sync F00036 WO +HDB1 Horizontal Display Begin 1 F00038 WO +HDB2 Horizontal Display Begin 2 F0003A WO +HDE Horizontal Display End F0003C WO +*VP Vertical Period F0003E WO +*VBB Vertical Blank Begin F00040 WO +*VBE Vertical Blank End F00042 WO +*VS Vertical Sync F00044 WO +VDB Vertical Display Begin F00046 WO +VDE Vertical Display End F00048 WO +*VEB Vertical Equalization Begin F0004A WO +*VEE Vertical Equalization End F0004C WO +VI Vertical Interrupt F0004E WO +PIT[0-1] Programmable Interrupt Timer F00050-52 WO +*HEQ Horizontal Equalization End F00054 WO +BG Background Colour F00058 WO +INT1 CPU Interrupt Control Register F000E0 RW +INT2 CPU Interrupt Resume Register F000E2 WO +CLUT Colour Look-Up Table F00400-7FE RW +LBUF Line Buffer F00800-1D9E RW + +GPU REGISTERS + +G_FLAGS GPU Flags Register F02100 RW +G_MTXC Matrix Control Register F02104 WO +G_MTXA Matrix Address Register F02108 WO +G_END Data Organization Register F0210C WO +G_PC GPU Program Counter F02110 RW +G_CTRL GPU Control/Status Register F02114 RW +G_HIDATA High Data Register F02118 RW +G_REMAIN Divide Unit Remainder F0211C RO +G_DIVCTRL Divide Unit Control F0211C WO + +BLITTER REGISTERS + +A1_BASE A1 Base Register F02200 WO +A1_FLAGS Flags Register F02204 WO +A1_CLIP A1 Clipping Size F02208 WO +A1_PIXEL A1 Pixel Pointer F0220C WO + F02204 RO +A1_STEP A1 Step Value F02210 WO +A1_FSTEP A1 Step Fraction Value F02214 WO +A1_FPIXEL A1 Pixel Pointer Fraction F02218 RW +A1_INC A1 Increment F0221C WO +A1_FINC A1 Increment Fraction F02220 WO +A2_BASE A2 Base Register F02224 WO +A2_FLAGS A2 Flags Register F02228 WO +A2_MASK A2 Window Mask F0222C WO +A2_PIXEL A2 Pixel Pointer F02230 WO + F0222C RO +A2_STEP A2 Step Value F02234 WO +B_CMD Command/Status Register F02238 RW +B_COUNT Counters Register F0223C WO +B_SRCD Source Data Register F02240 WO +B_DSTD Destination Data Register F02248 WO +B_DSTZ Destination Z Register F02250 WO +B_SRCZ1 Source Z Register 1 F02258 WO +B_SRCZ2 Source Z Register 2 F02260 WO +B_PATD Pattern Data Register F02268 WO +B_IINC Intensity Increment F02270 WO +B_ZINC Z Increment F02274 WO +B_STOP Collision Control F02278 WO +B_I3 Intensity 3 F0227C WO +B_I2 Intensity 2 F02280 WO +B_I1 Intensity 1 F02284 WO +B_I0 Intensity 0 F02288 WO +B_Z3 Z 3 F0228C WO +B_Z2 Z 2 F02290 WO +B_Z1 Z 1 F02294 WO +B_Z0 Z 0 F02298 WO + +JERRY REGISTERS + +*CLK1 Processor Clock Divider F10010 WO +*CLK2 Video Clock Divider F10012 WO +*CLK3 Chroma Clock Divider F10014 WO +JPIT1 Timer 1 Pre-scaler F10000 WO +JPIT3 Timer 2 Pre-scaler F10004 WO +JPIT2 Timer 1 Divider F10002 WO +JPIT4 Timer 2 Divider F10006 WO +J_INT Interrup Control Register F10020 RW +SCLK Serial Clock Frequency F1A150 WO +SMODE Serial Mode F1A154 WO +LTXD Left Transmit Data F1A148 WO +RTXD Right Transmit Data F1A14C WO +LRXD Left Receive Data F1A148 RO +RRXD Right Receive Data F1A14C RO +L_I2S Left I2S Serial Interface F1A148 RW +R_I2S Right I2S Serial Interface F1A14C RW +SSTAT Serial Status F1A150 RO +ASICLK Asynchronous Serial Interface Clock F10034 RW +ASICTRL Asynchronous Serial Control F10032 WO +ASISTAT Asynchronous Serial Status F10032 RO +ASIDATA Asynchronous Serial Data F10030 RW + +JOYSTICK REGISTERS + +JOYSTICK Joystick Register F14000 RW +JOYBUTS Button Register F14002 RW + +DSP REGISTERS + +D_FLAGS DSP Flags Register F1A100 RW +D_MTXC DSP Matrix Control Register F1A104 WO +D_MTXA DSP Matrix Address Register F1A108 WO +D_END DSP Data Organization Register F1A10C WO +D_PC DSP Program Counter F1A110 RW +D_CTRL DSP Control/Status Register F1A114 RW +D_MOD Modulo Instruction Mask F1A118 WO +D_REMAIN Divide Unit Remainder F1A11C RO +D_DIVCTRL Divide Unit Control F1A11C WO +D_MACHI MAC High Result Bits F1A120 RO +*/ + +/* +The approach here is to have a list of addresses and who handles them. Could be +a one-to-one memory location up to a range for each function. Will look +something like this: + + { 0xF14000, 0xF14001, MM_IO, JoystickReadHandler, JoystickWriteHandler }, + +Would be nice to have a way of either calling a handler function or reading/writing +directly to/from a variable or array... +*/ + +enum MemType { MM_NOP = 0, MM_RAM = 1, MM_ROM = 2, MM_IO_R = 4, MM_IO_W = 8, MM_IO = 12 }; + +/* +Would be nice to have different structs tailored to different memory access types, +but if we don't do that, we can encode things as follows: + +MM_NOP: readFunc = writeFunc = NULL +MM_RAM: readFunc = byte array pointer, writeFunc = NULL +MM_ROM: readFunc = byte array pointer, writeFunc = NULL +MM_IO_R: readFunc = function pointer to read function, writeFunc = NULL +MM_IO_W: readFunc = NULL, writeFunc = function pointer to write function +MM_IO: readFunc = function pointer to read function, writeFunc = function pointer to write function + +There may be a need to have readFunc do both read & write functions (makes sense? perhaps) + +Should we have a read mask as well, for the purposes of reading? +*/ + +struct MemDesc { + uint32_t startAddr; + uint32_t endAddr; + MemType type; +// (void (* ioFunc)(uint32, uint32)); // <-- could also be a pointer to RAM... + void * readFunc; // This is read & write with MM_IO + void * writeFunc; + uint32_t mask; +}; + + +MemDesc memoryMap[] = { + { 0x000000, 0x1FFFFF, MM_RAM, jaguarMainRAM }, + { 0x200000, 0x3FFFFF, MM_RAM, jaguarMainRAM }, // Mirror of 1st 2 megs + { 0x400000, 0x5FFFFF, MM_RAM, jaguarMainRAM }, // " " + { 0x600000, 0x7FFFFF, MM_RAM, jaguarMainRAM }, // " " + { 0x800000, 0xDFFEFF, MM_ROM, jaguarMainROM }, + + { 0xDFFF00, 0xDFFF03, MM_IO, &butch }, // base of Butch == interrupt control register, R/W + { 0xDFFF04, 0xDFFF07, MM_IO, &dscntrl }, // DSA control register, R/W + { 0xDFFF0A, 0xDFFF0B, MM_IO, &ds_data }, // DSA TX/RX data, R/W + { 0xDFFF10, 0xDFFF13, MM_IO, &i2cntrl }, // i2s bus control register, R/W + { 0xDFFF14, 0xDFFF17, MM_IO, &sbcntrl }, // CD subcode control register, R/W + { 0xDFFF18, 0xDFFF1B, MM_IO, &subdata }, // Subcode data register A + { 0xDFFF1C, 0xDFFF1F, MM_IO, &subdatb }, // Subcode data register B + { 0xDFFF20, 0xDFFF23, MM_IO, &sb_time }, // Subcode time and compare enable (D24) + { 0xDFFF24, 0xDFFF27, MM_IO, &fifo_data }, // i2s FIFO data + { 0xDFFF28, 0xDFFF2B, MM_IO, &i2sdat2 }, // i2s FIFO data (old) + { 0xDFFF2C, 0xDFFF2F, MM_IO, &unknown }, // Seems to be some sort of I2S interface + + //{ 0xE00000, 0xE1FFFF, MM_ROM, jaguarBootROM }, + + // TOM REGISTERS + + { 0xF00000, 0xF00001, MM_IO, &memcon1 }, // *MEMCON1 Memory Control Register 1 F00000 RW + { 0xF00002, 0xF00003, MM_IO, &memcon2 }, // *MEMCON2 Memory Control Register 2 F00002 RW + { 0xF00004, 0xF00005, MM_IO, &hc }, // HC Horizontal Count F00004 RW + { 0xF00006, 0xF00007, MM_IO, &vc }, // VC Vertical Count F00006 RW + { 0xF00008, 0xF00009, MM_IO_R, &lph }, // LPH Light Pen Horizontal F00008 RO + { 0xF0000A, 0xF0000B, MM_IO_R, &lpv }, // LPV Light Pen Vertical F0000A RO + { 0xF00010, 0xF00017, MM_IO_R, &obData }, // OB[0-3] Object Data Field F00010-16 RO + { 0xF00020, 0xF00023, MM_IO_W, &olp }, // OLP Object List Pointer F00020-23 WO + { 0xF00026, 0xF00027, MM_IO_W, &obf }, // OBF Object Flag F00026 WO + { 0xF00028, 0xF00029, MM_IO_W, &vmode }, // VMODE Video Mode F00028 WO + { 0xF0002A, 0xF0002B, MM_IO_W, &bord1 }, // BORD1 Border Colour (Red & Green) F0002A WO + { 0xF0002C, 0xF0002D, MM_IO_W, &bord2 }, // BORD2 Border Colour (Blue) F0002C WO + { 0xF0002E, 0xF0002F, MM_IO_W, &hp }, // *HP Horizontal Period F0002E WO + { 0xF00030, 0xF00031, MM_IO_W, &hbb }, // *HBB Horizontal Blank Begin F00030 WO + { 0xF00032, 0xF00033, MM_IO_W, &hbe }, // *HBE Horizontal Blank End F00032 WO + { 0xF00034, 0xF00035, MM_IO_W, &hs }, // *HS Horizontal Sync F00034 WO + { 0xF00036, 0xF00037, MM_IO_W, &hvs }, // *HVS Horizontal Vertical Sync F00036 WO + { 0xF00038, 0xF00039, MM_IO_W, &hdb1 }, // HDB1 Horizontal Display Begin 1 F00038 WO + { 0xF0003A, 0xF0003B, MM_IO_W, &hdb2 }, // HDB2 Horizontal Display Begin 2 F0003A WO + { 0xF0003C, 0xF0003D, MM_IO_W, &hde }, // HDE Horizontal Display End F0003C WO + { 0xF0003E, 0xF0003F, MM_IO_W, &vp }, // *VP Vertical Period F0003E WO + { 0xF00040, 0xF00041, MM_IO_W, &vbb }, // *VBB Vertical Blank Begin F00040 WO + { 0xF00042, 0xF00043, MM_IO_W, &vbe }, // *VBE Vertical Blank End F00042 WO + { 0xF00044, 0xF00045, MM_IO_W, &vs }, // *VS Vertical Sync F00044 WO + { 0xF00046, 0xF00047, MM_IO_W, &vdb }, // VDB Vertical Display Begin F00046 WO + { 0xF00048, 0xF00049, MM_IO_W, &vde }, // VDE Vertical Display End F00048 WO + { 0xF0004A, 0xF0004B, MM_IO_W, &veb }, // *VEB Vertical Equalization Begin F0004A WO + { 0xF0004C, 0xF0004D, MM_IO_W, &vee }, // *VEE Vertical Equalization End F0004C WO + { 0xF0004E, 0xF0004F, MM_IO_W, &vi }, // VI Vertical Interrupt F0004E WO + { 0xF00050, 0xF00051, MM_IO_W, &pit0 }, // PIT[0-1] Programmable Interrupt Timer F00050-52 WO + { 0xF00052, 0xF00053, MM_IO_W, &pit1 }, + { 0xF00054, 0xF00055, MM_IO_W, &heq }, // *HEQ Horizontal Equalization End F00054 WO + { 0xF00058, 0xF0005B, MM_IO_W, &bg }, // BG Background Colour F00058 WO + { 0xF000E0, 0xF000E1, MM_IO, &int1 }, // INT1 CPU Interrupt Control Register F000E0 RW + { 0xF000E2, 0xF000E3, MM_IO_W, &int2 }, // INT2 CPU Interrupt Resume Register F000E2 WO +//Some of these RAM spaces may be 16- or 32-bit only... in which case, we need +//to cast appropriately (in memory.cpp, that is)... + { 0xF00400, 0xF005FF, MM_RAM, clut }, // CLUT Colour Look-Up Table F00400-7FE RW + { 0xF00600, 0xF007FF, MM_RAM, clut }, + { 0xF00800, 0xF01D9F, MM_RAM, lbuf }, // LBUF Line Buffer F00800-1D9E RW +//Need high speed RAM interface for GPU & DSP (we have it now...) + + // GPU REGISTERS + + { 0xF02100, 0xF02103, MM_IO, &g_flags }, // G_FLAGS GPU Flags Register F02100 RW + { 0xF02104, 0xF02107, MM_IO_W, &g_mtxc }, // G_MTXC Matrix Control Register F02104 WO + { 0xF02108, 0xF0210B, MM_IO_W, &g_mtxa }, // G_MTXA Matrix Address Register F02108 WO + { 0xF0210C, 0xF0210F, MM_IO_W, &g_end }, // G_END Data Organization Register F0210C WO + { 0xF02110, 0xF02113, MM_IO, &g_pc }, // G_PC GPU Program Counter F02110 RW + { 0xF02114, 0xF02117, MM_IO, &g_ctrl }, // G_CTRL GPU Control/Status Register F02114 RW + { 0xF02118, 0xF0211B, MM_IO, &g_hidata }, // G_HIDATA High Data Register F02118 RW + { 0xF0211C, 0xF0211F, MM_IO, &g_remain, &g_divctrl }, // G_REMAIN Divide Unit Remainder F0211C RO + // G_DIVCTRL Divide Unit Control F0211C WO + { 0xF03000, 0xF03FFF, MM_RAM, gpuRAM }, + + // BLITTER REGISTERS + + { 0xF02200, 0xF02203, MM_IO_W, &a1_base }, // A1_BASE A1 Base Register F02200 WO + { 0xF02204, 0xF02207, MM_IO, &a1_pixel, &a1_flags }, // A1_FLAGS Flags Register F02204 WO + { 0xF02208, 0xF0220B, MM_IO_W, &a1_clip }, // A1_CLIP A1 Clipping Size F02208 WO + { 0xF0220C, 0xF0220F, MM_IO_W, &a1_pixel }, // A1_PIXEL A1 Pixel Pointer F0220C WO +// F02204 RO + { 0xF02210, 0xF02213, MM_IO_W, &a1_step }, // A1_STEP A1 Step Value F02210 WO + { 0xF02214, 0xF02217, MM_IO_W, &a1_fstep }, // A1_FSTEP A1 Step Fraction Value F02214 WO + { 0xF02218, 0xF0221B, MM_IO, &a1_fpixel }, // A1_FPIXEL A1 Pixel Pointer Fraction F02218 RW + { 0xF0221C, 0xF0221F, MM_IO_W, &a1_inc }, // A1_INC A1 Increment F0221C WO + { 0xF02220, 0xF02223, MM_IO_W, &a1_finc }, // A1_FINC A1 Increment Fraction F02220 WO + { 0xF02224, 0xF02227, MM_IO_W, &a2_base }, // A2_BASE A2 Base Register F02224 WO + { 0xF02228, 0xF0222B, MM_IO_W, &a2_flags }, // A2_FLAGS A2 Flags Register F02228 WO + { 0xF0222C, 0xF0222F, MM_IO, &a2_pixel, &a2_mask }, // A2_MASK A2 Window Mask F0222C WO + { 0xF02230, 0xF02233, MM_IO_W, &a2_pixel }, // A2_PIXEL A2 Pixel Pointer F02230 WO +// F0222C RO + { 0xF02234, 0xF02237, MM_IO_W, &a2_step }, // A2_STEP A2 Step Value F02234 WO + { 0xF02238, 0xF0223B, MM_IO, &b_cmd }, // B_CMD Command/Status Register F02238 RW + { 0xF0223C, 0xF0223F, MM_IO_W, &b_count }, // B_COUNT Counters Register F0223C WO + { 0xF02240, 0xF02247, MM_IO_W, &b_srcd }, // B_SRCD Source Data Register F02240 WO + { 0xF02248, 0xF0224F, MM_IO_W, &b_dstd }, // B_DSTD Destination Data Register F02248 WO + { 0xF02250, 0xF02258, MM_IO_W, &b_dstz }, // B_DSTZ Destination Z Register F02250 WO + { 0xF02258, 0xF0225F, MM_IO_W, &b_srcz1 }, // B_SRCZ1 Source Z Register 1 F02258 WO + { 0xF02260, 0xF02267, MM_IO_W, &b_srcz2 }, // B_SRCZ2 Source Z Register 2 F02260 WO + { 0xF02268, 0xF0226F, MM_IO_W, &b_patd }, // B_PATD Pattern Data Register F02268 WO + { 0xF02270, 0xF02273, MM_IO_W, &b_iinc }, // B_IINC Intensity Increment F02270 WO + { 0xF02274, 0xF02277, MM_IO_W, &b_zinc }, // B_ZINC Z Increment F02274 WO + { 0xF02278, 0xF0227B, MM_IO_W, &b_stop }, // B_STOP Collision Control F02278 WO + { 0xF0227C, 0xF0227F, MM_IO_W, &b_i3 }, // B_I3 Intensity 3 F0227C WO + { 0xF02280, 0xF02283, MM_IO_W, &b_i2 }, // B_I2 Intensity 2 F02280 WO + { 0xF02284, 0xF02287, MM_IO_W, &b_i1 }, // B_I1 Intensity 1 F02284 WO + { 0xF02288, 0xF0228B, MM_IO_W, &b_i0 }, // B_I0 Intensity 0 F02288 WO + { 0xF0228C, 0xF0228F, MM_IO_W, &b_z3 }, // B_Z3 Z 3 F0228C WO + { 0xF02290, 0xF02293, MM_IO_W, &b_z2 }, // B_Z2 Z 2 F02290 WO + { 0xF02294, 0xF02297, MM_IO_W, &b_z1 }, // B_Z1 Z 1 F02294 WO + { 0xF02298, 0xF0229B, MM_IO_W, &b_z0 }, // B_Z0 Z 0 F02298 WO + +// JTRM sez ALL GPU address space is accessible from $8000 offset as "fast" 32-bit WO access +// Dunno if anything actually USED it tho... :-P + { 0xF0A100, 0xF0A103, MM_IO_W, &g_flags }, // G_FLAGS GPU Flags Register F02100 RW + { 0xF0A104, 0xF0A107, MM_IO_W, &g_mtxc }, // G_MTXC Matrix Control Register F02104 WO + { 0xF0A108, 0xF0A10B, MM_IO_W, &g_mtxa }, // G_MTXA Matrix Address Register F02108 WO + { 0xF0A10C, 0xF0A10F, MM_IO_W, &g_end }, // G_END Data Organization Register F0210C WO + { 0xF0A110, 0xF0A113, MM_IO_W, &g_pc }, // G_PC GPU Program Counter F02110 RW + { 0xF0A114, 0xF0A117, MM_IO_W, &g_ctrl }, // G_CTRL GPU Control/Status Register F02114 RW + { 0xF0A118, 0xF0A11B, MM_IO_W, &g_hidata }, // G_HIDATA High Data Register F02118 RW + { 0xF0A11C, 0xF0A11F, MM_IO_W, &g_divctrl }, // G_REMAIN Divide Unit Remainder F0211C RO + { 0xF0B000, 0xF0BFFF, MM_IO_W, gpuRAM }, // "Fast" interface to GPU RAM + + // JERRY REGISTERS + + { 0xF10000, 0xF10001, MM_IO_W, &jpit1 }, // JPIT1 Timer 1 Pre-scaler F10000 WO + { 0xF10002, 0xF10003, MM_IO_W, &jpit2 }, // JPIT2 Timer 1 Divider F10002 WO + { 0xF10004, 0xF10005, MM_IO_W, &jpit3 }, // JPIT3 Timer 2 Pre-scaler F10004 WO + { 0xF10006, 0xF10007, MM_IO_W, &jpit4 }, // JPIT4 Timer 2 Divider F10006 WO + { 0xF10010, 0xF10011, MM_IO_W, &clk1 }, // *CLK1 Processor Clock Divider F10010 WO + { 0xF10012, 0xF10013, MM_IO_W, &clk2 }, // *CLK2 Video Clock Divider F10012 WO + { 0xF10014, 0xF10015, MM_IO_W, &clk3 }, // *CLK3 Chroma Clock Divider F10014 WO + { 0xF10020, 0xF10021, MM_IO, &j_int }, // J_INT Interrup Control Register F10020 RW + { 0xF10030, 0xF10031, MM_IO, &asidata }, // ASIDATA Asynchronous Serial Data F10030 RW + { 0xF10032, 0xF10033, MM_IO, &asistat, &asictrl }, // ASICTRL Asynchronous Serial Control F10032 WO + // ASISTAT Asynchronous Serial Status F10032 RO + { 0xF10034, 0xF10035, MM_IO, &asiclk }, // ASICLK Asynchronous Serial Interface Clock F10034 RW + { 0xF10036, 0xF10037, MM_IO_R, &jpit1 }, // JPIT1 Timer 1 Pre-scaler F10036 RO + { 0xF10038, 0xF10039, MM_IO_R, &jpit2 }, // JPIT2 Timer 1 Divider F10038 RO + { 0xF1003A, 0xF1003B, MM_IO_R, &jpit3 }, // JPIT3 Timer 2 Pre-scaler F1003A RO + { 0xF1003C, 0xF1003D, MM_IO_R, &jpit4 }, // JPIT4 Timer 2 Divider F1003C RO + + { 0xF14000, 0xF14001, MM_IO, &joystick }, // JOYSTICK Joystick Register F14000 RW + { 0xF14002, 0xF14003, MM_IO, &joybuts }, // JOYBUTS Button Register F14002 RW + + // DSP REGISTERS + + { 0xF1A100, 0xF1A103, MM_IO, &d_flags }, // D_FLAGS DSP Flags Register F1A100 RW + { 0xF1A104, 0xF1A107, MM_IO_W, &d_mtxc }, // D_MTXC DSP Matrix Control Register F1A104 WO + { 0xF1A108, 0xF1A10B, MM_IO_W, &d_mtxa }, // D_MTXA DSP Matrix Address Register F1A108 WO + { 0xF1A10C, 0xF1A10F, MM_IO_W, &d_end }, // D_END DSP Data Organization Register F1A10C WO + { 0xF1A110, 0xF1A113, MM_IO, &d_pc }, // D_PC DSP Program Counter F1A110 RW + { 0xF1A114, 0xF1A117, MM_IO, &d_ctrl }, // D_CTRL DSP Control/Status Register F1A114 RW + { 0xF1A118, 0xF1A11B, MM_IO_W, &d_mod }, // D_MOD Modulo Instruction Mask F1A118 WO + { 0xF1A11C, 0xF1A11F, MM_IO_W, &d_remain, &d_divctrl }, // D_REMAIN Divide Unit Remainder F1A11C RO + // D_DIVCTRL Divide Unit Control F1A11C WO + { 0xF1A120, 0xF1A123, MM_IO_R, &d_machi }, // D_MACHI MAC High Result Bits F1A120 RO + + + { 0xF1A148, 0xF1A149, MM_IO, &lrxd, <xd }, // LTXD Left Transmit Data F1A148 WO + // LRXD Left Receive Data F1A148 RO + // L_I2S Left I2S Serial Interface F1A148 RW + { 0xF1A14C, 0xF1A14D, MM_IO, &rrxd, &rtxd }, // RTXD Right Transmit Data F1A14C WO + // RRXD Right Receive Data F1A14C RO + // R_I2S Right I2S Serial Interface F1A14C RW + { 0xF1A150, 0xF1A150, MM_IO, &sstat, &sclk }, // SCLK Serial Clock Frequency F1A150 WO + // SSTAT Serial Status F1A150 RO + { 0xF1A154, 0xF1A157, MM_IO_W, &smode }, // SMODE Serial Mode F1A154 WO + + { 0xF1B000, 0xF1CFFF, MM_RAM, dspRAM }, // F1B000-F1CFFF R/W xxxxxxxx xxxxxxxx Local DSP RAM + { 0xF1D000, 0xF1DFFF, MM_ROM, waveTableROM }, +// hi-speed interface for DSP??? Ain't no such thang... + { 0xFFFFFF, 0xFFFFFF, MM_NOP } // End of memory address sentinel +}; + +#if 0 + +// Jaguar Memory map/handlers +uint32_t memoryMap[] = { + { 0x000000, 0x3FFFFF, MM_RAM, jaguarMainRAM }, + { 0x800000, 0xDFFEFF, MM_ROM, jaguarMainROM }, +// Note that this is really memory mapped I/O region... +// { 0xDFFF00, 0xDFFFFF, MM_RAM, cdRAM }, + { 0xDFFF00, 0xDFFF03, MM_IO, cdBUTCH }, // base of Butch == interrupt control register, R/W + { 0xDFFF04, 0xDFFF07, MM_IO, cdDSCNTRL }, // DSA control register, R/W + { 0xDFFF0A, 0xDFFF0B, MM_IO, cdDS_DATA }, // DSA TX/RX data, R/W + { 0xDFFF10, 0xDFFF13, MM_IO, cdI2CNTRL }, // i2s bus control register, R/W + { 0xDFFF14, 0xDFFF17, MM_IO, cdSBCNTRL }, // CD subcode control register, R/W + { 0xDFFF18, 0xDFFF1B, MM_IO, cdSUBDATA }, // Subcode data register A + { 0xDFFF1C, 0xDFFF1F, MM_IO, cdSUBDATB }, // Subcode data register B + { 0xDFFF20, 0xDFFF23, MM_IO, cdSB_TIME }, // Subcode time and compare enable (D24) + { 0xDFFF24, 0xDFFF27, MM_IO, cdFIFO_DATA }, // i2s FIFO data + { 0xDFFF28, 0xDFFF2B, MM_IO, cdI2SDAT2 }, // i2s FIFO data (old) + { 0xDFFF2C, 0xDFFF2F, MM_IO, cdUNKNOWN }, // Seems to be some sort of I2S interface + + { 0xE00000, 0xE3FFFF, MM_ROM, jaguarBootROM }, + +// { 0xF00000, 0xF0FFFF, MM_IO, TOM_REGS_RW }, + { 0xF00050, 0xF00051, MM_IO, tomTimerPrescaler }, + { 0xF00052, 0xF00053, MM_IO, tomTimerDivider }, + { 0xF00400, 0xF005FF, MM_RAM, tomRAM }, // CLUT A&B: How to link these? Write to one writes to the other... + { 0xF00600, 0xF007FF, MM_RAM, tomRAM }, // Actually, this is a good approach--just make the reads the same as well + //What about LBUF writes??? + { 0xF02100, 0xF0211F, MM_IO, GPUWriteByte }, // GPU CONTROL + { 0xF02200, 0xF0229F, MM_IO, BlitterWriteByte }, // BLITTER + { 0xF03000, 0xF03FFF, MM_RAM, GPUWriteByte }, // GPU RAM + + { 0xF10000, 0xF1FFFF, MM_IO, JERRY_REGS_RW }, + +/* + EEPROM: + { 0xF14001, 0xF14001, MM_IO_RO, eepromFOO } + { 0xF14801, 0xF14801, MM_IO_WO, eepromBAR } + { 0xF15001, 0xF15001, MM_IO_RW, eepromBAZ } + + JOYSTICK: + { 0xF14000, 0xF14003, MM_IO, joystickFoo } + 0 = pad0/1 button values (4 bits each), RO(?) + 1 = pad0/1 index value (4 bits each), WO + 2 = unused, RO + 3 = NTSC/PAL, certain button states, RO + +JOYSTICK $F14000 Read/Write + 15.....8 7......0 +Read fedcba98 7654321q f-1 Signals J15 to J1 + q Cartridge EEPROM output data +Write exxxxxxm 76543210 e 1 = enable J7-J0 outputs + 0 = disable J7-J0 outputs + x don't care + m Audio mute + 0 = Audio muted (reset state) + 1 = Audio enabled + 7-4 J7-J4 outputs (port 2) + 3-0 J3-J0 outputs (port 1) +JOYBUTS $F14002 Read Only + 15.....8 7......0 +Read xxxxxxxx rrdv3210 x don't care + r Reserved + d Reserved + v 1 = NTSC Video hardware + 0 = PAL Video hardware + 3-2 Button inputs B3 & B2 (port 2) + 1-0 Button inputs B1 & B0 (port 1) + +J4 J5 J6 J7 Port 2 B2 B3 J12 J13 J14 J15 +J3 J2 J1 J0 Port 1 B0 B1 J8 J9 J10 J11 + 0 0 0 0 + 0 0 0 1 + 0 0 1 0 + 0 0 1 1 + 0 1 0 0 + 0 1 0 1 + 0 1 1 0 + 0 1 1 1 Row 3 C3 Option # 9 6 3 + 1 0 0 0 + 1 0 0 1 + 1 0 1 0 + 1 0 1 1 Row 2 C2 C 0 8 5 2 + 1 1 0 0 + 1 1 0 1 Row 1 C1 B * 7 4 1 + 1 1 1 0 Row 0 Pause A Up Down Left Right + 1 1 1 1 + +0 bit read in any position means that button is pressed. +C3 = C2 = 1 means std. Jag. cntrlr. or nothing attached. +*/ +}; +#endif + +void MMUWrite8(uint32_t address, uint8_t data, uint32_t who/*= UNKNOWN*/) +{ +} + +void MMUWrite16(uint32_t address, uint16_t data, uint32_t who/*= UNKNOWN*/) +{ +} + +void MMUWrite32(uint32_t address, uint32_t data, uint32_t who/*= UNKNOWN*/) +{ +} + +void MMUWrite64(uint32_t address, uint64_t data, uint32_t who/*= UNKNOWN*/) +{ +} + +uint8_t MMURead8(uint32_t address, uint32_t who/*= UNKNOWN*/) +{ + // Search for address in the memory map + // NOTE: This assumes that all entries are linear and sorted in ascending order! + + MemDesc memory; + uint8_t byte = 0xFE; + + uint32_t i = 0; + while (true) + { + if (address <= memoryMap[i].endAddr) + { + if (address >= memoryMap[i].startAddr) + { + memory = memoryMap[i]; + break; + } + else + return 0xFF; // Wasn't found... + } + + i++; + + if (memoryMap[i].startAddr == 0xFFFFFF) + return 0xFF; // Exhausted the list, so bail! + } + + uint32_t offset = address - memory.startAddr; + uint32_t size = memory.endAddr - memory.startAddr + 1; + uint8_t byteShift[8] = { 0, 8, 16, 24, 32, 40, 48, 56 }; + + if (memory.type == MM_RAM || memory.type == MM_ROM) + { + byte = ((uint8_t *)memory.readFunc)[offset]; + } + else if (memory.type == MM_IO_R || memory.type == MM_IO) + { + // Problem here: We don't know yet how wide the function is, so we don't know + // how to properly cast it. We COULD ignore the problem by passing in/receiving + // 64-bits of data and letting the function make heads or tails of it, but we + // still have the problem of, say, taking a byte from a 32-bit value. +/* +We can do like so: + uint8_t byteShift[8] = { 0, 8, 16, 24, 32, 40, 48, 56 }; + size = memory.endAddr - memory.startAddr + 1; + byte = (returnValFromFunc >> byteShift[offset]) & 0xFF; + +Let's see, will this work depending on the endianess? +uint32_t dword +accessing it like so: +((uint8_t *)dword &)[0] --> should give us high byte +but if we assign it directly... +dword = 0x12345678 --> becomes 78 56 34 12 in memory, ptr[0] will be 78 in LE! +dword = 0x12345678 --> becomes 12 34 56 78 in memory, ptr[0] will be 12 in BE! + +So we're in danger if we use the variables directly! We'd need something like +#define ENDIAN_SAFE_16(x) swap lo & hi bytes on LE systems +#define ENDIAN_SAFE_16(x) do nothing on BE systems + +Then, if we want to use a jaguar variable, we need to cast it like so: +uint16_t my_vbb = ENDIAN_SAFE_16(vbb); + +We have something like this already in jaguar.h, since we treat I/O spaces like +contiguous memory anyway... For reference: + +// Some handy macros to help converting native endian to big endian (jaguar native) +// & vice versa + +#define SET64(r, a, v) r[(a)] = ((v) & 0xFF00000000000000) >> 56, r[(a)+1] = ((v) & 0x00FF000000000000) >> 48, \ + r[(a)+2] = ((v) & 0x0000FF0000000000) >> 40, r[(a)+3] = ((v) & 0x000000FF00000000) >> 32, \ + r[(a)+4] = ((v) & 0xFF000000) >> 24, r[(a)+5] = ((v) & 0x00FF0000) >> 16, \ + r[(a)+6] = ((v) & 0x0000FF00) >> 8, r[(a)+7] = (v) & 0x000000FF +#define GET64(r, a) (((uint64)r[(a)] << 56) | ((uint64)r[(a)+1] << 48) | \ + ((uint64)r[(a)+2] << 40) | ((uint64)r[(a)+3] << 32) | \ + ((uint64)r[(a)+4] << 24) | ((uint64)r[(a)+5] << 16) | \ + ((uint64)r[(a)+6] << 8) | (uint64)r[(a)+7]) +#define SET32(r, a, v) r[(a)] = ((v) & 0xFF000000) >> 24, r[(a)+1] = ((v) & 0x00FF0000) >> 16, \ + r[(a)+2] = ((v) & 0x0000FF00) >> 8, r[(a)+3] = (v) & 0x000000FF +#define GET32(r, a) ((r[(a)] << 24) | (r[(a)+1] << 16) | (r[(a)+2] << 8) | r[(a)+3]) +#define SET16(r, a, v) r[(a)] = ((v) & 0xFF00) >> 8, r[(a)+1] = (v) & 0xFF +#define GET16(r, a) ((r[(a)] << 8) | r[(a)+1]) +*/ + // Confused? Let me enlighten... What we're doing here is casting + // data1 as a pointer to a function which returns a Window pointer and + // which takes no parameters (the "(Window *(*)(void))" part), then + // derefencing it (the "*" in front of that) in order to call the + // function that it points to. Clear as mud? Yeah, I hate function + // pointers too, but what else are you gonna do? +// mainWindow = (*(Window *(*)(void))event.user.data1)(); +// uint32_t retVal = (*(uint32(*)(uint32))memory.readFunc)(offset); +//#define FUNC_CAST(x) (*(uint32(*)(uint32))x) +// uint32_t retVal = FUNC_CAST(memory.readFunc)(offset); +#define FUNC_CAST(retVal, function, params) (*(retVal(*)(params))function) + uint64_t retVal = FUNC_CAST(uint64_t, memory.readFunc, uint32_t)(offset); + byte = (retVal >> byteShift[offset]) & 0xFF; + } + else if (memory.type == MM_IO_W) + { + byte = 0xFF; // Write only, what do we return? A fixed value? + } + + return byte; +} + +uint16_t MMURead16(uint32_t address, uint32_t who/*= UNKNOWN*/) +{ + return 0; +} + +uint32_t MMURead32(uint32_t address, uint32_t who/*= UNKNOWN*/) +{ + return 0; +} + +uint64_t MMURead64(uint32_t address, uint32_t who/*= UNKNOWN*/) +{ + return 0; +} + diff --git a/waterbox/virtualjaguar/src/mmu.h b/waterbox/virtualjaguar/src/mmu.h new file mode 100644 index 0000000000..36ef8d7bc5 --- /dev/null +++ b/waterbox/virtualjaguar/src/mmu.h @@ -0,0 +1,24 @@ +// +// mmu.h +// +// Jaguar Memory Manager Unit +// +// by James L. Hammons +// + +#ifndef __MMU_H__ +#define __MMU_H__ + +//#include "types.h" +#include "memory.h" + +void MMUWrite8(uint32_t address, uint8_t data, uint32_t who = UNKNOWN); +void MMUWrite16(uint32_t address, uint16_t data, uint32_t who = UNKNOWN); +void MMUWrite32(uint32_t address, uint32_t data, uint32_t who = UNKNOWN); +void MMUWrite64(uint32_t address, uint64_t data, uint32_t who = UNKNOWN); +uint8_t MMURead8(uint32_t address, uint32_t who = UNKNOWN); +uint16_t MMURead16(uint32_t address, uint32_t who = UNKNOWN); +uint32_t MMURead32(uint32_t address, uint32_t who = UNKNOWN); +uint64_t MMURead64(uint32_t address, uint32_t who = UNKNOWN); + +#endif // __MMU_H__ diff --git a/waterbox/virtualjaguar/src/op.cpp b/waterbox/virtualjaguar/src/op.cpp new file mode 100644 index 0000000000..f8132e49f0 --- /dev/null +++ b/waterbox/virtualjaguar/src/op.cpp @@ -0,0 +1,1904 @@ +// +// Object Processor +// +// Original source by David Raingeard (Cal2) +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Extensive cleanups/fixes/rewrites by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ----------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +#include "op.h" + +#include +#include +#include "gpu.h" +#include "jaguar.h" +#include "log.h" +#include "m68000/m68kinterface.h" +#include "memory.h" +#include "tom.h" + +//#define OP_DEBUG +//#define OP_DEBUG_BMP + +#define BLEND_Y(dst, src) op_blend_y[(((uint16_t)dst<<8)) | ((uint16_t)(src))] +#define BLEND_CR(dst, src) op_blend_cr[(((uint16_t)dst)<<8) | ((uint16_t)(src))] + +#define OBJECT_TYPE_BITMAP 0 // 000 +#define OBJECT_TYPE_SCALE 1 // 001 +#define OBJECT_TYPE_GPU 2 // 010 +#define OBJECT_TYPE_BRANCH 3 // 011 +#define OBJECT_TYPE_STOP 4 // 100 + +#define CONDITION_EQUAL 0 // VC == YPOS +#define CONDITION_LESS_THAN 1 // VC < YPOS +#define CONDITION_GREATER_THAN 2 // VC > YPOS +#define CONDITION_OP_FLAG_SET 3 +#define CONDITION_SECOND_HALF_LINE 4 + +#if 0 +#define OPFLAG_RELEASE 8 // Bus release bit +#define OPFLAG_TRANS 4 // Transparency bit +#define OPFLAG_RMW 2 // Read-Modify-Write bit +#define OPFLAG_REFLECT 1 // Horizontal mirror bit +#endif + +// Private function prototypes + +void OPProcessFixedBitmap(uint64_t p0, uint64_t p1, bool render); +void OPProcessScaledBitmap(uint64_t p0, uint64_t p1, uint64_t p2, bool render); +void OPDiscoverObjects(uint32_t address); +void OPDumpObjectList(void); +void DumpScaledObject(uint64_t p0, uint64_t p1, uint64_t p2); +void DumpFixedObject(uint64_t p0, uint64_t p1); +void DumpBitmapCore(uint64_t p0, uint64_t p1); +uint64_t OPLoadPhrase(uint32_t offset); + +// Local global variables + +// Blend tables (64K each) +static uint8_t op_blend_y[0x10000]; +static uint8_t op_blend_cr[0x10000]; +// There may be a problem with this "RAM" overlapping (and thus being independent of) +// some of the regular TOM RAM... +//#warning objectp_ram is separated from TOM RAM--need to fix that! +//static uint8_t objectp_ram[0x40]; // This is based at $F00000 +uint8_t objectp_running = 0; +//bool objectp_stop_reading_list; + +static uint8_t op_bitmap_bit_depth[8] = { 1, 2, 4, 8, 16, 24, 32, 0 }; +//static uint32_t op_bitmap_bit_size[8] = +// { (uint32_t)(0.125*65536), (uint32_t)(0.25*65536), (uint32_t)(0.5*65536), (uint32_t)(1*65536), +// (uint32_t)(2*65536), (uint32_t)(1*65536), (uint32_t)(1*65536), (uint32_t)(1*65536) }; +static uint32_t op_pointer; + +int32_t phraseWidthToPixels[8] = { 64, 32, 16, 8, 4, 2, 0, 0 }; + + +// +// Object Processor initialization +// +void OPInit(void) +{ + // Here we calculate the saturating blend of a signed 4-bit value and an + // existing Cyan/Red value as well as a signed 8-bit value and an existing intensity... + // Note: CRY is 4 bits Cyan, 4 bits Red, 16 bits intensitY + for(int i=0; i<256*256; i++) + { + int y = (i >> 8) & 0xFF; + int dy = (int8_t)i; // Sign extend the Y index + int c1 = (i >> 8) & 0x0F; + int dc1 = (int8_t)(i << 4) >> 4; // Sign extend the R index + int c2 = (i >> 12) & 0x0F; + int dc2 = (int8_t)(i & 0xF0) >> 4; // Sign extend the C index + + y += dy; + + if (y < 0) + y = 0; + else if (y > 0xFF) + y = 0xFF; + + op_blend_y[i] = y; + + c1 += dc1; + + if (c1 < 0) + c1 = 0; + else if (c1 > 0x0F) + c1 = 0x0F; + + c2 += dc2; + + if (c2 < 0) + c2 = 0; + else if (c2 > 0x0F) + c2 = 0x0F; + + op_blend_cr[i] = (c2 << 4) | c1; + } + + OPReset(); +} + + +// +// Object Processor reset +// +void OPReset(void) +{ +// memset(objectp_ram, 0x00, 0x40); + objectp_running = 0; +} + + +static const char * opType[8] = +{ "(BITMAP)", "(SCALED BITMAP)", "(GPU INT)", "(BRANCH)", "(STOP)", "???", "???", "???" }; +static const char * ccType[8] = + { "==", "<", ">", "(opflag set)", "(second half line)", "?", "?", "?" }; +static uint32_t object[8192]; +static uint32_t numberOfObjects; +//static uint32_t objectLink[8192]; +//static uint32_t numberOfLinks; + + +void OPDone(void) +{ +//#warning "!!! Fix OL dump so that it follows links !!!" +// const char * opType[8] = +// { "(BITMAP)", "(SCALED BITMAP)", "(GPU INT)", "(BRANCH)", "(STOP)", "???", "???", "???" }; +// const char * ccType[8] = +// { "\"==\"", "\"<\"", "\">\"", "(opflag set)", "(second half line)", "?", "?", "?" }; + + uint32_t olp = OPGetListPointer(); + WriteLog("\nOP: OLP = $%08X\n", olp); + WriteLog("OP: Phrase dump\n ----------\n"); + +#if 0 + for(uint32_t i=0; i<0x100; i+=8) + { + uint32_t hi = JaguarReadLong(olp + i, OP), lo = JaguarReadLong(olp + i + 4, OP); + WriteLog("\t%08X: %08X %08X %s", olp + i, hi, lo, opType[lo & 0x07]); + + if ((lo & 0x07) == 3) + { + uint16_t ypos = (lo >> 3) & 0x7FF; + uint8_t cc = (lo >> 14) & 0x03; + uint32_t link = ((hi << 11) | (lo >> 21)) & 0x3FFFF8; + WriteLog(" YPOS=%u, CC=%s, link=%08X", ypos, ccType[cc], link); + } + + WriteLog("\n"); + + if ((lo & 0x07) == 0) + DumpFixedObject(OPLoadPhrase(olp+i), OPLoadPhrase(olp+i+8)); + + if ((lo & 0x07) == 1) + DumpScaledObject(OPLoadPhrase(olp+i), OPLoadPhrase(olp+i+8), OPLoadPhrase(olp+i+16)); + } + + WriteLog("\n"); +#else +//#warning "!!! Fix lockup in OPDiscoverObjects() !!!" +//temp, to keep the following function from locking up on bad/weird OLs +//return; + + numberOfObjects = 0; + OPDiscoverObjects(olp); + OPDumpObjectList(); +#endif +} + + +bool OPObjectExists(uint32_t address) +{ + // Yes, we really do a linear search, every time. :-/ + for(uint32_t i=0; i> 21)) & 0x3FFFF8; + + if (objectType == 3) + { + // Branch if YPOS < 2047 (or YPOS > 0) can be treated as a GOTO, so + // don't do any discovery in that case. Otherwise, have at it: + if (((lo & 0xFFFF) != 0x7FFB) && ((lo & 0xFFFF) != 0x8003)) + // Recursion needed to follow all links! This does depth-first + // recursion on the not-taken objects + OPDiscoverObjects(address + 8); + } + + // Get the next object... + address = link; + } + while (objectType != 4); +} + + +void OPDumpObjectList(void) +{ + for(uint32_t i=0; i> 21)) & 0x3FFFF8; + WriteLog("%08X: %08X %08X %s -> $%08X", address, hi, lo, opType[objectType], link); + + if (objectType == 3) + { + uint16_t ypos = (lo >> 3) & 0x7FF; + uint8_t cc = (lo >> 14) & 0x07; // Proper # of bits == 3 + WriteLog(" YPOS %s %u", ccType[cc], ypos); + } + + WriteLog("\n"); + + // Yes, this is how the OP finds follow-on phrases for bitmap/scaled + // bitmap objects...! + if (objectType == 0) + DumpFixedObject(OPLoadPhrase(address + 0), + OPLoadPhrase(address | 0x08)); + + if (objectType == 1) + DumpScaledObject(OPLoadPhrase(address + 0), + OPLoadPhrase(address | 0x08), OPLoadPhrase(address | 0x10)); + + if (address == link) // Ruh roh... + { + // Runaway recursive link is bad! + WriteLog("***** SELF REFERENTIAL LINK *****\n\n"); + } + } + + WriteLog("\n"); +} + + +// +// Object Processor memory access +// Memory range: F00010 - F00027 +// +// F00010-F00017 R xxxxxxxx xxxxxxxx OB - current object code from the graphics processor +// F00020-F00023 W xxxxxxxx xxxxxxxx OLP - start of the object list +// F00026 W -------- -------x OBF - object processor flag +// + +#if 0 +uint8_t OPReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0x3F; + return objectp_ram[offset]; +} + +uint16_t OPReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0x3F; + return GET16(objectp_ram, offset); +} + +void OPWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0x3F; + objectp_ram[offset] = data; +} + +void OPWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + offset &= 0x3F; + SET16(objectp_ram, offset, data); + +/*if (offset == 0x20) +WriteLog("OP: Setting lo list pointer: %04X\n", data); +if (offset == 0x22) +WriteLog("OP: Setting hi list pointer: %04X\n", data);//*/ +} +#endif + + +uint32_t OPGetListPointer(void) +{ + // Note: This register is LO / HI WORD, hence the funky look of this... + return GET16(tomRam8, 0x20) | (GET16(tomRam8, 0x22) << 16); +} + + +// This is WRONG, since the OBF is only 16 bits wide!!! [FIXED] + +uint32_t OPGetStatusRegister(void) +{ + return GET16(tomRam8, 0x26); +} + + +// This is WRONG, since the OBF is only 16 bits wide!!! [FIXED] + +void OPSetStatusRegister(uint32_t data) +{ + tomRam8[0x26] = (data & 0x0000FF00) >> 8; + tomRam8[0x27] |= (data & 0xFE); +} + + +void OPSetCurrentObject(uint64_t object) +{ +//Not sure this is right... Wouldn't it just be stored 64 bit BE? + // Stored as least significant 32 bits first, ms32 last in big endian +/* objectp_ram[0x13] = object & 0xFF; object >>= 8; + objectp_ram[0x12] = object & 0xFF; object >>= 8; + objectp_ram[0x11] = object & 0xFF; object >>= 8; + objectp_ram[0x10] = object & 0xFF; object >>= 8; + + objectp_ram[0x17] = object & 0xFF; object >>= 8; + objectp_ram[0x16] = object & 0xFF; object >>= 8; + objectp_ram[0x15] = object & 0xFF; object >>= 8; + objectp_ram[0x14] = object & 0xFF;*/ +// Let's try regular good old big endian... + tomRam8[0x17] = object & 0xFF; object >>= 8; + tomRam8[0x16] = object & 0xFF; object >>= 8; + tomRam8[0x15] = object & 0xFF; object >>= 8; + tomRam8[0x14] = object & 0xFF; object >>= 8; + + tomRam8[0x13] = object & 0xFF; object >>= 8; + tomRam8[0x12] = object & 0xFF; object >>= 8; + tomRam8[0x11] = object & 0xFF; object >>= 8; + tomRam8[0x10] = object & 0xFF; +} + + +uint64_t OPLoadPhrase(uint32_t offset) +{ + offset &= ~0x07; // 8 byte alignment + return ((uint64_t)JaguarReadLong(offset, OP) << 32) | (uint64_t)JaguarReadLong(offset+4, OP); +} + + +void OPStorePhrase(uint32_t offset, uint64_t p) +{ + offset &= ~0x07; // 8 byte alignment + JaguarWriteLong(offset, p >> 32, OP); + JaguarWriteLong(offset + 4, p & 0xFFFFFFFF, OP); +} + + +// +// Debugging routines +// +void DumpScaledObject(uint64_t p0, uint64_t p1, uint64_t p2) +{ + WriteLog(" %08X %08X\n", (uint32_t)(p1>>32), (uint32_t)(p1&0xFFFFFFFF)); + WriteLog(" %08X %08X\n", (uint32_t)(p2>>32), (uint32_t)(p2&0xFFFFFFFF)); + DumpBitmapCore(p0, p1); + uint32_t hscale = p2 & 0xFF; + uint32_t vscale = (p2 >> 8) & 0xFF; + uint32_t remainder = (p2 >> 16) & 0xFF; + WriteLog(" [hsc: %02X, vsc: %02X, rem: %02X]\n", hscale, vscale, remainder); +} + + +void DumpFixedObject(uint64_t p0, uint64_t p1) +{ + WriteLog(" %08X %08X\n", (uint32_t)(p1>>32), (uint32_t)(p1&0xFFFFFFFF)); + DumpBitmapCore(p0, p1); +} + + +void DumpBitmapCore(uint64_t p0, uint64_t p1) +{ + uint32_t bdMultiplier[8] = { 64, 32, 16, 8, 4, 2, 1, 1 }; + uint8_t bitdepth = (p1 >> 12) & 0x07; +//WAS: int16_t ypos = ((p0 >> 3) & 0x3FF); // ??? What if not interlaced (/2)? + int16_t ypos = ((p0 >> 3) & 0x7FF); // ??? What if not interlaced (/2)? + int32_t xpos = p1 & 0xFFF; + xpos = (xpos & 0x800 ? xpos | 0xFFFFF000 : xpos); // Sign extend that mutha! + uint32_t iwidth = ((p1 >> 28) & 0x3FF); + uint32_t dwidth = ((p1 >> 18) & 0x3FF); // Unsigned! + uint16_t height = ((p0 >> 14) & 0x3FF); + uint32_t link = ((p0 >> 24) & 0x7FFFF) << 3; + uint32_t ptr = ((p0 >> 43) & 0x1FFFFF) << 3; + uint32_t firstPix = (p1 >> 49) & 0x3F; + uint8_t flags = (p1 >> 45) & 0x0F; + uint8_t idx = (p1 >> 38) & 0x7F; + uint32_t pitch = (p1 >> 15) & 0x07; + WriteLog(" [%u x %u @ (%i, %u) (iw:%u, dw:%u) (%u bpp), p:%08X fp:%02X, fl:%s%s%s%s, idx:%02X, pt:%02X]\n", + iwidth * bdMultiplier[bitdepth], + height, xpos, ypos, iwidth, dwidth, op_bitmap_bit_depth[bitdepth], + ptr, firstPix, (flags&OPFLAG_REFLECT ? "REFLECT " : ""), + (flags&OPFLAG_RMW ? "RMW " : ""), (flags&OPFLAG_TRANS ? "TRANS " : ""), + (flags&OPFLAG_RELEASE ? "RELEASE" : ""), idx, pitch); +} + + +// +// Object Processor main routine +// +#warning "Need to fix this so that when an GPU object IRQ happens, we can pick up OP processing where we left off. !!! FIX !!!" +void OPProcessList(int halfline, bool render) +{ +#warning "!!! NEED TO HANDLE MULTIPLE FIELDS PROPERLY !!!" +// We ignore them, for now; not good D-: +// N.B.: Half-lines are exactly that, half-lines. When in interlaced mode, it +// draws the screen exactly the same way as it does in non, one line at a +// time. The only way you know you're in field #2 is that the topmost bit +// of VC is set. Half-line mode is so you can draw higher horizontal +// resolutions than you normally could, as the line buffer is only 720 +// pixels wide... + halfline &= 0x7FF; + +extern int op_start_log; + + op_pointer = OPGetListPointer(); + +// objectp_stop_reading_list = false; + +//WriteLog("OP: Processing line #%u (OLP=%08X)...\n", halfline, op_pointer); +//op_done(); + +// *** BEGIN OP PROCESSOR TESTING ONLY *** +extern bool interactiveMode; +extern bool iToggle; +extern int objectPtr; +bool inhibit; +int bitmapCounter = 0; +// *** END OP PROCESSOR TESTING ONLY *** + + uint32_t opCyclesToRun = 30000; // This is a pulled-out-of-the-air value (will need to be fixed, obviously!) + +// if (op_pointer) WriteLog(" new op list at 0x%.8x halfline %i\n",op_pointer,halfline); + while (op_pointer) + { +// *** BEGIN OP PROCESSOR TESTING ONLY *** +if (interactiveMode && bitmapCounter == objectPtr) + inhibit = iToggle; +else + inhibit = false; +// *** END OP PROCESSOR TESTING ONLY *** +// if (objectp_stop_reading_list) +// return; + + uint64_t p0 = OPLoadPhrase(op_pointer); + op_pointer += 8; +//WriteLog("\t%08X type %i\n", op_pointer, (uint8_t)p0 & 0x07); + +#if 1 +if (halfline == TOMGetVDB() && op_start_log) +//if (halfline == 215 && op_start_log) +//if (halfline == 28 && op_start_log) +//if (halfline == 0) +{ +WriteLog("%08X --> phrase %08X %08X", op_pointer - 8, (int)(p0>>32), (int)(p0&0xFFFFFFFF)); +if ((p0 & 0x07) == OBJECT_TYPE_BITMAP) +{ +WriteLog(" (BITMAP) "); +uint64_t p1 = OPLoadPhrase(op_pointer); +WriteLog("\n%08X --> phrase %08X %08X ", op_pointer, (int)(p1>>32), (int)(p1&0xFFFFFFFF)); + uint8_t bitdepth = (p1 >> 12) & 0x07; +//WAS: int16_t ypos = ((p0 >> 3) & 0x3FF); // ??? What if not interlaced (/2)? + int16_t ypos = ((p0 >> 3) & 0x7FF); // ??? What if not interlaced (/2)? +int32_t xpos = p1 & 0xFFF; +xpos = (xpos & 0x800 ? xpos | 0xFFFFF000 : xpos); + uint32_t iwidth = ((p1 >> 28) & 0x3FF); + uint32_t dwidth = ((p1 >> 18) & 0x3FF); // Unsigned! + uint16_t height = ((p0 >> 14) & 0x3FF); + uint32_t link = ((p0 >> 24) & 0x7FFFF) << 3; + uint32_t ptr = ((p0 >> 43) & 0x1FFFFF) << 3; + uint32_t firstPix = (p1 >> 49) & 0x3F; + uint8_t flags = (p1 >> 45) & 0x0F; + uint8_t idx = (p1 >> 38) & 0x7F; + uint32_t pitch = (p1 >> 15) & 0x07; +WriteLog("\n [%u (%u) x %u @ (%i, %u) (%u bpp), l: %08X, p: %08X fp: %02X, fl:%s%s%s%s, idx:%02X, pt:%02X]\n", + iwidth, dwidth, height, xpos, ypos, op_bitmap_bit_depth[bitdepth], link, ptr, firstPix, (flags&OPFLAG_REFLECT ? "REFLECT " : ""), (flags&OPFLAG_RMW ? "RMW " : ""), (flags&OPFLAG_TRANS ? "TRANS " : ""), (flags&OPFLAG_RELEASE ? "RELEASE" : ""), idx, pitch); +} +if ((p0 & 0x07) == OBJECT_TYPE_SCALE) +{ +WriteLog(" (SCALED BITMAP)"); +uint64_t p1 = OPLoadPhrase(op_pointer), p2 = OPLoadPhrase(op_pointer+8); +WriteLog("\n%08X --> phrase %08X %08X ", op_pointer, (int)(p1>>32), (int)(p1&0xFFFFFFFF)); +WriteLog("\n%08X --> phrase %08X %08X ", op_pointer+8, (int)(p2>>32), (int)(p2&0xFFFFFFFF)); + uint8_t bitdepth = (p1 >> 12) & 0x07; +//WAS: int16_t ypos = ((p0 >> 3) & 0x3FF); // ??? What if not interlaced (/2)? + int16_t ypos = ((p0 >> 3) & 0x7FF); // ??? What if not interlaced (/2)? +int32_t xpos = p1 & 0xFFF; +xpos = (xpos & 0x800 ? xpos | 0xFFFFF000 : xpos); + uint32_t iwidth = ((p1 >> 28) & 0x3FF); + uint32_t dwidth = ((p1 >> 18) & 0x3FF); // Unsigned! + uint16_t height = ((p0 >> 14) & 0x3FF); + uint32_t link = ((p0 >> 24) & 0x7FFFF) << 3; + uint32_t ptr = ((p0 >> 43) & 0x1FFFFF) << 3; + uint32_t firstPix = (p1 >> 49) & 0x3F; + uint8_t flags = (p1 >> 45) & 0x0F; + uint8_t idx = (p1 >> 38) & 0x7F; + uint32_t pitch = (p1 >> 15) & 0x07; +WriteLog("\n [%u (%u) x %u @ (%i, %u) (%u bpp), l: %08X, p: %08X fp: %02X, fl:%s%s%s%s, idx:%02X, pt:%02X]\n", + iwidth, dwidth, height, xpos, ypos, op_bitmap_bit_depth[bitdepth], link, ptr, firstPix, (flags&OPFLAG_REFLECT ? "REFLECT " : ""), (flags&OPFLAG_RMW ? "RMW " : ""), (flags&OPFLAG_TRANS ? "TRANS " : ""), (flags&OPFLAG_RELEASE ? "RELEASE" : ""), idx, pitch); + uint32_t hscale = p2 & 0xFF; + uint32_t vscale = (p2 >> 8) & 0xFF; + uint32_t remainder = (p2 >> 16) & 0xFF; +WriteLog(" [hsc: %02X, vsc: %02X, rem: %02X]\n", hscale, vscale, remainder); +} +if ((p0 & 0x07) == OBJECT_TYPE_GPU) +WriteLog(" (GPU)\n"); +if ((p0 & 0x07) == OBJECT_TYPE_BRANCH) +{ +WriteLog(" (BRANCH)\n"); +uint8_t * jaguarMainRam = GetRamPtr(); +WriteLog("[RAM] --> "); +for(int k=0; k<8; k++) + WriteLog("%02X ", jaguarMainRam[op_pointer-8 + k]); +WriteLog("\n"); +} +if ((p0 & 0x07) == OBJECT_TYPE_STOP) +WriteLog(" --> List end\n\n"); +} +#endif + + switch ((uint8_t)p0 & 0x07) + { + case OBJECT_TYPE_BITMAP: + { + uint16_t ypos = (p0 >> 3) & 0x7FF; +// This is only theory implied by Rayman...! +// It seems that if the YPOS is zero, then bump the YPOS value so that it +// coincides with the VDB value. With interlacing, this would be slightly more +// tricky. There's probably another bit somewhere that enables this mode--but +// so far, doesn't seem to affect any other game in a negative way (that I've +// seen). Either that, or it's an undocumented bug... + +//No, the reason this was needed is that the OP code before was wrong. Any value +//less than VDB will get written to the top line of the display! +#if 0 +// Not so sure... Let's see what happens here... +// No change... + if (ypos == 0) + ypos = TOMReadWord(0xF00046, OP) / 2; // Get the VDB value +#endif +// Actually, no. Any item less than VDB will get only the lines that hang over +// VDB displayed. Actually, this is incorrect. It seems that VDB value is wrong +// somewhere and that's what's causing things to fuck up. Still no idea why. + + uint32_t height = (p0 & 0xFFC000) >> 14; + uint32_t oldOPP = op_pointer - 8; +// *** BEGIN OP PROCESSOR TESTING ONLY *** +if (inhibit && op_start_log) + WriteLog("!!! ^^^ This object is INHIBITED! ^^^ !!!\n"); +bitmapCounter++; +if (!inhibit) // For OP testing only! +// *** END OP PROCESSOR TESTING ONLY *** + if (halfline >= ypos && height > 0) + { + // Believe it or not, this is what the OP actually does... + // which is why they're required to be on a dphrase boundary! + uint64_t p1 = OPLoadPhrase(oldOPP | 0x08); +//unneeded op_pointer += 8; +//WriteLog("OP: Writing halfline %d with ypos == %d...\n", halfline, ypos); +//WriteLog("--> Writing %u BPP bitmap...\n", op_bitmap_bit_depth[(p1 >> 12) & 0x07]); +// OPProcessFixedBitmap(halfline, p0, p1, render); + OPProcessFixedBitmap(p0, p1, render); + + // OP write-backs + + height--; + + uint64_t data = (p0 & 0xFFFFF80000000000LL) >> 40; + uint64_t dwidth = (p1 & 0xFFC0000) >> 15; + data += dwidth; + + p0 &= ~0xFFFFF80000FFC000LL; // Mask out old data... + p0 |= (uint64_t)height << 14; + p0 |= data << 40; + OPStorePhrase(oldOPP, p0); + } + + // OP bottom 3 bits are hardwired to zero. The link address + // reflects this, so we only need the top 19 bits of the address + // (which is why we only shift 21, and not 24). + op_pointer = (p0 & 0x000007FFFF000000LL) >> 21; + + // KLUDGE: Seems that memory access is mirrored in the first 8MB of + // memory... + if (op_pointer > 0x1FFFFF && op_pointer < 0x800000) + op_pointer &= 0xFF1FFFFF; // Knock out bits 21-23 + + break; + } + case OBJECT_TYPE_SCALE: + { +//WAS: uint16_t ypos = (p0 >> 3) & 0x3FF; + uint16_t ypos = (p0 >> 3) & 0x7FF; + uint32_t height = (p0 & 0xFFC000) >> 14; + uint32_t oldOPP = op_pointer - 8; +//WriteLog("OP: Scaled Object (ypos=%04X, height=%04X", ypos, height); +// *** BEGIN OP PROCESSOR TESTING ONLY *** +if (inhibit && op_start_log) +{ + WriteLog("!!! ^^^ This object is INHIBITED! ^^^ !!! (halfline=%u, ypos=%u, height=%u)\n", halfline, ypos, height); + DumpScaledObject(p0, OPLoadPhrase(op_pointer), OPLoadPhrase(op_pointer+8)); +} +bitmapCounter++; +if (!inhibit) // For OP testing only! +// *** END OP PROCESSOR TESTING ONLY *** + if (halfline >= ypos && height > 0) + { + // Believe it or not, this is what the OP actually does... + // which is why they're required to be on a qphrase boundary! + uint64_t p1 = OPLoadPhrase(oldOPP | 0x08); + uint64_t p2 = OPLoadPhrase(oldOPP | 0x10); +//unneeded op_pointer += 16; + OPProcessScaledBitmap(p0, p1, p2, render); + + // OP write-backs + + uint16_t remainder = (p2 >> 16) & 0xFF;//, vscale = p2 >> 8; + uint8_t /*remainder = p2 >> 16,*/ vscale = p2 >> 8; +//Actually, we should skip this object if it has a vscale of zero. +//Or do we? Not sure... Atari Karts has a few lines that look like: +// (SCALED BITMAP) +//000E8268 --> phrase 00010000 7000B00D +// [7 (0) x 1 @ (13, 0) (8 bpp), l: 000E82A0, p: 000E0FC0 fp: 00, fl:RELEASE, idx:00, pt:01] +// [hsc: 9A, vsc: 00, rem: 00] +// Could it be the vscale is overridden if the DWIDTH is zero? Hmm... +//WriteLog("OP: Scaled bitmap processing (rem=%02X, vscale=%02X)...\n", remainder, vscale);//*/ + + if (vscale == 0) + vscale = 0x20; // OP bug??? Nope, it isn't...! Or is it? + +//extern int start_logging; +//if (start_logging) +// WriteLog("--> Returned from scaled bitmap processing (rem=%02X, vscale=%02X)...\n", remainder, vscale);//*/ +//Locks up here: +//--> Returned from scaled bitmap processing (rem=20, vscale=80)... +//There are other problems here, it looks like... +//Another lock up: +//About to execute OP (508)... +/* +OP: Scaled bitmap 4x? 4bpp at 38,? hscale=7C fpix=0 data=00075E28 pitch 1 hflipped=no dwidth=? (linked to 00071118) Transluency=no +--> Returned from scaled bitmap processing (rem=50, vscale=7C)... +OP: Scaled bitmap 4x? 4bpp at 38,? hscale=7C fpix=0 data=00075E28 pitch 1 hflipped=no dwidth=? (linked to 00071118) Transluency=no +--> Returned from scaled bitmap processing (rem=30, vscale=7C)... +OP: Scaled bitmap 4x? 4bpp at 38,? hscale=7C fpix=0 data=00075E28 pitch 1 hflipped=no dwidth=? (linked to 00071118) Transluency=no +--> Returned from scaled bitmap processing (rem=10, vscale=7C)... +OP: Scaled bitmap 4x? 4bpp at 36,? hscale=7E fpix=0 data=000756A8 pitch 1 hflipped=no dwidth=? (linked to 00073058) Transluency=no +--> Returned from scaled bitmap processing (rem=00, vscale=7E)... +OP: Scaled bitmap 4x? 4bpp at 34,? hscale=80 fpix=0 data=000756C8 pitch 1 hflipped=no dwidth=? (linked to 00073078) Transluency=no +--> Returned from scaled bitmap processing (rem=00, vscale=80)... +OP: Scaled bitmap 4x? 4bpp at 36,? hscale=7E fpix=0 data=000756C8 pitch 1 hflipped=no dwidth=? (linked to 00073058) Transluency=no +--> Returned from scaled bitmap processing (rem=5E, vscale=7E)... +OP: Scaled bitmap 4x? 4bpp at 34,? hscale=80 fpix=0 data=000756E8 pitch 1 hflipped=no dwidth=? (linked to 00073078) Transluency=no +--> Returned from scaled bitmap processing (rem=60, vscale=80)... +OP: Scaled bitmap 4x? 4bpp at 36,? hscale=7E fpix=0 data=000756C8 pitch 1 hflipped=no dwidth=? (linked to 00073058) Transluency=no +--> Returned from scaled bitmap processing (rem=3E, vscale=7E)... +OP: Scaled bitmap 4x? 4bpp at 34,? hscale=80 fpix=0 data=000756E8 pitch 1 hflipped=no dwidth=? (linked to 00073078) Transluency=no +--> Returned from scaled bitmap processing (rem=40, vscale=80)... +OP: Scaled bitmap 4x? 4bpp at 36,? hscale=7E fpix=0 data=000756C8 pitch 1 hflipped=no dwidth=? (linked to 00073058) Transluency=no +--> Returned from scaled bitmap processing (rem=1E, vscale=7E)... +OP: Scaled bitmap 4x? 4bpp at 34,? hscale=80 fpix=0 data=000756E8 pitch 1 hflipped=no dwidth=? (linked to 00073078) Transluency=no +--> Returned from scaled bitmap processing (rem=20, vscale=80)... +*/ +//Here's another problem: +// [hsc: 20, vsc: 20, rem: 00] +// Since we're not checking for $E0 (but that's what we get from the above), we +// end up repeating this halfline unnecessarily... !!! FIX !!! [DONE, but... +// still not quite right. Either that, or the Accolade team that wrote Bubsy +// screwed up royal.] +//Also note: $E0 = 7.0 which IS a legal vscale value... + +// if (remainder & 0x80) // I.e., it's negative +// if ((remainder & 0x80) || remainder == 0) // I.e., it's <= 0 +// if ((remainder - 1) >= 0xE0) // I.e., it's <= 0 +// if ((remainder >= 0xE1) || remainder == 0)// I.e., it's <= 0 +// if ((remainder >= 0xE1 && remainder <= 0xFF) || remainder == 0)// I.e., it's <= 0 +// if (remainder <= 0x20) // I.e., it's <= 1.0 + // I.e., it's < 1.0f -> means it'll go negative when we subtract 1.0f. + if (remainder < 0x20) + { + uint64_t data = (p0 & 0xFFFFF80000000000LL) >> 40; + uint64_t dwidth = (p1 & 0xFFC0000) >> 15; + +// while (remainder & 0x80) +// while ((remainder & 0x80) || remainder == 0) +// while ((remainder - 1) >= 0xE0) +// while ((remainder >= 0xE1) || remainder == 0) +// while ((remainder >= 0xE1 && remainder <= 0xFF) || remainder == 0) +// while (remainder <= 0x20) + while (remainder < 0x20) + { + remainder += vscale; + + if (height) + height--; + + data += dwidth; + } + + p0 &= ~0xFFFFF80000FFC000LL; // Mask out old data... + p0 |= (uint64_t)height << 14; + p0 |= data << 40; + OPStorePhrase(oldOPP, p0); + } + + remainder -= 0x20; // 1.0f in [3.5] fixed point format + +//if (start_logging) +// WriteLog("--> Finished writebacks...\n");//*/ + +//WriteLog(" [%08X%08X -> ", (uint32_t)(p2>>32), (uint32_t)(p2&0xFFFFFFFF)); + p2 &= ~0x0000000000FF0000LL; + p2 |= (uint64_t)remainder << 16; +//WriteLog("%08X%08X]\n", (uint32_t)(p2>>32), (uint32_t)(p2&0xFFFFFFFF)); + OPStorePhrase(oldOPP + 16, p2); +//remainder = (uint8_t)(p2 >> 16), vscale = (uint8_t)(p2 >> 8); +//WriteLog(" [after]: rem=%02X, vscale=%02X\n", remainder, vscale); + } + + // OP bottom 3 bits are hardwired to zero. The link address + // reflects this, so we only need the top 19 bits of the address + // (which is why we only shift 21, and not 24). + op_pointer = (p0 & 0x000007FFFF000000LL) >> 21; + + // KLUDGE: Seems that memory access is mirrored in the first 8MB of + // memory... + if (op_pointer > 0x1FFFFF && op_pointer < 0x800000) + op_pointer &= 0xFF1FFFFF; // Knock out bits 21-23 + + break; + } + case OBJECT_TYPE_GPU: + { +//WriteLog("OP: Asserting GPU IRQ #3...\n"); +#warning "Need to fix OP GPU IRQ handling! !!! FIX !!!" + OPSetCurrentObject(p0); + GPUSetIRQLine(3, ASSERT_LINE); +//Also, OP processing is suspended from this point until OBF (F00026) is written to... +// !!! FIX !!! +//Do something like: +//OPSuspendedByGPU = true; +//Dunno if the OP keeps processing from where it was interrupted, or if it just continues +//on the next halfline... +// --> It continues from where it was interrupted! !!! FIX !!! + break; + } + case OBJECT_TYPE_BRANCH: + { + uint16_t ypos = (p0 >> 3) & 0x7FF; + // JTRM is wrong: CC is bits 14-16 (3 bits, *not* 2) + uint8_t cc = (p0 >> 14) & 0x07; + uint32_t link = (p0 >> 21) & 0x3FFFF8; + + switch (cc) + { + case CONDITION_EQUAL: + if (halfline == ypos || ypos == 0x7FF) + op_pointer = link; + break; + case CONDITION_LESS_THAN: + if (halfline < ypos) + op_pointer = link; + break; + case CONDITION_GREATER_THAN: + if (halfline > ypos) + op_pointer = link; + break; + case CONDITION_OP_FLAG_SET: + if (OPGetStatusRegister() & 0x01) + op_pointer = link; + break; + case CONDITION_SECOND_HALF_LINE: + // Branch if bit 10 of HC is set... + if (TOMGetHC() & 0x0400) + op_pointer = link; + break; + default: + // Basically, if you do this, the OP does nothing. :-) + WriteLog("OP: Unimplemented branch condition %i\n", cc); + } + break; + } + case OBJECT_TYPE_STOP: + { + OPSetCurrentObject(p0); + + if ((p0 & 0x08) && TOMIRQEnabled(IRQ_OPFLAG)) + { + TOMSetPendingObjectInt(); + m68k_set_irq(2); // Cause a 68K IPL 2 to occur... + } + + // Bail out, we're done... + return; + } + default: + WriteLog("OP: Unknown object type %i\n", (uint8_t)p0 & 0x07); + } + + // Here is a little sanity check to keep the OP from locking up the + // machine when fed bad data. Better would be to count how many actual + // cycles it used and bail out/reenter to properly simulate an + // overloaded OP... !!! FIX !!! +#warning "Better would be to count how many actual cycles it used and bail out/reenter to properly simulate an overloaded OP... !!! FIX !!!" + opCyclesToRun--; + + if (!opCyclesToRun) + return; + } +} + + +// +// Store fixed size bitmap in line buffer +// +void OPProcessFixedBitmap(uint64_t p0, uint64_t p1, bool render) +{ +// Need to make sure that when writing that it stays within the line buffer... +// LBUF ($F01800 - $F01D9E) 360 x 32-bit RAM + uint8_t depth = (p1 >> 12) & 0x07; // Color depth of image + int32_t xpos = ((int16_t)((p1 << 4) & 0xFFFF)) >> 4;// Image xpos in LBUF + uint32_t iwidth = (p1 >> 28) & 0x3FF; // Image width in *phrases* + uint32_t data = (p0 >> 40) & 0xFFFFF8; // Pixel data address + uint32_t firstPix = (p1 >> 49) & 0x3F; + // "The LSB is significant only for scaled objects..." -JTRM + // "In 1 BPP mode, all five bits are significant. In 2 BPP mode, the top + // four are significant..." + firstPix &= 0x3E; + +// We can ignore the RELEASE (high order) bit for now--probably forever...! +// uint8_t flags = (p1 >> 45) & 0x0F; // REFLECT, RMW, TRANS, RELEASE +//Optimize: break these out to their own BOOL values + uint8_t flags = (p1 >> 45) & 0x07; // REFLECT (0), RMW (1), TRANS (2) + bool flagREFLECT = (flags & OPFLAG_REFLECT ? true : false), + flagRMW = (flags & OPFLAG_RMW ? true : false), + flagTRANS = (flags & OPFLAG_TRANS ? true : false); +// "For images with 1 to 4 bits/pixel the top 7 to 4 bits of the index +// provide the most significant bits of the palette address." + uint8_t index = (p1 >> 37) & 0xFE; // CLUT index offset (upper pix, 1-4 bpp) + uint32_t pitch = (p1 >> 15) & 0x07; // Phrase pitch + pitch <<= 3; // Optimization: Multiply pitch by 8 + +// int16_t scanlineWidth = tom_getVideoModeWidth(); + uint8_t * tomRam8 = TOMGetRamPointer(); + uint8_t * paletteRAM = &tomRam8[0x400]; + // This is OK as long as it's used correctly: For 16-bit RAM to RAM direct + // copies--NOT for use when using endian-corrected data (i.e., any of the + // *_word_read functions!) + uint16_t * paletteRAM16 = (uint16_t *)paletteRAM; + +// WriteLog("bitmap %ix? %ibpp at %i,? firstpix=? data=0x%.8x pitch %i hflipped=%s dwidth=? (linked to ?) RMW=%s Tranparent=%s\n", +// iwidth, op_bitmap_bit_depth[bitdepth], xpos, ptr, pitch, (flags&OPFLAG_REFLECT ? "yes" : "no"), (flags&OPFLAG_RMW ? "yes" : "no"), (flags&OPFLAG_TRANS ? "yes" : "no")); + +// Is it OK to have a 0 for the data width??? (i.e., undocumented?) +// Seems to be... Seems that dwidth *can* be zero (i.e., reuse same line) as +// well. +// Pitch == 0 is OK too... + +//kludge: Seems that the OP treats iwidth == 0 as iwidth == 1... Need to +// investigate on real hardware... +#warning "!!! Need to investigate iwidth == 0 behavior on real hardware !!!" +if (iwidth == 0) + iwidth = 1; + +// if (!render || op_pointer == 0 || ptr == 0 || pitch == 0) +//I'm not convinced that we need to concern ourselves with data & op_pointer +//here either! + if (!render || iwidth == 0) + return; + +//OK, so we know the position in the line buffer is correct. It's the clipping +//in 24bpp mode that's wrong! +#if 0 +//This is a total kludge, based upon the fact that 24BPP mode puts *4* bytes +//into the line buffer for each pixel. +if (depth == 5) // i.e., 24bpp mode... + xpos >>= 1; // Cut it in half... +#endif + +//#define OP_DEBUG_BMP +//#ifdef OP_DEBUG_BMP +// WriteLog("bitmap %ix%i %ibpp at %i,%i firstpix=%i data=0x%.8x pitch %i hflipped=%s dwidth=%i (linked to 0x%.8x) Transluency=%s\n", +// iwidth, height, op_bitmap_bit_depth[bitdepth], xpos, ypos, firstPix, ptr, pitch, (flags&OPFLAG_REFLECT ? "yes" : "no"), dwidth, op_pointer, (flags&OPFLAG_RMW ? "yes" : "no")); +//#endif + +// int32_t leftMargin = xpos, rightMargin = (xpos + (phraseWidthToPixels[depth] * iwidth)) - 1; + int32_t startPos = xpos, endPos = xpos + + (!flagREFLECT ? (phraseWidthToPixels[depth] * iwidth) - 1 + : -((phraseWidthToPixels[depth] * iwidth) + 1)); + uint32_t clippedWidth = 0, phraseClippedWidth = 0, dataClippedWidth = 0;//, phrasePixel = 0; + bool in24BPPMode = (((GET16(tomRam8, 0x0028) >> 1) & 0x03) == 1 ? true : false); // VMODE + // This is correct, the OP line buffer is a constant size... + int32_t limit = 720; + int32_t lbufWidth = 719; + + // If the image is completely to the left or right of the line buffer, then + // bail. +//If in REFLECT mode, then these values are swapped! !!! FIX !!! [DONE] +//There are four possibilities: +// 1. image sits on left edge and no REFLECT; starts out of bounds but ends in bounds. +// 2. image sits on left edge and REFLECT; starts in bounds but ends out of bounds. +// 3. image sits on right edge and REFLECT; starts out of bounds but ends in bounds. +// 4. image sits on right edge and no REFLECT; starts in bounds but ends out of bounds. +//Numbers 2 & 4 can be caught by checking the LBUF clip while in the inner loop, +// numbers 1 & 3 are of concern. +// This *indirectly* handles only cases 2 & 4! And is WRONG is REFLECT is set...! +// if (rightMargin < 0 || leftMargin > lbufWidth) + +// It might be easier to swap these (if REFLECTed) and just use XPOS down below... +// That way, you could simply set XPOS to leftMargin if !REFLECT and to rightMargin otherwise. +// Still have to be careful with the DATA and IWIDTH values though... + +// if ((!flagREFLECT && (rightMargin < 0 || leftMargin > lbufWidth)) +// || (flagREFLECT && (leftMargin < 0 || rightMargin > lbufWidth))) +// return; + if ((!flagREFLECT && (endPos < 0 || startPos > lbufWidth)) + || (flagREFLECT && (startPos < 0 || endPos > lbufWidth))) + return; + + // Otherwise, find the clip limits and clip the phrase as well... + // NOTE: I'm fudging here by letting the actual blit overstep the bounds of the + // line buffer, but it shouldn't matter since there are two unused line + // buffers below and nothing above and I'll at most write 8 bytes outside + // the line buffer... I could use a fractional clip begin/end value, but + // this makes the blit a *lot* more hairy. I might fix this in the future + // if it becomes necessary. (JLH) + // Probably wouldn't be *that* hairy. Just use a delta that tells the inner loop + // which pixel in the phrase is being written, and quit when either end of phrases + // is reached or line buffer extents are surpassed. + +//This stuff is probably wrong as well... !!! FIX !!! +//The strange thing is that it seems to work, but that's no guarantee that it's bulletproof! +//Yup. Seems that JagMania doesn't work correctly with this... +//Dunno if this is the problem, but Atari Karts is showing *some* of the road now... +// if (!flagREFLECT) + +/* + if (leftMargin < 0) + clippedWidth = 0 - leftMargin, + phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth], + leftMargin = 0 - (clippedWidth % phraseWidthToPixels[depth]); +// leftMargin = 0; + + if (rightMargin > lbufWidth) + clippedWidth = rightMargin - lbufWidth, + phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth];//, +// rightMargin = lbufWidth + (clippedWidth % phraseWidthToPixels[depth]); +// rightMargin = lbufWidth; +*/ +if (depth > 5) + WriteLog("OP: We're about to encounter a divide by zero error!\n"); + // NOTE: We're just using endPos to figure out how much, if any, to clip by. + // ALSO: There may be another case where we start out of bounds and end out + // of bounds...! + // !!! FIX !!! + if (startPos < 0) // Case #1: Begin out, end in, L to R + clippedWidth = 0 - startPos, + dataClippedWidth = phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth], + startPos = 0 - (clippedWidth % phraseWidthToPixels[depth]); + + if (endPos < 0) // Case #2: Begin in, end out, R to L + clippedWidth = 0 - endPos, + phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth]; + + if (endPos > lbufWidth) // Case #3: Begin in, end out, L to R + clippedWidth = endPos - lbufWidth, + phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth]; + + if (startPos > lbufWidth) // Case #4: Begin out, end in, R to L + clippedWidth = startPos - lbufWidth, + dataClippedWidth = phraseClippedWidth = clippedWidth / phraseWidthToPixels[depth], + startPos = lbufWidth + (clippedWidth % phraseWidthToPixels[depth]); +//printf("> 5) | 0x02; + + // Fetch 1st phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); +//Note that firstPix should only be honored *if* we start with the 1st phrase of the bitmap +//i.e., we didn't clip on the margin... !!! FIX !!! + pixels <<= firstPix; // Skip first N pixels (N=firstPix)... + int i = firstPix; // Start counter at right spot... + + while (iwidth--) + { + while (i++ < 64) + { + uint8_t bit = pixels >> 63; +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bit == 0) +#else + if (flagTRANS && (paletteRAM16[index | bit] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) +//Optimize: Set palleteRAM16 to beginning of palette RAM + index*2 and use only [bit] as index... +//Won't optimize RMW case though... + // This is the *only* correct use of endian-dependent code + // (i.e., mem-to-mem direct copying)! + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bit]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bit) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bit) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + pixels <<= 1; + } + i = 0; + // Fetch next phrase... + data += pitch; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + } + } + else if (depth == 1) // 2 BPP + { +if (firstPix) + WriteLog("OP: Fixed bitmap @ 2 BPP requesting FIRSTPIX! (fp=%u)\n", firstPix); + index &= 0xFC; // Top six bits form CLUT index + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + while (iwidth--) + { + // Fetch phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + data += pitch; + + for(int i=0; i<32; i++) + { + uint8_t bits = pixels >> 62; +// Seems to me that both of these are in the same endian, so we could cast it as +// uint16_t * and do straight across copies (what about 24 bpp? Treat it differently...) +// This only works for the palettized modes (1 - 8 BPP), since we actually have to +// copy data from memory in 16 BPP mode (or does it? Isn't this the same as the CLUT case?) +// No, it isn't because we read the memory in an endian safe way--this *won't* work... +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[index | bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bits) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bits) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + pixels <<= 2; + } + } + } + else if (depth == 2) // 4 BPP + { +if (firstPix) + WriteLog("OP: Fixed bitmap @ 4 BPP requesting FIRSTPIX! (fp=%u)\n", firstPix); + index &= 0xF0; // Top four bits form CLUT index + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + while (iwidth--) + { + // Fetch phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + data += pitch; + + for(int i=0; i<16; i++) + { + uint8_t bits = pixels >> 60; +// Seems to me that both of these are in the same endian, so we could cast it as +// uint16_t * and do straight across copies (what about 24 bpp? Treat it differently...) +// This only works for the palettized modes (1 - 8 BPP), since we actually have to +// copy data from memory in 16 BPP mode (or does it? Isn't this the same as the CLUT case?) +// No, it isn't because we read the memory in an endian safe way--this *won't* work... +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[index | bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bits) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bits) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + pixels <<= 4; + } + } + } + else if (depth == 3) // 8 BPP + { + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + // Fetch 1st phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); +//Note that firstPix should only be honored *if* we start with the 1st phrase of the bitmap +//i.e., we didn't clip on the margin... !!! FIX !!! + firstPix &= 0x30; // Only top two bits are valid for 8 BPP + pixels <<= firstPix; // Skip first N pixels (N=firstPix)... + int i = firstPix >> 3; // Start counter at right spot... + + while (iwidth--) + { + while (i++ < 8) + { + uint8_t bits = pixels >> 56; +// Seems to me that both of these are in the same endian, so we could cast it as +// uint16_t * and do straight across copies (what about 24 bpp? Treat it differently...) +// This only works for the palettized modes (1 - 8 BPP), since we actually have to +// copy data from memory in 16 BPP mode (or does it? Isn't this the same as the CLUT case?) +// No, it isn't because we read the memory in an endian safe way--this *won't* work... +//This would seem to be problematic... +//Because it's the palette entry being zero that makes the pixel transparent... +//Let's try it and see. +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + *(uint16_t *)currentLineBuffer = paletteRAM16[bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[bits << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[(bits << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + pixels <<= 8; + } + i = 0; + // Fetch next phrase... + data += pitch; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + } + } + else if (depth == 4) // 16 BPP + { +if (firstPix) + WriteLog("OP: Fixed bitmap @ 16 BPP requesting FIRSTPIX! (fp=%u)\n", firstPix); + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + while (iwidth--) + { + // Fetch phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + data += pitch; + + for(int i=0; i<4; i++) + { + uint8_t bitsHi = pixels >> 56, bitsLo = pixels >> 48; +// Seems to me that both of these are in the same endian, so we could cast it +// as uint16_t * and do straight across copies (what about 24 bpp? Treat it +// differently...) This only works for the palettized modes (1 - 8 BPP), since +// we actually have to copy data from memory in 16 BPP mode (or does it? Isn't +// this the same as the CLUT case?) No, it isn't because we read the memory in +// an endian safe way--it *won't* work... +//This doesn't seem right... Let's try the encoded black value ($8800): +//Apparently, CRY 0 maps to $8800... + if (flagTRANS && ((bitsLo | bitsHi) == 0)) +// if (flagTRANS && (bitsHi == 0x88) && (bitsLo == 0x00)) + ; // Do nothing... + else + { + if (!flagRMW) + *currentLineBuffer = bitsHi, + *(currentLineBuffer + 1) = bitsLo; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, bitsHi), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), bitsLo); + } + + currentLineBuffer += lbufDelta; + pixels <<= 16; + } + } + } + else if (depth == 5) // 24 BPP + { +//Looks like Iron Soldier is the only game that uses 24BPP mode... +//There *might* be others... +//WriteLog("OP: Writing 24 BPP bitmap!\n"); +if (firstPix) + WriteLog("OP: Fixed bitmap @ 24 BPP requesting FIRSTPIX! (fp=%u)\n", firstPix); + // Not sure, but I think RMW only works with 16 BPP and below, and only in CRY mode... + // The LSB of flags is OPFLAG_REFLECT, so sign extend it and OR 4 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 4) | 0x04; + + while (iwidth--) + { + // Fetch phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + data += pitch; + + for(int i=0; i<2; i++) + { + // We don't use a 32-bit var here because of endian issues...! + uint8_t bits3 = pixels >> 56, bits2 = pixels >> 48, + bits1 = pixels >> 40, bits0 = pixels >> 32; + + if (flagTRANS && (bits3 | bits2 | bits1 | bits0) == 0) + ; // Do nothing... + else + *currentLineBuffer = bits3, + *(currentLineBuffer + 1) = bits2, + *(currentLineBuffer + 2) = bits1, + *(currentLineBuffer + 3) = bits0; + + currentLineBuffer += lbufDelta; + pixels <<= 32; + } + } + } +} + + +// +// Store scaled bitmap in line buffer +// +void OPProcessScaledBitmap(uint64_t p0, uint64_t p1, uint64_t p2, bool render) +{ +// Need to make sure that when writing that it stays within the line buffer... +// LBUF ($F01800 - $F01D9E) 360 x 32-bit RAM + uint8_t depth = (p1 >> 12) & 0x07; // Color depth of image + int32_t xpos = ((int16_t)((p1 << 4) & 0xFFFF)) >> 4;// Image xpos in LBUF + uint32_t iwidth = (p1 >> 28) & 0x3FF; // Image width in *phrases* + uint32_t data = (p0 >> 40) & 0xFFFFF8; // Pixel data address +//#ifdef OP_DEBUG_BMP +// Prolly should use this... Though not sure exactly how. +//Use the upper bits as an offset into the phrase depending on the BPP. That's how! + uint32_t firstPix = (p1 >> 49) & 0x3F; +//This is WEIRD! I'm sure I saw Atari Karts request 8 BPP FIRSTPIX! What happened??? +if (firstPix) + WriteLog("OP: FIRSTPIX != 0! (Scaled BM)\n"); +//#endif +// We can ignore the RELEASE (high order) bit for now--probably forever...! +// uint8_t flags = (p1 >> 45) & 0x0F; // REFLECT, RMW, TRANS, RELEASE +//Optimize: break these out to their own BOOL values [DONE] + uint8_t flags = (p1 >> 45) & 0x07; // REFLECT (0), RMW (1), TRANS (2) + bool flagREFLECT = (flags & OPFLAG_REFLECT ? true : false), + flagRMW = (flags & OPFLAG_RMW ? true : false), + flagTRANS = (flags & OPFLAG_TRANS ? true : false); + uint8_t index = (p1 >> 37) & 0xFE; // CLUT index offset (upper pix, 1-4 bpp) + uint32_t pitch = (p1 >> 15) & 0x07; // Phrase pitch + + uint8_t * tomRam8 = TOMGetRamPointer(); + uint8_t * paletteRAM = &tomRam8[0x400]; + // This is OK as long as it's used correctly: For 16-bit RAM to RAM direct + // copies--NOT for use when using endian-corrected data (i.e., any of the + // *ReadWord functions!) + uint16_t * paletteRAM16 = (uint16_t *)paletteRAM; + + uint16_t hscale = p2 & 0xFF; +// Hmm. It seems that fixing the horizontal scale necessitated re-fixing this. +// Not sure why, but seems to be consistent with the vertical scaling now (and +// it may turn out to be wrong!)... + uint16_t horizontalRemainder = hscale; // Not sure if it starts full, but seems reasonable [It's not!] +// uint8_t horizontalRemainder = 0; // Let's try zero! Seems to work! Yay! [No, it doesn't!] + int32_t scaledWidthInPixels = (iwidth * phraseWidthToPixels[depth] * hscale) >> 5; + uint32_t scaledPhrasePixels = (phraseWidthToPixels[depth] * hscale) >> 5; + +// WriteLog("bitmap %ix? %ibpp at %i,? firstpix=? data=0x%.8x pitch %i hflipped=%s dwidth=? (linked to ?) RMW=%s Tranparent=%s\n", +// iwidth, op_bitmap_bit_depth[bitdepth], xpos, ptr, pitch, (flags&OPFLAG_REFLECT ? "yes" : "no"), (flags&OPFLAG_RMW ? "yes" : "no"), (flags&OPFLAG_TRANS ? "yes" : "no")); + +// Looks like an hscale of zero means don't draw! + if (!render || iwidth == 0 || hscale == 0) + return; + +/*extern int start_logging; +if (start_logging) + WriteLog("OP: Scaled bitmap %ix? %ibpp at %i,? hscale=%02X fpix=%i data=%08X pitch %i hflipped=%s dwidth=? (linked to %08X) Transluency=%s\n", + iwidth, op_bitmap_bit_depth[depth], xpos, hscale, firstPix, data, pitch, (flagREFLECT ? "yes" : "no"), op_pointer, (flagRMW ? "yes" : "no"));*/ +//#define OP_DEBUG_BMP +//#ifdef OP_DEBUG_BMP +// WriteLog("OP: Scaled bitmap %ix%i %ibpp at %i,%i firstpix=%i data=0x%.8x pitch %i hflipped=%s dwidth=%i (linked to 0x%.8x) Transluency=%s\n", +// iwidth, height, op_bitmap_bit_depth[bitdepth], xpos, ypos, firstPix, ptr, pitch, (flags&OPFLAG_REFLECT ? "yes" : "no"), dwidth, op_pointer, (flags&OPFLAG_RMW ? "yes" : "no")); +//#endif + + int32_t startPos = xpos, endPos = xpos + + (!flagREFLECT ? scaledWidthInPixels - 1 : -(scaledWidthInPixels + 1)); + uint32_t clippedWidth = 0, phraseClippedWidth = 0, dataClippedWidth = 0; + bool in24BPPMode = (((GET16(tomRam8, 0x0028) >> 1) & 0x03) == 1 ? true : false); // VMODE + // Not sure if this is Jaguar Two only location or what... + // From the docs, it is... If we want to limit here we should think of something else. +// int32_t limit = GET16(tom_ram_8, 0x0008); // LIMIT + int32_t limit = 720; +// int32_t lbufWidth = (!in24BPPMode ? limit - 1 : (limit / 2) - 1); // Zero based limit... + int32_t lbufWidth = 719; // Zero based limit... + + // If the image is completely to the left or right of the line buffer, then bail. +//If in REFLECT mode, then these values are swapped! !!! FIX !!! [DONE] +//There are four possibilities: +// 1. image sits on left edge and no REFLECT; starts out of bounds but ends in bounds. +// 2. image sits on left edge and REFLECT; starts in bounds but ends out of bounds. +// 3. image sits on right edge and REFLECT; starts out of bounds but ends in bounds. +// 4. image sits on right edge and no REFLECT; starts in bounds but ends out of bounds. +//Numbers 2 & 4 can be caught by checking the LBUF clip while in the inner loop, +// numbers 1 & 3 are of concern. +// This *indirectly* handles only cases 2 & 4! And is WRONG if REFLECT is set...! +// if (rightMargin < 0 || leftMargin > lbufWidth) + +// It might be easier to swap these (if REFLECTed) and just use XPOS down below... +// That way, you could simply set XPOS to leftMargin if !REFLECT and to rightMargin otherwise. +// Still have to be careful with the DATA and IWIDTH values though... + + if ((!flagREFLECT && (endPos < 0 || startPos > lbufWidth)) + || (flagREFLECT && (startPos < 0 || endPos > lbufWidth))) + return; + + // Otherwise, find the clip limits and clip the phrase as well... + // NOTE: I'm fudging here by letting the actual blit overstep the bounds of + // the line buffer, but it shouldn't matter since there are two + // unused line buffers below and nothing above and I'll at most write + // 40 bytes outside the line buffer... I could use a fractional clip + // begin/end value, but this makes the blit a *lot* more hairy. I + // might fix this in the future if it becomes necessary. (JLH) + // Probably wouldn't be *that* hairy. Just use a delta that tells the + // inner loop which pixel in the phrase is being written, and quit + // when either end of phrases is reached or line buffer extents are + // surpassed. + +//This stuff is probably wrong as well... !!! FIX !!! +//The strange thing is that it seems to work, but that's no guarantee that it's +//bulletproof! +//Yup. Seems that JagMania doesn't work correctly with this... +//Dunno if this is the problem, but Atari Karts is showing *some* of the road +//now... +//Actually, it is! Or, it was. It doesn't seem to be clipping here, so the +//problem lies elsewhere! Hmm. Putting the scaling code into the 1/2/8 BPP cases +//seems to draw the ground a bit more accurately... Strange! +//It's probably a case of the REFLECT flag being set and the background being +//written from the right side of the screen... +//But no, it isn't... At least if the diagnostics are telling the truth! + + // NOTE: We're just using endPos to figure out how much, if any, to clip by. + // ALSO: There may be another case where we start out of bounds and end out + // of bounds...! + // !!! FIX !!! + +//There's a problem here with scaledPhrasePixels in that it can be forced to +//zero when the scaling factor is small. So fix it already! !!! FIX !!! +/*if (scaledPhrasePixels == 0) +{ + WriteLog("OP: [Scaled] We're about to encounter a divide by zero error!\n"); + DumpScaledObject(p0, p1, p2); +}//*/ +//NOTE: I'm almost 100% sure that this is wrong... And it is! :-p + +//Try a simple example... +// Let's say we have a 8 BPP scanline with an hscale of $80 (4). Our xpos is -10, +// non-flipped. Pixels in the bitmap are XYZXYZXYZXYZXYZ. +// Scaled up, they would be XXXXYYYYZZZZXXXXYYYYZZZZXXXXYYYYZZZZ... +// +// Normally, we would expect this in the line buffer: +// ZZXXXXYYYYZZZZXXXXYYYYZZZZ... +// +// But instead we're getting: +// XXXXYYYYZZZZXXXXYYYYZZZZ... +// +// or are we??? It would seem so, simply by virtue of the fact that we're NOT starting +// on negative boundary--or are we? Hmm... +// cw = 10, dcw = pcw = 10 / ([8 * 4 = 32] 32) = 0, sp = -10 +// +// Let's try a real world example: +// +//OP: Scaled bitmap (70, 8 BPP, spp=28) sp (-400) < 0... [new sp=-8, cw=400, dcw=pcw=14] +//OP: Scaled bitmap (6F, 8 BPP, spp=27) sp (-395) < 0... [new sp=-17, cw=395, dcw=pcw=14] +// +// Really, spp is 27.75 in the second case... +// So... If we do 395 / 27.75, we get 14. Ok so far... If we scale that against the +// start position (14 * 27.75), we get -6.5... NOT -17! + +//Now it seems we're working OK, at least for the first case... +uint32_t scaledPhrasePixelsUS = phraseWidthToPixels[depth] * hscale; + + if (startPos < 0) // Case #1: Begin out, end in, L to R +{ +extern int start_logging; +if (start_logging) + WriteLog("OP: Scaled bitmap (%02X, %u BPP, spp=%u) start pos (%i) < 0...", hscale, op_bitmap_bit_depth[depth], scaledPhrasePixels, startPos); +// clippedWidth = 0 - startPos, + clippedWidth = (0 - startPos) << 5, +// dataClippedWidth = phraseClippedWidth = clippedWidth / scaledPhrasePixels, + dataClippedWidth = phraseClippedWidth = (clippedWidth / scaledPhrasePixelsUS) >> 5, +// startPos = 0 - (clippedWidth % scaledPhrasePixels); + startPos += (dataClippedWidth * scaledPhrasePixelsUS) >> 5; +if (start_logging) + WriteLog(" [new sp=%i, cw=%i, dcw=pcw=%i]\n", startPos, clippedWidth, dataClippedWidth); +} + + if (endPos < 0) // Case #2: Begin in, end out, R to L + clippedWidth = 0 - endPos, + phraseClippedWidth = clippedWidth / scaledPhrasePixels; + + if (endPos > lbufWidth) // Case #3: Begin in, end out, L to R + clippedWidth = endPos - lbufWidth, + phraseClippedWidth = clippedWidth / scaledPhrasePixels; + + if (startPos > lbufWidth) // Case #4: Begin out, end in, R to L + clippedWidth = startPos - lbufWidth, + dataClippedWidth = phraseClippedWidth = clippedWidth / scaledPhrasePixels, + startPos = lbufWidth + (clippedWidth % scaledPhrasePixels); + +extern int op_start_log; +if (op_start_log && clippedWidth != 0) + WriteLog("OP: Clipped line. SP=%i, EP=%i, clip=%u, iwidth=%u, hscale=%02X\n", startPos, endPos, clippedWidth, iwidth, hscale); +if (op_start_log && startPos == 13) +{ + WriteLog("OP: Scaled line. SP=%i, EP=%i, clip=%u, iwidth=%u, hscale=%02X, depth=%u, firstPix=%u\n", startPos, endPos, clippedWidth, iwidth, hscale, depth, firstPix); + DumpScaledObject(p0, p1, p2); + if (iwidth == 7) + { + WriteLog(" %08X: ", data); + for(int i=0; i<7*8; i++) + WriteLog("%02X ", JaguarReadByte(data+i)); + WriteLog("\n"); + } +} + // If the image is sitting on the line buffer left or right edge, we need to compensate + // by decreasing the image phrase width accordingly. + iwidth -= phraseClippedWidth; + + // Also, if we're clipping the phrase we need to make sure we're in the correct part of + // the pixel data. +// data += phraseClippedWidth * (pitch << 3); + data += dataClippedWidth * (pitch << 3); + + // NOTE: When the bitmap is in REFLECT mode, the XPOS marks the *right* side of the + // bitmap! This makes clipping & etc. MUCH, much easier...! +// uint32_t lbufAddress = 0x1800 + (!in24BPPMode ? leftMargin * 2 : leftMargin * 4); +// uint32_t lbufAddress = 0x1800 + (!in24BPPMode ? startPos * 2 : startPos * 4); + uint32_t lbufAddress = 0x1800 + startPos * 2; + uint8_t * currentLineBuffer = &tomRam8[lbufAddress]; +//uint8_t * lineBufferLowerLimit = &tom_ram_8[0x1800], +// * lineBufferUpperLimit = &tom_ram_8[0x1800 + 719]; + + // Render. + +// Hmm. We check above for 24 BPP mode, but don't do anything about it below... +// If we *were* in 24 BPP mode, how would you convert CRY to RGB24? Seems to me +// that if you're in CRY mode then you wouldn't be able to use 24 BPP bitmaps +// anyway. +// This seems to be the case (at least according to the Midsummer docs)...! + + if (depth == 0) // 1 BPP + { +if (firstPix != 0) + WriteLog("OP: Scaled bitmap @ 1 BPP requesting FIRSTPIX!\n"); + // The LSB of flags is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + int pixCount = 0; + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + + while ((int32_t)iwidth > 0) + { + uint8_t bits = pixels >> 63; + +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[index | bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + // This is the *only* correct use of endian-dependent code + // (i.e., mem-to-mem direct copying)! + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bits) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bits) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + +/* +The reason we subtract the horizontalRemainder *after* the test is because we had too few +bytes for horizontalRemainder to properly recognize a negative number. But now it's 16 bits +wide, so we could probably go back to that (as long as we make it an int16_t and not a uint16!) +*/ +/* horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + while (horizontalRemainder & 0x80) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 1; + }//*/ +// while (horizontalRemainder <= 0x20) // I.e., it's <= 1.0 (*before* subtraction) + while (horizontalRemainder < 0x20) // I.e., it's <= 1.0 (*before* subtraction) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 1; + } + horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + + if (pixCount > 63) + { + int phrasesToSkip = pixCount / 64, pixelShift = pixCount % 64; + + data += (pitch << 3) * phrasesToSkip; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + pixels <<= 1 * pixelShift; + iwidth -= phrasesToSkip; + pixCount = pixelShift; + } + } + } + else if (depth == 1) // 2 BPP + { +if (firstPix != 0) + WriteLog("OP: Scaled bitmap @ 2 BPP requesting FIRSTPIX!\n"); + index &= 0xFC; // Top six bits form CLUT index + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + int pixCount = 0; + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + + while ((int32_t)iwidth > 0) + { + uint8_t bits = pixels >> 62; + +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[index | bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + // This is the *only* correct use of endian-dependent code + // (i.e., mem-to-mem direct copying)! + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bits) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bits) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + +/* horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + while (horizontalRemainder & 0x80) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 2; + }//*/ +// while (horizontalRemainder <= 0x20) // I.e., it's <= 0 (*before* subtraction) + while (horizontalRemainder < 0x20) // I.e., it's <= 1.0 (*before* subtraction) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 2; + } + horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + + if (pixCount > 31) + { + int phrasesToSkip = pixCount / 32, pixelShift = pixCount % 32; + + data += (pitch << 3) * phrasesToSkip; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + pixels <<= 2 * pixelShift; + iwidth -= phrasesToSkip; + pixCount = pixelShift; + } + } + } + else if (depth == 2) // 4 BPP + { +if (firstPix != 0) + WriteLog("OP: Scaled bitmap @ 4 BPP requesting FIRSTPIX!\n"); + index &= 0xF0; // Top four bits form CLUT index + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + int pixCount = 0; + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + + while ((int32_t)iwidth > 0) + { + uint8_t bits = pixels >> 60; + +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[index | bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + // This is the *only* correct use of endian-dependent code + // (i.e., mem-to-mem direct copying)! + *(uint16_t *)currentLineBuffer = paletteRAM16[index | bits]; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[(index | bits) << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[((index | bits) << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + +/* horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + while (horizontalRemainder & 0x80) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 4; + }//*/ +// while (horizontalRemainder <= 0x20) // I.e., it's <= 0 (*before* subtraction) + while (horizontalRemainder < 0x20) // I.e., it's <= 0 (*before* subtraction) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 4; + } + horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + + if (pixCount > 15) + { + int phrasesToSkip = pixCount / 16, pixelShift = pixCount % 16; + + data += (pitch << 3) * phrasesToSkip; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + pixels <<= 4 * pixelShift; + iwidth -= phrasesToSkip; + pixCount = pixelShift; + } + } + } + else if (depth == 3) // 8 BPP + { +if (firstPix) + WriteLog("OP: Scaled bitmap @ 8 BPP requesting FIRSTPIX! (fp=%u)\n", firstPix); + // The LSB is OPFLAG_REFLECT, so sign extend it and or 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + int pixCount = 0; + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + + while ((int32_t)iwidth > 0) + { + uint8_t bits = pixels >> 56; + +#ifndef OP_USES_PALETTE_ZERO + if (flagTRANS && bits == 0) +#else + if (flagTRANS && (paletteRAM16[bits] == 0)) +#endif + ; // Do nothing... + else + { + if (!flagRMW) + // This is the *only* correct use of endian-dependent code + // (i.e., mem-to-mem direct copying)! + *(uint16_t *)currentLineBuffer = paletteRAM16[bits]; +/* { + if (currentLineBuffer >= lineBufferLowerLimit && currentLineBuffer <= lineBufferUpperLimit) + *(uint16_t *)currentLineBuffer = paletteRAM16[bits]; + }*/ + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, paletteRAM[bits << 1]), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), paletteRAM[(bits << 1) + 1]); + } + + currentLineBuffer += lbufDelta; + +// while (horizontalRemainder <= 0x20) // I.e., it's <= 0 (*before* subtraction) + while (horizontalRemainder < 0x20) // I.e., it's <= 1.0 (*before* subtraction) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 8; + } + horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + + if (pixCount > 7) + { + int phrasesToSkip = pixCount / 8, pixelShift = pixCount % 8; + + data += (pitch << 3) * phrasesToSkip; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + pixels <<= 8 * pixelShift; + iwidth -= phrasesToSkip; + pixCount = pixelShift; + } + } + } + else if (depth == 4) // 16 BPP + { +if (firstPix != 0) + WriteLog("OP: Scaled bitmap @ 16 BPP requesting FIRSTPIX!\n"); + // The LSB is OPFLAG_REFLECT, so sign extend it and OR 2 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 5) | 0x02; + + int pixCount = 0; + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + + while ((int32_t)iwidth > 0) + { + uint8_t bitsHi = pixels >> 56, bitsLo = pixels >> 48; + +//This doesn't seem right... Let's try the encoded black value ($8800): +//Apparently, CRY 0 maps to $8800... + if (flagTRANS && ((bitsLo | bitsHi) == 0)) +// if (flagTRANS && (bitsHi == 0x88) && (bitsLo == 0x00)) + ; // Do nothing... + else + { + if (!flagRMW) + *currentLineBuffer = bitsHi, + *(currentLineBuffer + 1) = bitsLo; + else + *currentLineBuffer = + BLEND_CR(*currentLineBuffer, bitsHi), + *(currentLineBuffer + 1) = + BLEND_Y(*(currentLineBuffer + 1), bitsLo); + } + + currentLineBuffer += lbufDelta; + +/* horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format + while (horizontalRemainder & 0x80) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 16; + }//*/ +// while (horizontalRemainder <= 0x20) // I.e., it's <= 0 (*before* subtraction) + while (horizontalRemainder < 0x20) // I.e., it's <= 1.0 (*before* subtraction) + { + horizontalRemainder += hscale; + pixCount++; + pixels <<= 16; + } + horizontalRemainder -= 0x20; // Subtract 1.0f in [3.5] fixed point format +//*/ + if (pixCount > 3) + { + int phrasesToSkip = pixCount / 4, pixelShift = pixCount % 4; + + data += (pitch << 3) * phrasesToSkip; + pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + pixels <<= 16 * pixelShift; + + iwidth -= phrasesToSkip; + + pixCount = pixelShift; + } + } + } + else if (depth == 5) // 24 BPP + { +//I'm not sure that you can scale a 24 BPP bitmap properly--the JTRM seem to indicate as much. +WriteLog("OP: Writing 24 BPP scaled bitmap!\n"); +if (firstPix != 0) + WriteLog("OP: Scaled bitmap @ 24 BPP requesting FIRSTPIX!\n"); + // Not sure, but I think RMW only works with 16 BPP and below, and only in CRY mode... + // The LSB is OPFLAG_REFLECT, so sign extend it and or 4 into it. + int32_t lbufDelta = ((int8_t)((flags << 7) & 0xFF) >> 4) | 0x04; + + while (iwidth--) + { + // Fetch phrase... + uint64_t pixels = ((uint64_t)JaguarReadLong(data, OP) << 32) | JaguarReadLong(data + 4, OP); + data += pitch << 3; // Multiply pitch * 8 (optimize: precompute this value) + + for(int i=0; i<2; i++) + { + uint8_t bits3 = pixels >> 56, bits2 = pixels >> 48, + bits1 = pixels >> 40, bits0 = pixels >> 32; + + if (flagTRANS && (bits3 | bits2 | bits1 | bits0) == 0) + ; // Do nothing... + else + *currentLineBuffer = bits3, + *(currentLineBuffer + 1) = bits2, + *(currentLineBuffer + 2) = bits1, + *(currentLineBuffer + 3) = bits0; + + currentLineBuffer += lbufDelta; + pixels <<= 32; + } + } + } +} diff --git a/waterbox/virtualjaguar/src/op.h b/waterbox/virtualjaguar/src/op.h new file mode 100644 index 0000000000..ad9040088b --- /dev/null +++ b/waterbox/virtualjaguar/src/op.h @@ -0,0 +1,31 @@ +// +// OBJECTP.H: Object Processor header file +// + +#ifndef __OBJECTP_H__ +#define __OBJECTP_H__ + +#include + +void OPInit(void); +void OPReset(void); +void OPDone(void); + +uint64_t OPLoadPhrase(uint32_t offset); + +void OPProcessList(int scanline, bool render); +uint32_t OPGetListPointer(void); +void OPSetStatusRegister(uint32_t data); +uint32_t OPGetStatusRegister(void); +void OPSetCurrentObject(uint64_t object); + +#define OPFLAG_RELEASE 8 // Bus release bit +#define OPFLAG_TRANS 4 // Transparency bit +#define OPFLAG_RMW 2 // Read-Modify-Write bit +#define OPFLAG_REFLECT 1 // Horizontal mirror bit + +// Exported variables + +extern uint8_t objectp_running; + +#endif // __OBJECTP_H__ diff --git a/waterbox/virtualjaguar/src/settings.cpp b/waterbox/virtualjaguar/src/settings.cpp new file mode 100644 index 0000000000..7cf1efaea4 --- /dev/null +++ b/waterbox/virtualjaguar/src/settings.cpp @@ -0,0 +1,20 @@ +// +// SETTINGS.CPP: Virtual Jaguar configuration loading/saving support +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------ +// JLH 01/16/2010 Created this log +// JLH 02/23/2013 Finally removed commented out stuff :-P +// + +#include "settings.h" + +// Global variables + +VJSettings vjs; + diff --git a/waterbox/virtualjaguar/src/settings.h b/waterbox/virtualjaguar/src/settings.h new file mode 100644 index 0000000000..0b196b72d0 --- /dev/null +++ b/waterbox/virtualjaguar/src/settings.h @@ -0,0 +1,72 @@ +// +// settings.h: Header file +// + +#ifndef __SETTINGS_H__ +#define __SETTINGS_H__ + +#define MAX_PATH 69 + +// MAX_PATH isn't defined in stdlib.h on *nix, so we do it here... +#ifdef __GCCUNIX__ +#include +#define MAX_PATH _POSIX_PATH_MAX +#else +#include // for MAX_PATH on MinGW/Darwin +// Kludge for Win64 +#ifndef MAX_PATH +#define MAX_PATH _MAX_PATH // Urgh. +#endif +#endif +#include + +// Settings struct + +struct VJSettings +{ + bool useJoystick; + int32_t joyport; // Joystick port + bool hardwareTypeNTSC; // Set to false for PAL + bool useJaguarBIOS; + bool GPUEnabled; + bool DSPEnabled; + bool usePipelinedDSP; + bool fullscreen; + bool useOpenGL; + uint32_t glFilter; + bool hardwareTypeAlpine; + bool audioEnabled; + uint32_t frameSkip; + uint32_t renderType; + bool allowWritesToROM; + uint32_t biosType; + bool useFastBlitter; + + // Keybindings in order of U, D, L, R, C, B, A, Op, Pa, 0-9, #, * + + uint32_t p1KeyBindings[21]; + uint32_t p2KeyBindings[21]; + + // Paths + + char ROMPath[MAX_PATH]; + char jagBootPath[MAX_PATH]; + char CDBootPath[MAX_PATH]; + char EEPROMPath[MAX_PATH]; + char alpineROMPath[MAX_PATH]; + char absROMPath[MAX_PATH]; +}; + +// Render types + +enum { RT_NORMAL = 0, RT_TV = 1 }; + +// BIOS types + +enum { BT_K_SERIES, BT_M_SERIES, BT_STUBULATOR_1, BT_STUBULATOR_2 }; + +// Exported variables + +extern VJSettings vjs; + +#endif // __SETTINGS_H__ diff --git a/waterbox/virtualjaguar/src/state.cpp b/waterbox/virtualjaguar/src/state.cpp new file mode 100644 index 0000000000..10fe306d95 --- /dev/null +++ b/waterbox/virtualjaguar/src/state.cpp @@ -0,0 +1,25 @@ +// +// state.cpp: VJ machine state save/load support +// +// by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +#include "state.h" + +bool SaveState(void) +{ + return false; +} + +bool LoadState(void) +{ + return false; +} + diff --git a/waterbox/virtualjaguar/src/state.h b/waterbox/virtualjaguar/src/state.h new file mode 100644 index 0000000000..54e3730121 --- /dev/null +++ b/waterbox/virtualjaguar/src/state.h @@ -0,0 +1,13 @@ +// +// state.h: Machine state save/load support +// +// by James L. Hammons +// + +#ifndef __STATE_H__ +#define __STATE_H__ + +bool SaveState(void); +bool LoadState(void); + +#endif // __STATE_H__ diff --git a/waterbox/virtualjaguar/src/tom.cpp b/waterbox/virtualjaguar/src/tom.cpp new file mode 100644 index 0000000000..ac67a3fcb4 --- /dev/null +++ b/waterbox/virtualjaguar/src/tom.cpp @@ -0,0 +1,1728 @@ +// +// TOM Processing +// +// Originally by David Raingeard (cal2) +// GCC/SDL port by Niels Wagenaar (Linux/WIN32) and Caz (BeOS) +// Cleanups, endian wrongness amelioration, and extensive fixes by James Hammons +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ----------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// JLH 01/20/2011 Change rendering to RGBA, removed unnecessary code +// +// Note: TOM has only a 16K memory space +// +// ------------------------------------------------------------ +// TOM REGISTERS (Mapped by Aaron Giles) +// ------------------------------------------------------------ +// F00000-F0FFFF R/W xxxxxxxx xxxxxxxx Internal Registers +// F00000 R/W -x-xx--- xxxxxxxx MEMCON1 - memory config reg 1 +// -x------ -------- (CPU32 - is the CPU 32bits?) +// ---xx--- -------- (IOSPEED - external I/O clock cycles) +// -------- x------- (FASTROM - reduces ROM clock cycles) +// -------- -xx----- (DRAMSPEED - sets RAM clock cycles) +// -------- ---xx--- (ROMSPEED - sets ROM clock cycles) +// -------- -----xx- (ROMWIDTH - sets width of ROM: 8,16,32,64 bits) +// -------- -------x (ROMHI - controls ROM mapping) +// F00002 R/W --xxxxxx xxxxxxxx MEMCON2 - memory config reg 2 +// --x----- -------- (HILO - image display bit order) +// ---x---- -------- (BIGEND - big endian addressing?) +// ----xxxx -------- (REFRATE - DRAM refresh rate) +// -------- xx------ (DWIDTH1 - DRAM1 width: 8,16,32,64 bits) +// -------- --xx---- (COLS1 - DRAM1 columns: 256,512,1024,2048) +// -------- ----xx-- (DWIDTH0 - DRAM0 width: 8,16,32,64 bits) +// -------- ------xx (COLS0 - DRAM0 columns: 256,512,1024,2048) +// F00004 R/W -----xxx xxxxxxxx HC - horizontal count +// -----x-- -------- (which half of the display) +// ------xx xxxxxxxx (10-bit counter) +// F00006 R/W ----xxxx xxxxxxxx VC - vertical count +// ----x--- -------- (which field is being generated) +// -----xxx xxxxxxxx (11-bit counter) +// F00008 R -----xxx xxxxxxxx LPH - light pen horizontal position +// F0000A R -----xxx xxxxxxxx LPV - light pen vertical position +// F00010-F00017 R xxxxxxxx xxxxxxxx OB - current object code from the graphics processor +// F00020-F00023 W xxxxxxxx xxxxxxxx OLP - start of the object list +// F00026 W -------- -------x OBF - object processor flag +// F00028 W ----xxxx xxxxxxxx VMODE - video mode +// W ----xxx- -------- (PWIDTH1-8 - width of pixel in video clock cycles) +// W -------x -------- (VARMOD - enable variable color resolution) +// W -------- x------- (BGEN - clear line buffer to BG color) +// W -------- -x------ (CSYNC - enable composite sync on VSYNC) +// W -------- --x----- (BINC - local border color if INCEN) +// W -------- ---x---- (INCEN - encrustation enable) +// W -------- ----x--- (GENLOCK - enable genlock) +// W -------- -----xx- (MODE - CRY16,RGB24,DIRECT16,RGB16) +// W -------- -------x (VIDEN - enables video) +// F0002A W xxxxxxxx xxxxxxxx BORD1 - border color (red/green) +// F0002C W -------- xxxxxxxx BORD2 - border color (blue) +// F0002E W ------xx xxxxxxxx HP - horizontal period +// F00030 W -----xxx xxxxxxxx HBB - horizontal blanking begin +// F00032 W -----xxx xxxxxxxx HBE - horizontal blanking end +// F00034 W -----xxx xxxxxxxx HSYNC - horizontal sync +// F00036 W ------xx xxxxxxxx HVS - horizontal vertical sync +// F00038 W -----xxx xxxxxxxx HDB1 - horizontal display begin 1 +// F0003A W -----xxx xxxxxxxx HDB2 - horizontal display begin 2 +// F0003C W -----xxx xxxxxxxx HDE - horizontal display end +// F0003E W -----xxx xxxxxxxx VP - vertical period +// F00040 W -----xxx xxxxxxxx VBB - vertical blanking begin +// F00042 W -----xxx xxxxxxxx VBE - vertical blanking end +// F00044 W -----xxx xxxxxxxx VS - vertical sync +// F00046 W -----xxx xxxxxxxx VDB - vertical display begin +// F00048 W -----xxx xxxxxxxx VDE - vertical display end +// F0004A W -----xxx xxxxxxxx VEB - vertical equalization begin +// F0004C W -----xxx xxxxxxxx VEE - vertical equalization end +// F0004E W -----xxx xxxxxxxx VI - vertical interrupt +// F00050 W xxxxxxxx xxxxxxxx PIT0 - programmable interrupt timer 0 +// F00052 W xxxxxxxx xxxxxxxx PIT1 - programmable interrupt timer 1 +// F00054 W ------xx xxxxxxxx HEQ - horizontal equalization end +// F00058 W xxxxxxxx xxxxxxxx BG - background color +// F000E0 R/W ---xxxxx ---xxxxx INT1 - CPU interrupt control register +// ---x---- -------- (C_JERCLR - clear pending Jerry ints) +// ----x--- -------- (C_PITCLR - clear pending PIT ints) +// -----x-- -------- (C_OPCLR - clear pending object processor ints) +// ------x- -------- (C_GPUCLR - clear pending graphics processor ints) +// -------x -------- (C_VIDCLR - clear pending video timebase ints) +// -------- ---x---- (C_JERENA - enable Jerry ints) +// -------- ----x--- (C_PITENA - enable PIT ints) +// -------- -----x-- (C_OPENA - enable object processor ints) +// -------- ------x- (C_GPUENA - enable graphics processor ints) +// -------- -------x (C_VIDENA - enable video timebase ints) +// F000E2 W -------- -------- INT2 - CPU interrupt resume register +// F00400-F005FF R/W xxxxxxxx xxxxxxxx CLUT - color lookup table A +// F00600-F007FF R/W xxxxxxxx xxxxxxxx CLUT - color lookup table B +// F00800-F00D9F R/W xxxxxxxx xxxxxxxx LBUF - line buffer A +// F01000-F0159F R/W xxxxxxxx xxxxxxxx LBUF - line buffer B +// F01800-F01D9F R/W xxxxxxxx xxxxxxxx LBUF - line buffer currently selected +// ------------------------------------------------------------ +// F02000-F021FF R/W xxxxxxxx xxxxxxxx GPU control registers +// F02100 R/W xxxxxxxx xxxxxxxx G_FLAGS - GPU flags register +// R/W x------- -------- (DMAEN - DMA enable) +// R/W -x------ -------- (REGPAGE - register page) +// W --x----- -------- (G_BLITCLR - clear blitter interrupt) +// W ---x---- -------- (G_OPCLR - clear object processor int) +// W ----x--- -------- (G_PITCLR - clear PIT interrupt) +// W -----x-- -------- (G_JERCLR - clear Jerry interrupt) +// W ------x- -------- (G_CPUCLR - clear CPU interrupt) +// R/W -------x -------- (G_BLITENA - enable blitter interrupt) +// R/W -------- x------- (G_OPENA - enable object processor int) +// R/W -------- -x------ (G_PITENA - enable PIT interrupt) +// R/W -------- --x----- (G_JERENA - enable Jerry interrupt) +// R/W -------- ---x---- (G_CPUENA - enable CPU interrupt) +// R/W -------- ----x--- (IMASK - interrupt mask) +// R/W -------- -----x-- (NEGA_FLAG - ALU negative) +// R/W -------- ------x- (CARRY_FLAG - ALU carry) +// R/W -------- -------x (ZERO_FLAG - ALU zero) +// F02104 W -------- ----xxxx G_MTXC - matrix control register +// W -------- ----x--- (MATCOL - column/row major) +// W -------- -----xxx (MATRIX3-15 - matrix width) +// F02108 W ----xxxx xxxxxx-- G_MTXA - matrix address register +// F0210C W -------- -----xxx G_END - data organization register +// W -------- -----x-- (BIG_INST - big endian instruction fetch) +// W -------- ------x- (BIG_PIX - big endian pixels) +// W -------- -------x (BIG_IO - big endian I/O) +// F02110 R/W xxxxxxxx xxxxxxxx G_PC - GPU program counter +// F02114 R/W xxxxxxxx xx-xxxxx G_CTRL - GPU control/status register +// R xxxx---- -------- (VERSION - GPU version code) +// R/W ----x--- -------- (BUS_HOG - hog the bus!) +// R/W -----x-- -------- (G_BLITLAT - blitter interrupt latch) +// R/W ------x- -------- (G_OPLAT - object processor int latch) +// R/W -------x -------- (G_PITLAT - PIT interrupt latch) +// R/W -------- x------- (G_JERLAT - Jerry interrupt latch) +// R/W -------- -x------ (G_CPULAT - CPU interrupt latch) +// R/W -------- ---x---- (SINGLE_GO - single step one instruction) +// R/W -------- ----x--- (SINGLE_STEP - single step mode) +// R/W -------- -----x-- (FORCEINT0 - cause interrupt 0 on GPU) +// R/W -------- ------x- (CPUINT - send GPU interrupt to CPU) +// R/W -------- -------x (GPUGO - enable GPU execution) +// F02118-F0211B R/W xxxxxxxx xxxxxxxx G_HIDATA - high data register +// F0211C-F0211F R xxxxxxxx xxxxxxxx G_REMAIN - divide unit remainder +// F0211C W -------- -------x G_DIVCTRL - divide unit control +// W -------- -------x (DIV_OFFSET - 1=16.16 divide, 0=32-bit divide) +// ------------------------------------------------------------ +// BLITTER REGISTERS +// ------------------------------------------------------------ +// F02200-F022FF R/W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Blitter registers +// F02200 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_BASE - A1 base register +// F02204 W -------- ---xxxxx -xxxxxxx xxxxx-xx A1_FLAGS - A1 flags register +// W -------- ---x---- -------- -------- (YSIGNSUB - invert sign of Y delta) +// W -------- ----x--- -------- -------- (XSIGNSUB - invert sign of X delta) +// W -------- -----x-- -------- -------- (Y add control) +// W -------- ------xx -------- -------- (X add control) +// W -------- -------- -xxxxxx- -------- (width in 6-bit floating point) +// W -------- -------- -------x xx------ (ZOFFS1-6 - Z data offset) +// W -------- -------- -------- --xxx--- (PIXEL - pixel size) +// W -------- -------- -------- ------xx (PITCH1-4 - data phrase pitch) +// F02208 W -xxxxxxx xxxxxxxx -xxxxxxx xxxxxxxx A1_CLIP - A1 clipping size +// W -xxxxxxx xxxxxxxx -------- -------- (height) +// W -------- -------- -xxxxxxx xxxxxxxx (width) +// F0220C R/W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_PIXEL - A1 pixel pointer +// R/W xxxxxxxx xxxxxxxx -------- -------- (Y pixel value) +// R/W -------- -------- xxxxxxxx xxxxxxxx (X pixel value) +// F02210 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_STEP - A1 step value +// W xxxxxxxx xxxxxxxx -------- -------- (Y step value) +// W -------- -------- xxxxxxxx xxxxxxxx (X step value) +// F02214 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_FSTEP - A1 step fraction value +// W xxxxxxxx xxxxxxxx -------- -------- (Y step fraction value) +// W -------- -------- xxxxxxxx xxxxxxxx (X step fraction value) +// F02218 R/W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_FPIXEL - A1 pixel pointer fraction +// R/W xxxxxxxx xxxxxxxx -------- -------- (Y pixel fraction value) +// R/W -------- -------- xxxxxxxx xxxxxxxx (X pixel fraction value) +// F0221C W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_INC - A1 increment +// W xxxxxxxx xxxxxxxx -------- -------- (Y increment) +// W -------- -------- xxxxxxxx xxxxxxxx (X increment) +// F02220 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A1_FINC - A1 increment fraction +// W xxxxxxxx xxxxxxxx -------- -------- (Y increment fraction) +// W -------- -------- xxxxxxxx xxxxxxxx (X increment fraction) +// F02224 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A2_BASE - A2 base register +// F02228 W -------- ---xxxxx -xxxxxxx xxxxx-xx A2_FLAGS - A2 flags register +// W -------- ---x---- -------- -------- (YSIGNSUB - invert sign of Y delta) +// W -------- ----x--- -------- -------- (XSIGNSUB - invert sign of X delta) +// W -------- -----x-- -------- -------- (Y add control) +// W -------- ------xx -------- -------- (X add control) +// W -------- -------- -xxxxxx- -------- (width in 6-bit floating point) +// W -------- -------- -------x xx------ (ZOFFS1-6 - Z data offset) +// W -------- -------- -------- --xxx--- (PIXEL - pixel size) +// W -------- -------- -------- ------xx (PITCH1-4 - data phrase pitch) +// F0222C W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A2_MASK - A2 window mask +// F02230 R/W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A2_PIXEL - A2 pixel pointer +// R/W xxxxxxxx xxxxxxxx -------- -------- (Y pixel value) +// R/W -------- -------- xxxxxxxx xxxxxxxx (X pixel value) +// F02234 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx A2_STEP - A2 step value +// W xxxxxxxx xxxxxxxx -------- -------- (Y step value) +// W -------- -------- xxxxxxxx xxxxxxxx (X step value) +// F02238 W -xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_CMD - command register +// W -x------ -------- -------- -------- (SRCSHADE - modify source intensity) +// W --x----- -------- -------- -------- (BUSHI - hi priority bus) +// W ---x---- -------- -------- -------- (BKGWREN - writeback destination) +// W ----x--- -------- -------- -------- (DCOMPEN - write inhibit from data comparator) +// W -----x-- -------- -------- -------- (BCOMPEN - write inhibit from bit coparator) +// W ------x- -------- -------- -------- (CMPDST - compare dest instead of src) +// W -------x xxx----- -------- -------- (logical operation) +// W -------- ---xxx-- -------- -------- (ZMODE - Z comparator mode) +// W -------- ------x- -------- -------- (ADDDSEL - select sum of src & dst) +// W -------- -------x -------- -------- (PATDSEL - select pattern data) +// W -------- -------- x------- -------- (TOPNEN - enable carry into top intensity nibble) +// W -------- -------- -x------ -------- (TOPBEN - enable carry into top intensity byte) +// W -------- -------- --x----- -------- (ZBUFF - enable Z updates in inner loop) +// W -------- -------- ---x---- -------- (GOURD - enable gouraud shading in inner loop) +// W -------- -------- ----x--- -------- (DSTA2 - reverses A2/A1 roles) +// W -------- -------- -----x-- -------- (UPDA2 - add A2 step to A2 in outer loop) +// W -------- -------- ------x- -------- (UPDA1 - add A1 step to A1 in outer loop) +// W -------- -------- -------x -------- (UPDA1F - add A1 fraction step to A1 in outer loop) +// W -------- -------- -------- x------- (diagnostic use) +// W -------- -------- -------- -x------ (CLIP_A1 - clip A1 to window) +// W -------- -------- -------- --x----- (DSTWRZ - enable dest Z write in inner loop) +// W -------- -------- -------- ---x---- (DSTENZ - enable dest Z read in inner loop) +// W -------- -------- -------- ----x--- (DSTEN - enables dest data read in inner loop) +// W -------- -------- -------- -----x-- (SRCENX - enable extra src read at start of inner) +// W -------- -------- -------- ------x- (SRCENZ - enables source Z read in inner loop) +// W -------- -------- -------- -------x (SRCEN - enables source data read in inner loop) +// F02238 R xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_CMD - status register +// R xxxxxxxx xxxxxxxx -------- -------- (inner count) +// R -------- -------- xxxxxxxx xxxxxx-- (diagnostics) +// R -------- -------- -------- ------x- (STOPPED - when stopped in collision detect) +// R -------- -------- -------- -------x (IDLE - when idle) +// F0223C W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_COUNT - counters register +// W xxxxxxxx xxxxxxxx -------- -------- (outer loop count) +// W -------- -------- xxxxxxxx xxxxxxxx (inner loop count) +// F02240-F02247 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_SRCD - source data register +// F02248-F0224F W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_DSTD - destination data register +// F02250-F02257 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_DSTZ - destination Z register +// F02258-F0225F W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_SRCZ1 - source Z register 1 +// F02260-F02267 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_SRCZ2 - source Z register 2 +// F02268-F0226F W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_PATD - pattern data register +// F02270 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_IINC - intensity increment +// F02274 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_ZINC - Z increment +// F02278 W -------- -------- -------- -----xxx B_STOP - collision control +// W -------- -------- -------- -----x-- (STOPEN - enable blitter collision stops) +// W -------- -------- -------- ------x- (ABORT - abort after stop) +// W -------- -------- -------- -------x (RESUME - resume after stop) +// F0227C W -------- xxxxxxxx xxxxxxxx xxxxxxxx B_I3 - intensity 3 +// F02280 W -------- xxxxxxxx xxxxxxxx xxxxxxxx B_I2 - intensity 2 +// F02284 W -------- xxxxxxxx xxxxxxxx xxxxxxxx B_I1 - intensity 1 +// F02288 W -------- xxxxxxxx xxxxxxxx xxxxxxxx B_I0 - intensity 0 +// F0228C W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_Z3 - Z3 +// F02290 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_Z2 - Z2 +// F02294 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_Z1 - Z1 +// F02298 W xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B_Z0 - Z0 +// ------------------------------------------------------------ + +#include "tom.h" + +#include // For memset() +#include // For rand() +#include "blitter.h" +#include "cry2rgb.h" +#include "event.h" +#include "gpu.h" +#include "jaguar.h" +#include "log.h" +#include "m68000/m68kinterface.h" +//#include "memory.h" +#include "op.h" +#include "settings.h" + +#define NEW_TIMER_SYSTEM + +// TOM registers (offset from $F00000) + +#define MEMCON1 0x00 +#define MEMCON2 0x02 +#define HC 0x04 +#define VC 0x06 +#define OLP 0x20 // Object list pointer +#define OBF 0x26 // Object processor flag +#define VMODE 0x28 +#define MODE 0x0006 // Line buffer to video generator mode +#define BGEN 0x0080 // Background enable (CRY & RGB16 only) +#define VARMOD 0x0100 // Mixed CRY/RGB16 mode (only works in MODE 0!) +#define PWIDTH 0x0E00 // Pixel width in video clock cycles (value written + 1) +#define BORD1 0x2A // Border green/red values (8 BPP) +#define BORD2 0x2C // Border blue value (8 BPP) +#define HP 0x2E // Values range from 1 - 1024 (value written + 1) +#define HBB 0x30 // Horizontal blank begin +#define HBE 0x32 +#define HS 0x34 // Horizontal sync +#define HVS 0x36 // Horizontal vertical sync +#define HDB1 0x38 // Horizontal display begin 1 +#define HDB2 0x3A +#define HDE 0x3C +#define VP 0x3E // Value ranges from 1 - 2048 (value written + 1) +#define VBB 0x40 // Vertical blank begin +#define VBE 0x42 +#define VS 0x44 // Vertical sync +#define VDB 0x46 // Vertical display begin +#define VDE 0x48 +#define VEB 0x4A // Vertical equalization begin +#define VEE 0x4C // Vertical equalization end +#define VI 0x4E // Vertical interrupt +#define PIT0 0x50 +#define PIT1 0x52 +#define HEQ 0x54 // Horizontal equalization end +#define BG 0x58 // Background color +#define INT1 0xE0 +#define INT2 0xE2 + +// Arbitrary video cutoff values (i.e., first/last visible spots on a TV, in HC +// ticks) +// Also note that VC is in *half* lines, i.e. divide by 2 to get the scanline +/*#define LEFT_VISIBLE_HC 208 +#define RIGHT_VISIBLE_HC 1528//*/ +// These were right for Rayman, but that one is offset on a real TV too. +//#define LEFT_VISIBLE_HC 208 +//#define RIGHT_VISIBLE_HC 1488 +// This is more like a real TV display... +//#define LEFT_VISIBLE_HC (208 - 32) +//#define RIGHT_VISIBLE_HC (1488 - 32) +// Split the difference? (Seems to be OK for the most part...) + +// (-10 +10)*4 is for opening up the display by 16 pixels (may go to 20). Need to change VIRTUAL_SCREEN_WIDTH to match this as well (went from 320 to 340; this is 4 HCs per one of those pixels). +//NB: Went back to 330. May shrink more. :-) +//#define LEFT_VISIBLE_HC (208 - 16 - (8 * 4)) +//#define LEFT_VISIBLE_HC (208 - 16 - (3 * 4)) +#define LEFT_VISIBLE_HC (208 - 16 - (1 * 4)) +//#define RIGHT_VISIBLE_HC (1488 - 16 + (10 * 4)) +#define RIGHT_VISIBLE_HC (LEFT_VISIBLE_HC + (VIRTUAL_SCREEN_WIDTH * 4)) +//#define TOP_VISIBLE_VC 25 +//#define BOTTOM_VISIBLE_VC 503 +#define TOP_VISIBLE_VC 31 +#define BOTTOM_VISIBLE_VC 511 + +//Are these PAL horizontals correct? +//They seem to be for the most part, but there are some games that seem to be +//shifted over to the right from this "window". +//#define LEFT_VISIBLE_HC_PAL (208 - 16 - (4 * 4)) +//#define LEFT_VISIBLE_HC_PAL (208 - 16 - (-1 * 4)) +#define LEFT_VISIBLE_HC_PAL (208 - 16 - (-3 * 4)) +//#define RIGHT_VISIBLE_HC_PAL (1488 - 16 + (10 * 4)) +#define RIGHT_VISIBLE_HC_PAL (LEFT_VISIBLE_HC_PAL + (VIRTUAL_SCREEN_WIDTH * 4)) +#define TOP_VISIBLE_VC_PAL 67 +#define BOTTOM_VISIBLE_VC_PAL 579 + +//This can be defined in the makefile as well... +//(It's easier to do it here, though...) +//#define TOM_DEBUG + +uint8_t tomRam8[0x4000]; +uint32_t tomWidth, tomHeight; +uint32_t tomTimerPrescaler; +uint32_t tomTimerDivider; +int32_t tomTimerCounter; +uint16_t tom_jerry_int_pending, tom_timer_int_pending, tom_object_int_pending, + tom_gpu_int_pending, tom_video_int_pending; + +// These are set by the "user" of the Jaguar core lib, since these are +// OS/system dependent. +uint32_t * screenBuffer; +uint32_t screenPitch; + +static const char * videoMode_to_str[8] = + { "16 BPP CRY", "24 BPP RGB", "16 BPP DIRECT", "16 BPP RGB", + "Mixed mode", "24 BPP RGB", "16 BPP DIRECT", "16 BPP RGB" }; + +typedef void (render_xxx_scanline_fn)(uint32_t *); + +// Private function prototypes + +void tom_render_16bpp_cry_scanline(uint32_t * backbuffer); +void tom_render_24bpp_scanline(uint32_t * backbuffer); +void tom_render_16bpp_direct_scanline(uint32_t * backbuffer); +void tom_render_16bpp_rgb_scanline(uint32_t * backbuffer); +void tom_render_16bpp_cry_rgb_mix_scanline(uint32_t * backbuffer); + +//render_xxx_scanline_fn * scanline_render_normal[] = +render_xxx_scanline_fn * scanline_render[] = +{ + tom_render_16bpp_cry_scanline, + tom_render_24bpp_scanline, + tom_render_16bpp_direct_scanline, + tom_render_16bpp_rgb_scanline, + tom_render_16bpp_cry_rgb_mix_scanline, + tom_render_24bpp_scanline, + tom_render_16bpp_direct_scanline, + tom_render_16bpp_rgb_scanline +}; + +// Screen info for various games [PAL]... +/* +BIOS +TOM: Horizontal Period written by M68K: 850 (+1*2 = 1702) +TOM: Horizontal Blank Begin written by M68K: 1711 +TOM: Horizontal Blank End written by M68K: 158 +TOM: Horizontal Display End written by M68K: 1696 +TOM: Horizontal Display Begin 1 written by M68K: 166 +TOM: Vertical Period written by M68K: 623 (non-interlaced) +TOM: Vertical Blank End written by M68K: 34 +TOM: Vertical Display Begin written by M68K: 46 +TOM: Vertical Display End written by M68K: 526 +TOM: Vertical Blank Begin written by M68K: 600 +TOM: Vertical Sync written by M68K: 618 +TOM: Horizontal Display End written by M68K: 1665 +TOM: Horizontal Display Begin 1 written by M68K: 203 +TOM: Vertical Display Begin written by M68K: 38 +TOM: Vertical Display End written by M68K: 518 +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 151) +TOM: Horizontal Display End written by M68K: 1713 +TOM: Horizontal Display Begin 1 written by M68K: 157 +TOM: Vertical Display Begin written by M68K: 35 +TOM: Vertical Display End written by M68K: 2047 +Horizontal range: 157 - 1713 (width: 1557 / 4 = 389.25, / 5 = 315.4) + +Asteroid +TOM: Horizontal Period written by M68K: 845 (+1*2 = 1692) +TOM: Horizontal Blank Begin written by M68K: 1700 +TOM: Horizontal Blank End written by M68K: 122 +TOM: Horizontal Display End written by M68K: 1600 +TOM: Horizontal Display Begin 1 written by M68K: 268 +TOM: Vertical Period written by M68K: 523 (non-interlaced) +TOM: Vertical Blank End written by M68K: 40 +TOM: Vertical Display Begin written by M68K: 44 +TOM: Vertical Display End written by M68K: 492 +TOM: Vertical Blank Begin written by M68K: 532 +TOM: Vertical Sync written by M68K: 513 +TOM: Video Mode written by M68K: 04C7. PWIDTH = 3, MODE = 16 BPP RGB, flags: BGEN (VC = 461) + +Rayman +TOM: Horizontal Display End written by M68K: 1713 +TOM: Horizontal Display Begin 1 written by M68K: 157 +TOM: Vertical Display Begin written by M68K: 35 +TOM: Vertical Display End written by M68K: 2047 +TOM: Video Mode written by M68K: 06C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN (VC = 89) +TOM: Horizontal Display Begin 1 written by M68K: 208 +TOM: Horizontal Display End written by M68K: 1662 +TOM: Vertical Display Begin written by M68K: 100 +TOM: Vertical Display End written by M68K: 2047 +TOM: Video Mode written by M68K: 07C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN VARMOD (VC = 205) +Horizontal range: 208 - 1662 (width: 1455 / 4 = 363.5) + +Alien vs Predator +TOM: Vertical Display Begin written by M68K: 96 +TOM: Vertical Display End written by M68K: 2047 +TOM: Horizontal Display Begin 1 written by M68K: 239 +TOM: Horizontal Display End written by M68K: 1692 +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 378) +TOM: Vertical Display Begin written by M68K: 44 +TOM: Vertical Display End written by M68K: 2047 +TOM: Horizontal Display Begin 1 written by M68K: 239 +TOM: Horizontal Display End written by M68K: 1692 +TOM: Video Mode written by M68K: 06C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN (VC = 559) +TOM: Vertical Display Begin written by M68K: 84 +TOM: Vertical Display End written by M68K: 2047 +TOM: Horizontal Display Begin 1 written by M68K: 239 +TOM: Horizontal Display End written by M68K: 1692 +TOM: Vertical Display Begin written by M68K: 44 +TOM: Vertical Display End written by M68K: 2047 +TOM: Horizontal Display Begin 1 written by M68K: 239 +TOM: Horizontal Display End written by M68K: 1692 +Horizontal range: 239 - 1692 (width: 1454 / 4 = 363.5) + +*/ + +// Screen info for various games [NTSC]... +/* +Doom +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 123 +TOM: Vertical Display Begin written by M68K: 25 +TOM: Vertical Display End written by M68K: 2047 +TOM: Video Mode written by M68K: 0EC1. PWIDTH = 8, MODE = 16 BPP CRY, flags: BGEN (VC = 5) +Also does PWIDTH = 4... +Vertical resolution: 238 lines + +Rayman +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 123 +TOM: Vertical Display Begin written by M68K: 25 +TOM: Vertical Display End written by M68K: 2047 +TOM: Vertical Interrupt written by M68K: 507 +TOM: Video Mode written by M68K: 06C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN (VC = 92) +TOM: Horizontal Display Begin 1 written by M68K: 208 +TOM: Horizontal Display End written by M68K: 1670 +Display starts at 31, then 52! +Vertical resolution: 238 lines + +Atari Karts +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 123 +TOM: Vertical Display Begin written by M68K: 25 +TOM: Vertical Display End written by M68K: 2047 +TOM: Video Mode written by GPU: 08C7. PWIDTH = 5, MODE = 16 BPP RGB, flags: BGEN (VC = 4) +TOM: Video Mode written by GPU: 06C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN (VC = 508) +Display starts at 31 (PWIDTH = 4), 24 (PWIDTH = 5) + +Iron Soldier +TOM: Vertical Interrupt written by M68K: 2047 +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 0) +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 123 +TOM: Vertical Display Begin written by M68K: 25 +TOM: Vertical Display End written by M68K: 2047 +TOM: Vertical Interrupt written by M68K: 507 +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 369) +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 510) +TOM: Video Mode written by M68K: 06C3. PWIDTH = 4, MODE = 24 BPP RGB, flags: BGEN (VC = 510) +Display starts at 31 +Vertical resolution: 238 lines +[Seems to be a problem between the horizontal positioning of the 16-bit CRY & 24-bit RGB] + +JagMania +TOM: Horizontal Period written by M68K: 844 (+1*2 = 1690) +TOM: Horizontal Blank Begin written by M68K: 1713 +TOM: Horizontal Blank End written by M68K: 125 +TOM: Horizontal Display End written by M68K: 1696 +TOM: Horizontal Display Begin 1 written by M68K: 166 +TOM: Vertical Period written by M68K: 523 (non-interlaced) +TOM: Vertical Blank End written by M68K: 24 +TOM: Vertical Display Begin written by M68K: 46 +TOM: Vertical Display End written by M68K: 496 +TOM: Vertical Blank Begin written by M68K: 500 +TOM: Vertical Sync written by M68K: 517 +TOM: Vertical Interrupt written by M68K: 497 +TOM: Video Mode written by M68K: 04C1. PWIDTH = 3, MODE = 16 BPP CRY, flags: BGEN (VC = 270) +Display starts at 55 + +Double Dragon V +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 123 +TOM: Vertical Display Begin written by M68K: 25 +TOM: Vertical Display End written by M68K: 2047 +TOM: Vertical Interrupt written by M68K: 507 +TOM: Video Mode written by M68K: 06C7. PWIDTH = 4, MODE = 16 BPP RGB, flags: BGEN (VC = 9) + +Dino Dudes +TOM: Horizontal Display End written by M68K: 1823 +TOM: Horizontal Display Begin 1 written by M68K: 45 +TOM: Vertical Display Begin written by M68K: 40 +TOM: Vertical Display End written by M68K: 2047 +TOM: Vertical Interrupt written by M68K: 491 +TOM: Video Mode written by M68K: 06C1. PWIDTH = 4, MODE = 16 BPP CRY, flags: BGEN (VC = 398) +Display starts at 11 (123 - 45 = 78, 78 / 4 = 19 pixels to skip) +Width is 417, so maybe width of 379 would be good (starting at 123, ending at 1639) +Vertical resolution: 238 lines + +Flashback +TOM: Horizontal Display End written by M68K: 1727 +TOM: Horizontal Display Begin 1 written by M68K: 188 +TOM: Vertical Display Begin written by M68K: 1 +TOM: Vertical Display End written by M68K: 2047 +TOM: Vertical Interrupt written by M68K: 483 +TOM: Video Mode written by M68K: 08C7. PWIDTH = 5, MODE = 16 BPP RGB, flags: BGEN (VC = 99) +Width would be 303 with above scheme, but border width would be 13 pixels + +Trevor McFur +Vertical resolution: 238 lines +*/ + +// 16-bit color lookup tables +uint32_t RGB16ToRGB32[0x10000]; +uint32_t CRY16ToRGB32[0x10000]; +uint32_t MIX16ToRGB32[0x10000]; + + +#warning "This is not endian-safe. !!! FIX !!!" +void TOMFillLookupTables(void) +{ + // NOTE: Jaguar 16-bit (non-CRY) color is RBG 556 like so: + // RRRR RBBB BBGG GGGG + for(uint32_t i=0; i<0x10000; i++) + RGB16ToRGB32[i] = + ((i & 0xF800) << 8) // Red + | ((i & 0x003F) << 10) // Green + | ((i & 0x07C0) >> 3); // Blue + + for(uint32_t i=0; i<0x10000; i++) + { + uint32_t cyan = (i & 0xF000) >> 12, + red = (i & 0x0F00) >> 8, + intensity = (i & 0x00FF); + + uint32_t r = (((uint32_t)redcv[cyan][red]) * intensity) >> 8, + g = (((uint32_t)greencv[cyan][red]) * intensity) >> 8, + b = (((uint32_t)bluecv[cyan][red]) * intensity) >> 8; + + CRY16ToRGB32[i] = (r << 16) | (g << 8) | b; + MIX16ToRGB32[i] = (i & 0x01 ? RGB16ToRGB32[i] : CRY16ToRGB32[i]); + } +} + + +void TOMSetPendingJERRYInt(void) +{ + tom_jerry_int_pending = 1; +} + + +void TOMSetPendingTimerInt(void) +{ + tom_timer_int_pending = 1; +} + + +void TOMSetPendingObjectInt(void) +{ + tom_object_int_pending = 1; +} + + +void TOMSetPendingGPUInt(void) +{ + tom_gpu_int_pending = 1; +} + + +void TOMSetPendingVideoInt(void) +{ + tom_video_int_pending = 1; +} + + +uint8_t * TOMGetRamPointer(void) +{ + return tomRam8; +} + + +uint8_t TOMGetVideoMode(void) +{ + uint16_t vmode = GET16(tomRam8, VMODE); + return ((vmode & VARMOD) >> 6) | ((vmode & MODE) >> 1); +} + + +//Used in only one place (and for debug purposes): OBJECTP.CPP +#warning "Used in only one place (and for debug purposes): OBJECTP.CPP !!! FIX !!!" +uint16_t TOMGetVDB(void) +{ + return GET16(tomRam8, VDB); +} + + +uint16_t TOMGetHC(void) +{ + return GET16(tomRam8, HC); +} + + +uint16_t TOMGetVP(void) +{ + return GET16(tomRam8, VP); +} + + +uint16_t TOMGetMEMCON1(void) +{ + return GET16(tomRam8, MEMCON1); +} + + +#define LEFT_BG_FIX +// +// 16 BPP CRY/RGB mixed mode rendering +// +void tom_render_16bpp_cry_rgb_mix_scanline(uint32_t * backbuffer) +{ +//CHANGED TO 32BPP RENDERING + uint16_t width = tomWidth; + uint8_t * current_line_buffer = (uint8_t *)&tomRam8[0x1800]; + + //New stuff--restrict our drawing... + uint8_t pwidth = ((GET16(tomRam8, VMODE) & PWIDTH) >> 9) + 1; + //NOTE: May have to check HDB2 as well! + // Get start position in HC ticks + int16_t startPos = GET16(tomRam8, HDB1) - (vjs.hardwareTypeNTSC ? LEFT_VISIBLE_HC : LEFT_VISIBLE_HC_PAL); + // Convert to pixels + startPos /= pwidth; + + if (startPos < 0) + // This is x2 because current_line_buffer is uint8_t & we're in a 16bpp mode + current_line_buffer += 2 * -startPos; + else +//This case doesn't properly handle the "start on the right side of virtual screen" case +//Dunno why--looks Ok... +//What *is* for sure wrong is that it doesn't copy the linebuffer's BG pixels... [FIXED NOW] +//This should likely be 4 instead of 2 (?--not sure) +// Actually, there should be NO multiplier, as startPos is expressed in PIXELS +// and so is the backbuffer. +#ifdef LEFT_BG_FIX + { + uint8_t g = tomRam8[BORD1], r = tomRam8[BORD1 + 1], b = tomRam8[BORD2 + 1]; + uint32_t pixel = (r << 16) | (g << 8) | b; + + for(int16_t i=0; i> 9) + 1; + //NOTE: May have to check HDB2 as well! + int16_t startPos = GET16(tomRam8, HDB1) - (vjs.hardwareTypeNTSC ? LEFT_VISIBLE_HC : LEFT_VISIBLE_HC_PAL);// Get start position in HC ticks + startPos /= pwidth; + + if (startPos < 0) + current_line_buffer += 2 * -startPos; + else +#ifdef LEFT_BG_FIX + { + uint8_t g = tomRam8[BORD1], r = tomRam8[BORD1 + 1], b = tomRam8[BORD2 + 1]; + uint32_t pixel = (r << 16) | (g << 8) | b; + + for(int16_t i=0; i> 9) + 1; + //NOTE: May have to check HDB2 as well! + int16_t startPos = GET16(tomRam8, HDB1) - (vjs.hardwareTypeNTSC ? LEFT_VISIBLE_HC : LEFT_VISIBLE_HC_PAL); // Get start position in HC ticks + startPos /= pwidth; + + if (startPos < 0) + current_line_buffer += 4 * -startPos; + else +#ifdef LEFT_BG_FIX + { + uint8_t g = tomRam8[BORD1], r = tomRam8[BORD1 + 1], b = tomRam8[BORD2 + 1]; + uint32_t pixel = (r << 16) | (g << 8) | b; + + for(int16_t i=0; i> 1; + width--; + } +} + + +// +// 16 BPP RGB mode rendering +// +void tom_render_16bpp_rgb_scanline(uint32_t * backbuffer) +{ +//CHANGED TO 32BPP RENDERING + // 16 BPP RGB: 0-5 green, 6-10 blue, 11-15 red + + uint16_t width = tomWidth; + uint8_t * current_line_buffer = (uint8_t *)&tomRam8[0x1800]; + + //New stuff--restrict our drawing... + uint8_t pwidth = ((GET16(tomRam8, VMODE) & PWIDTH) >> 9) + 1; + //NOTE: May have to check HDB2 as well! + int16_t startPos = GET16(tomRam8, HDB1) - (vjs.hardwareTypeNTSC ? LEFT_VISIBLE_HC : LEFT_VISIBLE_HC_PAL); // Get start position in HC ticks + startPos /= pwidth; + + if (startPos < 0) + current_line_buffer += 2 * -startPos; + else +#ifdef LEFT_BG_FIX + { + uint8_t g = tomRam8[BORD1], r = tomRam8[BORD1 + 1], b = tomRam8[BORD2 + 1]; + uint32_t pixel = (r << 16) | (g << 8) | b; + + for(int16_t i=0; i GET16(tomRam8, VP)) + startingHalfline = 0; + + if ((halfline >= startingHalfline) && (halfline < endingHalfline)) + { + if (render) + { + uint8_t * current_line_buffer = (uint8_t *)&tomRam8[0x1800]; + uint8_t bgHI = tomRam8[BG], bgLO = tomRam8[BG + 1]; + + // Clear line buffer with BG + if (GET16(tomRam8, VMODE) & BGEN) // && (CRY or RGB16)... + for(uint32_t i=0; i<720; i++) + *current_line_buffer++ = bgHI, *current_line_buffer++ = bgLO; + + OPProcessList(halfline, render); + } + } + else + inActiveDisplayArea = false; + + // Take PAL into account... + + uint16_t topVisible = (vjs.hardwareTypeNTSC ? TOP_VISIBLE_VC : TOP_VISIBLE_VC_PAL), + bottomVisible = (vjs.hardwareTypeNTSC ? BOTTOM_VISIBLE_VC : BOTTOM_VISIBLE_VC_PAL); + uint32_t * TOMCurrentLine = 0; + + // Bit 0 in VP is interlace flag. 0 = interlace, 1 = non-interlaced + if (tomRam8[VP + 1] & 0x01) + TOMCurrentLine = &(screenBuffer[((halfline - topVisible) / 2) * screenPitch]);//non-interlace + else + TOMCurrentLine = &(screenBuffer[(((halfline - topVisible) / 2) * screenPitch * 2) + (field2 ? 0 : screenPitch)]);//interlace + + // Here's our virtualized scanline code... + + if ((halfline >= topVisible) && (halfline < bottomVisible)) + { + if (inActiveDisplayArea) + { +#warning "The following doesn't put BORDER color on the sides... !!! FIX !!!" + if (vjs.renderType == RT_NORMAL) + { + scanline_render[TOMGetVideoMode()](TOMCurrentLine); + } + else + { + // TV type render +/* + tom_render_16bpp_cry_scanline, + tom_render_24bpp_scanline, + tom_render_16bpp_direct_scanline, + tom_render_16bpp_rgb_scanline, + tom_render_16bpp_cry_rgb_mix_scanline, + tom_render_24bpp_scanline, + tom_render_16bpp_direct_scanline, + tom_render_16bpp_rgb_scanline +#define VMODE 0x28 +#define MODE 0x0006 // Line buffer to video generator mode +#define VARMOD 0x0100 // Mixed CRY/RGB16 mode (only works in MODE 0!) +*/ + uint8_t pwidth = ((GET16(tomRam8, VMODE) & PWIDTH) >> 9) + 1; + uint8_t mode = ((GET16(tomRam8, VMODE) & MODE) >> 1); + bool varmod = GET16(tomRam8, VMODE) & VARMOD; +//The video texture line buffer ranges from 0 to 1279, with its left edge +//starting at LEFT_VISIBLE_HC. So, we need to start writing into the backbuffer +//at HDB1, using pwidth as our scaling factor. The way it generates its image +//on a real TV! + +//So, for example, if HDB1 is less than LEFT_VISIBLE_HC, then we have to figure +//out where in the VTLB that we start writing pixels from the Jaguar line +//buffer (VTLB start=0, JLB=something). +#if 0 +// +// 24 BPP mode rendering +// +void tom_render_24bpp_scanline(uint32_t * backbuffer) +{ +//CHANGED TO 32BPP RENDERING + uint16_t width = tomWidth; + uint8_t * current_line_buffer = (uint8_t *)&tomRam8[0x1800]; + + //New stuff--restrict our drawing... + uint8_t pwidth = ((GET16(tomRam8, VMODE) & PWIDTH) >> 9) + 1; + //NOTE: May have to check HDB2 as well! + int16_t startPos = GET16(tomRam8, HDB1) - (vjs.hardwareTypeNTSC ? LEFT_VISIBLE_HC : LEFT_VISIBLE_HC_PAL); // Get start position in HC ticks + startPos /= pwidth; + if (startPos < 0) + current_line_buffer += 4 * -startPos; + else +//This should likely be 4 instead of 2 (?--not sure) + backbuffer += 2 * startPos, width -= startPos; + + while (width) + { + uint32_t g = *current_line_buffer++; + uint32_t r = *current_line_buffer++; + current_line_buffer++; + uint32_t b = *current_line_buffer++; + *backbuffer++ = (r << 16) | (g << 8) | b; + width--; + } +} +#endif + + } + } + else + { + // If outside of VDB & VDE, then display the border color + uint32_t * currentLineBuffer = TOMCurrentLine; + uint8_t g = tomRam8[BORD1], r = tomRam8[BORD1 + 1], b = tomRam8[BORD2 + 1]; +//Hm. uint32_t pixel = 0xFF000000 | (b << 16) | (g << 8) | r; + uint32_t pixel = (r << 16) | (g << 8) | b; + + for(uint32_t i=0; i 0.25:1 (1:4) pixels (X:Y ratio) + // PWIDTH = 2 -> 0.50:1 (1:2) pixels + // PWIDTH = 3 -> 0.75:1 (3:4) pixels + // PWIDTH = 4 -> 1.00:1 (1:1) pixels + // PWIDTH = 5 -> 1.25:1 (5:4) pixels + // PWIDTH = 6 -> 1.50:1 (3:2) pixels + // PWIDTH = 7 -> 1.75:1 (7:4) pixels + // PWIDTH = 8 -> 2.00:1 (2:1) pixels + + // Also note that the JTRM says that PWIDTH of 4 gives pixels that are + // "about" square--this implies that the other modes have pixels that are + // *not* square (and they aren't)! + // Also, I seriously doubt that you will see any games that use PWIDTH = 1! + + // To make it easier to make a quasi-fixed display size, we restrict the + // viewing area to an arbitrary range of the Horizontal Count. + uint16_t pwidth = ((GET16(tomRam8, VMODE) & PWIDTH) >> 9) + 1; + return (vjs.hardwareTypeNTSC ? RIGHT_VISIBLE_HC - LEFT_VISIBLE_HC : RIGHT_VISIBLE_HC_PAL - LEFT_VISIBLE_HC_PAL) / pwidth; +} + + +uint32_t TOMGetVideoModeHeight(void) +{ + // Set virtual screen height to 240 (NTSC) or 256 (PAL) lines... + return (vjs.hardwareTypeNTSC ? 240 : 256); +} + + +// +// TOM reset code +// Now PAL friendly! +// +/* +The values in TOMReset come from the Jaguar BIOS. +These values are from BJL: + +NSTC: +CLK2 181 +HP 844 +HBB 1713 +HBE 125 +HS 1741 +HVS 651 +HEQ 784 +HDE 1696 +HDB1 166 +HDB2 166 +VP 523 +VEE 6 +VBE 24 +VDB 46 +VDE 496 +VBB 500 +VEB 511 +VS 517 + +PAL: +CLK2 226 +HP 850 +HBB 1711 +HBE 158 +HS 1749 +HVS 601 +HEQ 787 +HDE 1696 +HDB1 166 +HDB2 166 +VP 625 +VEE 6 +VBE 34 +VDB 46 +VDE 429 +VBB 600 +VEB 613 +VS 618 +*/ +void TOMReset(void) +{ + OPReset(); + BlitterReset(); + memset(tomRam8, 0x00, 0x4000); + + if (vjs.hardwareTypeNTSC) + { + SET16(tomRam8, MEMCON1, 0x1861); +// SET16(tomRam8, MEMCON1, 0x1865);//Bunch of BS + SET16(tomRam8, MEMCON2, 0x35CC); + SET16(tomRam8, HP, 844); // Horizontal Period (1-based; HP=845) + SET16(tomRam8, HBB, 1713); // Horizontal Blank Begin + SET16(tomRam8, HBE, 125); // Horizontal Blank End + SET16(tomRam8, HDE, 1665); // Horizontal Display End + SET16(tomRam8, HDB1, 203); // Horizontal Display Begin 1 + SET16(tomRam8, VP, 523); // Vertical Period (1-based; in this case VP = 524) + SET16(tomRam8, VBE, 24); // Vertical Blank End + SET16(tomRam8, VDB, 38); // Vertical Display Begin + SET16(tomRam8, VDE, 518); // Vertical Display End + SET16(tomRam8, VBB, 500); // Vertical Blank Begin + SET16(tomRam8, VS, 517); // Vertical Sync + SET16(tomRam8, VMODE, 0x06C1); + } + else // PAL Jaguar + { + SET16(tomRam8, MEMCON1, 0x1861); + SET16(tomRam8, MEMCON2, 0x35CC); + SET16(tomRam8, HP, 850); // Horizontal Period + SET16(tomRam8, HBB, 1711); // Horizontal Blank Begin + SET16(tomRam8, HBE, 158); // Horizontal Blank End + SET16(tomRam8, HDE, 1665); // Horizontal Display End + SET16(tomRam8, HDB1, 203); // Horizontal Display Begin 1 + SET16(tomRam8, VP, 623); // Vertical Period (1-based; in this case VP = 624) + SET16(tomRam8, VBE, 34); // Vertical Blank End + SET16(tomRam8, VDB, 38); // Vertical Display Begin + SET16(tomRam8, VDE, 518); // Vertical Display End + SET16(tomRam8, VBB, 600); // Vertical Blank Begin + SET16(tomRam8, VS, 618); // Vertical Sync + SET16(tomRam8, VMODE, 0x06C1); + } + + tomWidth = 0; + tomHeight = 0; + + tom_jerry_int_pending = 0; + tom_timer_int_pending = 0; + tom_object_int_pending = 0; + tom_gpu_int_pending = 0; + tom_video_int_pending = 0; + + tomTimerPrescaler = 0; // TOM PIT is disabled + tomTimerDivider = 0; + tomTimerCounter = 0; +} + + +// +// Dump all TOM register values to the log +// +void TOMDumpIORegistersToLog(void) +{ + WriteLog("\n\n---------------------------------------------------------------------\n"); + WriteLog("TOM I/O Registers\n"); + WriteLog("---------------------------------------------------------------------\n"); + WriteLog("F000%02X (MEMCON1): $%04X\n", MEMCON1, GET16(tomRam8, MEMCON1)); + WriteLog("F000%02X (MEMCON2): $%04X\n", MEMCON2, GET16(tomRam8, MEMCON2)); + WriteLog("F000%02X (HC): $%04X\n", HC, GET16(tomRam8, HC)); + WriteLog("F000%02X (VC): $%04X\n", VC, GET16(tomRam8, VC)); + WriteLog("F000%02X (OLP): $%08X\n", OLP, GET32(tomRam8, OLP)); + WriteLog("F000%02X (OBF): $%04X\n", OBF, GET16(tomRam8, OBF)); + WriteLog("F000%02X (VMODE): $%04X\n", VMODE, GET16(tomRam8, VMODE)); + WriteLog("F000%02X (BORD1): $%04X\n", BORD1, GET16(tomRam8, BORD1)); + WriteLog("F000%02X (BORD2): $%04X\n", BORD2, GET16(tomRam8, BORD2)); + WriteLog("F000%02X (HP): $%04X\n", HP, GET16(tomRam8, HP)); + WriteLog("F000%02X (HBB): $%04X\n", HBB, GET16(tomRam8, HBB)); + WriteLog("F000%02X (HBE): $%04X\n", HBE, GET16(tomRam8, HBE)); + WriteLog("F000%02X (HS): $%04X\n", HS, GET16(tomRam8, HS)); + WriteLog("F000%02X (HVS): $%04X\n", HVS, GET16(tomRam8, HVS)); + WriteLog("F000%02X (HDB1): $%04X\n", HDB1, GET16(tomRam8, HDB1)); + WriteLog("F000%02X (HDB2): $%04X\n", HDB2, GET16(tomRam8, HDB2)); + WriteLog("F000%02X (HDE): $%04X\n", HDE, GET16(tomRam8, HDE)); + WriteLog("F000%02X (VP): $%04X\n", VP, GET16(tomRam8, VP)); + WriteLog("F000%02X (VBB): $%04X\n", VBB, GET16(tomRam8, VBB)); + WriteLog("F000%02X (VBE): $%04X\n", VBE, GET16(tomRam8, VBE)); + WriteLog("F000%02X (VS): $%04X\n", VS, GET16(tomRam8, VS)); + WriteLog("F000%02X (VDB): $%04X\n", VDB, GET16(tomRam8, VDB)); + WriteLog("F000%02X (VDE): $%04X\n", VDE, GET16(tomRam8, VDE)); + WriteLog("F000%02X (VEB): $%04X\n", VEB, GET16(tomRam8, VEB)); + WriteLog("F000%02X (VEE): $%04X\n", VEE, GET16(tomRam8, VEE)); + WriteLog("F000%02X (VI): $%04X\n", VI, GET16(tomRam8, VI)); + WriteLog("F000%02X (PIT0): $%04X\n", PIT0, GET16(tomRam8, PIT0)); + WriteLog("F000%02X (PIT1): $%04X\n", PIT1, GET16(tomRam8, PIT1)); + WriteLog("F000%02X (HEQ): $%04X\n", HEQ, GET16(tomRam8, HEQ)); + WriteLog("F000%02X (BG): $%04X\n", BG, GET16(tomRam8, BG)); + WriteLog("F000%02X (INT1): $%04X\n", INT1, GET16(tomRam8, INT1)); + WriteLog("F000%02X (INT2): $%04X\n", INT2, GET16(tomRam8, INT2)); + WriteLog("---------------------------------------------------------------------\n\n\n"); +} + + +// +// TOM byte access (read) +// +uint8_t TOMReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ +//???Is this needed??? +// It seems so. Perhaps it's the +$8000 offset being written to (32-bit interface)? +// However, the 32-bit interface is WRITE ONLY, so that can't be it... +// Also, the 68K CANNOT make use of the 32-bit interface, since its bus width is only 16-bits... +// offset &= 0xFF3FFF; + +#ifdef TOM_DEBUG + WriteLog("TOM: Reading byte at %06X for %s\n", offset, whoName[who]); +#endif + + if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + return GPUReadByte(offset, who); + else if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) + return GPUReadByte(offset, who); +/* else if ((offset >= 0xF00010) && (offset < 0xF00028)) + return OPReadByte(offset, who);*/ + else if ((offset >= 0xF02200) && (offset < 0xF022A0)) + return BlitterReadByte(offset, who); + else if (offset == 0xF00050) + return tomTimerPrescaler >> 8; + else if (offset == 0xF00051) + return tomTimerPrescaler & 0xFF; + else if (offset == 0xF00052) + return tomTimerDivider >> 8; + else if (offset == 0xF00053) + return tomTimerDivider & 0xFF; + + return tomRam8[offset & 0x3FFF]; +} + + +// +// TOM word access (read) +// +uint16_t TOMReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/) +{ +//???Is this needed??? +// offset &= 0xFF3FFF; +#ifdef TOM_DEBUG + WriteLog("TOM: Reading word at %06X for %s\n", offset, whoName[who]); +#endif +if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("TOM: ReadWord attempted from GPU register file by %s (unimplemented)!\n", whoName[who]); + + if (offset == 0xF000E0) + { + // For reading, should only return the lower 5 bits... + uint16_t data = (tom_jerry_int_pending << 4) | (tom_timer_int_pending << 3) + | (tom_object_int_pending << 2) | (tom_gpu_int_pending << 1) + | (tom_video_int_pending << 0); + //WriteLog("tom: interrupt status is 0x%.4x \n",data); + return data; + } +//Shoud be handled by the jaguar main loop now... And it is! ;-) +/* else if (offset == 0xF00006) // VC + // What if we're in interlaced mode? + // According to docs, in non-interlace mode VC is ALWAYS even... +// return (tom_scanline << 1);// + 1; +//But it's causing Rayman to be fucked up... Why??? +//Because VC is even in NI mode when calling the OP! That's why! + return (tom_scanline << 1) + 1;//*/ +/* +// F00004 R/W -----xxx xxxxxxxx HC - horizontal count +// -----x-- -------- (which half of the display) +// ------xx xxxxxxxx (10-bit counter) +*/ +// This is a kludge to get the HC working somewhat... What we really should do here +// is check what the global time is at the time of the read and calculate the correct HC... +// !!! FIX !!! + else if (offset == 0xF00004) + return rand() & 0x03FF; + else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE + 0x20)) + return GPUReadWord(offset, who); + else if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE + 0x1000)) + return GPUReadWord(offset, who); +/* else if ((offset >= 0xF00010) && (offset < 0xF00028)) + return OPReadWord(offset, who);*/ + else if ((offset >= 0xF02200) && (offset < 0xF022A0)) + return BlitterReadWord(offset, who); + else if (offset == 0xF00050) + return tomTimerPrescaler; + else if (offset == 0xF00052) + return tomTimerDivider; + + offset &= 0x3FFF; + return (TOMReadByte(offset, who) << 8) | TOMReadByte(offset + 1, who); +} + + +#define TOM_STRICT_MEMORY_ACCESS +// +// TOM byte access (write) +// +void TOMWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/) +{ + // Moved here tentatively, so we can see everything written to TOM. + tomRam8[offset & 0x3FFF] = data; + +#ifdef TOM_DEBUG + WriteLog("TOM: Writing byte %02X at %06X", data, offset); +#endif +//???Is this needed??? +// Perhaps on the writes--32-bit writes that is! And masked with FF7FFF... +#ifndef TOM_STRICT_MEMORY_ACCESS + offset &= 0xFF3FFF; +#else + // "Fast" (32-bit only) write access to the GPU +// if ((offset >= 0xF0A100) && (offset <= 0xF0BFFF)) + if ((offset >= 0xF08000) && (offset <= 0xF0BFFF)) + offset &= 0xFF7FFF; +#endif +#ifdef TOM_DEBUG + WriteLog(" -->[%06X] by %s\n", offset, whoName[who]); +#endif + +#ifdef TOM_STRICT_MEMORY_ACCESS + // Sanity check ("Aww, there ain't no Sanity Clause...") + if ((offset < 0xF00000) || (offset > 0xF03FFF)) + return; +#endif + + if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + { + GPUWriteByte(offset, data, who); + return; + } + else if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) + { + GPUWriteByte(offset, data, who); + return; + } +/* else if ((offset >= 0xF00010) && (offset < 0xF00028)) + { + OPWriteByte(offset, data, who); + return; + }*/ + else if ((offset >= 0xF02200) && (offset < 0xF022A0)) + { + BlitterWriteByte(offset, data, who); + return; + } + else if (offset == 0xF00050) + { + tomTimerPrescaler = (tomTimerPrescaler & 0x00FF) | (data << 8); + TOMResetPIT(); + return; + } + else if (offset == 0xF00051) + { + tomTimerPrescaler = (tomTimerPrescaler & 0xFF00) | data; + TOMResetPIT(); + return; + } + else if (offset == 0xF00052) + { + tomTimerDivider = (tomTimerDivider & 0x00FF) | (data << 8); + TOMResetPIT(); + return; + } + else if (offset == 0xF00053) + { + tomTimerDivider = (tomTimerDivider & 0xFF00) | data; + TOMResetPIT(); + return; + } + else if (offset >= 0xF00400 && offset <= 0xF007FF) // CLUT (A & B) + { + // Writing to one CLUT writes to the other + offset &= 0x5FF; // Mask out $F00600 (restrict to $F00400-5FF) + tomRam8[offset] = data, tomRam8[offset + 0x200] = data; + } + +// tomRam8[offset & 0x3FFF] = data; +} + + +// +// TOM word access (write) +// +void TOMWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/) +{ + // Moved here tentatively, so we can see everything written to TOM. + tomRam8[(offset + 0) & 0x3FFF] = data >> 8; + tomRam8[(offset + 1) & 0x3FFF] = data & 0xFF; + +#ifdef TOM_DEBUG + WriteLog("TOM: Writing byte %04X at %06X", data, offset); +#endif +//???Is this needed??? Yes, but we need to be more vigilant than this. +#ifndef TOM_STRICT_MEMORY_ACCESS + offset &= 0xFF3FFF; +#else + // "Fast" (32-bit only) write access to the GPU +// if ((offset >= 0xF0A100) && (offset <= 0xF0BFFF)) + if ((offset >= 0xF08000) && (offset <= 0xF0BFFF)) + offset &= 0xFF7FFF; +#endif +#ifdef TOM_DEBUG + WriteLog(" -->[%06X] by %s\n", offset, whoName[who]); +#endif + +#ifdef TOM_STRICT_MEMORY_ACCESS + // Sanity check + if ((offset < 0xF00000) || (offset > 0xF03FFF)) + return; +#endif + +//if (offset == 0xF00000 + MEMCON1) +// WriteLog("TOM: Memory Configuration 1 written by %s: %04X\n", whoName[who], data); +//if (offset == 0xF00000 + MEMCON2) +// WriteLog("TOM: Memory Configuration 2 written by %s: %04X\n", whoName[who], data); +if (offset >= 0xF02000 && offset <= 0xF020FF) + WriteLog("TOM: WriteWord attempted to GPU register file by %s (unimplemented)!\n", whoName[who]); + + if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20)) + { + GPUWriteWord(offset, data, who); + return; + } + else if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000)) + { + GPUWriteWord(offset, data, who); + return; + } +//What's so special about this? +/* else if ((offset >= 0xF00000) && (offset < 0xF00002)) + { + TOMWriteByte(offset, data >> 8); + TOMWriteByte(offset+1, data & 0xFF); + }*/ +/* else if ((offset >= 0xF00010) && (offset < 0xF00028)) + { + OPWriteWord(offset, data, who); + return; + }*/ + else if (offset == 0xF00050) + { + tomTimerPrescaler = data; + TOMResetPIT(); + return; + } + else if (offset == 0xF00052) + { + tomTimerDivider = data; + TOMResetPIT(); + return; + } + else if (offset == 0xF000E0) + { +//Check this out... + if (data & 0x0100) + tom_video_int_pending = 0; + if (data & 0x0200) + tom_gpu_int_pending = 0; + if (data & 0x0400) + tom_object_int_pending = 0; + if (data & 0x0800) + tom_timer_int_pending = 0; + if (data & 0x1000) + tom_jerry_int_pending = 0; + +// return; + } + else if ((offset >= 0xF02200) && (offset <= 0xF0229F)) + { + BlitterWriteWord(offset, data, who); + return; + } + else if (offset >= 0xF00400 && offset <= 0xF007FE) // CLUT (A & B) + { + // Writing to one CLUT writes to the other + offset &= 0x5FF; // Mask out $F00600 (restrict to $F00400-5FF) +// Watch out for unaligned writes here! (Not fixed yet) +#warning "!!! Watch out for unaligned writes here !!! FIX !!!" + SET16(tomRam8, offset, data); + SET16(tomRam8, offset + 0x200, data); + } + + offset &= 0x3FFF; + if (offset == 0x28) // VMODE (Why? Why not OBF?) +//Actually, we should check to see if the Enable bit of VMODE is set before doing this... !!! FIX !!! +#warning "Actually, we should check to see if the Enable bit of VMODE is set before doing this... !!! FIX !!!" + objectp_running = 1; + + if (offset >= 0x30 && offset <= 0x4E) + data &= 0x07FF; // These are (mostly) 11-bit registers + if (offset == 0x2E || offset == 0x36 || offset == 0x54) + data &= 0x03FF; // These are all 10-bit registers + +// Fix a lockup bug... :-P +// TOMWriteByte(0xF00000 | offset, data >> 8, who); +// TOMWriteByte(0xF00000 | (offset+1), data & 0xFF, who); + +if (offset == MEMCON1) + WriteLog("TOM: Memory Config 1 written by %s: $%04X\n", whoName[who], data); +if (offset == MEMCON2) + WriteLog("TOM: Memory Config 2 written by %s: $%04X\n", whoName[who], data); +//if (offset == OLP) +// WriteLog("TOM: Object List Pointer written by %s: $%04X\n", whoName[who], data); +//if (offset == OLP + 2) +// WriteLog("TOM: Object List Pointer +2 written by %s: $%04X\n", whoName[who], data); +//if (offset == OBF) +// WriteLog("TOM: Object Processor Flag written by %s: %u\n", whoName[who], data); +if (offset == VMODE) + WriteLog("TOM: Video Mode written by %s: %04X. PWIDTH = %u, MODE = %s, flags:%s%s (VC = %u) (M68K PC = %06X)\n", whoName[who], data, ((data >> 9) & 0x07) + 1, videoMode_to_str[(data & MODE) >> 1], (data & BGEN ? " BGEN" : ""), (data & VARMOD ? " VARMOD" : ""), GET16(tomRam8, VC), m68k_get_reg(NULL, M68K_REG_PC)); +if (offset == BORD1) + WriteLog("TOM: Border 1 written by %s: $%04X\n", whoName[who], data); +if (offset == BORD2) + WriteLog("TOM: Border 2 written by %s: $%04X\n", whoName[who], data); +if (offset == HP) + WriteLog("TOM: Horizontal Period written by %s: %u (+1*2 = %u)\n", whoName[who], data, (data + 1) * 2); +if (offset == HBB) + WriteLog("TOM: Horizontal Blank Begin written by %s: %u\n", whoName[who], data); +if (offset == HBE) + WriteLog("TOM: Horizontal Blank End written by %s: %u\n", whoName[who], data); +if (offset == HS) + WriteLog("TOM: Horizontal Sync written by %s: %u\n", whoName[who], data); +if (offset == HVS) + WriteLog("TOM: Horizontal Vertical Sync written by %s: %u\n", whoName[who], data); +if (offset == HDB1) + WriteLog("TOM: Horizontal Display Begin 1 written by %s: %u\n", whoName[who], data); +if (offset == HDB2) + WriteLog("TOM: Horizontal Display Begin 2 written by %s: %u\n", whoName[who], data); +if (offset == HDE) + WriteLog("TOM: Horizontal Display End written by %s: %u\n", whoName[who], data); +if (offset == VP) + WriteLog("TOM: Vertical Period written by %s: %u (%sinterlaced)\n", whoName[who], data, (data & 0x01 ? "non-" : "")); +if (offset == VBB) + WriteLog("TOM: Vertical Blank Begin written by %s: %u\n", whoName[who], data); +if (offset == VBE) + WriteLog("TOM: Vertical Blank End written by %s: %u\n", whoName[who], data); +if (offset == VS) + WriteLog("TOM: Vertical Sync written by %s: %u\n", whoName[who], data); +if (offset == VDB) + WriteLog("TOM: Vertical Display Begin written by %s: %u\n", whoName[who], data); +if (offset == VDE) + WriteLog("TOM: Vertical Display End written by %s: %u\n", whoName[who], data); +if (offset == VEB) + WriteLog("TOM: Vertical Equalization Begin written by %s: %u\n", whoName[who], data); +if (offset == VEE) + WriteLog("TOM: Vertical Equalization End written by %s: %u\n", whoName[who], data); +if (offset == VI) + WriteLog("TOM: Vertical Interrupt written by %s: %u\n", whoName[who], data); +if (offset == PIT0) + WriteLog("TOM: PIT0 written by %s: %u\n", whoName[who], data); +if (offset == PIT1) + WriteLog("TOM: PIT1 written by %s: %u\n", whoName[who], data); +if (offset == HEQ) + WriteLog("TOM: Horizontal Equalization End written by %s: %u\n", whoName[who], data); +//if (offset == BG) +// WriteLog("TOM: Background written by %s: %u\n", whoName[who], data); +//if (offset == INT1) +// WriteLog("TOM: CPU Interrupt Control written by %s: $%04X (%s%s%s%s%s)\n", whoName[who], data, (data & 0x01 ? "Video" : ""), (data & 0x02 ? " GPU" : ""), (data & 0x04 ? " OP" : ""), (data & 0x08 ? " TOMPIT" : ""), (data & 0x10 ? " Jerry" : "")); + + // detect screen resolution changes +//This may go away in the future, if we do the virtualized screen thing... +//This may go away soon! +// TOM Shouldn't be mucking around with this, it's up to the host system to properly +// handle this kind of crap. +// NOTE: This is needed somehow, need to get rid of the dependency on this crap. +// N.B.: It's used in the rendering functions... So... +#warning "!!! Need to get rid of this dependency !!!" +#if 1 + if ((offset >= 0x28) && (offset <= 0x4F)) + { + uint32_t width = TOMGetVideoModeWidth(), height = TOMGetVideoModeHeight(); + + if ((width != tomWidth) || (height != tomHeight)) + { + tomWidth = width, tomHeight = height; + +#warning "!!! TOM: ResizeScreen commented out !!!" +// No need to resize anything, since we're prepared for this... +// if (vjs.renderType == RT_NORMAL) +// ResizeScreen(tomWidth, tomHeight); + } + } +#endif +} + + +int TOMIRQEnabled(int irq) +{ + // This is the correct byte in big endian... D'oh! +// return jaguar_byte_read(0xF000E1) & (1 << irq); + return tomRam8[INT1 + 1/*0xE1*/] & (1 << irq); +} + + +// NEW: +// TOM Programmable Interrupt Timer handler +// NOTE: TOM's PIT is only enabled if the prescaler is != 0 +// The PIT only generates an interrupt when it counts down to zero, not when loaded! + +void TOMPITCallback(void); + + +void TOMResetPIT(void) +{ +#ifndef NEW_TIMER_SYSTEM +//Probably should *add* this amount to the counter to retain cycle accuracy! !!! FIX !!! [DONE] +//Also, why +1??? 'Cause that's what it says in the JTRM...! +//There is a small problem with this approach: If both the prescaler and the divider are equal +//to $FFFF then the counter won't be large enough to handle it. !!! FIX !!! + if (tom_timer_prescaler) + tom_timer_counter += (1 + tom_timer_prescaler) * (1 + tom_timer_divider); +// WriteLog("tom: reseting timer to 0x%.8x (%i)\n",tom_timer_counter,tom_timer_counter); +#else + // Need to remove previous timer from the queue, if it exists... + RemoveCallback(TOMPITCallback); + + if (tomTimerPrescaler) + { + double usecs = (float)(tomTimerPrescaler + 1) * (float)(tomTimerDivider + 1) * RISC_CYCLE_IN_USEC; + SetCallbackTime(TOMPITCallback, usecs); + } +#endif +} + + +// +// TOM Programmable Interrupt Timer handler +// NOTE: TOM's PIT is only enabled if the prescaler is != 0 +// +//NOTE: This is only used by the old execution code... Safe to remove +// once the timer system is stable. +void TOMExecPIT(uint32_t cycles) +{ + if (tomTimerPrescaler) + { + tomTimerCounter -= cycles; + + if (tomTimerCounter <= 0) + { + TOMSetPendingTimerInt(); + GPUSetIRQLine(GPUIRQ_TIMER, ASSERT_LINE); // GPUSetIRQLine does the 'IRQ enabled' checking + + if (TOMIRQEnabled(IRQ_TIMER)) + m68k_set_irq(2); // Cause a 68000 IPL 2... + + TOMResetPIT(); + } + } +} + + +void TOMPITCallback(void) +{ +// INT1_RREG |= 0x08; // Set TOM PIT interrupt pending + TOMSetPendingTimerInt(); + GPUSetIRQLine(GPUIRQ_TIMER, ASSERT_LINE); // It does the 'IRQ enabled' checking + +// if (INT1_WREG & 0x08) + if (TOMIRQEnabled(IRQ_TIMER)) + m68k_set_irq(2); // Generate a 68K IPL 2... + + TOMResetPIT(); +} + diff --git a/waterbox/virtualjaguar/src/tom.h b/waterbox/virtualjaguar/src/tom.h new file mode 100644 index 0000000000..4ac5736b41 --- /dev/null +++ b/waterbox/virtualjaguar/src/tom.h @@ -0,0 +1,73 @@ +// +// TOM Header file +// + +#ifndef __TOM_H__ +#define __TOM_H__ + +#include "memory.h" + +#define VIDEO_MODE_16BPP_CRY 0 +#define VIDEO_MODE_24BPP_RGB 1 +#define VIDEO_MODE_16BPP_DIRECT 2 +#define VIDEO_MODE_16BPP_RGB 3 + +// Virtual screen size stuff + +// NB: This virtual width is for PWIDTH = 4 +//#define VIRTUAL_SCREEN_WIDTH 320 +//was:340, 330 +#define VIRTUAL_SCREEN_WIDTH 326 +#define VIRTUAL_SCREEN_HEIGHT_NTSC 240 +#define VIRTUAL_SCREEN_HEIGHT_PAL 256 + +// 68000 Interrupt bit positions (enabled at $F000E0) + +enum { IRQ_VIDEO = 0, IRQ_GPU, IRQ_OPFLAG, IRQ_TIMER, IRQ_DSP }; + +void TOMInit(void); +void TOMReset(void); +void TOMDone(void); + +uint8_t TOMReadByte(uint32_t offset, uint32_t who = UNKNOWN); +uint16_t TOMReadWord(uint32_t offset, uint32_t who = UNKNOWN); +void TOMWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN); +void TOMWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN); + +void TOMExecHalfline(uint16_t halfline, bool render); +uint32_t TOMGetVideoModeWidth(void); +uint32_t TOMGetVideoModeHeight(void); +uint8_t TOMGetVideoMode(void); +uint8_t * TOMGetRamPointer(void); +uint16_t TOMGetHDB(void); +uint16_t TOMGetVDB(void); +uint16_t TOMGetHC(void); +uint16_t TOMGetVP(void); +uint16_t TOMGetMEMCON1(void); +void TOMDumpIORegistersToLog(void); + + +int TOMIRQEnabled(int irq); +uint16_t TOMIRQControlReg(void); +void TOMSetIRQLatch(int irq, int enabled); +void TOMExecPIT(uint32_t cycles); +void TOMSetPendingJERRYInt(void); +void TOMSetPendingTimerInt(void); +void TOMSetPendingObjectInt(void); +void TOMSetPendingGPUInt(void); +void TOMSetPendingVideoInt(void); +void TOMResetPIT(void); + +// Exported variables + +extern uint32_t tomWidth; +extern uint32_t tomHeight; +extern uint8_t tomRam8[]; +extern uint32_t tomTimerPrescaler; +extern uint32_t tomTimerDivider; +extern int32_t tomTimerCounter; + +extern uint32_t screenPitch; +extern uint32_t * screenBuffer; + +#endif // __TOM_H__ diff --git a/waterbox/virtualjaguar/src/universalhdr.cpp b/waterbox/virtualjaguar/src/universalhdr.cpp new file mode 100644 index 0000000000..dff42d3c9f --- /dev/null +++ b/waterbox/virtualjaguar/src/universalhdr.cpp @@ -0,0 +1,274 @@ +// +// Universal Header for Jaguar carts +// +// (C) 2011 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 06/28/2011 Created this file ;-) +// + +// +// This file was automagically generated by bin2c (by James Hammons) +// + +unsigned char universalCartHeader[0x2000] = { + 0xF6, 0x42, 0x23, 0x3C, 0x0D, 0xAC, 0x1D, 0x8D, 0xB0, 0x23, 0x71, 0x53, 0xBE, 0x87, 0x11, 0x17, 0x98, 0x27, 0x04, 0x26, 0x22, 0xC1, 0xBE, 0x1F, 0x79, 0x30, 0xDB, 0x90, 0xC6, 0xC8, 0x13, 0xF8, + 0x09, 0x41, 0x99, 0x78, 0x51, 0xCB, 0xFF, 0x8C, 0xF9, 0x7F, 0x75, 0xF0, 0x6B, 0x0E, 0xFE, 0x13, 0x2D, 0x84, 0xD8, 0x21, 0xE5, 0x91, 0xD4, 0x01, 0x3F, 0x23, 0x5E, 0x13, 0xAE, 0xF2, 0x2F, 0xEF, + 0x6C, 0x09, 0xD8, 0x06, 0x9F, 0x39, 0x27, 0x8F, 0x6D, 0x4F, 0x03, 0xD3, 0xD9, 0x84, 0x3D, 0xEA, 0xAB, 0xB7, 0x48, 0xF1, 0xE6, 0x98, 0x51, 0x27, 0xF0, 0x6E, 0x94, 0x0E, 0x90, 0x92, 0xC8, 0xF4, + 0x50, 0x3B, 0x46, 0x58, 0x08, 0x23, 0xE0, 0x4B, 0xD2, 0x3C, 0x1C, 0xC5, 0x30, 0x6B, 0x11, 0x24, 0xFA, 0xC6, 0x78, 0x29, 0xD1, 0x53, 0x5A, 0x64, 0xE0, 0x91, 0x5A, 0x16, 0xEC, 0xD9, 0x87, 0xC4, + 0xD8, 0x2D, 0x16, 0x98, 0x6A, 0x85, 0x29, 0x01, 0xF7, 0x25, 0xFB, 0xF6, 0xF9, 0xC1, 0x0F, 0x38, 0xA7, 0xB3, 0x9B, 0x1E, 0xC6, 0x19, 0x69, 0x1E, 0x6B, 0x05, 0x01, 0x77, 0xD0, 0xCD, 0x09, 0xF0, + 0xA7, 0x0F, 0xAA, 0x76, 0x24, 0x92, 0x26, 0x28, 0xEF, 0x72, 0xE4, 0x86, 0x41, 0x3B, 0x83, 0x22, 0x3C, 0x07, 0x4F, 0x67, 0x0B, 0xB6, 0x27, 0x5F, 0x7C, 0xD7, 0xEC, 0x52, 0xF6, 0xBF, 0x44, 0xEE, + 0x9C, 0x6B, 0x33, 0x0A, 0x36, 0xBE, 0x4C, 0xEB, 0x3E, 0x34, 0xE4, 0x3A, 0xFD, 0xF6, 0x75, 0x87, 0xB1, 0xED, 0xF6, 0x51, 0x72, 0x06, 0x99, 0x28, 0x10, 0x71, 0xD7, 0x44, 0x7E, 0xDE, 0x0F, 0x96, + 0xF3, 0x84, 0x01, 0xFF, 0x59, 0x71, 0x33, 0xB2, 0x18, 0x55, 0x4E, 0x56, 0x43, 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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +}; diff --git a/waterbox/virtualjaguar/src/universalhdr.h b/waterbox/virtualjaguar/src/universalhdr.h new file mode 100644 index 0000000000..6f0ce532ac --- /dev/null +++ b/waterbox/virtualjaguar/src/universalhdr.h @@ -0,0 +1,10 @@ +// +// Universal Header for Jaguar carts +// + +#ifndef __UNIVERSALHDR_H__ +#define __UNIVERSALHDR_H__ + +extern unsigned char universalCartHeader[]; + +#endif // __UNIVERSALHDR_H__ diff --git a/waterbox/virtualjaguar/src/wavetable.cpp b/waterbox/virtualjaguar/src/wavetable.cpp new file mode 100644 index 0000000000..7f576e6d74 --- /dev/null +++ b/waterbox/virtualjaguar/src/wavetable.cpp @@ -0,0 +1,278 @@ +// +// Jaguar Wavetable ROM +// +// (C) 2010 Underground Software +// +// JLH = James Hammons +// +// Who When What +// --- ---------- ------------------------------------------------------------- +// JLH 01/16/2010 Created this log ;-) +// + +// +// In a real Jaguar, these are 16-bit values that are sign-extended to 32 bits. +// Each entry has 128 values (e.g., SINE goes from F1D200-F1D3FF) +// +// NOTE: This can probably be converted to 32-bit table, since I don't think +// that unaligned access is allowed... + +/*const*/ unsigned char waveTableROM[4096] = +{ + 0xFF, 0xFF, 0xC2, 0x01, 0xFF, 0xFF, 0xC4, 0x01, 0xFF, 0xFF, 0xC6, 0x01, 0xFF, 0xFF, 0xC8, 0x01, + 0xFF, 0xFF, 0xCA, 0x01, 0xFF, 0xFF, 0xCC, 0x01, 0xFF, 0xFF, 0xCE, 0x01, 0xFF, 0xFF, 0xD0, 0x01, + 0xFF, 0xFF, 0xD2, 0x01, 0xFF, 0xFF, 0xD4, 0x01, 0xFF, 0xFF, 0xD6, 0x01, 0xFF, 0xFF, 0xD8, 0x01, + 0xFF, 0xFF, 0xDA, 0x01, 0xFF, 0xFF, 0xDC, 0x01, 0xFF, 0xFF, 0xDE, 0x01, 0xFF, 0xFF, 0xE0, 0x01, + 0xFF, 0xFF, 0xE2, 0x01, 0xFF, 0xFF, 0xE4, 0x01, 0xFF, 0xFF, 0xE6, 0x01, 0xFF, 0xFF, 0xE8, 0x01, + 0xFF, 0xFF, 0xEA, 0x01, 0xFF, 0xFF, 0xEC, 0x01, 0xFF, 0xFF, 0xEE, 0x01, 0xFF, 0xFF, 0xF0, 0x01, + 0xFF, 0xFF, 0xF2, 0x01, 0xFF, 0xFF, 0xF4, 0x01, 0xFF, 0xFF, 0xF6, 0x01, 0xFF, 0xFF, 0xF8, 0x01, + 0xFF, 0xFF, 0xFA, 0x01, 0xFF, 0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x05, 0xFF, 0x00, 0x00, 0x07, 0xFF, + 0x00, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x0B, 0xFF, 0x00, 0x00, 0x0D, 0xFF, 0x00, 0x00, 0x0F, 0xFF, + 0x00, 0x00, 0x11, 0xFF, 0x00, 0x00, 0x13, 0xFF, 0x00, 0x00, 0x15, 0xFF, 0x00, 0x00, 0x17, 0xFF, + 0x00, 0x00, 0x19, 0xFF, 0x00, 0x00, 0x1B, 0xFF, 0x00, 0x00, 0x1D, 0xFF, 0x00, 0x00, 0x1F, 0xFF, + 0x00, 0x00, 0x21, 0xFF, 0x00, 0x00, 0x23, 0xFF, 0x00, 0x00, 0x25, 0xFF, 0x00, 0x00, 0x27, 0xFF, + 0x00, 0x00, 0x29, 0xFF, 0x00, 0x00, 0x2B, 0xFF, 0x00, 0x00, 0x2D, 0xFF, 0x00, 0x00, 0x2F, 0xFF, + 0x00, 0x00, 0x31, 0xFF, 0x00, 0x00, 0x33, 0xFF, 0x00, 0x00, 0x35, 0xFF, 0x00, 0x00, 0x37, 0xFF, + 0x00, 0x00, 0x39, 0xFF, 0x00, 0x00, 0x3B, 0xFF, 0x00, 0x00, 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0xFF, 0xFF, 0xD3, 0x92, + 0x00, 0x00, 0x14, 0xA4, 0xFF, 0xFF, 0xE8, 0x95, 0xFF, 0xFF, 0xF2, 0xD8, 0x00, 0x00, 0x30, 0x8A, + 0xFF, 0xFF, 0xF9, 0x85, 0xFF, 0xFF, 0xFB, 0x89, 0x00, 0x00, 0x19, 0x0E, 0x00, 0x00, 0x21, 0x02, + 0xFF, 0xFF, 0xF2, 0x6B, 0xFF, 0xFF, 0xEE, 0x43, 0xFF, 0xFF, 0xE9, 0xFE, 0x00, 0x00, 0x0D, 0x8A, + 0xFF, 0xFF, 0xFA, 0x2B, 0x00, 0x00, 0x09, 0xA5, 0x00, 0x00, 0x1F, 0x45, 0x00, 0x00, 0x1C, 0x1D, + 0xFF, 0xFF, 0xEA, 0x2A, 0xFF, 0xFF, 0xE8, 0xDB, 0x00, 0x00, 0x11, 0xE2, 0x00, 0x00, 0x0C, 0x5A, + 0x00, 0x00, 0x14, 0xC7, 0x00, 0x00, 0x08, 0x64, 0xFF, 0xFF, 0xD7, 0x61, 0xFF, 0xFF, 0xE8, 0x6E, + 0xFF, 0xFF, 0xF0, 0x47, 0xFF, 0xFF, 0xF7, 0x6F, 0x00, 0x00, 0x02, 0x0E, 0xFF, 0xFF, 0xFE, 0xC9, + 0xFF, 0xFF, 0xF0, 0x44, 0x00, 0x00, 0x06, 0x27, 0x00, 0x00, 0x03, 0x33, 0xFF, 0xFF, 0xFA, 0x47, + 0xFF, 0xFF, 0xF5, 0xFE, 0xFF, 0xFF, 0xDC, 0x9F, 0x00, 0x00, 0x1B, 0x8D, 0x00, 0x00, 0x20, 0x7F, + 0x00, 0x00, 0x0C, 0x79, 0xFF, 0xFF, 0xE7, 0x85, 0x00, 0x00, 0x0B, 0x90, 0xFF, 0xFF, 0xDF, 0xE8, + 0x00, 0x00, 0x06, 0x90, 0x00, 0x00, 0x0A, 0xC8, 0x00, 0x00, 0x1A, 0xAF, 0x00, 0x00, 0x1E, 0xF3, + 0x00, 0x00, 0x13, 0xFD, 0xFF, 0xFF, 0xE1, 0xCC, 0x00, 0x00, 0x19, 0xA2, 0xFF, 0xFF, 0xE5, 0xC4, + 0xFF, 0xFF, 0xE4, 0xF3, 0x00, 0x00, 0x49, 0xEC, 0xFF, 0xFF, 0xF9, 0x26, 0xFF, 0xFF, 0xF3, 0x7F, + 0x00, 0x00, 0x0A, 0xBC, 0xFF, 0xFF, 0xEC, 0xFD, 0x00, 0x00, 0x0E, 0xAA, 0xFF, 0xFF, 0xFC, 0x53, + 0xFF, 0xFF, 0xFB, 0xFD, 0xFF, 0xFF, 0xF0, 0x58, 0x00, 0x00, 0x02, 0x91, 0xFF, 0xFF, 0xE3, 0x83, + 0x00, 0x00, 0x18, 0x80, 0xFF, 0xFF, 0xF1, 0x35, 0xFF, 0xFF, 0xF3, 0x0C, 0xFF, 0xFF, 0xE6, 0xD6, +}; diff --git a/waterbox/virtualjaguar/src/wavetable.h b/waterbox/virtualjaguar/src/wavetable.h new file mode 100644 index 0000000000..cfd905c108 --- /dev/null +++ b/waterbox/virtualjaguar/src/wavetable.h @@ -0,0 +1,17 @@ +// +// Jaguar Wavetable ROM +// +// In a real Jaguar, these are 16-bit values that are sign-extended to 32 bits. +// Each entry has 128 values (e.g., SINE goes from F1D200-F1D3FF) +// + +// NOTE: This can probably be converted to 32-bit table, since I don't think +// that unaligned access is allowed... + +#ifndef __WAVETABLE_H__ +#define __WAVETABLE_H__ + +// How to preserve const-ness of this stuff without introducing tons of hairiness? +extern /*const*/ unsigned char waveTableROM[]; + +#endif // __WAVETABLE_H__