From 3e495e3a2862a69bea96728d89fe5bf04db2d22a Mon Sep 17 00:00:00 2001
From: alyosha-tas <alexei.f.k@gmail.com>
Date: Thu, 14 Jun 2018 08:02:06 -0400
Subject: [PATCH] z80: reset cleanup

---
 BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt   |  8 +++-----
 BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs |  6 ------
 BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs      | 15 +++++++++------
 3 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt b/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
index 10804fde94..db37bed6fa 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/ReadMe.txt
@@ -1,7 +1,5 @@
 TODO: 
 
-Mode 0
-Check T-cycle level memory access timing
-Check R register 
-new tests for WZ Registers
-Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
+Mode 0 (nothing to test with)
+IRQ BUS timings (nothing to test with)
+BusAQ (nothing to test with)
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs
index b081996cde..339fb6864e 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs
@@ -127,12 +127,6 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 				Regs[i] = 0;
 			}
 
-			// These registers are set as part of the reset process
-			Regs[A] = 0xFF;
-			Regs[F] = 0xFF;
-			Regs[SPl] = 0xFF;
-			Regs[SPh] = 0xFF;
-
 			// the IRQ1 vector is 0x38
 			Regs[IRQ_V] = 0x38;
 			// The NMI vector is constant 0x66
diff --git a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
index cc4d21ce60..242b21dbac 100644
--- a/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
+++ b/BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
@@ -97,13 +97,16 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
 			ResetInterrupts();
 			TotalExecutedCycles = 0;
 			cur_instr = new ushort[] 
-						{ IDLE,
-						  WAIT,
-						  OP_F,
-						  OP };
+						{IDLE,
+						DEC16, F, A,
+						DEC16, SPl, SPh,
+						IDLE,
+						WAIT,
+						OP_F,
+						OP };
 
-			BUSRQ = new ushort[] { PCh, 0, 0, 0 };
-			MEMRQ = new ushort[] { PCh, 0, 0, 0 };
+			BUSRQ = new ushort[] { 0, 0, 0, PCh, 0, 0, 0 };
+			MEMRQ = new ushort[] { 0, 0, 0, PCh, 0, 0, 0 };
 			instr_pntr = 0; bus_pntr = 0; mem_pntr = 0;
 			NO_prefix = true;
 		}