Vectrex: some cleanup

This commit is contained in:
alyosha-tas 2019-04-21 19:11:45 -04:00
parent 1976e8e027
commit 25d4d6a840
4 changed files with 89 additions and 8 deletions

View File

@ -125,7 +125,6 @@ namespace BizHawk.Emulation.Common.Components.MC6809
WR_HI_INC, IDX_EA, ADDR,
WR_DEC_LO, IDX_EA, B);
Console.WriteLine("here");
IRQS = 3;
}

View File

@ -37,7 +37,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
public const ushort CWAI = 26;
public const ushort SYNC = 27;
public const ushort INT_GET = 28;
public const ushort HALT_CHK = 29; // when in halt mode, actually check I Flag here
public const ushort HALT_CHK = 29;
public const ushort RD_INC = 30;
public const ushort SET_ADDR = 31;
public const ushort NEG = 32;
@ -148,7 +148,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
// Execute instructions
public void ExecuteOne()
{
Console.Write(opcode_see + " ");
//Console.Write(opcode_see + " ");
switch (cur_instr[instr_pntr++])
{
case IDLE:

View File

@ -5,15 +5,61 @@ using BizHawk.Common;
namespace BizHawk.Emulation.Cores.Consoles.Vectrex
{
// MOS6522 Interface
/* Port B writes to both the PSG and the DAC simultaneously
* The trick here is that bits 3 and 4 both zero represent PSG disabled
* So it's easy to not interfere with the PSG
* However, the DAC will always receive some input, controlled by the multiplexer and selector bits
* BIOS functions keep everything in order
*/
public partial class VectrexHawk
{
public byte dir_dac, dir_ctrl;
public byte portB_ret, portA_ret;
public byte Read_Registers(int addr)
{
byte ret = 0;
switch (addr)
{
default:
case 0x0:
ret = portB_ret;
break;
case 0x1:
ret = portA_ret;
break;
case 0x2:
ret = dir_ctrl;
break;
case 0x3:
ret = dir_dac;
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xA:
break;
case 0xB:
break;
case 0xC:
break;
case 0xD:
break;
case 0xE:
break;
case 0xF:
break;
}
return ret;
@ -21,9 +67,45 @@ namespace BizHawk.Emulation.Cores.Consoles.Vectrex
public void Write_Registers(int addr, byte value)
{
byte wrt_val = 0;
switch (addr)
{
default:
case 0x0:
wrt_val = (byte)(value & dir_ctrl);
break;
case 0x1:
wrt_val = (byte)(value & dir_dac);
break;
case 0x2:
dir_ctrl = value;
break;
case 0x3:
dir_dac = value;
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xA:
break;
case 0xB:
break;
case 0xC:
break;
case 0xD:
break;
case 0xE:
break;
case 0xF:
break;
}
}

View File

@ -33,7 +33,7 @@ namespace BizHawk.Emulation.Cores.Consoles.Vectrex
}
else if (addr < 0xD800)
{
return 0xFF;
return Read_Registers(addr & 0xF);
}
else if (addr < 0xE000)
{
@ -67,7 +67,7 @@ namespace BizHawk.Emulation.Cores.Consoles.Vectrex
}
else if (addr < 0xD800)
{
Write_Registers(addr & 0xF, value);
}
else if (addr < 0xE000)
{
@ -99,7 +99,7 @@ namespace BizHawk.Emulation.Cores.Consoles.Vectrex
}
else if (addr < 0xD800)
{
return 0xFF;
return Read_Registers(addr & 0xF);
}
else if (addr < 0xE000)
{