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CPCHawk2024 (#4071) 

* [CPCHawk] Start of new gate array and CRTC implementation

* [CPCHawk] Some cleanup

* [CPCHawk] More Cleanup

* [CPCHawk] More CRTC work

* [CPCHawk] More crtc work

* [CPCHawk] more CRTC work

* [CPCHawk] More CRTC work

* [CPCHawk] more crtc

* [CPCHawk] GateArray breaking changes WIP

* [CPCHawk] GA, CRTC and Screen changes

* [CPCHawk] CRTC and GateArray

* [CPCHawk] More stuff

* [CPCHawk] Progress

* [CPCHawk] Starting CRTC type abstraction

* [CPCHawk] Start CRTC status register implementation

* [CPCHAWK] Update colour palatte

* [CPCHawk] Trying to fix GA colour issues

* [CPCHawk] Actually use the Z80 /WAIT line

* [CPCHawk] Frame now running at req 19968 x6 INT

* [CPCHawk] Implement PAL16L8 as a separate device

* [CPCHawk] Border cropping SyncSetting

* [CPCHawk] Stuff

* [CPCHawk] More accurate CRT emulation

* [CPCHawk] Reset vertical timing var only when VSYNC ends in the middle of a scaline

* [CPCHawk] Allow IN port accesses to affect certain write-only devices

* [CPCHawk] Fixed high-impedence returns

* [CPCHawk] Readme update

* [CPCHawk] Update readme with Z80 timing test failures

* [CPCHawk] Update readme
This commit is contained in:
Asnivor 2024-10-02 12:54:22 +01:00 committed by GitHub
parent 5cc4c1f924
commit 2193c0a0e5
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GPG Key ID: B5690EEEBB952194
32 changed files with 4526 additions and 6065 deletions
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3
src/BizHawk.Client.Common/movie/PlatformFrameRates.cs
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@ -72,7 +72,8 @@ namespace BizHawk.Client.Common
["INTV"] = 59.92,
["ZXSpectrum_PAL"] = 50.080128205,
["AmstradCPC_PAL"] = 50.08012820512821,
["AmstradCPC_PAL"] = 50.08012820512821, // = 1 / ((1024 * 312) / 16,000,000)
["UZE"] = 1125000.0 / 18733.0, // = 8 * 315000000 / 88 / 1820 / 262 ≈ 60.05444936742646666
["VEC"] = 50,
["O2"] = 89478485.0 / 1495643, // 59.8260982065907439141559850846

12
src/BizHawk.Client.EmuHawk/BizHawk.Client.EmuHawk.csproj
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@ -267,10 +267,10 @@
<EmbeddedResource Update="LogWindow.resx" DependentUpon="LogWindow.cs" />
<Compile Update="MainForm.cs" SubType="Form" />
<Compile Update="MainForm.Designer.cs" DependentUpon="MainForm.cs" />
<Compile Update="MainForm.Events.cs" DependentUpon="MainForm.cs" SubType="Form" />
<Compile Update="MainForm.Events.cs" DependentUpon="MainForm.cs" />
<Compile Update="MainForm.FileLoader.cs" DependentUpon="MainForm.cs" SubType="Form" />
<Compile Update="MainForm.Hotkey.cs" DependentUpon="MainForm.cs" SubType="Form" />
<Compile Update="MainForm.Movie.cs" DependentUpon="MainForm.cs" SubType="Form" />
<Compile Update="MainForm.Hotkey.cs" DependentUpon="MainForm.cs" />
<Compile Update="MainForm.Movie.cs" DependentUpon="MainForm.cs" />
<EmbeddedResource Update="MainForm.resx" DependentUpon="MainForm.cs" SubType="Designer" />
<Compile Update="movie/EditCommentsForm.cs" SubType="Form" />
<Compile Update="movie/EditCommentsForm.Designer.cs" DependentUpon="EditCommentsForm.cs" />
@ -330,9 +330,9 @@
<EmbeddedResource Update="tools/Debugger/BreakpointControl.resx" DependentUpon="BreakpointControl.cs" />
<Compile Update="tools/Debugger/GenericDebugger.cs" SubType="Form" />
<Compile Update="tools/Debugger/GenericDebugger.Designer.cs" DependentUpon="GenericDebugger.cs" />
<Compile Update="tools/Debugger/GenericDebugger.Disassembler.cs" DependentUpon="GenericDebugger.cs" SubType="Form" />
<Compile Update="tools/Debugger/GenericDebugger.IControlMainform.cs" DependentUpon="GenericDebugger.cs" SubType="Form" />
<Compile Update="tools/Debugger/GenericDebugger.IToolForm.cs" DependentUpon="GenericDebugger.cs" SubType="Form" />
<Compile Update="tools/Debugger/GenericDebugger.Disassembler.cs" DependentUpon="GenericDebugger.cs" />
<Compile Update="tools/Debugger/GenericDebugger.IControlMainform.cs" DependentUpon="GenericDebugger.cs" />
<Compile Update="tools/Debugger/GenericDebugger.IToolForm.cs" DependentUpon="GenericDebugger.cs" />
<EmbeddedResource Update="tools/Debugger/GenericDebugger.resx" DependentUpon="GenericDebugger.cs" />
<Compile Update="tools/Debugger/RegisterBoxControl.cs" SubType="UserControl" />
<Compile Update="tools/Debugger/RegisterBoxControl.Designer.cs" DependentUpon="RegisterBoxControl.cs" />

5
src/BizHawk.Client.EmuHawk/config/AmstradCPC/AmstradCPCCoreEmulationSettings.cs
View File

@ -99,9 +99,8 @@ namespace BizHawk.Client.EmuHawk
{
lblBorderInfo.Text = type switch
{
AmstradCPC.BorderType.Uniform => "Attempts to equalize the border areas",
AmstradCPC.BorderType.Uncropped => "Pretty much the signal the gate array is generating (looks pants)",
AmstradCPC.BorderType.Widescreen => "Top and bottom border removed so that the result is *almost* 16:9",
AmstradCPC.BorderType.Visible => "Approximates what you see on a CPC monitor",
AmstradCPC.BorderType.Uncropped => "The full display area",
_ => lblBorderInfo.Text
};
}

13
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/AmstradCPC.ISettable.cs
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@ -106,7 +106,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
[DisplayName("Border type")]
[Description("Select how to show the border area")]
[DefaultValue(BorderType.Uniform)]
[DefaultValue(BorderType.Visible)]
public BorderType BorderType { get; set; }
public AmstradCPCSyncSettings Clone()
@ -331,19 +331,14 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
public enum BorderType
{
/// <summary>
/// Attempts to equalise the border areas
/// Roughly what you might see on an Amstrad monitor
/// </summary>
Uniform,
Visible,
/// <summary>
/// Pretty much the signal the gate array is generating (looks shit)
/// The full display area
/// </summary>
Uncropped,
/// <summary>
/// Top and bottom border removed so that the result is *almost* 16:9
/// </summary>
Widescreen,
}
}
}

3
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/AmstradCPC.cs
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@ -57,7 +57,8 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
ser.Register<ITraceable>(_tracer);
ser.Register<IDisassemblable>(_cpu);
ser.Register<IVideoProvider>(_machine.GateArray);
//ser.Register<IVideoProvider>(_machine.GateArray);
ser.Register<IVideoProvider>(_machine.CRTScreen);
ser.Register<IStatable>(new StateSerializer(SyncState));
// initialize sound mixer and attach the various ISoundProvider devices

0
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/SoundOutput/AY38912.cs → src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/AY38912.cs
View File

0
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/SoundOutput/Beeper.cs → src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Beeper.cs
View File

347
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.Type0.cs Normal file
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@ -0,0 +1,347 @@
using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// TYPE 0
/// - Hitachi HD6845S http://www.cpcwiki.eu/imgs/c/c0/Hd6845.hitachi.pdf
/// - UMC UM6845 http://www.cpcwiki.eu/imgs/1/13/Um6845.umc.pdf
/// </summary>
public class CRTC_Type0 : CRTC
{
/// <summary>
/// Defined CRTC type number
/// </summary>
public override int CrtcType => 0;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public override void Clock()
{
base.Clock();
int maxScanLine;
if (HCC == R0_HorizontalTotal)
{
// end of displayable area reached
// set up for the next line
HCC = 0;
if (R8_Interlace == 3)
{
// in interlace sync and video mask off bit 0 of the max scanline address
maxScanLine = R9_MaxScanline & 0b11110;
}
else
{
maxScanLine = R9_MaxScanline;
}
if (VLC == maxScanLine)
{
// we have reached the final scanline within this vertical character row
// move to next character
VLC = 0;
// TODO: implement vertical adjust
if (VCC == R4_VerticalTotal)
{
// check the interlace mode
if (R8_Interlace.Bit(0))
{
// toggle the field
_field = !_field;
}
else
{
// stay on the even field
_field = false;
}
// we have reached the end of the vertical display area
// address loaded from start address register at the top of each field
_vmaRowStart = (Register[R12_START_ADDR_H] << 8) | Register[R13_START_ADDR_L];
// reset the vertical character counter
VCC = 0;
// increment field counter
CFC++;
}
else
{
// row start address is increased by Horiztonal Displayed
_vmaRowStart += R1_HorizontalDisplayed;
// increment vertical character counter
VCC++;
}
}
else
{
// next scanline
if (R8_Interlace == 3)
{
// interlace sync+video mode
// vertical line counter increments by 2
VLC += 2;
// ensure vertical line counter is an even value
VLC &= ~1;
}
else
{
// non-interlace mode
// increment vertical line counter
VLC++;
}
}
// MA set to row start at the beginning of each line
_vma = _vmaRowStart;
}
else
{
// next horizontal character (1us)
// increment horizontal character counter
HCC++;
// increment VMA
_vma++;
}
hssstart = false;
hhclock = false;
if (HCC == R2_HorizontalSyncPosition)
{
// start of horizontal sync
hssstart = true;
}
if (HCC == R2_HorizontalSyncPosition / 2)
{
// we are half way through the line
hhclock = true;
}
/* Hor active video */
if (HCC == 0)
{
// active display
latch_hdisp = true;
}
if (HCC == R1_HorizontalDisplayed)
{
// inactive display
latch_hdisp = false;
}
/* Hor sync */
if (hssstart || // start of horizontal sync
HSYNC) // already in horizontal sync
{
// start of horizontal sync
HSYNC = true;
HSC++;
}
else
{
// reset hsync counter
HSC = 0;
}
if (HSC == R3_HorizontalSyncWidth)
{
// end of horizontal sync
HSYNC = false;
}
/* Ver active video */
if (VCC == 0)
{
// active display
latch_vdisp = true;
}
if (VCC == R6_VerticalDisplayed)
{
// inactive display
latch_vdisp = false;
}
// vertical sync occurs at different times depending on the interlace field
// even field: the same time as HSYNC
// odd field: half a line later than HSYNC
if ((!_field && hssstart) || (_field && hhclock))
{
if ((VCC == R7_VerticalSyncPosition && VLC == 0) // vsync starts on the first line
|| VSYNC) // vsync is already in progress
{
// start of vertical sync
VSYNC = true;
// increment vertical sync counter
VSC++;
}
else
{
// reset vsync counter
VSC = 0;
}
if (VSYNC && VSC == R3_VerticalSyncWidth - 1)
{
// end of vertical sync
VSYNC = false;
}
}
/* Address Generation */
int line = VLC;
if (R8_Interlace == 3)
{
// interlace sync+video mode
// the least significant bit is based on the current field number
int fNum = _field ? 1 : 0;
int lNum = VLC.Bit(0) ? 1 : 0;
line &= ~1;
_RA = line & (fNum | lNum);
}
else
{
// raster address is just the VLC
_RA = VLC;
}
_LA = _vma;
// DISPTMG Generation
if (!latch_hdisp || !latch_vdisp)
{
// HSYNC output pin is fed through a NOR gate with either 2 or 3 inputs
// - H Display
// - V Display
// - TODO: R8 DISPTMG Skew (only on certain CRTC types)
DISPTMG = false;
}
else
{
DISPTMG = true;
}
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected override bool ReadRegister(ref int data)
{
bool addressed;
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R3_SYNC_WIDTHS:
case R4_V_TOTAL:
case R5_V_TOTAL_ADJUST:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R8_INTERLACE_MODE:
case R9_MAX_SL_ADDRESS:
case R10_CURSOR_START:
case R11_CURSOR_END:
// write-only registers return 0x0 on Type 0 CRTC
addressed = true;
data = 0;
break;
case R12_START_ADDR_H:
case R14_CURSOR_H:
case R16_LIGHT_PEN_H:
// read/write registers (6bit)
addressed = true;
data = Register[AddressRegister] & 0x3F;
break;
case R13_START_ADDR_L:
case R15_CURSOR_L:
case R17_LIGHT_PEN_L:
// read/write regiters (8bit)
addressed = true;
data = Register[AddressRegister];
break;
default:
// non-existent registers return 0x0
addressed = true;
data = 0;
break;
}
return addressed;
}
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected override void WriteRegister(int data)
{
byte v = (byte)data;
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R3_SYNC_WIDTHS:
case R13_START_ADDR_L:
case R15_CURSOR_L:
// 8-bit registers
Register[AddressRegister] = v;
break;
case R4_V_TOTAL:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R10_CURSOR_START:
// 7-bit registers
Register[AddressRegister] = (byte)(v & 0x7F);
break;
case R12_START_ADDR_H:
case R14_CURSOR_H:
// 6-bit registers
Register[AddressRegister] = (byte)(v & 0x3F);
break;
case R5_V_TOTAL_ADJUST:
case R9_MAX_SL_ADDRESS:
case R11_CURSOR_END:
// 5-bit registers
Register[AddressRegister] = (byte)(v & 0x1F);
break;
case R8_INTERLACE_MODE:
// Interlace & skew masks bits 2 & 3
Register[AddressRegister] = (byte)(v & 0xF3);
break;
}
}
/// <summary>
/// CRTC 0 has no status register
/// </summary>
protected override bool ReadStatus(ref int data)
{
// ACCC1.8 - 21.3.2
// CRTC0 randomly apparently returns 255 or 127 on this port
// For the purposes of Bizhawk determinism, we will return one of the above values based on the current HCC
data = HCC.Bit(0) ? 255 : 127;
return true;
}
}
}

361
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.Type1.cs Normal file
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@ -0,0 +1,361 @@
using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// TYPE 1
/// - UMC UM6845R http://www.cpcwiki.eu/imgs/b/b5/Um6845r.umc.pdf
/// </summary>
public class CRTC_Type1 : CRTC
{
/// <summary>
/// Defined CRTC type number
/// </summary>
public override int CrtcType => 1;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public override void Clock()
{
base.Clock();
int maxScanLine;
if (HCC == R0_HorizontalTotal)
{
// end of displayable area reached
// set up for the next line
HCC = 0;
// TODO: handle interlace setup
if (R8_Interlace == 3)
{
// in interlace sync and video mask off bit 0 of the max scanline address
maxScanLine = R9_MaxScanline & 0b11110;
}
else
{
maxScanLine = R9_MaxScanline;
}
if (VLC == maxScanLine)
{
// we have reached the final scanline within this vertical character row
// move to next character
VLC = 0;
// TODO: implement vertical adjust
if (VCC == R4_VerticalTotal)
{
// check the interlace mode
if (R8_Interlace.Bit(0))
{
// toggle the field
_field = !_field;
}
else
{
// stay on the even field
_field = false;
}
// we have reached the end of the vertical display area
// address loaded from start address register at the top of each field
_vmaRowStart = (Register[R12_START_ADDR_H] << 8) | Register[R13_START_ADDR_L];
// reset the vertical character counter
VCC = 0;
// increment field counter
CFC++;
}
else
{
// row start address is increased by Horiztonal Displayed
_vmaRowStart += R1_HorizontalDisplayed;
// increment vertical character counter
VCC++;
}
}
else
{
// next scanline
if (R8_Interlace == 3)
{
// interlace sync+video mode
// vertical line counter increments by 2
VLC += 2;
// ensure vertical line counter is an even value
VLC &= ~1;
}
else
{
// non-interlace mode
// increment vertical line counter
VLC++;
}
}
// MA set to row start at the beginning of each line
_vma = _vmaRowStart;
}
else
{
// next horizontal character (1us)
// increment horizontal character counter
HCC++;
// increment VMA
_vma++;
}
hssstart = false;
hhclock = false;
if (HCC == R2_HorizontalSyncPosition)
{
// start of horizontal sync
hssstart = true;
}
if (HCC == R2_HorizontalSyncPosition / 2)
{
// we are half way through the line
hhclock = true;
}
/* Hor active video */
if (HCC == 0)
{
// active display
latch_hdisp = true;
}
if (HCC == R1_HorizontalDisplayed)
{
// inactive display
latch_hdisp = false;
}
/* Hor sync */
if (hssstart || // start of horizontal sync
HSYNC) // already in horizontal sync
{
// start of horizontal sync
HSYNC = true;
HSC++;
}
else
{
// reset hsync counter
HSC = 0;
}
if (HSC == R3_HorizontalSyncWidth)
{
// end of horizontal sync
HSYNC = false;
}
/* Ver active video */
if (VCC == 0)
{
// active display
latch_vdisp = true;
}
if (VCC == R6_VerticalDisplayed)
{
// inactive display
latch_vdisp = false;
// ACCC1.8 - 21.3.3
// On CRTC 1, bit 5 of the Status register is updated when C0=R0 according to the BORDER R6
// conditions (False: C4=C9=C0=0 / True: C4=R6 & C9=C0=0)
StatusRegister |= (1 << 5);
}
// vertical sync occurs at different times depending on the interlace field
// even field: the same time as HSYNC
// odd field: half a line later than HSYNC
if ((!_field && hssstart) || (_field && hhclock))
{
if ((VCC == R7_VerticalSyncPosition && VLC == 0) // vsync starts on the first line
|| VSYNC) // vsync is already in progress
{
// start of vertical sync
VSYNC = true;
// increment vertical sync counter
VSC++;
}
else
{
// reset vsync counter
VSC = 0;
}
if (VSYNC && VSC == R3_VerticalSyncWidth - 1)
{
// end of vertical sync
VSYNC = false;
}
}
/* Address Generation */
int line = VLC;
if (R8_Interlace == 3)
{
// interlace sync+video mode
// the least significant bit is based on the current field number
int fNum = _field ? 1 : 0;
int lNum = VLC.Bit(0) ? 1 : 0;
line &= ~1;
_RA = line & (fNum | lNum);
}
else
{
// raster address is just the VLC
_RA = VLC;
}
_LA = _vma;
// DISPTMG Generation
if (!latch_hdisp || !latch_vdisp)
{
// HSYNC output pin is fed through a NOR gate with either 2 or 3 inputs
// - H Display
// - V Display
// - TODO: R8 DISPTMG Skew (only on certain CRTC types)
DISPTMG = false;
}
else
{
DISPTMG = true;
}
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected override bool ReadRegister(ref int data)
{
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R3_SYNC_WIDTHS:
case R4_V_TOTAL:
case R5_V_TOTAL_ADJUST:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R8_INTERLACE_MODE:
case R9_MAX_SL_ADDRESS:
case R10_CURSOR_START:
case R11_CURSOR_END:
case R12_START_ADDR_H:
case R13_START_ADDR_L:
// write-only registers return 0x0 on Type 1 CRTC
data = 0;
break;
case R14_CURSOR_H:
data = Register[AddressRegister] & 0x3F;
break;
case R15_CURSOR_L:
data = Register[AddressRegister];
break;
case R16_LIGHT_PEN_H:
// read/write registers (6bit)
data = Register[AddressRegister] & 0x3F;
// reading from R16 resets bit6 of the status register
StatusRegister &= byte.MaxValue ^ (1 << 6);
break;
case R17_LIGHT_PEN_L:
// read/write regiters (8bit)
data = Register[AddressRegister];
// reading from R17 resets bit6 of the status register
StatusRegister &= byte.MaxValue ^ (1 << 6);
break;
case 31:
// Dummy Register. Datasheet describes this as N/A but CPCWIKI suggests that reading from it return 0xFF;
data = 0xFF;
break;
default:
// non-existent registers return 0x0
data = 0;
break;
}
return true;
}
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected override void WriteRegister(int data)
{
byte v = (byte)data;
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R13_START_ADDR_L:
case R15_CURSOR_L:
// 8-bit registers
Register[AddressRegister] = v;
break;
case R4_V_TOTAL:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R10_CURSOR_START:
// 7-bit registers
Register[AddressRegister] = (byte)(v & 0x7F);
break;
case R12_START_ADDR_H:
case R14_CURSOR_H:
// 6-bit registers
Register[AddressRegister] = (byte)(v & 0x3F);
break;
case R5_V_TOTAL_ADJUST:
case R9_MAX_SL_ADDRESS:
case R11_CURSOR_END:
// 5-bit registers
Register[AddressRegister] = (byte)(v & 0x1F);
break;
case R3_SYNC_WIDTHS:
// 4-bit register
Register[AddressRegister] = (byte)(v & 0x0F);
break;
case R8_INTERLACE_MODE:
// Interlace & skew - 2bit
Register[AddressRegister] = (byte)(v & 0x03);
break;
}
}
/// <summary>
/// CRTC 1 has a status register
/// </summary>
protected override bool ReadStatus(ref int data)
{
// ACCC1.8 - 21.3.1
// Only CRTC 1 has a status register present on the specific port &BE00.
// This port is a mirror of the read port for CRTC’s 3 and 4, which handle status differently
data = StatusRegister;
return true;
}
}
}

343
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.Type2.cs Normal file
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@ -0,0 +1,343 @@
using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// TYPE 2
/// - Motorola MC6845
/// http://www.cpcwiki.eu/imgs/d/da/Mc6845.motorola.pdf
/// http://bitsavers.trailing-edge.com/components/motorola/_dataSheets/6845.pdf
/// </summary>
public class CRTC_Type2 : CRTC
{
/// <summary>
/// Defined CRTC type number
/// </summary>
public override int CrtcType => 2;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public override void Clock()
{
base.Clock();
int maxScanLine;
if (HCC == R0_HorizontalTotal)
{
// end of displayable area reached
// set up for the next line
HCC = 0;
// TODO: handle interlace setup
if (R8_Interlace == 3)
{
// in interlace sync and video mask off bit 0 of the max scanline address
maxScanLine = R9_MaxScanline & 0b11110;
}
else
{
maxScanLine = R9_MaxScanline;
}
if (VLC == maxScanLine)
{
// we have reached the final scanline within this vertical character row
// move to next character
VLC = 0;
// TODO: implement vertical adjust
if (VCC == R4_VerticalTotal)
{
// check the interlace mode
if (R8_Interlace.Bit(0))
{
// toggle the field
_field = !_field;
}
else
{
// stay on the even field
_field = false;
}
// we have reached the end of the vertical display area
// address loaded from start address register at the top of each field
_vmaRowStart = (Register[R12_START_ADDR_H] << 8) | Register[R13_START_ADDR_L];
// reset the vertical character counter
VCC = 0;
// increment field counter
CFC++;
}
else
{
// row start address is increased by Horiztonal Displayed
_vmaRowStart += R1_HorizontalDisplayed;
// increment vertical character counter
VCC++;
}
}
else
{
// next scanline
if (R8_Interlace == 3)
{
// interlace sync+video mode
// vertical line counter increments by 2
VLC += 2;
// ensure vertical line counter is an even value
VLC &= ~1;
}
else
{
// non-interlace mode
// increment vertical line counter
VLC++;
}
}
// MA set to row start at the beginning of each line
_vma = _vmaRowStart;
}
else
{
// next horizontal character (1us)
// increment horizontal character counter
HCC++;
// increment VMA
_vma++;
}
hssstart = false;
hhclock = false;
if (HCC == R2_HorizontalSyncPosition)
{
// start of horizontal sync
hssstart = true;
}
if (HCC == R2_HorizontalSyncPosition / 2)
{
// we are half way through the line
hhclock = true;
}
/* Hor active video */
if (HCC == 0)
{
// active display
latch_hdisp = true;
}
if (HCC == R1_HorizontalDisplayed)
{
// inactive display
latch_hdisp = false;
}
/* Hor sync */
if (hssstart || // start of horizontal sync
HSYNC) // already in horizontal sync
{
// start of horizontal sync
HSYNC = true;
HSC++;
}
else
{
// reset hsync counter
HSC = 0;
}
if (HSC == R3_HorizontalSyncWidth)
{
// end of horizontal sync
HSYNC = false;
}
/* Ver active video */
if (VCC == 0)
{
// active display
latch_vdisp = true;
}
if (VCC == R6_VerticalDisplayed)
{
// inactive display
latch_vdisp = false;
}
// vertical sync occurs at different times depending on the interlace field
// even field: the same time as HSYNC
// odd field: half a line later than HSYNC
if ((!_field && hssstart) || (_field && hhclock))
{
if ((VCC == R7_VerticalSyncPosition && VLC == 0) // vsync starts on the first line
|| VSYNC) // vsync is already in progress
{
// start of vertical sync
VSYNC = true;
// increment vertical sync counter
VSC++;
}
else
{
// reset vsync counter
VSC = 0;
}
if (VSYNC && VSC == R3_VerticalSyncWidth - 1)
{
// end of vertical sync
VSYNC = false;
}
}
/* Address Generation */
int line = VLC;
if (R8_Interlace == 3)
{
// interlace sync+video mode
// the least significant bit is based on the current field number
int fNum = _field ? 1 : 0;
int lNum = VLC.Bit(0) ? 1 : 0;
line &= ~1;
_RA = line & (fNum | lNum);
}
else
{
// raster address is just the VLC
_RA = VLC;
}
_LA = _vma;
// DISPTMG Generation
if (!latch_hdisp || !latch_vdisp)
{
// HSYNC output pin is fed through a NOR gate with either 2 or 3 inputs
// - H Display
// - V Display
// - TODO: R8 DISPTMG Skew (only on certain CRTC types)
DISPTMG = false;
}
else
{
DISPTMG = true;
}
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected override bool ReadRegister(ref int data)
{
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R3_SYNC_WIDTHS:
case R4_V_TOTAL:
case R5_V_TOTAL_ADJUST:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R8_INTERLACE_MODE:
case R9_MAX_SL_ADDRESS:
case R10_CURSOR_START:
case R11_CURSOR_END:
case R12_START_ADDR_H:
case R13_START_ADDR_L:
// write-only registers do not respond on type 2
return false;
case R14_CURSOR_H:
case R16_LIGHT_PEN_H:
// read/write registers (6bit)
data = Register[AddressRegister] & 0x3F;
break;
case R17_LIGHT_PEN_L:
case R15_CURSOR_L:
// read/write regiters (8bit)
data = Register[AddressRegister];
break;
default:
// non-existent registers return 0x0
data = 0;
break;
}
return true;
}
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected override void WriteRegister(int data)
{
byte v = (byte)data;
switch (AddressRegister)
{
case R0_H_TOTAL:
case R1_H_DISPLAYED:
case R2_H_SYNC_POS:
case R13_START_ADDR_L:
case R15_CURSOR_L:
// 8-bit registers
Register[AddressRegister] = v;
break;
case R4_V_TOTAL:
case R6_V_DISPLAYED:
case R7_V_SYNC_POS:
case R10_CURSOR_START:
// 7-bit registers
Register[AddressRegister] = (byte)(v & 0x7F);
break;
case R12_START_ADDR_H:
case R14_CURSOR_H:
// 6-bit registers
Register[AddressRegister] = (byte)(v & 0x3F);
break;
case R5_V_TOTAL_ADJUST:
case R9_MAX_SL_ADDRESS:
case R11_CURSOR_END:
// 5-bit registers
Register[AddressRegister] = (byte)(v & 0x1F);
break;
case R3_SYNC_WIDTHS:
// 4-bit register
Register[AddressRegister] = (byte)(v & 0x0F);
break;
case R8_INTERLACE_MODE:
// Interlace & skew - 2bit
Register[AddressRegister] = (byte)(v & 0x03);
break;
}
}
/// <summary>
/// CRTC 2 has no status register
/// </summary>
protected override bool ReadStatus(ref int data)
{
// ACCC1.8 - 21.3.2
// CRTC2 always returns 255 on this port
data = 255;
return true;
}
}
}

303
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.Type3.cs Normal file
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using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// TYPE 3
/// - Amstrad AMS40489
/// </summary>
public class CRTC_Type3 : CRTC
{
/// <summary>
/// Defined CRTC type number
/// </summary>
public override int CrtcType => 3;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public override void Clock()
{
base.Clock();
int maxScanLine;
if (HCC == R0_HorizontalTotal)
{
// end of displayable area reached
// set up for the next line
HCC = 0;
// TODO: handle interlace setup
if (R8_Interlace == 3)
{
// in interlace sync and video mask off bit 0 of the max scanline address
maxScanLine = R9_MaxScanline & 0b11110;
}
else
{
maxScanLine = R9_MaxScanline;
}
if (VLC == maxScanLine)
{
// we have reached the final scanline within this vertical character row
// move to next character
VLC = 0;
// TODO: implement vertical adjust
if (VCC == R4_VerticalTotal)
{
// check the interlace mode
if (R8_Interlace.Bit(0))
{
// toggle the field
_field = !_field;
}
else
{
// stay on the even field
_field = false;
}
// we have reached the end of the vertical display area
// address loaded from start address register at the top of each field
_vmaRowStart = (Register[R12_START_ADDR_H] << 8) | Register[R13_START_ADDR_L];
// reset the vertical character counter
VCC = 0;
// increment field counter
CFC++;
}
else
{
// row start address is increased by Horiztonal Displayed
_vmaRowStart += R1_HorizontalDisplayed;
// increment vertical character counter
VCC++;
}
}
else
{
// next scanline
if (R8_Interlace == 3)
{
// interlace sync+video mode
// vertical line counter increments by 2
VLC += 2;
// ensure vertical line counter is an even value
VLC &= ~1;
}
else
{
// non-interlace mode
// increment vertical line counter
VLC++;
}
}
// MA set to row start at the beginning of each line
_vma = _vmaRowStart;
}
else
{
// next horizontal character (1us)
// increment horizontal character counter
HCC++;
// increment VMA
_vma++;
}
hssstart = false;
hhclock = false;
if (HCC == R2_HorizontalSyncPosition)
{
// start of horizontal sync
hssstart = true;
}
if (HCC == R2_HorizontalSyncPosition / 2)
{
// we are half way through the line
hhclock = true;
}
/* Hor active video */
if (HCC == 0)
{
// active display
latch_hdisp = true;
}
if (HCC == R1_HorizontalDisplayed)
{
// inactive display
latch_hdisp = false;
}
/* Hor sync */
if (hssstart || // start of horizontal sync
HSYNC) // already in horizontal sync
{
// start of horizontal sync
HSYNC = true;
HSC++;
}
else
{
// reset hsync counter
HSC = 0;
}
if (HSC == R3_HorizontalSyncWidth)
{
// end of horizontal sync
HSYNC = false;
}
/* Ver active video */
if (VCC == 0)
{
// active display
latch_vdisp = true;
}
if (VCC == R6_VerticalDisplayed)
{
// inactive display
latch_vdisp = false;
}
// vertical sync occurs at different times depending on the interlace field
// even field: the same time as HSYNC
// odd field: half a line later than HSYNC
if ((!_field && hssstart) || (_field && hhclock))
{
if ((VCC == R7_VerticalSyncPosition && VLC == 0) // vsync starts on the first line
|| VSYNC) // vsync is already in progress
{
// start of vertical sync
VSYNC = true;
// increment vertical sync counter
VSC++;
}
else
{
// reset vsync counter
VSC = 0;
}
if (VSYNC && VSC == R3_VerticalSyncWidth - 1)
{
// end of vertical sync
VSYNC = false;
}
}
/* Address Generation */
int line = VLC;
if (R8_Interlace == 3)
{
// interlace sync+video mode
// the least significant bit is based on the current field number
int fNum = _field ? 1 : 0;
int lNum = VLC.Bit(0) ? 1 : 0;
line &= ~1;
_RA = line & (fNum | lNum);
}
else
{
// raster address is just the VLC
_RA = VLC;
}
_LA = _vma;
// DISPTMG Generation
if (!latch_hdisp || !latch_vdisp)
{
// HSYNC output pin is fed through a NOR gate with either 2 or 3 inputs
// - H Display
// - V Display
// - TODO: R8 DISPTMG Skew (only on certain CRTC types)
DISPTMG = false;
}
else
{
DISPTMG = true;
}
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected override bool ReadRegister(ref int data)
{
// http://cpctech.cpc-live.com/docs/cpcplus.html
switch (AddressRegister & 0x6F)
{
case 0:
data = Register[R16_LIGHT_PEN_H] & 0x3F;
break;
case 1:
data = Register[R17_LIGHT_PEN_L];
break;
case 2:
// Status 1
break;
case 3:
// Status 2
break;
case 4:
data = Register[R12_START_ADDR_H] & 0x3F;
break;
case 5:
data = Register[R13_START_ADDR_L];
break;
case 6:
case 7:
data = 0;
break;
}
return true;
}
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected override void WriteRegister(int data)
{
byte v3 = (byte)data;
switch (AddressRegister)
{
case 16:
case 17:
// read only registers
return;
default:
if (AddressRegister < 16)
{
Register[AddressRegister] = v3;
}
else
{
// read only dummy registers
return;
}
break;
}
}
}
}

304
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.Type4.cs Normal file
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using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// TYPE 4
/// - Amstrad AMS40041
/// - Amstrad AMS40226
/// </summary>
public class CRTC_Type4 : CRTC
{
/// <summary>
/// Defined CRTC type number
/// </summary>
public override int CrtcType => 4;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public override void Clock()
{
base.Clock();
int maxScanLine;
if (HCC == R0_HorizontalTotal)
{
// end of displayable area reached
// set up for the next line
HCC = 0;
// TODO: handle interlace setup
if (R8_Interlace == 3)
{
// in interlace sync and video mask off bit 0 of the max scanline address
maxScanLine = R9_MaxScanline & 0b11110;
}
else
{
maxScanLine = R9_MaxScanline;
}
if (VLC == maxScanLine)
{
// we have reached the final scanline within this vertical character row
// move to next character
VLC = 0;
// TODO: implement vertical adjust
if (VCC == R4_VerticalTotal)
{
// check the interlace mode
if (R8_Interlace.Bit(0))
{
// toggle the field
_field = !_field;
}
else
{
// stay on the even field
_field = false;
}
// we have reached the end of the vertical display area
// address loaded from start address register at the top of each field
_vmaRowStart = (Register[R12_START_ADDR_H] << 8) | Register[R13_START_ADDR_L];
// reset the vertical character counter
VCC = 0;
// increment field counter
CFC++;
}
else
{
// row start address is increased by Horiztonal Displayed
_vmaRowStart += R1_HorizontalDisplayed;
// increment vertical character counter
VCC++;
}
}
else
{
// next scanline
if (R8_Interlace == 3)
{
// interlace sync+video mode
// vertical line counter increments by 2
VLC += 2;
// ensure vertical line counter is an even value
VLC &= ~1;
}
else
{
// non-interlace mode
// increment vertical line counter
VLC++;
}
}
// MA set to row start at the beginning of each line
_vma = _vmaRowStart;
}
else
{
// next horizontal character (1us)
// increment horizontal character counter
HCC++;
// increment VMA
_vma++;
}
hssstart = false;
hhclock = false;
if (HCC == R2_HorizontalSyncPosition)
{
// start of horizontal sync
hssstart = true;
}
if (HCC == R2_HorizontalSyncPosition / 2)
{
// we are half way through the line
hhclock = true;
}
/* Hor active video */
if (HCC == 0)
{
// active display
latch_hdisp = true;
}
if (HCC == R1_HorizontalDisplayed)
{
// inactive display
latch_hdisp = false;
}
/* Hor sync */
if (hssstart || // start of horizontal sync
HSYNC) // already in horizontal sync
{
// start of horizontal sync
HSYNC = true;
HSC++;
}
else
{
// reset hsync counter
HSC = 0;
}
if (HSC == R3_HorizontalSyncWidth)
{
// end of horizontal sync
HSYNC = false;
}
/* Ver active video */
if (VCC == 0)
{
// active display
latch_vdisp = true;
}
if (VCC == R6_VerticalDisplayed)
{
// inactive display
latch_vdisp = false;
}
// vertical sync occurs at different times depending on the interlace field
// even field: the same time as HSYNC
// odd field: half a line later than HSYNC
if ((!_field && hssstart) || (_field && hhclock))
{
if ((VCC == R7_VerticalSyncPosition && VLC == 0) // vsync starts on the first line
|| VSYNC) // vsync is already in progress
{
// start of vertical sync
VSYNC = true;
// increment vertical sync counter
VSC++;
}
else
{
// reset vsync counter
VSC = 0;
}
if (VSYNC && VSC == R3_VerticalSyncWidth - 1)
{
// end of vertical sync
VSYNC = false;
}
}
/* Address Generation */
int line = VLC;
if (R8_Interlace == 3)
{
// interlace sync+video mode
// the least significant bit is based on the current field number
int fNum = _field ? 1 : 0;
int lNum = VLC.Bit(0) ? 1 : 0;
line &= ~1;
_RA = line & (fNum | lNum);
}
else
{
// raster address is just the VLC
_RA = VLC;
}
_LA = _vma;
// DISPTMG Generation
if (!latch_hdisp || !latch_vdisp)
{
// HSYNC output pin is fed through a NOR gate with either 2 or 3 inputs
// - H Display
// - V Display
// - TODO: R8 DISPTMG Skew (only on certain CRTC types)
DISPTMG = false;
}
else
{
DISPTMG = true;
}
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected override bool ReadRegister(ref int data)
{
// http://cpctech.cpc-live.com/docs/cpcplus.html
switch (AddressRegister & 0x6F)
{
case 0:
data = Register[R16_LIGHT_PEN_H] & 0x3F;
break;
case 1:
data = Register[R17_LIGHT_PEN_L];
break;
case 2:
// Status 1
break;
case 3:
// Status 2
break;
case 4:
data = Register[R12_START_ADDR_H] & 0x3F;
break;
case 5:
data = Register[R13_START_ADDR_L];
break;
case 6:
case 7:
data = 0;
break;
}
return true;
}
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected override void WriteRegister(int data)
{
byte v3 = (byte)data;
switch (AddressRegister)
{
case 16:
case 17:
// read only registers
return;
default:
if (AddressRegister < 16)
{
Register[AddressRegister] = v3;
}
else
{
// read only dummy registers
return;
}
break;
}
}
}
}

880
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/CRTC.cs Normal file
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using BizHawk.Common;
using BizHawk.Common.NumberExtensions;
using System.Collections;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// CATHODE RAY TUBE CONTROLLER (CRTC) IMPLEMENTATION
/// http://www.cpcwiki.eu/index.php/CRTC
/// http://cpctech.cpc-live.com/docs/cpcplus.html
/// https://shaker.logonsystem.eu/
/// https://shaker.logonsystem.eu/ACCC1.8-EN.pdf
/// https://shaker.logonsystem.eu/tests
/// This implementation aims to emulate all the various CRTC chips that appear within
/// the CPC, CPC+ and GX4000 ranges. The CPC community have assigned them type numbers.
/// If different implementations share the same type number it indicates that they are functionally identical
///
/// Part No. Manufacturer Type No. Info.
/// ------------------------------------------------------------------------------------------------------
/// HD6845S Hitachi 0
/// Datasheet: http://www.cpcwiki.eu/imgs/c/c0/Hd6845.hitachi.pdf
/// ------------------------------------------------------------------------------------------------------
/// UM6845 UMC 0
/// Datasheet: http://www.cpcwiki.eu/imgs/1/13/Um6845.umc.pdf
/// ------------------------------------------------------------------------------------------------------
/// UM6845R UMC 1
/// Datasheet: http://www.cpcwiki.eu/imgs/b/b5/Um6845r.umc.pdf
/// ------------------------------------------------------------------------------------------------------
/// MC6845 Motorola 2
/// Datasheet: http://www.cpcwiki.eu/imgs/d/da/Mc6845.motorola.pdf &amp; http://bitsavers.trailing-edge.com/components/motorola/_dataSheets/6845.pdf
/// ------------------------------------------------------------------------------------------------------
/// AMS40489 Amstrad 3 Only exists in the CPC464+, CPC6128+ and GX4000 and is integrated into a single CPC+ ASIC chip (along with the gatearray)
/// Datasheet: {none}
/// ------------------------------------------------------------------------------------------------------
/// AMS40041 Amstrad 4 'Pre-ASIC' IC. The CRTC is integrated into a aingle ASIC IC with functionality being almost identical to the AMS40489
/// (or 40226) Used in the 'Cost-Down' range of CPC464 and CPC6128 systems
/// Datasheet: {none}
///
/// </summary>
public abstract partial class CRTC : IPortIODevice
{
/// <summary>
/// Instantiation helper
/// </summary>
public static CRTC Create(int crtcType)
{
return crtcType switch
{
0 => new CRTC_Type0(),
2 => new CRTC_Type2(),
3 => new CRTC_Type3(),
4 => new CRTC_Type4(),
_ => new CRTC_Type1(),
};
}
/// <summary>
/// Defined CRTC type number
/// </summary>
public virtual int CrtcType { get; }
/// <summary>
/// CPC register default values
/// </summary>
public byte[] RegDefaults = { 63, 40, 46, 142, 38, 0, 25, 30, 0, 7, 0, 0, 48, 0, 192, 7, 0, 0 };
/// <summary>
/// The ClK isaTTUMOS-compatible input used to synchronize all CRT' functions except for the processor interface.
/// An external dot counter is used to derive this signal which is usually the character rate in an alphanumeric CRT.
/// The active transition is high-to-low
/// </summary>
public bool CLK;
/// <summary>
/// This TTL compatible output is an active high signal which drives the monitor directly or is fed to Video Processing Logic for composite generation.
/// This signal determines the horizontal position of the displayed text.
/// </summary>
public virtual bool HSYNC
{
get => _HSYNC;
protected set
{
if (value != _HSYNC)
{
// value has changed
if (value) { HSYNC_On_Callbacks(); }
else { HSYNC_Off_Callbacks(); }
}
_HSYNC = value;
}
}
private bool _HSYNC;
/// <summary>
/// This TTL compatible output is an active high signal which drives the monitor directly or is fed to Video Processing Logic for composite generation.
/// This signal determines the vertical position of the displayed text.
/// </summary>
public virtual bool VSYNC
{
get => _VSYNC;
protected set
{
if (value != _VSYNC)
{
// value has changed
if (value) { VSYNC_On_Callbacks(); }
else { VSYNC_Off_Callbacks(); }
}
_VSYNC = value;
}
}
private bool _VSYNC;
/// <summary>
/// This TTL compatible output is an active high signal which indicates the CRTC is providing addressing in the active Display Area.
/// </summary>
public virtual bool DISPTMG
{
get => _DISPTMG;
protected set => _DISPTMG = value;
}
private bool _DISPTMG;
/// <summary>
/// This TTL compatible output indicates Cursor Display to external Video Processing Logic.Active high signal.
/// </summary>
public virtual bool CUDISP
{
get => _CUDISP;
protected set => _CUDISP = value;
}
private bool _CUDISP;
/// <summary>
/// Linear Address Generator
/// Character pos address (0 index).
/// Feeds the MA lines
/// </summary>
protected int _LA;
/// <summary>
/// Generated by the Vertical Control Raster Counter
/// Feeds the RA lines
/// </summary>
protected int _RA;
/// <summary>
/// This 16-bit property emulates how the Amstrad CPC Gate Array is wired up to the CRTC
/// Built from LA, RA and CLK
///
/// Memory Address Signal Signal source Signal name
/// A15 6845 MA13
/// A14 6845 MA12
/// A13 6845 RA2
/// A12 6845 RA1
/// A11 6845 RA0
/// A10 6845 MA9
/// A9 6845 MA8
/// A8 6845 MA7
/// A7 6845 MA6
/// A6 6845 MA5
/// A5 6845 MA4
/// A4 6845 MA3
/// A3 6845 MA2
/// A2 6845 MA1
/// A1 6845 MA0
/// A0 Gate-Array CLK
/// </summary>
public ushort MA_Address
{
get
{
var MA = new BitArray(16);
MA[0] = CLK;
MA[1] = _LA.Bit(0);
MA[2] = _LA.Bit(1);
MA[3] = _LA.Bit(2);
MA[4] = _LA.Bit(3);
MA[5] = _LA.Bit(4);
MA[6] = _LA.Bit(5);
MA[7] = _LA.Bit(6);
MA[8] = _LA.Bit(7);
MA[9] = _LA.Bit(8);
MA[10] = _LA.Bit(9);
MA[11] = _RA.Bit(0);
MA[12] = _RA.Bit(1);
MA[13] = _RA.Bit(2);
MA[14] = _LA.Bit(12);
MA[15] = _LA.Bit(13);
int[] array = new int[1];
MA.CopyTo(array, 0);
return (ushort)array[0];
}
}
/// <summary>
/// Public Delegate
/// </summary>
public delegate void CallBack();
/// <summary>
/// Fired on CRTC HSYNC signal rising edge
/// </summary>
protected CallBack HSYNC_On_Callbacks;
/// <summary>
/// Fired on CRTC HSYNC signal falling edge
/// </summary>
protected CallBack HSYNC_Off_Callbacks;
/// <summary>
/// Fired on CRTC VSYNC signal rising edge
/// </summary>
protected CallBack VSYNC_On_Callbacks;
/// <summary>
/// Fired on CRTC VSYNC signal falling edge
/// </summary>
protected CallBack VSYNC_Off_Callbacks;
public void AttachHSYNCOnCallback(CallBack hCall) => HSYNC_On_Callbacks += hCall;
public void AttachHSYNCOffCallback(CallBack hCall) => HSYNC_Off_Callbacks += hCall;
public void AttachVSYNCOnCallback(CallBack vCall) => VSYNC_On_Callbacks += vCall;
public void AttachVSYNCOffCallback(CallBack vCall) => VSYNC_Off_Callbacks += vCall;
/// <summary>
/// Reset Counter
/// </summary>
protected int _inReset;
/// <summary>
/// This is a 5 bit register which is used as a pointer to direct data transfers to and from the system MPU
/// </summary>
protected byte AddressRegister
{
get => (byte)(_addressRegister & 0b0001_1111);
set => _addressRegister = (byte)(value & 0b0001_1111);
}
private byte _addressRegister;
/// <summary>
/// This 8 bit write-only register determines the horizontal frequency of HS.
/// It is the total of displayed plus non-displayed character time units minus one.
/// </summary>
protected const int R0_H_TOTAL = 0;
/// <summary>
/// This 8 bit write-only register determines the number of displayed characters per horizontal line.
/// </summary>
protected const int R1_H_DISPLAYED = 1;
/// <summary>
/// This 8 bit write-only register determines the horizontal sync postiion on the horizontal line.
/// </summary>
protected const int R2_H_SYNC_POS = 2;
/// <summary>
/// This 4 bit write-only register determines the width of the HS pulse. It may not be apparent why this width needs to be programmed.However,
/// consider that all timing widths must be programmed as multiples of the character clock period which varies.If HS width were fixed as an integral
/// number of character times, it would vary with character rate and be out of tolerance for certain monitors.
/// The rate programmable feature allows compensating HS width.
/// NOTE: Dependent on chiptype this also may include VSYNC width - check the UpdateWidths() method
/// </summary>
protected const int R3_SYNC_WIDTHS = 3;
/* Vertical Timing Register Constants */
/// <summary>
/// The vertical frequency of VS is determined by both R4 and R5.The calculated number of character I ine times is usual I y an integer plus a fraction to
/// get exactly a 50 or 60Hz vertical refresh rate. The integer number of character line times minus one is programmed in the 7 bit write-only Vertical Total Register;
/// the fraction is programmed in the 5 bit write-only Vertical Scan Adjust Register as a number of scan line times.
/// </summary>
protected const int R4_V_TOTAL = 4;
protected const int R5_V_TOTAL_ADJUST = 5;
/// <summary>
/// This 7 bit write-only register determines the number of displayed character rows on the CRT screen, and is programmed in character row times.
/// </summary>
protected const int R6_V_DISPLAYED = 6;
/// <summary>
/// This 7 bit write-only register determines the vertical sync position with respect to the reference.It is programmed in character row times.
/// </summary>
protected const int R7_V_SYNC_POS = 7;
/// <summary>
/// This 2 bit write-only register controls the raster scan mode(see Figure 11 ). When bit 0 and bit 1 are reset, or bit 0 is reset and bit 1 set,
/// the non· interlace raster scan mode is selected.Two interlace modes are available.Both are interlaced 2 fields per frame.When bit 0 is set and bit 1 is reset,
/// the interlace sync raster scan mode is selected.Also when bit 0 and bit 1 are set, the interlace sync and video raster scan mode is selected.
/// </summary>
protected const int R8_INTERLACE_MODE = 8;
/// <summary>
/// This 5 bit write·only register determines the number of scan lines per character row including spacing.
/// The programmed value is a max address and is one less than the number of scan l1nes.
/// </summary>
protected const int R9_MAX_SL_ADDRESS = 9;
/// <summary>
/// This 7 bit write-only register controls the cursor format(see Figure 10). Bit 5 is the blink timing control.When bit 5 is low, the blink frequency is 1/16 of the
/// vertical field rate, and when bit 5 is high, the blink frequency is 1/32 of the vertical field rate.Bit 6 is used to enable a blink.
/// The cursor start scan line is set by the lower 5 bits.
/// </summary>
protected const int R10_CURSOR_START = 10;
/// <summary>
/// This 5 bit write-only register sets the cursor end scan line
/// </summary>
protected const int R11_CURSOR_END = 11;
/// <summary>
/// Start Address Register is a 14 bit write-only register which determines the first address put out as a refresh address after vertical blanking.
/// It consists of an 8 bit lower register, and a 6 bit higher register.
/// </summary>
protected const int R12_START_ADDR_H = 12;
protected const int R13_START_ADDR_L = 13;
/// <summary>
/// This 14 bit read/write register stores the cursor location.This register consists of an 8 bit lower and 6 bit higher register.
/// </summary>
protected const int R14_CURSOR_H = 14;
protected const int R15_CURSOR_L = 15;
/// <summary>
/// This 14 bit read -only register is used to store the contents of the Address Register(H &amp; L) when the LPSTB input pulses high.
/// This register consists of an 8 bit lower and 6 bit higher register.
/// </summary>
protected const int R16_LIGHT_PEN_H = 16;
protected const int R17_LIGHT_PEN_L = 17;
/// <summary>
/// Storage for main MPU registers
///
/// RegIdx Register Name Type
/// 0 1 2 3 4
/// 0 Horizontal Total Write Only Write Only Write Only (note 2) (note 3)
/// 1 Horizontal Displayed Write Only Write Only Write Only (note 2) (note 3)
/// 2 Horizontal Sync Position Write Only Write Only Write Only (note 2) (note 3)
/// 3 H and V Sync Widths Write Only Write Only Write Only (note 2) (note 3)
/// 4 Vertical Total Write Only Write Only Write Only (note 2) (note 3)
/// 5 Vertical Total Adjust Write Only Write Only Write Only (note 2) (note 3)
/// 6 Vertical Displayed Write Only Write Only Write Only (note 2) (note 3)
/// 7 Vertical Sync position Write Only Write Only Write Only (note 2) (note 3)
/// 8 Interlace and Skew Write Only Write Only Write Only (note 2) (note 3)
/// 9 Maximum Raster Address Write Only Write Only Write Only (note 2) (note 3)
/// 10 Cursor Start Raster Write Only Write Only Write Only (note 2) (note 3)
/// 11 Cursor End Raster Write Only Write Only Write Only (note 2) (note 3)
/// 12 Disp. Start Address (High) Read/Write Write Only Write Only Read/Write (note 2) (note 3)
/// 13 Disp. Start Address (Low) Read/Write Write Only Write Only Read/Write (note 2) (note 3)
/// 14 Cursor Address (High) Read/Write Read/Write Read/Write Read/Write (note 2) (note 3)
/// 15 Cursor Address (Low) Read/Write Read/Write Read/Write Read/Write (note 2) (note 3)
/// 16 Light Pen Address (High) Read Only Read Only Read Only Read Only (note 2) (note 3)
///
/// 18-31 Not Used
///
/// 1. On type 0 and 1, if a Write Only register is read from, "0" is returned.
/// 2. See the document "Extra CPC Plus Hardware Information" for more details.
/// 3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.
/// </summary>
protected byte[] Register = new byte[32];
/// <summary>
/// Internal Status Register specific to the Type 1 UM6845R
/// </summary>
protected byte StatusRegister;
/// <summary>
/// CRTC-type horizontal total independent helper function
/// </summary>
protected virtual int R0_HorizontalTotal
{
get
{
int ht = Register[R0_H_TOTAL];
return ht;
}
}
/// <summary>
/// CRTC-type horizontal displayed independent helper function
/// </summary>
protected virtual int R1_HorizontalDisplayed
{
get
{
int hd = Register[R1_H_DISPLAYED];
return hd;
}
}
/// <summary>
/// CRTC-type horizontal sync position independent helper function
/// </summary>
protected virtual int R2_HorizontalSyncPosition
{
get
{
int hsp = Register[R2_H_SYNC_POS];
return hsp;
}
}
/// <summary>
/// CRTC-type horizontal sync width independent helper function
/// </summary>
protected virtual int R3_HorizontalSyncWidth
{
get
{
int swr;
// Bits 3..0 define Horizontal Sync Width
int sw = Register[R3_SYNC_WIDTHS] & 0x0F;
switch (CrtcType)
{
case 0:
case 1:
// If 0 is programmed no HSYNC is generated
swr = sw;
break;
case 2:
case 3:
case 4:
default:
// If 0 is programmed this gives a HSYNC width of 16
swr = sw > 0 ? sw : 16;
break;
}
return swr;
}
}
/// <summary>
/// CRTC-type vertical sync width independent helper function
/// </summary>
protected virtual int R3_VerticalSyncWidth
{
get
{
int swr;
//Bits 7..4 define Vertical Sync Width
int sw = (Register[R3_SYNC_WIDTHS] >> 4) & 0x0F;
switch (CrtcType)
{
case 0:
case 3:
case 4:
default:
// If 0 is programmed this gives 16 lines of VSYNC
swr = sw > 0 ? sw : 16;
break;
case 1:
case 2:
// Vertical Sync is fixed at 16 lines
swr = 16;
break;
}
return swr;
}
}
/// <summary>
/// CRTC-type vertical total independent helper function
/// </summary>
protected virtual int R4_VerticalTotal
{
get
{
int vt = Register[R4_V_TOTAL];
return vt;
}
}
/// <summary>
/// CRTC-type vertical total adjust independent helper function
/// </summary>
protected virtual int R5_VerticalTotalAdjust
{
get
{
int vta = Register[R5_V_TOTAL_ADJUST];
return vta;
}
}
/// <summary>
/// CRTC-type vertical displayed independent helper function
/// </summary>
protected virtual int R6_VerticalDisplayed
{
get
{
int vd = Register[R6_V_DISPLAYED];
return vd;
}
}
/// <summary>
/// CRTC-type vertical sync position independent helper function
/// </summary>
protected virtual int R7_VerticalSyncPosition
{
get
{
int vsp = Register[R7_V_SYNC_POS];
return vsp;
}
}
/// <summary>
/// CRTC-type DISPTMG Active Display Skew helper function
/// </summary>
protected virtual int R8_Skew
{
get
{
int skew = 0;
switch (CrtcType)
{
case 0:
// For Hitachi HD6845:
// 0 = no skew
// 1 = one-character skew
// 2 = two-character skew
// 3 = non-output
skew = (Register[R8_INTERLACE_MODE] >> 4) & 0x03;
break;
case 1:
// skew not implemented
break;
case 2:
// skew not implemented
break;
default:
return skew;
}
return skew;
}
}
/// <summary>
/// CRTC-type Interlace Mode helper function
/// </summary>
protected virtual int R8_Interlace
{
get
{
int interlace = 0;
switch (CrtcType)
{
case 0:
case 1:
case 2:
// 0 = Non-interlace
// 1 = Interlace SYNC Raster Scan
// 2 = Interlace SYNC and Video Raster Scan
interlace = Register[R8_INTERLACE_MODE] & 0x03;
if (!interlace.Bit(0))
{
interlace = 0;
}
break;
default:
break;
}
return interlace;
}
}
/// <summary>
/// Max Scanlines
/// </summary>
protected virtual int R9_MaxScanline
{
get
{
int max = Register[R9_MAX_SL_ADDRESS];
return max;
}
}
/// <summary>
/// C0: Horizontal Character Counter
/// 8-bit
/// </summary>
protected virtual int HCC
{
get => _hcCTR & 0xFF;
set => _hcCTR = value & 0xFF;
}
private int _hcCTR;
/// <summary>
/// C3l: Horizontal Sync Width Counter (HSYNC)
/// 4-bit
/// </summary>
protected virtual int HSC
{
get => _hswCTR & 0x0F;
set => _hswCTR = value & 0x0F;
}
private int _hswCTR;
/// <summary>
/// C4: Vertical Character Row Counter
/// 7-bit
/// </summary>
protected virtual int VCC
{
get => _rowCTR & 0x7F;
set => _rowCTR = value & 0x7F;
}
private int _rowCTR;
/// <summary>
/// C3h: Vertical Sync Width Counter (VSYNC)
/// 4-bit
/// </summary>
protected virtual int VSC
{
get => _vswCTR & 0x0F;
set => _vswCTR = value & 0x0F;
}
private int _vswCTR;
/// <summary>
/// C9: Vertical Line Counter (Scanline Counter)
/// 5-bit
/// If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
/// </summary>
protected virtual int VLC
{
get => _lineCTR & 0x1F;
set => _lineCTR = value & 0x1F;
}
private int _lineCTR;
/// <summary>
/// C5: Vertical Total Adjust Counter
/// 5-bit??
/// This counter does not exist on CRTCs 0/3/4. C9 (VLC) is reused instead
/// </summary>
protected virtual int VTAC
{
get
{
switch (CrtcType)
{
case 0:
case 3:
case 4:
return VLC;
default:
return _vtacCTR & 0x1F;
}
}
set
{
switch (CrtcType)
{
case 0:
case 3:
case 4:
//VLC = value;
break;
default:
_vtacCTR = value & 0x1F;
break;
}
}
}
private int _vtacCTR;
/// <summary>
/// Field Counter
/// 6-bit
/// Used for cursor flash - counts the number of completed fields
/// </summary>
protected virtual int CFC
{
get => _fieldCTR & 0x1F;
set => _fieldCTR = value & 0x1F;
}
private int _fieldCTR;
/// <summary>
/// Constructor
/// </summary>
public CRTC()
{
//Reset();
}
// persistent control signals
protected bool latch_hsync;
protected bool latch_vadjust;
protected bool latch_skew;
private bool hend;
private bool hsend;
protected bool adjusting;
private bool hclock;
protected bool latch_hdisp;
protected bool latch_vdisp;
protected bool latch_idisp;
protected bool hssstart;
protected bool hhclock;
protected bool _field;
protected int _vma;
protected int _vmaRowStart;
/// <summary>
/// CRTC is clocked at 1MHz (16 GA cycles)
/// </summary>
public virtual void Clock()
{
if (_inReset > 0)
{
// reset takes a whole CRTC clock cycle
_inReset--;
HCC = 0;
HSC = 0;
VCC = 0;
VSC = 0;
VLC = 0;
VTAC = 0;
CFC = 0;
_field = false;
_vmaRowStart = 0;
_vma = 0;
_LA = 0;
_RA = 0;
latch_hdisp = false;
latch_vdisp = false;
latch_idisp = false;
/*
// set regs to default
for (int i = 0; i < 18; i++)
Register[i] = RegDefaults[i];
*/
// regs aren't touched
return;
}
else
_inReset = -1;
}
/// <summary>
/// Selects a specific register
/// </summary>
protected void SelectRegister(int value)
{
byte v = (byte)(value & 0x1F);
AddressRegister = v;
}
/// <summary>
/// Attempts to read from the currently selected register
/// </summary>
protected virtual bool ReadRegister(ref int data) => false;
/// <summary>
/// Attempts to write to the currently selected register
/// </summary>
protected virtual void WriteRegister(int data) {}
/// <summary>
/// Attempts to read from the internal status register (if present)
/// </summary>
protected virtual bool ReadStatus(ref int data) => false;
/// <summary>
/// Device responds to an IN instruction
/// </summary>
public virtual bool ReadPort(ushort port, ref int result)
{
byte portUpper = (byte)(port >> 8);
bool accessed = false;
// The 6845 is selected when bit 14 of the I/O port address is set to "0"
if (portUpper.Bit(6))
return accessed;
// Bit 9 and 8 of the I/O port address define the function to access
if (portUpper.Bit(1) && !portUpper.Bit(0))
{
// read status register
accessed = ReadStatus(ref result);
}
else if ((portUpper & 3) == 3)
{
// read data register
accessed = ReadRegister(ref result);
}
else
{
result = 0;
}
return accessed;
}
/// <summary>
/// Device responds to an OUT instruction
/// </summary>
public virtual bool WritePort(ushort port, int result)
{
byte portUpper = (byte)(port >> 8);
bool accessed = false;
// The 6845 is selected when bit 14 of the I/O port address is set to "0"
if (portUpper.Bit(6))
return accessed;
int func = portUpper & 3;
switch (func)
{
// reg select
case 0:
SelectRegister(result);
break;
// data write
case 1:
WriteRegister(result);
break;
}
return accessed;
}
/// <summary>
/// Simulates the RESET pin
/// This should take at least one cycle
/// </summary>
public void Reset() => _inReset = 1;
public void SyncState(Serializer ser)
{
ser.BeginSection("CRTC");
ser.Sync(nameof(CLK), ref CLK);
ser.Sync(nameof(_VSYNC), ref _VSYNC);
ser.Sync(nameof(_HSYNC), ref _HSYNC);
ser.Sync(nameof(_DISPTMG), ref _DISPTMG);
ser.Sync(nameof(_CUDISP), ref _CUDISP);
ser.Sync(nameof(_LA), ref _LA);
ser.Sync(nameof(_RA), ref _RA);
ser.Sync(nameof(_addressRegister), ref _addressRegister);
ser.Sync(nameof(Register), ref Register, false);
ser.Sync(nameof(StatusRegister), ref StatusRegister);
ser.Sync(nameof(_hcCTR), ref _hcCTR);
ser.Sync(nameof(_hswCTR), ref _hswCTR);
ser.Sync(nameof(_vswCTR), ref _vswCTR);
ser.Sync(nameof(_rowCTR), ref _rowCTR);
ser.Sync(nameof(_lineCTR), ref _lineCTR);
ser.Sync(nameof(_vtacCTR), ref _vtacCTR);
ser.Sync(nameof(_fieldCTR), ref _fieldCTR);
ser.Sync(nameof(latch_hdisp), ref latch_hdisp);
ser.Sync(nameof(latch_vdisp), ref latch_vdisp);
ser.Sync(nameof(latch_hsync), ref latch_hsync);
ser.Sync(nameof(latch_vadjust), ref latch_vadjust);
ser.Sync(nameof(latch_skew), ref latch_skew);
ser.Sync(nameof(_field), ref _field);
ser.Sync(nameof(adjusting), ref adjusting);
ser.Sync(nameof(_inReset), ref _inReset);
ser.Sync(nameof(hend), ref hend);
ser.Sync(nameof(hsend), ref hsend);
ser.Sync(nameof(hclock), ref hclock);
ser.Sync(nameof(latch_idisp), ref latch_idisp);
ser.Sync(nameof(hssstart), ref hssstart);
ser.Sync(nameof(hhclock), ref hhclock);
ser.Sync(nameof(_vma), ref _vma);
ser.Sync(nameof(_vmaRowStart), ref _vmaRowStart);
ser.EndSection();
}
}
}

112
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Datacorder/DatacorderDevice.cs
View File

@ -13,8 +13,8 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
public sealed class DatacorderDevice
{
private CPCBase _machine;
private Z80A<AmstradCPC.CpuLink> _cpu => _machine.CPU;
private IBeeperDevice _buzzer => _machine.TapeBuzzer;
private Z80A<AmstradCPC.CpuLink> CPU => _machine.CPU;
private IBeeperDevice Buzzer => _machine.TapeBuzzer;
/// <summary>
/// Default constructor
@ -27,10 +27,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// <summary>
/// Initializes the datacorder device
/// </summary>
public void Init(CPCBase machine)
{
_machine = machine;
}
public void Init(CPCBase machine) => _machine = machine;
/// <summary>
/// Signs whether the tape motor is running
@ -81,7 +78,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
get
{
if (_dataBlocks.Any())
if (DataBlocks.Any())
{
return _currentDataBlockIndex;
}
@ -91,7 +88,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
set
{
if (value == _currentDataBlockIndex) { return; }
if (value < _dataBlocks.Count && value >= 0)
if (value < DataBlocks.Count && value >= 0)
{
_currentDataBlockIndex = value;
_position = 0;
@ -103,7 +100,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// The current position within the current data block
/// </summary>
private int _position = 0;
public int Position => _position >= _dataBlocks[_currentDataBlockIndex].DataPeriods.Count ? 0 : _position;
public int Position => _position >= DataBlocks[_currentDataBlockIndex].DataPeriods.Count ? 0 : _position;
/// <summary>
/// Signs whether the tape is currently playing or not
@ -111,15 +108,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
private bool _tapeIsPlaying = false;
public bool TapeIsPlaying => _tapeIsPlaying;
/// <summary>
/// A list of the currently loaded data blocks
/// </summary>
private List<TapeDataBlock> _dataBlocks = new List<TapeDataBlock>();
public List<TapeDataBlock> DataBlocks
{
get => _dataBlocks;
set => _dataBlocks = value;
}
public List<TapeDataBlock> DataBlocks { get; set; } = new List<TapeDataBlock>();
/// <summary>
/// Stores the last CPU t-state value
@ -140,7 +129,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// Signs whether the device should autodetect when the Z80 has entered into
/// 'load' mode and auto-play the tape if neccesary
/// </summary>
private bool _autoPlay;
private readonly bool _autoPlay;
/// <summary>
/// Should be fired at the end of every frame
@ -170,29 +159,29 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
_machine.CPC.OSD_TapeMotorActive();
// update the lastCycle
_lastCycle = _cpu.TotalExecutedCycles;
_lastCycle = CPU.TotalExecutedCycles;
// reset waitEdge and position
_waitEdge = 0;
_position = 0;
if (_dataBlocks.Count > 0 && _currentDataBlockIndex >= 0) //TODO removed a comment that said "index is 1 or greater", but code is clearly "0 or greater"--which is correct? --yoshi
if (DataBlocks.Count > 0 && _currentDataBlockIndex >= 0) //TODO removed a comment that said "index is 1 or greater", but code is clearly "0 or greater"--which is correct? --yoshi
{
while (_position >= _dataBlocks[_currentDataBlockIndex].DataPeriods.Count)
while (_position >= DataBlocks[_currentDataBlockIndex].DataPeriods.Count)
{
// we are at the end of a data block - move to the next
_position = 0;
_currentDataBlockIndex++;
// are we at the end of the tape?
if (_currentDataBlockIndex >= _dataBlocks.Count)
if (_currentDataBlockIndex >= DataBlocks.Count)
{
break;
}
}
// check for end of tape
if (_currentDataBlockIndex >= _dataBlocks.Count)
if (_currentDataBlockIndex >= DataBlocks.Count)
{
// end of tape reached. Rewind to beginning
AutoStopTape();
@ -201,7 +190,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
// update waitEdge with the current position in the current block
_waitEdge = _dataBlocks[_currentDataBlockIndex].DataPeriods[_position];
_waitEdge = DataBlocks[_currentDataBlockIndex].DataPeriods[_position];
// sign that the tape is now playing
_tapeIsPlaying = true;
@ -223,12 +212,12 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
_tapeIsPlaying = false;
if (_currentDataBlockIndex >= 0 // we are at datablock 1 or above //TODO 1-indexed then? --yoshi
&& _position >= _dataBlocks[_currentDataBlockIndex].DataPeriods.Count - 1) // the block is still playing back
&& _position >= DataBlocks[_currentDataBlockIndex].DataPeriods.Count - 1) // the block is still playing back
{
// move to the next block
_currentDataBlockIndex++;
if (_currentDataBlockIndex >= _dataBlocks.Count)
if (_currentDataBlockIndex >= DataBlocks.Count)
{
_currentDataBlockIndex = -1;
}
@ -237,7 +226,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
_waitEdge = 0;
_position = 0;
if (_currentDataBlockIndex < 0 && _dataBlocks.Count > 0) //TODO deleted a comment that said "block index is -1", but code is clearly "is negative"--are lower values not reachable? --yoshi
if (_currentDataBlockIndex < 0 && DataBlocks.Count > 0) //TODO deleted a comment that said "block index is -1", but code is clearly "is negative"--are lower values not reachable? --yoshi
{
// move the index on to 0
_currentDataBlockIndex = 0;
@ -245,7 +234,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
// update the lastCycle
_lastCycle = _cpu.TotalExecutedCycles;
_lastCycle = CPU.TotalExecutedCycles;
}
/// <summary>
@ -265,7 +254,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public void SkipBlock(bool skipForward)
{
int blockCount = _dataBlocks.Count;
int blockCount = DataBlocks.Count;
int targetBlockId = _currentDataBlockIndex;
if (skipForward)
@ -293,11 +282,11 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
}
var bl = _dataBlocks[targetBlockId];
var bl = DataBlocks[targetBlockId];
StringBuilder sbd = new StringBuilder();
var sbd = new StringBuilder();
sbd.Append('(');
sbd.Append((targetBlockId + 1) + " of " + _dataBlocks.Count);
sbd.Append((targetBlockId + 1) + " of " + DataBlocks.Count);
sbd.Append(") : ");
//sbd.Append("ID" + bl.BlockID.ToString("X2") + " - ");
sbd.Append(bl.BlockDescription);
@ -323,7 +312,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
public void LoadTape(byte[] tapeData)
{
// instantiate converters
CdtConverter cdtSer = new CdtConverter(this);
var cdtSer = new CdtConverter(this);
// CDT
if (cdtSer.CheckType(tapeData))
@ -347,10 +336,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// <summary>
/// Resets the tape
/// </summary>
public void Reset()
{
RTZ();
}
public void Reset() => RTZ();
/// <summary>
/// Is called every cpu cycle but runs every 50 t-states
@ -367,7 +353,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
counter = 0;
bool state = GetEarBit(_machine.CPU.TotalExecutedCycles);
_buzzer.ProcessPulseValue(state);
Buzzer.ProcessPulseValue(state);
}
}
}
@ -377,6 +363,12 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public bool GetEarBit(long cpuCycle)
{
if (DataBlocks.Count == 0)
{
// no tape loaded
return false;
}
// decide how many cycles worth of data we are capturing
long cycles = cpuCycle - _lastCycle;
@ -400,12 +392,12 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
while (cycles >= _waitEdge)
{
// decrement cycles
cycles -= _waitEdge;
cycles -= _waitEdge;
if (_position == 0 && tapeMotor)
{
// start of block - take care of initial pulse level for PZX
switch (_dataBlocks[_currentDataBlockIndex].BlockDescription)
switch (DataBlocks[_currentDataBlockIndex].BlockDescription)
{
case BlockType.PULS:
// initial pulse level is always low
@ -414,19 +406,19 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
break;
case BlockType.DATA:
// initial pulse level is stored in block
if (currentState != _dataBlocks[_currentDataBlockIndex].InitialPulseLevel)
if (currentState != DataBlocks[_currentDataBlockIndex].InitialPulseLevel)
FlipTapeState();
break;
case BlockType.PAUS:
// initial pulse level is stored in block
if (currentState != _dataBlocks[_currentDataBlockIndex].InitialPulseLevel)
if (currentState != DataBlocks[_currentDataBlockIndex].InitialPulseLevel)
FlipTapeState();
break;
}
// most of these amstrad tapes appear to have a pause block at the start
// skip this if it is the first block
switch (_dataBlocks[_currentDataBlockIndex].BlockDescription)
switch (DataBlocks[_currentDataBlockIndex].BlockDescription)
{
case BlockType.PAUS:
case BlockType.PAUSE_BLOCK:
@ -442,7 +434,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
bool okToSkipPause = true;
for (int i = _currentDataBlockIndex; i >= 0; i--)
{
switch (_dataBlocks[i].BlockDescription)
switch (DataBlocks[i].BlockDescription)
{
case BlockType.Archive_Info:
case BlockType.BRWS:
@ -472,11 +464,11 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
// notify about the current block
var bl = _dataBlocks[_currentDataBlockIndex];
var bl = DataBlocks[_currentDataBlockIndex];
StringBuilder sbd = new StringBuilder();
var sbd = new StringBuilder();
sbd.Append('(');
sbd.Append((_currentDataBlockIndex + 1) + " of " + _dataBlocks.Count);
sbd.Append((_currentDataBlockIndex + 1) + " of " + DataBlocks.Count);
sbd.Append(") : ");
//sbd.Append("ID" + bl.BlockID.ToString("X2") + " - ");
sbd.Append(bl.BlockDescription);
@ -492,17 +484,17 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
// increment the current period position
_position++;
if (_position >= _dataBlocks[_currentDataBlockIndex].DataPeriods.Count)
if (_position >= DataBlocks[_currentDataBlockIndex].DataPeriods.Count)
{
// we have reached the end of the current block
if (_dataBlocks[_currentDataBlockIndex].DataPeriods.Count == 0)
if (DataBlocks[_currentDataBlockIndex].DataPeriods.Count == 0)
{
// notify about the current block (we are skipping it because its empty)
var bl = _dataBlocks[_currentDataBlockIndex];
StringBuilder sbd = new StringBuilder();
var bl = DataBlocks[_currentDataBlockIndex];
var sbd = new StringBuilder();
sbd.Append('(');
sbd.Append((_currentDataBlockIndex + 1) + " of " + _dataBlocks.Count);
sbd.Append((_currentDataBlockIndex + 1) + " of " + DataBlocks.Count);
sbd.Append(") : ");
//sbd.Append("ID" + bl.BlockID.ToString("X2") + " - ");
sbd.Append(bl.BlockDescription);
@ -516,11 +508,11 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
// skip any empty blocks (and process any command blocks)
while (_position >= _dataBlocks[_currentDataBlockIndex].DataPeriods.Count)
while (_position >= DataBlocks[_currentDataBlockIndex].DataPeriods.Count)
{
// check for any commands
var command = _dataBlocks[_currentDataBlockIndex].Command;
var block = _dataBlocks[_currentDataBlockIndex];
var command = DataBlocks[_currentDataBlockIndex].Command;
var block = DataBlocks[_currentDataBlockIndex];
bool shouldStop = false;
switch (command)
{
@ -573,14 +565,14 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
_position = 0;
_currentDataBlockIndex++;
if (_currentDataBlockIndex >= _dataBlocks.Count)
if (_currentDataBlockIndex >= DataBlocks.Count)
{
break;
}
}
// check for end of tape
if (_currentDataBlockIndex >= _dataBlocks.Count)
if (_currentDataBlockIndex >= DataBlocks.Count)
{
_currentDataBlockIndex = -1;
RTZ();
@ -589,7 +581,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
}
// update waitEdge with current position within the current block
_waitEdge = _dataBlocks[_currentDataBlockIndex].DataPeriods[_position];
_waitEdge = DataBlocks[_currentDataBlockIndex].DataPeriods[_position];
// flip the current state
FlipTapeState();
@ -720,7 +712,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
if (TapeIsPlaying)
{
GetEarBit(_cpu.TotalExecutedCycles);
GetEarBit(CPU.TotalExecutedCycles);
}
/*
if (currentState)

1323
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Display/AmstradGateArray.cs
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1100
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Display/CRCT_6845.cs
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2278
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Display/CRTC6845.cs
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637
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Display/CRTDevice.cs
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@ -1,637 +0,0 @@
using BizHawk.Common;
using BizHawk.Common.NumberExtensions;
using BizHawk.Emulation.Common;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// Render pixels to the screen
/// </summary>
public class CRTDevice : IVideoProvider
{
private readonly CPCBase _machine;
private CRCT_6845 CRCT => _machine.CRCT;
private AmstradGateArray GateArray => _machine.GateArray;
public CRTDevice(CPCBase machine)
{
_machine = machine;
CurrentLine = new ScanLine(this);
CRCT.AttachHSYNCCallback(OnHSYNC);
CRCT.AttachVSYNCCallback(OnVSYNC);
}
/// <summary>
/// The standard CPC Pallete (ordered by firmware #)
/// http://www.cpcwiki.eu/index.php/CPC_Palette
/// </summary>
public static readonly int[] CPCFirmwarePalette =
{
Colors.ARGB(0x00, 0x00, 0x00), // Black
Colors.ARGB(0x00, 0x00, 0x80), // Blue
Colors.ARGB(0x00, 0x00, 0xFF), // Bright Blue
Colors.ARGB(0x80, 0x00, 0x00), // Red
Colors.ARGB(0x80, 0x00, 0x80), // Magenta
Colors.ARGB(0x80, 0x00, 0xFF), // Mauve
Colors.ARGB(0xFF, 0x00, 0x00), // Bright Red
Colors.ARGB(0xFF, 0x00, 0x80), // Purple
Colors.ARGB(0xFF, 0x00, 0xFF), // Bright Magenta
Colors.ARGB(0x00, 0x80, 0x00), // Green
Colors.ARGB(0x00, 0x80, 0x80), // Cyan
Colors.ARGB(0x00, 0x80, 0xFF), // Sky Blue
Colors.ARGB(0x80, 0x80, 0x00), // Yellow
Colors.ARGB(0x80, 0x80, 0x80), // White
Colors.ARGB(0x80, 0x80, 0xFF), // Pastel Blue
Colors.ARGB(0xFF, 0x80, 0x00), // Orange
Colors.ARGB(0xFF, 0x80, 0x80), // Pink
Colors.ARGB(0xFF, 0x80, 0xFF), // Pastel Magenta
Colors.ARGB(0x00, 0xFF, 0x00), // Bright Green
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green
Colors.ARGB(0x00, 0xFF, 0xFF), // Bright Cyan
Colors.ARGB(0x80, 0xFF, 0x00), // Lime
Colors.ARGB(0x80, 0xFF, 0x80), // Pastel Green
Colors.ARGB(0x80, 0xFF, 0xFF), // Pastel Cyan
Colors.ARGB(0xFF, 0xFF, 0x00), // Bright Yellow
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow
Colors.ARGB(0xFF, 0xFF, 0xFF), // Bright White
};
/// <summary>
/// The standard CPC Pallete (ordered by hardware #)
/// http://www.cpcwiki.eu/index.php/CPC_Palette
/// </summary>
public static readonly int[] CPCHardwarePalette =
{
Colors.ARGB(0x80, 0x80, 0x80), // White
Colors.ARGB(0x80, 0x80, 0x80), // White (duplicate)
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow
Colors.ARGB(0x00, 0x00, 0x80), // Blue
Colors.ARGB(0xFF, 0x00, 0x80), // Purple
Colors.ARGB(0x00, 0x80, 0x80), // Cyan
Colors.ARGB(0xFF, 0x80, 0x80), // Pink
Colors.ARGB(0xFF, 0x00, 0x80), // Purple (duplicate)
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow (duplicate)
Colors.ARGB(0xFF, 0xFF, 0x00), // Bright Yellow
Colors.ARGB(0xFF, 0xFF, 0xFF), // Bright White
Colors.ARGB(0xFF, 0x00, 0x00), // Bright Red
Colors.ARGB(0xFF, 0x00, 0xFF), // Bright Magenta
Colors.ARGB(0xFF, 0x80, 0x00), // Orange
Colors.ARGB(0xFF, 0x80, 0xFF), // Pastel Magenta
Colors.ARGB(0x00, 0x00, 0x80), // Blue (duplicate)
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green (duplicate)
Colors.ARGB(0x00, 0xFF, 0x00), // Bright Green
Colors.ARGB(0x00, 0xFF, 0xFF), // Bright Cyan
Colors.ARGB(0x00, 0x00, 0x00), // Black
Colors.ARGB(0x00, 0x00, 0xFF), // Bright Blue
Colors.ARGB(0x00, 0x80, 0x00), // Green
Colors.ARGB(0x00, 0x80, 0xFF), // Sky Blue
Colors.ARGB(0x80, 0x00, 0x80), // Magenta
Colors.ARGB(0x80, 0xFF, 0x80), // Pastel Green
Colors.ARGB(0x80, 0xFF, 0x00), // Lime
Colors.ARGB(0x80, 0xFF, 0xFF), // Pastel Cyan
Colors.ARGB(0x80, 0x00, 0x00), // Red
Colors.ARGB(0x80, 0x00, 0xFF), // Mauve
Colors.ARGB(0x80, 0x80, 0x00), // Yellow
Colors.ARGB(0x80, 0x80, 0xFF), // Pastel Blue
};
/// <summary>
/// The current scanline that is being added to
/// (will be processed and committed to the screen buffer every HSYNC)
/// </summary>
public ScanLine CurrentLine;
/// <summary>
/// The number of top border scanlines to ommit when rendering
/// </summary>
public int TopLinesToTrim = 20;
/// <summary>
/// Count of rendered scanlines this frame
/// </summary>
public int ScanlineCounter = 0;
/// <summary>
/// Video buffer processing
/// </summary>
public int[] ProcessVideoBuffer()
{
return ScreenBuffer;
}
/// <summary>
/// Sets up buffers and the like at the start of a frame
/// </summary>
public void SetupVideo()
{
if (BufferHeight == 576)
return;
BufferWidth = 800;
BufferHeight = 576;
VirtualWidth = BufferWidth / 2;
VirtualHeight = BufferHeight / 2;
ScreenBuffer = new int[BufferWidth * BufferHeight];
}
/// <summary>
/// Fired when the CRCT flags HSYNC
/// </summary>
public void OnHSYNC()
{
}
/// <summary>
/// Fired when the CRCT flags VSYNC
/// </summary>
public void OnVSYNC()
{
}
/// <summary>
/// Video output buffer
/// </summary>
public int[] ScreenBuffer;
private int _virtualWidth;
private int _virtualHeight;
private int _bufferWidth;
private int _bufferHeight;
public int BackgroundColor => CPCHardwarePalette[0];
public int VirtualWidth
{
get => _virtualWidth;
set => _virtualWidth = value;
}
public int VirtualHeight
{
get => _virtualHeight;
set => _virtualHeight = value;
}
public int BufferWidth
{
get => _bufferWidth;
set => _bufferWidth = value;
}
public int BufferHeight
{
get => _bufferHeight;
set => _bufferHeight = value;
}
public int VsyncNumerator
{
get => GateArray.Z80ClockSpeed * 50;
set { }
}
public int VsyncDenominator => GateArray.Z80ClockSpeed;
public int[] GetVideoBuffer() => ProcessVideoBuffer()!;
public void SetupScreenSize()
{
BufferWidth = 1024; // 512;
BufferHeight = 768;
VirtualHeight = BufferHeight;
VirtualWidth = BufferWidth;
ScreenBuffer = new int[BufferWidth * BufferHeight];
croppedBuffer = ScreenBuffer;
}
protected int[] croppedBuffer;
public void SyncState(Serializer ser)
{
ser.BeginSection("CRT");
ser.Sync("BufferWidth", ref _bufferWidth);
ser.Sync("BufferHeight", ref _bufferHeight);
ser.Sync("VirtualHeight", ref _virtualHeight);
ser.Sync("VirtualWidth", ref _virtualWidth);
ser.Sync(nameof(ScreenBuffer), ref ScreenBuffer, false);
ser.Sync(nameof(ScanlineCounter), ref ScanlineCounter);
ser.EndSection();
}
}
/// <summary>
/// Represents a single scanline buffer
/// </summary>
public class ScanLine
{
/// <summary>
/// Array of character information
/// </summary>
public Character[] Characters;
/// <summary>
/// The screenmode that was set at the start of this scanline
/// </summary>
public int ScreenMode = 1;
/// <summary>
/// The scanline number (0 based)
/// </summary>
public int LineIndex;
/// <summary>
/// The calling CRT device
/// </summary>
private readonly CRTDevice CRT;
public ScanLine(CRTDevice crt)
{
Reset();
CRT = crt;
}
// To be run after scanline has been fully processed
public void InitScanline(int screenMode, int lineIndex)
{
Reset();
ScreenMode = screenMode;
LineIndex = lineIndex;
}
/// <summary>
/// Adds a single scanline character into the matrix
/// </summary>
public void AddScanlineCharacter(int index, RenderPhase phase, byte vid1, byte vid2, int[] pens)
{
if (index >= 64)
{
return;
}
switch (phase)
{
case RenderPhase.BORDER:
AddBorderValue(index, CRTDevice.CPCHardwarePalette[pens[16]]);
break;
case RenderPhase.DISPLAY:
AddDisplayValue(index, vid1, vid2, pens);
break;
default:
AddSyncValue(index, phase);
break;
}
}
/// <summary>
/// Adds a HSYNC, VSYNC or HSYNC+VSYNC character into the scanline
/// </summary>
private void AddSyncValue(int charIndex, RenderPhase phase)
{
Characters[charIndex].Phase = phase;
Characters[charIndex].Pixels = new int[0];
}
/// <summary>
/// Adds a border character into the scanline
/// </summary>
private void AddBorderValue(int charIndex, int colourValue)
{
Characters[charIndex].Phase = RenderPhase.BORDER;
switch (ScreenMode)
{
case 0:
Characters[charIndex].Pixels = new int[4];
break;
case 1:
Characters[charIndex].Pixels = new int[8];
break;
case 2:
Characters[charIndex].Pixels = new int[16];
break;
case 3:
Characters[charIndex].Pixels = new int[8];
break;
}
for (int i = 0; i < Characters[charIndex].Pixels.Length; i++)
{
Characters[charIndex].Pixels[i] = colourValue;
}
}
/// <summary>
/// Adds a display character into the scanline
/// Pixel matrix is calculated based on the current ScreenMode
/// </summary>
public void AddDisplayValue(int charIndex, byte vid1, byte vid2, int[] pens)
{
Characters[charIndex].Phase = RenderPhase.DISPLAY;
// generate pixels based on screen mode
switch (ScreenMode)
{
// 4 bits per pixel - 2 bytes - 4 pixels (8 CRT pixels)
// RECT
case 0:
Characters[charIndex].Pixels = new int[16];
int m0Count = 0;
int pix = vid1 & 0xaa;
pix = ((pix & 0x80) >> 7) | ((pix & 0x08) >> 2) | ((pix & 0x20) >> 3) | ((pix & 0x02 << 2));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
pix = vid1 & 0x55;
pix = (((pix & 0x40) >> 6) | ((pix & 0x04) >> 1) | ((pix & 0x10) >> 2) | ((pix & 0x01 << 3)));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
pix = vid2 & 0xaa;
pix = ((pix & 0x80) >> 7) | ((pix & 0x08) >> 2) | ((pix & 0x20) >> 3) | ((pix & 0x02 << 2));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
pix = vid2 & 0x55;
pix = (((pix & 0x40) >> 6) | ((pix & 0x04) >> 1) | ((pix & 0x10) >> 2) | ((pix & 0x01 << 3)));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[pix]];
/*
int m0B0P0i = vid1 & 0xaa;
int m0B0P0 = ((m0B0P0i & 0x80) >> 7) | ((m0B0P0i & 0x08) >> 2) | ((m0B0P0i & 0x20) >> 3) | ((m0B0P0i & 0x02 << 2));
int m0B0P1i = vid1 & 85;
int m0B0P1 = ((m0B0P1i & 0x40) >> 6) | ((m0B0P1i & 0x04) >> 1) | ((m0B0P1i & 0x10) >> 2) | ((m0B0P1i & 0x01 << 3));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B0P0]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B0P0]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B0P1]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B0P1]];
int m0B1P0i = vid2 & 170;
int m0B1P0 = ((m0B1P0i & 0x80) >> 7) | ((m0B1P0i & 0x08) >> 2) | ((m0B1P0i & 0x20) >> 3) | ((m0B1P0i & 0x02 << 2));
int m0B1P1i = vid2 & 85;
int m0B1P1 = ((m0B1P1i & 0x40) >> 6) | ((m0B1P1i & 0x04) >> 1) | ((m0B1P1i & 0x10) >> 2) | ((m0B1P1i & 0x01 << 3));
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B1P0]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B1P0]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B1P1]];
Characters[charIndex].Pixels[m0Count++] = CRTDevice.CPCHardwarePalette[pens[m0B1P1]];
*/
break;
// 2 bits per pixel - 2 bytes - 8 pixels (16 CRT pixels)
// SQUARE
case 1:
Characters[charIndex].Pixels = new int[8];
int m1Count = 0;
int m1B0P0 = (((vid1 & 0x80) >> 7) | ((vid1 & 0x08) >> 2));
int m1B0P1 = (((vid1 & 0x40) >> 6) | ((vid1 & 0x04) >> 1));
int m1B0P2 = (((vid1 & 0x20) >> 5) | ((vid1 & 0x02)));
int m1B0P3 = (((vid1 & 0x10) >> 4) | ((vid1 & 0x01) << 1));
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B0P0]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B0P1]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B0P2]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B0P3]];
int m1B1P0 = (((vid2 & 0x80) >> 7) | ((vid2 & 0x08) >> 2));
int m1B1P1 = (((vid2 & 0x40) >> 6) | ((vid2 & 0x04) >> 1));
int m1B1P2 = (((vid2 & 0x20) >> 5) | ((vid2 & 0x02)));
int m1B1P3 = (((vid2 & 0x10) >> 4) | ((vid2 & 0x01) << 1));
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B1P0]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B1P1]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B1P2]];
Characters[charIndex].Pixels[m1Count++] = CRTDevice.CPCHardwarePalette[pens[m1B1P3]];
break;
// 1 bit per pixel - 2 bytes - 16 pixels (16 CRT pixels)
// RECT
case 2:
Characters[charIndex].Pixels = new int[16];
int m2Count = 0;
int[] pixBuff = new int[16];
for (int bit = 7; bit >= 0; bit--)
{
int val = vid1.Bit(bit) ? 1 : 0;
Characters[charIndex].Pixels[m2Count++] = CRTDevice.CPCHardwarePalette[pens[val]];
}
for (int bit = 7; bit >= 0; bit--)
{
int val = vid2.Bit(bit) ? 1 : 0;
Characters[charIndex].Pixels[m2Count++] = CRTDevice.CPCHardwarePalette[pens[val]];
}
break;
// 4 bits per pixel - 2 bytes - 4 pixels (8 CRT pixels)
// RECT
case 3:
Characters[charIndex].Pixels = new int[4];
int m3Count = 0;
int m3B0P0i = vid1 & 170;
int m3B0P0 = ((m3B0P0i & 0x80) >> 7) | ((m3B0P0i & 0x08) >> 2) | ((m3B0P0i & 0x20) >> 3) | ((m3B0P0i & 0x02 << 2));
int m3B0P1i = vid1 & 85;
int m3B0P1 = ((m3B0P1i & 0x40) >> 6) | ((m3B0P1i & 0x04) >> 1) | ((m3B0P1i & 0x10) >> 2) | ((m3B0P1i & 0x01 << 3));
Characters[charIndex].Pixels[m3Count++] = CRTDevice.CPCHardwarePalette[pens[m3B0P0]];
Characters[charIndex].Pixels[m3Count++] = CRTDevice.CPCHardwarePalette[pens[m3B0P1]];
int m3B1P0i = vid1 & 170;
int m3B1P0 = ((m3B1P0i & 0x80) >> 7) | ((m3B1P0i & 0x08) >> 2) | ((m3B1P0i & 0x20) >> 3) | ((m3B1P0i & 0x02 << 2));
int m3B1P1i = vid1 & 85;
int m3B1P1 = ((m3B1P1i & 0x40) >> 6) | ((m3B1P1i & 0x04) >> 1) | ((m3B1P1i & 0x10) >> 2) | ((m3B1P1i & 0x01 << 3));
Characters[charIndex].Pixels[m3Count++] = CRTDevice.CPCHardwarePalette[pens[m3B1P0]];
Characters[charIndex].Pixels[m3Count++] = CRTDevice.CPCHardwarePalette[pens[m3B1P1]];
break;
}
}
/// <summary>
/// Returns the number of pixels decoded in this scanline (border and display)
/// </summary>
private int GetPixelCount()
{
int cnt = 0;
foreach (var c in Characters)
{
if (c.Pixels != null)
cnt += c.Pixels.Length;
}
return cnt;
}
/// <summary>
/// Called at the start of HSYNC
/// Processes and adds the scanline to the Screen Buffer
/// </summary>
public void CommitScanline()
{
int hScale = 1;
int vScale = 1;
switch (ScreenMode)
{
case 0:
hScale = 1;
vScale = 2;
break;
case 1:
case 3:
hScale = 2;
vScale = 2;
break;
case 2:
hScale = 1;
vScale = 2;
break;
}
int hPix = GetPixelCount() * hScale;
//int hPix = GetPixelCount() * 2;
int leftOver = CRT.BufferWidth - hPix;
int lPad = leftOver / 2;
int rPad = lPad;
int rem = leftOver % 2;
if (rem != 0)
rPad += rem;
if (LineIndex < CRT.TopLinesToTrim)
{
return;
}
// render out the scanline
int pCount = (LineIndex - CRT.TopLinesToTrim) * vScale * CRT.BufferWidth;
// vScale
for (int s = 0; s < vScale; s++)
{
// left padding
for (int lP = 0; lP < lPad; lP++)
{
CRT.ScreenBuffer[pCount++] = 0;
}
// border and display
foreach (var c in Characters)
{
if (c.Pixels == null || c.Pixels.Length == 0)
continue;
for (int p = 0; p < c.Pixels.Length; p++)
{
// hScale
for (int h = 0; h < hScale; h++)
{
CRT.ScreenBuffer[pCount++] = c.Pixels[p];
}
//CRT.ScreenBuffer[pCount++] = c.Pixels[p];
}
}
// right padding
for (int rP = 0; rP < rPad; rP++)
{
CRT.ScreenBuffer[pCount++] = 0;
}
if (pCount != hPix)
{
}
CRT.ScanlineCounter++;
}
}
public void Reset()
{
ScreenMode = 1;
Characters = new Character[64];
for (int i = 0; i < Characters.Length; i++)
{
Characters[i] = new Character();
}
}
}
/// <summary>
/// Contains data relating to one character written on one scanline
/// </summary>
public class Character
{
/// <summary>
/// Array of pixels generated for this character
/// </summary>
public int[] Pixels;
/// <summary>
/// The type (NONE/BORDER/DISPLAY/HSYNC/VSYNC/HSYNC+VSYNC
/// </summary>
public RenderPhase Phase = RenderPhase.NONE;
public Character()
{
Pixels = new int[0];
}
}
[Flags]
public enum RenderPhase : int
{
/// <summary>
/// Nothing
/// </summary>
NONE = 0,
/// <summary>
/// Border is being rendered
/// </summary>
BORDER = 1,
/// <summary>
/// Display rendered from video RAM
/// </summary>
DISPLAY = 2,
/// <summary>
/// HSYNC in progress
/// </summary>
HSYNC = 3,
/// <summary>
/// VSYNC in process
/// </summary>
VSYNC = 4,
/// <summary>
/// HSYNC occurs within a VSYNC
/// </summary>
HSYNCandVSYNC = 5
}
}

1168
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/GateArray.cs Normal file
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File diff suppressed because it is too large Load Diff

72
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/PAL16L8.cs Normal file
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@ -0,0 +1,72 @@
using BizHawk.Common;
using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// Programmable Array Logic (PAL) device
/// The C6128's second page of 64KB of RAM is controlled by this chip
/// </summary>
public class PAL16L8 : IPortIODevice
{
private readonly CPCBase _machine;
/// <summary>
/// PAL MMR Register
/// This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with Standard Memory Expansions)
/// Note: In the CPC 6128, the register is a separate PAL that assists the Gate Array chip
///
/// Bit Value Function
/// 7 1 MMR register enable
/// 6 1 MMR register enable
/// 5 b 64K bank number(0..7); always 0 on an unexpanded CPC6128, 0-7 on Standard Memory Expansions
/// 4 b
/// 3 b
/// 2 x RAM Config(0..7)
/// 1 x ""
/// 0 x ""
///
/// The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions.
/// These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the
/// first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:
///
/// -Address- 0 1 2 3 4 5 6 7
/// 0000-3FFF RAM_0 RAM_0 RAM_4 RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
/// 4000-7FFF RAM_1 RAM_1 RAM_5 RAM_3 RAM_4 RAM_5 RAM_6 RAM_7
/// 8000-BFFF RAM_2 RAM_2 RAM_6 RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
/// C000-FFFF RAM_3 RAM_7 RAM_7 RAM_7 RAM_3 RAM_3 RAM_3 RAM_3
///
/// The Video RAM is always located in the first 64K, VRAM is in no way affected by this register
/// </summary>
public byte MMR => _MMR;
private byte _MMR;
public PAL16L8(CPCBase machine)
{
_machine = machine;
}
public bool ReadPort(ushort port, ref int result)
{
// this is write-only
return false;
}
public bool WritePort(ushort port, int result)
{
if (result.Bit(7) && result.Bit(6))
{
_MMR = (byte)result;
return true;
}
return false;
}
public void SyncState(Serializer ser)
{
ser.BeginSection("PAL");
ser.Sync(nameof(MMR), ref _MMR);
ser.EndSection();
}
}
}

26
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/PPI/PPI_8255.cs → src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/PPI_8255.cs
View File

@ -12,8 +12,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
public class PPI_8255 : IPortIODevice
{
private readonly CPCBase _machine;
private CRCT_6845 CRTC => _machine.CRCT;
private AmstradGateArray GateArray => _machine.GateArray;
private CRTC CRTC => _machine.CRTC;
private IPSG PSG => _machine.AYDevice;
private DatacorderDevice Tape => _machine.TapeDevice;
private IKeyboard Keyboard => _machine.KeyboardDevice;
@ -141,7 +140,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
bool isSet = data.Bit(0);
// get the bit in PortC that we wish to change
var bit = (data >> 1) & 7;
int bit = (data >> 1) & 7;
// modify this bit
if (isSet)
@ -202,7 +201,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
// build the PortB output
// start with every bit reset
BitArray rBits = new BitArray(8);
var rBits = new BitArray(8);
// Bit0 - Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)
if (CRTC.VSYNC)
@ -253,7 +252,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
val &= 0x0f;
// isolate control bits
var v = Regs[PORT_C] & 0xc0;
int v = Regs[PORT_C] & 0xc0;
if (v == 0xc0)
{
@ -302,14 +301,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public bool ReadPort(ushort port, ref int result)
{
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
// The 8255 responds to bit 11 reset with A10 and A12-A15 set
//if (portUpper.Bit(3))
//return false;
var PPIFunc = (port & 0x0300) >> 8; // portUpper & 3;
int PPIFunc = (port & 0x0300) >> 8; // portUpper & 3;
switch (PPIFunc)
{
@ -346,14 +338,10 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public bool WritePort(ushort port, int result)
{
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
// The 8255 responds to bit 11 reset with A10 and A12-A15 set
if (portUpper.Bit(3))
if (port.Bit(11))
return false;
var PPIFunc = portUpper & 3;
int PPIFunc = (port >> 8) & 3;
switch (PPIFunc)
{

328
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Hardware/Screen.cs Normal file
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@ -0,0 +1,328 @@
using BizHawk.Common;
using BizHawk.Emulation.Common;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// Basic emulation of a PAL Amstrad CPC CRT screen
///
/// Decoding of C-SYNC pulses are not emulated properly,
/// we just assume that so long as the C-VSYNC and C-HSYNC periods are correct, the screen will display.
///
/// References used:
/// - https://www.cpcwiki.eu/index.php/GT64/GT65
/// - https://www.cpcwiki.eu/index.php/CTM640/CTM644
/// - https://martin.hinner.info/vga/pal.html
/// - https://uzebox.org/forums/viewtopic.php?t=11062
/// - https://www.cpcwiki.eu/forum/emulators/wish-60hz60fps-support-in-emulators-thought-on-emulating-a-crt/
/// - https://www.batsocks.co.uk/readme/video_timing.htm
/// - https://web.archive.org/web/20170202185019/https://www.retroleum.co.uk/PALTVtimingandvoltages.html
/// - https://web.archive.org/web/20131125145905/http://lipas.uwasa.fi/~f76998/video/modes/
/// - https://cpcrulez.fr/coding_grimware-the_mighty_crtc_6845.htm
/// - https://www.monitortests.com/blog/timing-parameters-explained/
/// </summary>
public class CRTScreen : IVideoProvider
{
/// <summary>
/// The type of monitor to emulate
/// </summary>
public ScreenType ScreenType { get; }
/// <summary>
/// Checked and reset in the emulator loop. If true, framend processing happens
/// </summary>
public bool FrameEnd { get; set; }
/// <summary>
/// Total line period in microseconds
/// </summary>
private const int LINE_PERIOD = 64;
/// <summary>
/// Total horizontal time in pixels
/// </summary>
private const int TOTAL_PIXELS = LINE_PERIOD * PIXEL_TIME;
/// <summary>
/// Arbirary processing buffer width
/// </summary>
private const int FRAMEBUFFER_MAX_WIDTH = 1024;
/// <summary>
/// Total scanlines per frame
/// This is:
/// - 625 in interlaced mode (25Hz)
/// - 312 in non-interlaced mode (50.08Hz)
/// </summary>
private const int TOTAL_LINES = 625;
/// <summary>
/// The number or pixels being rendered every microsecond
/// </summary>
private const int PIXEL_TIME = 16;
public CRTScreen(ScreenType screenType, AmstradCPC.BorderType bordertype)
{
ScreenType = screenType;
TrimLeft = 121;
TrimTop = 39;
TrimRight = 87;
TrimBottom = 10;
switch (bordertype)
{
case AmstradCPC.BorderType.Visible:
TrimLeft += 25;
TrimTop += 45;
TrimRight += 40;
TrimBottom += 35;
break;
}
}
/// <summary>
/// X position of the electron gun (inluding sync areas)
/// </summary>
private int _gunPosH;
/// <summary>
/// Position in frame time on the X-axis
/// </summary>
private int _timePosH;
/// <summary>
/// Y position of the electron gun (inluding sync areas)
/// </summary>
private int _gunPosV;
/// <summary>
/// Position in frame time on the V-Axis
/// </summary>
private int _timePosV;
private int _verticalTiming;
private bool _isVsync;
private bool _frameEndPending;
/// <summary>
/// Should be called at the pixel clock rate (in the case of the Amstrad CPC, 16MHz)
/// </summary>
public void VideoClock(int colour, int field, bool cHsync = false, bool cVsync = false)
{
// Beam moves continuously downwards at 50 Hz and left to right with a HSYNC pulse every 15625Hz
// Horizontal and vertical movement are independent.
// PAL Horizontal:
// - Beam moves right at a rate of 16 pixels per usec
// - As soon as an HSYNC signal is detected, the PLL capacitor discharges and the beam moves back to the left
// - If an HSYNC is not detected in time, the PLL will eventually move the beam back to the left
// - https://uzebox.org/forums/viewtopic.php?t=11062 suggests that the horizontal line time if this happens is somewhere around 14000Hz (71.43 usec)
//
// PAL Vertical
// - Beam moves down at a rate of 1 line per 64 microseconds (although this movement covers two scanlines)
// - As soon as a VSYNC signal is detected, the PLL capacitor discharges and the beam moves back to the top (at the same horizontal position that VSYNC started)
// - If a VSYNC is not detected in time, the PLL will eventually move the beam back to the top
// - Unsure what the vertical screen time for this action is.
int hHold = 118; // pixels - approx (71.43 - 64) * 16
int vHold = 3; // scanlines
// * horizontal movement *
// gun moves left to right at a rate of 16 pixels per usec
_timePosH++;
_verticalTiming++;
if (cHsync)
{
// hsync signal detected - beam is moved to the left and held there until the signal is released
_gunPosH = 0;
_timePosH = 0;
}
else if (_timePosH == TOTAL_PIXELS + hHold)
{
// hsync signal not detected in time - PLL forces the beam back to the left
_gunPosH = 0;
_timePosH = 0;
}
else
{
_gunPosH++;
if (_gunPosH >= FRAMEBUFFER_MAX_WIDTH)
{
// gun is at the rightmost position of the screen and is being held there
_gunPosH = FRAMEBUFFER_MAX_WIDTH - 1;
}
}
// * vertical movement *
// gun moves downwards at a rate of 1 line per 64 microseconds - 1024 pixel times (although this movement covers two scanlines)
if (!cVsync && _verticalTiming % TOTAL_PIXELS == 0)
{
// gun moves down
_gunPosV += 2;
_verticalTiming = 0;
if (_gunPosV >= TOTAL_LINES - 1)
{
// gun is at the bottom of the screen and is being held there
_gunPosV = TOTAL_LINES - 1;
}
}
if (cVsync && !_isVsync)
{
// initial vsync signal detected - beam is moved back to the top of the screen and held there until the signal is released
_gunPosV = 0;
_isVsync = true;
FrameEnd = true;
HackHPos();
}
else if (cVsync)
{
// vsync signal ongoing - beam is held at the top of the screen
_gunPosV = 0;
//HackHPos();
}
else if (_gunPosV == TOTAL_LINES + vHold)
{
// vsync signal not detected in time - PLL forces the beam back to the top
_gunPosV = 0;
_isVsync = false;
FrameEnd = true;
HackHPos();
}
else
{
// no vsync
_isVsync = false;
}
void HackHPos()
{
// the field length is actually 312.5 scanlines, so HSYNC happens half way through a scanline
// this is for interlace mode and the first field starts half a scanline later
// the second field should start at the same time as HSYNC
// for now, we'll reset _verticalTiming to 0 when vertical flyback happens just so the screen isnt broken half way
// and deal with interlacing later
if (_verticalTiming == 665)
{
_verticalTiming = 0;
}
}
// video output
if (!cHsync && !cVsync)
{
int currPos = (_gunPosV * FRAMEBUFFER_MAX_WIDTH) + _gunPosH;
int nextPos = ((_gunPosV + 1) * FRAMEBUFFER_MAX_WIDTH) + _gunPosH;
_frameBuffer[currPos] = colour;
if (nextPos < TOTAL_LINES * FRAMEBUFFER_MAX_WIDTH)
_frameBuffer[nextPos] = colour;
}
}
public void Reset()
{
_gunPosH = 0;
_gunPosV = 0;
}
private int HDisplayable => FRAMEBUFFER_MAX_WIDTH - TrimLeft - TrimRight;
private int VDisplayable => TOTAL_LINES - TrimTop - TrimBottom;
private readonly int TrimLeft;
private readonly int TrimRight;
private readonly int TrimTop;
private readonly int TrimBottom;
/// <summary>
/// Working buffer that encapsulates the entire PAL frame time
/// </summary>
private readonly int[] _frameBuffer = new int[FRAMEBUFFER_MAX_WIDTH * TOTAL_LINES];
public int BackgroundColor => 0;
public int VsyncNumerator => 16_000_000; // pixel clock
public int VsyncDenominator => 319_488; // 1024 * 312
public int BufferWidth => HDisplayable;
public int BufferHeight => VDisplayable;
public int VirtualWidth => HDisplayable;
public int VirtualHeight => (int)(VDisplayable * GetVerticalModifier(HDisplayable, VDisplayable, 4.0 / 3.0));
public int[] GetVideoBuffer() => ClampBuffer(_frameBuffer, FRAMEBUFFER_MAX_WIDTH, TOTAL_LINES, TrimLeft, TrimTop, TrimRight, TrimBottom);
private static int[] ClampBuffer(int[] buffer, int originalWidth, int originalHeight, int trimLeft, int trimTop, int trimRight, int trimBottom)
{
int newWidth = originalWidth - trimLeft - trimRight;
int newHeight = originalHeight - trimTop - trimBottom;
int[] newBuffer = new int[newWidth * newHeight];
for (int y = 0; y < newHeight; y++)
{
for (int x = 0; x < newWidth; x++)
{
int originalIndex = (y + trimTop) * originalWidth + (x + trimLeft);
int newIndex = y * newWidth + x;
newBuffer[newIndex] = buffer[originalIndex];
}
}
return newBuffer;
}
private static double GetVerticalModifier(int bufferWidth, int bufferHeight, double targetAspectRatio)
{
double currentAspectRatio = (double)bufferWidth / bufferHeight;
double verticalModifier = currentAspectRatio / targetAspectRatio;
return verticalModifier;
}
public void SyncState(Serializer ser)
{
ser.BeginSection("CRTScreen");
ser.Sync(nameof(_gunPosH), ref _gunPosH);
ser.Sync(nameof(_timePosH), ref _timePosH);
ser.Sync(nameof(_gunPosV), ref _gunPosV);
ser.Sync(nameof(_timePosV), ref _timePosV);
ser.Sync(nameof(_isVsync), ref _isVsync);
ser.Sync(nameof(_frameEndPending), ref _frameEndPending);
ser.Sync(nameof(_verticalTiming), ref _verticalTiming);
ser.EndSection();
}
}
/// <summary>
/// The type of Amstrad CRT to emulate
/// </summary>
public enum ScreenType
{
/// <summary>
/// CTM640/CTM644
/// Amstrad colour monitors
/// </summary>
CTM064x,
/// <summary>
/// GT64/GT65/GT65-2
/// Amstrad green screen monitors
/// </summary>
GT6x
}
public class VideoData
{
public int R { get; set; }
public int G { get; set; }
public int B { get; set; }
public bool C_HSYNC { get; set; }
public bool C_VSYNC { get; set; }
}
}

109
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPC464/CPC464.Port.cs
View File

@ -1,4 +1,5 @@
using System.Collections;
using BizHawk.Common.NumberExtensions;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
@ -13,38 +14,87 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public override byte ReadPort(ushort port)
{
BitArray portBits = new BitArray(BitConverter.GetBytes(port));
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
int finalResult = 0;
int result = 0;
bool deviceResponse = false;
int result = 0xff;
var devs = DecodeINPort(port);
if (DecodeINPort(port) == PortDevice.GateArray)
{
GateArray.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.CRCT)
{
CRCT.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.ROMSelect)
foreach (var d in devs)
{
if (d == PortDevice.PPI)
{
PPI.ReadPort(port, ref result);
finalResult |= result;
deviceResponse = true;
}
}
else if (DecodeINPort(port) == PortDevice.Printer)
{
if (d == PortDevice.Expansion)
{
if (!port.Bit(7))
{
// FDC
if (port.Bit(8) && !port.Bit(0))
{
// FDC status register
UPDDiskDevice.ReadStatus(ref result);
}
else if (port.Bit(8) && port.Bit(0))
{
// FDC data register
UPDDiskDevice.ReadData(ref result);
}
}
else if (DecodeINPort(port) == PortDevice.PPI)
{
PPI.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.Expansion)
{
finalResult |= result;
deviceResponse = true;
}
}
if (d == PortDevice.GateArray && !deviceResponse)
{
// ACCC 4.4.2
// The GATE ARRAY is write-only, and the RD pin is in the inactive state, which implies that a read
// on this circuit is not considered. At best, a high impedance state available on the data bus is recovered.
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.CRCT)
{
// ACCC 4.4.2
// However, the CRTCs are not connected to the Z80A's RD and WR pins, so there is no detection of the I/O direction.
// Consequently, if a read instruction is used on a write register of the CRTC, then a data is sent to the CRTC
// (whatever is on the data bus). "it would be risky to trust the returned value".
CRTC.WritePort(port, CPU.Regs[CPU.DB]);
result = CPU.Regs[CPU.DB];
if (!deviceResponse)
finalResult |= result;
}
if (d == PortDevice.ROMSelect && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.Printer && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.PAL && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
}
return (byte)result;
return (byte)finalResult;
}
/// <summary>
@ -53,11 +103,6 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public override void WritePort(ushort port, byte value)
{
BitArray portBits = new BitArray(BitConverter.GetBytes(port));
BitArray dataBits = new BitArray(BitConverter.GetBytes(value));
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
var devs = DecodeOUTPort(port);
foreach (var d in devs)
@ -66,13 +111,13 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
GateArray.WritePort(port, value);
}
else if (d == PortDevice.RAMManagement)
else if (d == PortDevice.PAL)
{
// not present in the unexpanded CPC464
}
else if (d == PortDevice.CRCT)
{
CRCT.WritePort(port, value);
CRTC.WritePort(port, value);
}
else if (d == PortDevice.ROMSelect)
{

10
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPC464/CPC464.cs
View File

@ -16,12 +16,14 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
CPC = cpc;
CPU = cpu;
FrameLength = 79872;
CRTC = CRTC.Create(0);
GateArray = new GateArray(this, GateArrayType.Amstrad40008);
CRTScreen = new CRTScreen(ScreenType.CTM064x, borderType);
FrameLength = GateArray.FrameLength / 4;
CRCT = new CRCT_6845(CRCT_6845.CRCTType.MC6845, this);
//CRT = new CRTDevice(this);
GateArray = new AmstradGateArray(this, AmstradGateArray.GateArrayType.Amstrad40007);
PPI = new PPI_8255(this);
PAL = new PAL16L8(this);
TapeBuzzer = new Beeper(this);
TapeBuzzer.Init(44100, FrameLength);

127
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPC6128/CPC6128.Port.cs
View File

@ -1,7 +1,5 @@
using BizHawk.Common.NumberExtensions;
using System.Collections;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
@ -15,51 +13,87 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public override byte ReadPort(ushort port)
{
BitArray portBits = new BitArray(BitConverter.GetBytes(port));
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
int finalResult = 0;
int result = 0;
bool deviceResponse = false;
int result = 0xff;
var devs = DecodeINPort(port);
if (DecodeINPort(port) == PortDevice.GateArray)
foreach (var d in devs)
{
GateArray.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.CRCT)
{
CRCT.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.ROMSelect)
{
}
else if (DecodeINPort(port) == PortDevice.Printer)
{
}
else if (DecodeINPort(port) == PortDevice.PPI)
{
PPI.ReadPort(port, ref result);
}
else if (DecodeINPort(port) == PortDevice.Expansion)
{
if (!port.Bit(7))
if (d == PortDevice.PPI)
{
// FDC
if (port.Bit(8) && !port.Bit(0))
PPI.ReadPort(port, ref result);
finalResult |= result;
deviceResponse = true;
}
if (d == PortDevice.Expansion)
{
if (!port.Bit(7))
{
// FDC status register
UPDDiskDevice.ReadStatus(ref result);
}
if (port.Bit(8) && port.Bit(0))
{
// FDC data register
UPDDiskDevice.ReadData(ref result);
// FDC
if (port.Bit(8) && !port.Bit(0))
{
// FDC status register
UPDDiskDevice.ReadStatus(ref result);
}
else if (port.Bit(8) && port.Bit(0))
{
// FDC data register
UPDDiskDevice.ReadData(ref result);
}
finalResult |= result;
deviceResponse = true;
}
}
if (d == PortDevice.GateArray && !deviceResponse)
{
// ACCC 4.4.2
// The GATE ARRAY is write-only, and the RD pin is in the inactive state, which implies that a read
// on this circuit is not considered. At best, a high impedance state available on the data bus is recovered.
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.CRCT)
{
// ACCC 4.4.2
// However, the CRTCs are not connected to the Z80A's RD and WR pins, so there is no detection of the I/O direction.
// Consequently, if a read instruction is used on a write register of the CRTC, then a data is sent to the CRTC
// (whatever is on the data bus). "it would be risky to trust the returned value".
CRTC.WritePort(port, CPU.Regs[CPU.DB]);
result = CPU.Regs[CPU.DB];
if (!deviceResponse)
finalResult |= result;
}
if (d == PortDevice.ROMSelect && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.Printer && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
if (d == PortDevice.PAL && !deviceResponse)
{
// TODO: confirm this is a write-only port
result = 0xFF;
finalResult |= result;
}
}
return (byte)result;
return (byte)finalResult;
}
/// <summary>
@ -68,11 +102,6 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public override void WritePort(ushort port, byte value)
{
BitArray portBits = new BitArray(BitConverter.GetBytes(port));
BitArray dataBits = new BitArray(BitConverter.GetBytes(value));
byte portUpper = (byte)(port >> 8);
byte portLower = (byte)(port & 0xff);
var devs = DecodeOUTPort(port);
foreach (var d in devs)
@ -81,19 +110,13 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
GateArray.WritePort(port, value);
}
else if (d == PortDevice.RAMManagement)
else if (d == PortDevice.PAL)
{
if (value.Bit(7) && value.Bit(6))
{
RAMConfig = value & 0x07;
// additional 64K bank index
var b64 = value & 0x38;
}
PAL.WritePort(port, value);
}
else if (d == PortDevice.CRCT)
{
CRCT.WritePort(port, value);
CRTC.WritePort(port, value);
}
else if (d == PortDevice.ROMSelect)
{

10
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPC6128/CPC6128.cs
View File

@ -16,12 +16,14 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
CPC = cpc;
CPU = cpu;
FrameLength = 79872;
CRTC = CRTC.Create(0);
GateArray = new GateArray(this, GateArrayType.Amstrad40010);
CRTScreen = new CRTScreen(ScreenType.CTM064x, borderType);
FrameLength = GateArray.FrameLength / 4;
CRCT = new CRCT_6845(CRCT_6845.CRCTType.MC6845, this);
//CRT = new CRTDevice(this);
GateArray = new AmstradGateArray(this, AmstradGateArray.GateArrayType.Amstrad40007);
PPI = new PPI_8255(this);
PAL = new PAL16L8(this);
TapeBuzzer = new Beeper(this);
TapeBuzzer.Init(44100, FrameLength);

6
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPCBase.Memory.cs
View File

@ -50,13 +50,13 @@
/// <summary>
/// The currently selected RAM config
/// </summary>
public int RAMConfig;
public int RAMConfig => PAL.MMR & 0b0000_0111;
/// <summary>
/// Always 0 on a CPC6128
/// On a machine with more than 128K RAM (standard memory expansion) this selects each additional 64K above the first upper 64K
/// </summary>
public int RAM64KBank;
public int RAM64KBank => PAL.MMR & 0b0011_1000;
/// <summary>
/// Simulates reading from the bus
@ -96,7 +96,7 @@
public abstract void InitROM(RomData[] romData);
/// <summary>
/// ULA reads the memory at the specified address
/// Gate Array reads the memory at the specified address
/// (No memory contention)
/// </summary>
public virtual byte FetchScreenMemory(ushort addr)

41
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPCBase.Port.cs
View File

@ -26,32 +26,32 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// https://web.archive.org/web/20090808085929/http://www.cepece.info/amstrad/docs/iopord.html
/// http://www.cpcwiki.eu/index.php/I/O_Port_Summary
/// </summary>
protected virtual PortDevice DecodeINPort(ushort port)
protected virtual List<PortDevice> DecodeINPort(ushort port)
{
PortDevice dev = PortDevice.Unknown;
var devs = new List<PortDevice>();
if (!port.Bit(15) && port.Bit(14))
dev = PortDevice.GateArray;
devs.Add(PortDevice.GateArray);
else if (!port.Bit(15))
dev = PortDevice.RAMManagement;
if (!port.Bit(15))
devs.Add(PortDevice.PAL);
else if (!port.Bit(14))
dev = PortDevice.CRCT;
if (!port.Bit(14))
devs.Add(PortDevice.CRCT);
else if (!port.Bit(13))
dev = PortDevice.ROMSelect;
if (!port.Bit(13))
devs.Add(PortDevice.ROMSelect);
else if (!port.Bit(12))
dev = PortDevice.Printer;
if (!port.Bit(12))
devs.Add(PortDevice.Printer);
else if (!port.Bit(11))
dev = PortDevice.PPI;
if (!port.Bit(11))
devs.Add(PortDevice.PPI);
else if (!port.Bit(10))
dev = PortDevice.Expansion;
if (!port.Bit(10))
devs.Add(PortDevice.Expansion);
return dev;
return devs;
}
/// <summary>
@ -62,13 +62,16 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
protected virtual List<PortDevice> DecodeOUTPort(ushort port)
{
List<PortDevice> devs = new List<PortDevice>();
var devs = new List<PortDevice>();
if (!port.Bit(15) && port.Bit(14))
devs.Add(PortDevice.GateArray);
if (!port.Bit(15))
devs.Add(PortDevice.RAMManagement);
devs.Add(PortDevice.PAL);
if (!port.Bit(15))
devs.Add(PortDevice.PAL);
if (!port.Bit(14))
devs.Add(PortDevice.CRCT);
@ -95,7 +98,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
Unknown,
GateArray,
RAMManagement,
PAL,
CRCT,
ROMSelect,
Printer,

55
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/CPCBase.cs
View File

@ -53,23 +53,28 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// <summary>
/// The Cathode Ray Tube Controller chip
/// </summary>
public CRCT_6845 CRCT { get; set; }
public CRTC CRTC { get; set; }
/// <summary>
/// The Amstrad gate array
/// </summary>
public AmstradGateArray GateArray { get; set; }
public GateArray GateArray { get; set; }
// /// <summary>
// /// Renders pixels to the screen
// /// </summary>
// public CRTDevice CRT { get; set; }
/// <summary>
/// The CRT screen
/// </summary>
public CRTScreen CRTScreen { get; set; }
/// <summary>
/// The PPI contoller chip
/// </summary>
public PPI_8255 PPI { get; set; }
/// <summary>
/// PAL16L8 Programmable Logic Array Circuit
/// </summary>
public PAL16L8 PAL { get; set; }
/// <summary>
/// The length of a standard frame in CPU cycles
/// </summary>
@ -80,11 +85,6 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public bool FrameCompleted;
/// <summary>
/// Overflow from the previous frame (in Z80 cycles)
/// </summary>
public int OverFlow;
/// <summary>
/// The total number of frames rendered
/// </summary>
@ -103,7 +103,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// <summary>
/// Gets the current frame cycle according to the CPU tick count
/// </summary>
public virtual long CurrentFrameCycle => GateArray.FrameClock; // CPU.TotalExecutedCycles - LastFrameStartCPUTick;
public virtual long CurrentFrameCycle => GateArray.GAClockCounter; // GateArray.FrameClock; // CPU.TotalExecutedCycles - LastFrameStartCPUTick;
/// <summary>
/// Non-Deterministic bools
@ -125,9 +125,6 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
/// </summary>
public virtual void ExecuteFrame(bool render, bool renderSound)
{
GateArray.FrameEnd = false;
CRCT.lineCounter = 0;
InputRead = false;
_render = render;
_renderSound = renderSound;
@ -144,17 +141,24 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
PollInput();
//CRT.SetupVideo();
//CRT.ScanlineCounter = 0;
GateArray.GAClockCounter = 0;
GateArray.FrameEnd = false;
while (!GateArray.FrameEnd)
while (!CRTScreen.FrameEnd)
{
GateArray.ClockCycle();
GateArray.Clock();
// cycle the tape device
if (UPDDiskDevice == null || !UPDDiskDevice.FDD_IsDiskLoaded)
TapeDevice.TapeCycle();
}
CRTScreen.FrameEnd = false;
var ipf = GateArray.interruptsPerFrame;
GateArray.interruptsPerFrame = 0;
double nops = GateArray.LastGAFrameClocks / 16.0;
// we have reached the end of a frame
LastFrameStartCPUTick = CPU.TotalExecutedCycles; // - OverFlow;
@ -171,6 +175,7 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
CPC.IsLagFrame = !InputRead;
// FDC debug
/*
if (UPDDiskDevice != null && UPDDiskDevice.writeDebug)
{
// only write UPD log every second
@ -181,8 +186,10 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
//System.IO.File.WriteAllText(UPDDiskDevice.outputfile, UPDDiskDevice.outputString);
}
}
*/
GateArray.FrameClock = 0;
// setup GA for next frame
GateArray.GAClockCounter = 0;
}
/// <summary>
@ -297,7 +304,6 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
ser.BeginSection("CPCMachine");
ser.Sync(nameof(FrameCompleted), ref FrameCompleted);
ser.Sync(nameof(OverFlow), ref OverFlow);
ser.Sync(nameof(FrameCount), ref FrameCount);
ser.Sync(nameof(_frameCycles), ref _frameCycles);
ser.Sync(nameof(inputRead), ref inputRead);
@ -317,12 +323,11 @@ namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
ser.Sync(nameof(UpperROMPosition), ref UpperROMPosition);
ser.Sync(nameof(UpperROMPaged), ref UpperROMPaged);
ser.Sync(nameof(LowerROMPaged), ref LowerROMPaged);
ser.Sync(nameof(RAMConfig), ref RAMConfig);
ser.Sync(nameof(RAM64KBank), ref RAM64KBank);
CRCT.SyncState(ser);
//CRT.SyncState(ser);
CRTC.SyncState(ser);
GateArray.SyncState(ser);
PPI.SyncState(ser);
PAL.SyncState(ser);
KeyboardDevice.SyncState(ser);
TapeBuzzer.SyncState(ser);
AYDevice.SyncState(ser);

475
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/Machine/GateArrayBase.cs
View File

@ -1,475 +0,0 @@
using BizHawk.Common;
using BizHawk.Emulation.Common;
using BizHawk.Emulation.Cores.Components.Z80A;
using System.Collections;
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
/// <summary>
/// The abstract class that all emulated models will inherit from
/// * Amstrad Gate Array *
/// https://web.archive.org/web/20170612081209/http://www.grimware.org/doku.php/documentations/devices/gatearray
/// </summary>
public abstract class GateArrayBase : IVideoProvider
{
public int Z80ClockSpeed = 4000000;
public int FrameLength = 79872;
private readonly CPCBase _machine;
private Z80A<AmstradCPC.CpuLink> CPU => _machine.CPU;
private CRCT_6845 CRCT => _machine.CRCT;
private IPSG PSG => _machine.AYDevice;
/// <summary>
/// CRTC Register constants
/// </summary>
public const int HOR_TOTAL = 0;
public const int HOR_DISPLAYED = 1;
public const int HOR_SYNC_POS = 2;
public const int HOR_AND_VER_SYNC_WIDTHS = 3;
public const int VER_TOTAL = 4;
public const int VER_TOTAL_ADJUST = 5;
public const int VER_DISPLAYED = 6;
public const int VER_SYNC_POS = 7;
public const int INTERLACE_SKEW = 8;
public const int MAX_RASTER_ADDR = 9;
public const int CUR_START_RASTER = 10;
public const int CUR_END_RASTER = 11;
public const int DISP_START_ADDR_H = 12;
public const int DISP_START_ADDR_L = 13;
public const int CUR_ADDR_H = 14;
public const int CUR_ADDR_L = 15;
public const int LPEN_ADDR_H = 16;
public const int LPEN_ADDR_L = 17;
/// <summary>
/// The standard CPC Pallete (ordered by firmware #)
/// http://www.cpcwiki.eu/index.php/CPC_Palette
/// </summary>
private static readonly int[] CPCFirmwarePalette =
{
Colors.ARGB(0x00, 0x00, 0x00), // Black
Colors.ARGB(0x00, 0x00, 0x80), // Blue
Colors.ARGB(0x00, 0x00, 0xFF), // Bright Blue
Colors.ARGB(0x80, 0x00, 0x00), // Red
Colors.ARGB(0x80, 0x00, 0x80), // Magenta
Colors.ARGB(0x80, 0x00, 0xFF), // Mauve
Colors.ARGB(0xFF, 0x00, 0x00), // Bright Red
Colors.ARGB(0xFF, 0x00, 0x80), // Purple
Colors.ARGB(0xFF, 0x00, 0xFF), // Bright Magenta
Colors.ARGB(0x00, 0x80, 0x00), // Green
Colors.ARGB(0x00, 0x80, 0x80), // Cyan
Colors.ARGB(0x00, 0x80, 0xFF), // Sky Blue
Colors.ARGB(0x80, 0x80, 0x00), // Yellow
Colors.ARGB(0x80, 0x80, 0x80), // White
Colors.ARGB(0x80, 0x80, 0xFF), // Pastel Blue
Colors.ARGB(0xFF, 0x80, 0x00), // Orange
Colors.ARGB(0xFF, 0x80, 0x80), // Pink
Colors.ARGB(0xFF, 0x80, 0xFF), // Pastel Magenta
Colors.ARGB(0x00, 0xFF, 0x00), // Bright Green
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green
Colors.ARGB(0x00, 0xFF, 0xFF), // Bright Cyan
Colors.ARGB(0x80, 0xFF, 0x00), // Lime
Colors.ARGB(0x80, 0xFF, 0x80), // Pastel Green
Colors.ARGB(0x80, 0xFF, 0xFF), // Pastel Cyan
Colors.ARGB(0xFF, 0xFF, 0x00), // Bright Yellow
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow
Colors.ARGB(0xFF, 0xFF, 0xFF), // Bright White
};
/// <summary>
/// The standard CPC Pallete (ordered by hardware #)
/// http://www.cpcwiki.eu/index.php/CPC_Palette
/// </summary>
private static readonly int[] CPCHardwarePalette =
{
Colors.ARGB(0x80, 0x80, 0x80), // White
Colors.ARGB(0x80, 0x80, 0x80), // White (duplicate)
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow
Colors.ARGB(0x00, 0x00, 0x80), // Blue
Colors.ARGB(0xFF, 0x00, 0x80), // Purple
Colors.ARGB(0x00, 0x80, 0x80), // Cyan
Colors.ARGB(0xFF, 0x80, 0x80), // Pink
Colors.ARGB(0xFF, 0x00, 0x80), // Purple (duplicate)
Colors.ARGB(0xFF, 0xFF, 0x80), // Pastel Yellow (duplicate)
Colors.ARGB(0xFF, 0xFF, 0x00), // Bright Yellow
Colors.ARGB(0xFF, 0xFF, 0xFF), // Bright White
Colors.ARGB(0xFF, 0x00, 0x00), // Bright Red
Colors.ARGB(0xFF, 0x00, 0xFF), // Bright Magenta
Colors.ARGB(0xFF, 0x80, 0x00), // Orange
Colors.ARGB(0xFF, 0x80, 0xFF), // Pastel Magenta
Colors.ARGB(0x00, 0x00, 0x80), // Blue (duplicate)
Colors.ARGB(0x00, 0xFF, 0x80), // Sea Green (duplicate)
Colors.ARGB(0x00, 0xFF, 0x00), // Bright Green
Colors.ARGB(0x00, 0xFF, 0xFF), // Bright Cyan
Colors.ARGB(0x00, 0x00, 0x00), // Black
Colors.ARGB(0x00, 0x00, 0xFF), // Bright Blue
Colors.ARGB(0x00, 0x80, 0x00), // Green
Colors.ARGB(0x00, 0x80, 0xFF), // Sky Blue
Colors.ARGB(0x80, 0x00, 0x80), // Magenta
Colors.ARGB(0x80, 0xFF, 0x80), // Pastel Green
Colors.ARGB(0x80, 0xFF, 0x00), // Lime
Colors.ARGB(0x80, 0xFF, 0xFF), // Pastel Cyan
Colors.ARGB(0x80, 0x00, 0x00), // Red
Colors.ARGB(0x80, 0x00, 0xFF), // Mauve
Colors.ARGB(0x80, 0x80, 0x00), // Yellow
Colors.ARGB(0x80, 0x80, 0xFF), // Pastel Blue
};
public GateArrayBase(CPCBase machine)
{
_machine = machine;
PenColours = new int[17];
SetupScreenSize();
Reset();
}
/// <summary>
/// Inits the pen lookup table
/// </summary>
public void SetupScreenMapping()
{
for (int m = 0; m < 4; m++)
{
Lookup[m] = new int[256 * 8];
int pos = 0;
for (int b = 0; b < 256; b++)
{
switch (m)
{
case 1:
int pc = (((b & 0x80) >> 7) | ((b & 0x80) >> 2));
Lookup[m][pos++] = pc;
Lookup[m][pos++] = pc;
pc = (((b & 0x40) >> 6) | ((b & 0x04) >> 1));
Lookup[m][pos++] = pc;
Lookup[m][pos++] = pc;
pc = (((b & 0x20) >> 5) | (b & 0x02));
Lookup[m][pos++] = pc;
Lookup[m][pos++] = pc;
pc = (((b & 0x10) >> 4) | ((b & 0x01) << 1));
break;
case 2:
for (int i = 7; i >= 0; i--)
{
bool pixel_on = ((b & (1 << i)) != 0);
Lookup[m][pos++] = pixel_on ? 1 : 0;
}
break;
case 3:
case 0:
int pc2 = (b & 0xAA);
pc2 = (
((pc2 & 0x80) >> 7) |
((pc2 & 0x08) >> 2) |
((pc2 & 0x20) >> 3) |
((pc2 & 0x02) << 2));
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
pc2 = (b & 0x55);
pc2 = (
((pc2 & 0x40) >> 6) |
((pc2 & 0x04) >> 1) |
((pc2 & 0x10) >> 2) |
((pc2 & 0x01) << 3));
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
Lookup[m][pos++] = pc2;
break;
}
}
}
}
private readonly int[] PenColours;
private int CurrentPen;
private int ScreenMode;
private int INTScanlineCnt;
//private int VSYNCDelyCnt;
private readonly int[][] Lookup = new int[4][];
//private bool DoModeUpdate;
//private int LatchedMode;
//private int buffPos;
public bool FrameEnd;
public bool WaitLine;
/// <summary>
/// The gatearray runs on a 16Mhz clock
/// (for the purposes of emulation, we will use a 4Mhz clock)
/// From this it generates:
/// 1Mhz clock for the CRTC chip
/// 1Mhz clock for the AY-3-8912 PSG
/// 4Mhz clock for the Z80 CPU
/// </summary>
public void ClockCycle()
{
// 4-phase clock
for (int i = 1; i < 5; i++)
{
switch (i)
{
// Phase 1
case 1:
CRCT.ClockCycle();
CPU.ExecuteOne();
break;
// Phase 2
case 2:
CPU.ExecuteOne();
break;
// Phase 3
case 3:
// video fetch
break;
// Phase 4
case 4:
// video fetch
break;
}
}
}
/// <summary>
/// Selects the pen
/// </summary>
public virtual void SetPen(BitArray bi)
{
if (bi[4])
{
// border select
CurrentPen = 16;
}
else
{
// pen select
byte[] b = new byte[1];
bi.CopyTo(b, 0);
CurrentPen = b[0] & 0x0f;
}
}
/// <summary>
/// Selects colour for the currently selected pen
/// </summary>
public virtual void SetPenColour(BitArray bi)
{
byte[] b = new byte[1];
bi.CopyTo(b, 0);
var colour = b[0] & 0x1f;
PenColours[CurrentPen] = colour;
}
/// <summary>
/// Returns the actual ARGB pen colour value
/// </summary>
public virtual int GetPenColour(int idx)
{
return CPCHardwarePalette[PenColours[idx]];
}
/// <summary>
/// Screen mode and ROM config
/// </summary>
public virtual void SetReg2(BitArray bi)
{
byte[] b = new byte[1];
bi.CopyTo(b, 0);
// screen mode
var mode = b[0] & 0x03;
ScreenMode = mode;
// ROM
// upper
if ((b[0] & 0x08) != 0)
{
_machine.UpperROMPaged = false;
}
else
{
_machine.UpperROMPaged = true;
}
// lower
if ((b[0] & 0x04) != 0)
{
_machine.LowerROMPaged = false;
}
else
{
_machine.LowerROMPaged = true;
}
// INT delay
if ((b[0] & 0x10) != 0)
{
INTScanlineCnt = 0;
}
}
/// <summary>
/// Only available on machines with a 64KB memory expansion
/// Default assume we don't have this
/// </summary>
public virtual void SetRAM(BitArray bi)
{
return;
}
public void InterruptACK()
{
INTScanlineCnt &= 0x01f;
}
public void Reset()
{
CurrentPen = 0;
ScreenMode = 1;
for (int i = 0; i < 17; i++)
PenColours[i] = 0;
INTScanlineCnt = 0;
//VSYNCDelyCnt = 0;
}
/// <summary>
/// Device responds to an IN instruction
/// </summary>
public bool ReadPort(ushort port, ref int result)
{
// gate array is OUT only
return false;
}
/// <summary>
/// Device responds to an OUT instruction
/// </summary>
public bool WritePort(ushort port, int result)
{
BitArray portBits = new BitArray(BitConverter.GetBytes(port));
BitArray dataBits = new BitArray(BitConverter.GetBytes((byte)result));
// The gate array responds to port 0x7F
bool accessed = !portBits[15];
if (!accessed)
return false;
// Bit 9 and 8 of the data byte define the function to access
if (!dataBits[6] && !dataBits[7])
{
// select pen
SetPen(dataBits);
}
if (dataBits[6] && !dataBits[7])
{
// select colour for selected pen
SetPenColour(dataBits);
}
if (!dataBits[6] && dataBits[7])
{
// select screen mode, ROM configuration and interrupt control
SetReg2(dataBits);
}
if (dataBits[6] && dataBits[7])
{
// RAM memory management
SetRAM(dataBits);
}
return true;
}
/// <summary>
/// Video output buffer
/// </summary>
public int[] ScreenBuffer;
private int _virtualWidth;
private int _virtualHeight;
private int _bufferWidth;
private int _bufferHeight;
public int BackgroundColor => CPCHardwarePalette[16];
public int VirtualWidth
{
get => _virtualWidth;
set => _virtualWidth = value;
}
public int VirtualHeight
{
get => _virtualHeight;
set => _virtualHeight = value;
}
public int BufferWidth
{
get => _bufferWidth;
set => _bufferWidth = value;
}
public int BufferHeight
{
get => _bufferHeight;
set => _bufferHeight = value;
}
public int VsyncNumerator
{
get => Z80ClockSpeed * 50;
set { }
}
public int VsyncDenominator => Z80ClockSpeed;
public int[] GetVideoBuffer() => ScreenBuffer;
protected void SetupScreenSize()
{
/*
* Rect Pixels: Mode 0: 160×200 pixels with 16 colors (4 bpp)
Sqaure Pixels: Mode 1: 320×200 pixels with 4 colors (2 bpp)
Rect Pixels: Mode 2: 640×200 pixels with 2 colors (1 bpp)
Rect Pixels: Mode 3: 160×200 pixels with 4 colors (2bpp) (this is not an official mode, but rather a side-effect of the hardware)
*
* */
// define maximum screen buffer size
// to fit all possible resolutions, 640x400 should do it
// therefore a scanline will take two buffer rows
// and buffer columns will be:
// Mode 1: 2 pixels
// Mode 2: 1 pixel
// Mode 0: 4 pixels
// Mode 3: 4 pixels
BufferWidth = 640;
BufferHeight = 400;
VirtualHeight = BufferHeight;
VirtualWidth = BufferWidth;
ScreenBuffer = new int[BufferWidth * BufferHeight];
croppedBuffer = ScreenBuffer;
}
protected int[] croppedBuffer;
}
}

102
src/BizHawk.Emulation.Cores/Computers/AmstradCPC/readme.md
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@ -1,10 +1,9 @@
## CPCHawk
# CPCHawk
Still very much work in progress....
Work has started up again as of Sep2024.
#### In Place
* CPC464, CPC6128
## In Place
* CPC464, CPC6128 (default)
* Port IO decoding
* i8255 Programmable Peripheral Interface (PPI) chip emulation
* AY-3-8912 PSG (and Port IO)
@ -12,19 +11,94 @@ Still very much work in progress....
* FDC and FDD devices
* .DSK image parsing and identification (to auto differenciate from ZX Spectrum disk bootloader)
#### There, but needs more work
* CRCT (Cathode Ray Tube Controller) chip emulation
## Right now
* Gate array implementation undergoing a full re-write
* CRTC implementations are being re-written (based on https://shaker.logonsystem.eu/ACCC1.8-EN.pdf)
* CRT screen emulation in progress
* Amstrad Gate Array chip emulation
* Video rendering (modes 0, 1, 2 & 3)
* Datacorder (tape) device
* .CDT tape image file support
* Z80 timing verification
#### Not Yet
## Future..
* CPC664, CPC464plus, CPC6128plus, GX4000 models
* Expansion IO
* Working Datacorder (tape) emulation and handling of .CDT files
* Memory expansions
* External peripherals (Speech Synthesizers etc..)
* Optimisation of EVERYTHING
#### Known Issues
* The CRCT and Gatearray chips are undergoing a re-write at the moment, so video emulation is nowhere near accurate (yet)
* .CDT tape image files will nearly always fail to load - timing conversion is still needed (so the tape device 'plays back' at the wrong speed)
## Known Issues
* Lots of things
## References in use
* https://shaker.logonsystem.eu/ACCC1.8-EN.pdf
* https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/need-plustest-dsk-testbench-9-output-on-original-cpc-6128/
## Test suites
### WinAPU PlusTest (http://www.winape.net/download/plustest.zip)
#### Test 1: ASIC Sprite test
Plus models and GX4000 only - awaiting implementation
#### Test 2: Monitor HSYNC test
Failing
#### Test 3: Horizontal Split and Soft-Scroll test
Failing
#### Test 4: Interrupt, VSync and R52 timing test
Unknown
#### Test 5: Instruction timing test
| Prefix | OPC | Inst. | Comments |
|:----:|:----:|:-----:|:------------:|
|NONE| D3:4 | OUT A | |
|NONE| DB:4 | IN A | |
|NONE| D3:5 | OUT A | |
|NONE| DB:5 | IN A | |
|ED| 41:3 | OUT (C), B | |
|ED| 49:3 | OUT (C), C | |
|ED| 51:3 | OUT (C), D | |
|ED| 59:3 | OUT (C), E | |
|ED| 61:3 | OUT (C), H | |
|ED| 69:3 | OUT (C), L | |
|ED| 71:3 | OUT (C), 0 | |
|ED| 79:3 | OUT (C), A | |
|ED| A2:6 | INI | |
|ED| A3:6 | OUTI | |
|ED| AA:6 | IND | |
|ED| B2:7/6| INIR | |
|ED| B3:7/6| OTIR | |
|ED| BA:7/6| INDR | |
|ED| BB:7/6| OTDR | |
|DD CB| D3:5| SET 2, (ix+d), e | |
|DD CB| DB:5| SET 3, (ix+d), e | |
Everything else passes. Almost certainly the problems observed relate to IO timing.
#### Test 6: Register 0 test
Unknown
#### Test 7: Register 4 test
Unknown
#### Test 8: Register 9 test
Unknown
#### Test 9: Interrupt Wait test
### Amstrad Diagnostics (https://github.com/llopis/amstrad-diagnostics)
Program stalls. Likely because the firmware vertical flyback checks are not happening at the right time.
Might be fixed when port timing is correct.
### Shaker Tests (https://shaker.logonsystem.eu/shaker26.dsk)
Need to correct CRTC emulation and port access timing before even attempting these.
-Asnivor

38
src/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Hardware/GateArrayType.cs Normal file
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@ -0,0 +1,38 @@
namespace BizHawk.Emulation.Cores.Computers.AmstradCPC
{
public enum GateArrayType
{
/// <summary>
/// CPC 464
/// The first version of the Gate Array is the 40007 and was released with the CPC 464
/// </summary>
Amstrad40007,
/// <summary>
/// CPC 664
/// Later, the CPC 664 came out fitted with the 40008 version (and at the same time, the CPC 464 was also upgraded with this version).
/// This version is pinout incompatible with the 40007 (that's why the upgraded 464 of this period have two Gate Array slots on the motherboard,
/// one for a 40007 and one for a 40008)
/// </summary>
Amstrad40008,
/// <summary>
/// CPC 6128
/// The CPC 6128 was released with the 40010 version (and the CPC 464 and 664 manufactured at that time were also upgraded to this version).
/// The 40010 is pinout compatible with the previous 40008
/// </summary>
Amstrad40010,
/// <summary>
/// Costdown CPC
/// In the last serie of CPC 464 and 6128 produced by Amstrad in 1988, a small ASIC chip have been used to reduce the manufacturing costs.
/// This ASIC emulates the Gate Array, the PAL and the CRTC 6845. And no, there is no extra features like on the Amstrad Plus.
/// The only noticeable difference seems to be about the RGB output levels which are not exactly the same than those produced with a real Gate Array
/// </summary>
Amstrad40226,
/// <summary>
/// Plus &amp; GX-4000
/// All the Plus range is built upon a bigger ASIC chip which is integrating many features of the classic CPC (FDC, CRTC, PPI, Gate Array/PAL) and all
/// the new Plus specific features. The Gate Array on the Plus have a new register, named RMR2, to expand the ROM mapping functionnalities of the machine.
/// This register requires to be unlocked first to be available. And finally, the RGB levels produced by the ASIC on the Plus are noticeably differents
/// </summary>
Amstrad40489,
}
}