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Memory overhaul for a nice performance benefit

This commit is contained in:
Asnivor 2018-03-12 15:22:06 +00:00
parent deba6b18b8
commit 213437362d
17 changed files with 219 additions and 142 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.Memory.cs
View File

@ -104,7 +104,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
/// <summary>
/// Helper function to refresh memory array (probably not the best way to do things)
/// </summary>
public abstract void ReInitMemory();
//public abstract void ReInitMemory();
/// <summary>
/// Detects whether the 48k rom is resident (or paged in) at 0x0001

6
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.cs
View File

@ -194,9 +194,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
ULADevice.UpdateScreenBuffer(ULADevice.FrameLength);
if (_renderSound)
BuzzerDevice.EndFrame();
//TapeDevice.CPUFrameCompleted();
BuzzerDevice.EndFrame();
FrameCount++;
@ -276,7 +274,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
ser.EndSection();
ReInitMemory();
//ReInitMemory();
}
}
}

58
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.Memory.cs
View File

@ -49,24 +49,25 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
int divisor = addr / 0x4000;
byte result = 0xff;
switch (divisor)
{
// ROM 0x000
case 0:
if (ROMPaged == 0)
result = Memory[0][addr % 0x4000];
result = ROM0[addr % 0x4000];
else
result = Memory[1][addr % 0x4000];
result = ROM1[addr % 0x4000];
break;
// RAM 0x4000 (RAM5 - Bank5 or shadow bank RAM7)
// RAM 0x4000 (RAM5 - Bank5)
case 1:
result = Memory[7][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
result = Memory[4][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -74,28 +75,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
result = Memory[2][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
result = Memory[3][addr % 0x4000];
result = RAM1[addr % 0x4000];
break;
case 2:
result = Memory[4][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
case 3:
result = Memory[5][addr % 0x4000];
result = RAM3[addr % 0x4000];
break;
case 4:
result = Memory[6][addr % 0x4000];
result = RAM4[addr % 0x4000];
break;
case 5:
result = Memory[7][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
case 6:
result = Memory[8][addr % 0x4000];
result = RAM6[addr % 0x4000];
break;
case 7:
result = Memory[9][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -115,24 +116,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
public override void WriteBus(ushort addr, byte value)
{
int divisor = addr / 0x4000;
switch (divisor)
{
// ROM 0x000
case 0:
// cannot write to ROMs
/*
if (ROMPaged == 0)
Memory[0][addr % 0x4000] = value;
ROM0[addr % 0x4000] = value;
else
Memory[1][addr % 0x4000] = value;
ROM1[addr % 0x4000] = value;
*/
break;
// RAM 0x4000 (RAM5 - Bank5 or shadow bank RAM7)
case 1:
Memory[7][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
Memory[4][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -140,28 +145,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
Memory[2][addr % 0x4000] = value;
RAM0[addr % 0x4000] = value;
break;
case 1:
Memory[3][addr % 0x4000] = value;
RAM1[addr % 0x4000] = value;
break;
case 2:
Memory[4][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
case 3:
Memory[5][addr % 0x4000] = value;
RAM3[addr % 0x4000] = value;
break;
case 4:
Memory[6][addr % 0x4000] = value;
RAM4[addr % 0x4000] = value;
break;
case 5:
Memory[7][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
case 6:
Memory[8][addr % 0x4000] = value;
RAM6[addr % 0x4000] = value;
break;
case 7:
Memory[9][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -203,7 +208,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
WriteBus(addr, value);
}
/*
public override void ReInitMemory()
{
if (Memory.ContainsKey(0))
@ -256,6 +261,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
else
Memory.Add(9, RAM7);
}
*/
/// <summary>
/// ULA reads the memory at the specified address

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.ULA.cs
View File

@ -57,7 +57,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
contentionStartPeriod = 14361; // + LateTiming;
contentionEndPeriod = contentionStartPeriod + (ScreenHeight * TstatesPerScanline);
screen = _machine.Memory[7];
screen = _machine.RAM5;
screenByteCtr = DisplayStart;
ULAByteCtr = 0;
actualULAStart = 14366 - 24 - (TstatesPerScanline * BorderTopHeight);// + LateTiming;

3
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.cs
View File

@ -26,9 +26,6 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
RAMPaged = 0;
PagingDisabled = false;
// init addressable memory from ROM and RAM banks
ReInitMemory();
ULADevice = new ULA128(this);
BuzzerDevice = new Buzzer(this);

116
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.Memory.cs
View File

@ -75,12 +75,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[4][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
case 2:
case 3:
result = Memory[8][addr % 0x4000];
result = RAM4[addr % 0x4000];
break;
}
break;
@ -88,14 +88,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[5][addr % 0x4000];
result = RAM1[addr % 0x4000];
break;
case 1:
case 2:
result = Memory[9][addr % 0x4000];
case 2:
result = RAM5[addr % 0x4000];
break;
case 3:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -103,12 +103,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[6][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
case 2:
case 3:
result = Memory[10][addr % 0x4000];
result = RAM6[addr % 0x4000];
break;
}
break;
@ -118,10 +118,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
case 0:
case 2:
case 3:
result = Memory[7][addr % 0x4000];
result = RAM3[addr % 0x4000];
break;
case 1:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -133,17 +133,31 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
// ROM 0x000
case 0:
result = Memory[_ROMpaged][addr % 0x4000];
switch (_ROMpaged)
{
case 0:
result = ROM0[addr % 0x4000];
break;
case 1:
result = ROM1[addr % 0x4000];
break;
case 2:
result = ROM2[addr % 0x4000];
break;
case 3:
result = ROM3[addr % 0x4000];
break;
}
break;
// RAM 0x4000 (RAM5 - Bank5 always)
case 1:
result = Memory[9][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
result = Memory[6][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -151,28 +165,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
result = Memory[4][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
result = Memory[5][addr % 0x4000];
result = RAM1[addr % 0x4000];
break;
case 2:
result = Memory[6][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
case 3:
result = Memory[7][addr % 0x4000];
result = RAM3[addr % 0x4000];
break;
case 4:
result = Memory[8][addr % 0x4000];
result = RAM4[addr % 0x4000];
break;
case 5:
result = Memory[9][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
case 6:
result = Memory[10][addr % 0x4000];
result = RAM6[addr % 0x4000];
break;
case 7:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -203,12 +217,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[4][addr % 0x4000] = value;
RAM0[addr % 0x4000] = value;
break;
case 1:
case 2:
case 3:
Memory[8][addr % 0x4000] = value;
RAM4[addr % 0x4000] = value;
break;
}
break;
@ -216,14 +230,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[5][addr % 0x4000] = value;
RAM1[addr % 0x4000] = value;
break;
case 1:
case 2:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
case 3:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -231,12 +245,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
case 1:
case 2:
case 3:
Memory[10][addr % 0x4000] = value;
RAM6[addr % 0x4000] = value;
break;
}
break;
@ -246,10 +260,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
case 0:
case 2:
case 3:
Memory[7][addr % 0x4000] = value;
RAM3[addr % 0x4000] = value;
break;
case 1:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -261,17 +275,34 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
// ROM 0x000
case 0:
Memory[_ROMpaged][addr % 0x4000] = value;
/*
switch (_ROMpaged)
{
// cannot write to ROMs
case 0:
ROM0[addr % 0x4000] = value;
break;
case 1:
ROM1[addr % 0x4000] = value;
break;
case 2:
ROM2[addr % 0x4000] = value;
break;
case 3:
ROM3[addr % 0x4000] = value;
break;
}
*/
break;
// RAM 0x4000 (RAM5 - Bank5 only)
case 1:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -279,28 +310,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
Memory[4][addr % 0x4000] = value;
RAM0[addr % 0x4000] = value;
break;
case 1:
Memory[5][addr % 0x4000] = value;
RAM1[addr % 0x4000] = value;
break;
case 2:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
case 3:
Memory[7][addr % 0x4000] = value;
RAM3[addr % 0x4000] = value;
break;
case 4:
Memory[8][addr % 0x4000] = value;
RAM4[addr % 0x4000] = value;
break;
case 5:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
case 6:
Memory[10][addr % 0x4000] = value;
RAM6[addr % 0x4000] = value;
break;
case 7:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -343,7 +374,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
WriteBus(addr, value);
}
/*
public override void ReInitMemory()
{
if (Memory.ContainsKey(0))
@ -406,6 +437,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
else
Memory.Add(11, RAM7);
}
*/
/// <summary>
/// ULA reads the memory at the specified address

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.ULA.cs
View File

@ -57,7 +57,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
contentionStartPeriod = 14361; // + LateTiming;
contentionEndPeriod = contentionStartPeriod + (ScreenHeight * TstatesPerScanline);
screen = _machine.Memory[9];
screen = _machine.RAM5;
screenByteCtr = DisplayStart;
ULAByteCtr = 0;
actualULAStart = 14365 - 24 - (TstatesPerScanline * BorderTopHeight);// + LateTiming;

3
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.cs
View File

@ -26,9 +26,6 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
RAMPaged = 0;
PagingDisabled = false;
// init addressable memory from ROM and RAM banks
ReInitMemory();
ULADevice = new ULAPlus2a(this);
BuzzerDevice = new Buzzer(this);

114
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.Memory.cs
View File

@ -75,12 +75,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[4][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
case 2:
case 3:
result = Memory[8][addr % 0x4000];
result = RAM4[addr % 0x4000];
break;
}
break;
@ -88,14 +88,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[5][addr % 0x4000];
result = RAM1[addr % 0x4000];
break;
case 1:
case 2:
result = Memory[9][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
case 3:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -103,12 +103,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
result = Memory[6][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
case 2:
case 3:
result = Memory[10][addr % 0x4000];
result = RAM6[addr % 0x4000];
break;
}
break;
@ -118,10 +118,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
case 0:
case 2:
case 3:
result = Memory[7][addr % 0x4000];
result = RAM3[addr % 0x4000];
break;
case 1:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -133,17 +133,31 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
// ROM 0x000
case 0:
result = Memory[_ROMpaged][addr % 0x4000];
switch (_ROMpaged)
{
case 0:
result = ROM0[addr % 0x4000];
break;
case 1:
result = ROM1[addr % 0x4000];
break;
case 2:
result = ROM2[addr % 0x4000];
break;
case 3:
result = ROM3[addr % 0x4000];
break;
}
break;
// RAM 0x4000 (RAM5 - Bank5 always)
case 1:
result = Memory[9][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
result = Memory[6][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -151,28 +165,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
result = Memory[4][addr % 0x4000];
result = RAM0[addr % 0x4000];
break;
case 1:
result = Memory[5][addr % 0x4000];
result = RAM1[addr % 0x4000];
break;
case 2:
result = Memory[6][addr % 0x4000];
result = RAM2[addr % 0x4000];
break;
case 3:
result = Memory[7][addr % 0x4000];
result = RAM3[addr % 0x4000];
break;
case 4:
result = Memory[8][addr % 0x4000];
result = RAM4[addr % 0x4000];
break;
case 5:
result = Memory[9][addr % 0x4000];
result = RAM5[addr % 0x4000];
break;
case 6:
result = Memory[10][addr % 0x4000];
result = RAM6[addr % 0x4000];
break;
case 7:
result = Memory[11][addr % 0x4000];
result = RAM7[addr % 0x4000];
break;
}
break;
@ -203,12 +217,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[4][addr % 0x4000] = value;
RAM0[addr % 0x4000] = value;
break;
case 1:
case 2:
case 3:
Memory[8][addr % 0x4000] = value;
RAM4[addr % 0x4000] = value;
break;
}
break;
@ -216,14 +230,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[5][addr % 0x4000] = value;
RAM1[addr % 0x4000] = value;
break;
case 1:
case 2:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
case 3:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -231,12 +245,12 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (PagingConfiguration)
{
case 0:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
case 1:
case 2:
case 3:
Memory[10][addr % 0x4000] = value;
RAM6[addr % 0x4000] = value;
break;
}
break;
@ -246,10 +260,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
case 0:
case 2:
case 3:
Memory[7][addr % 0x4000] = value;
RAM3[addr % 0x4000] = value;
break;
case 1:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -261,17 +275,34 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
// ROM 0x000
case 0:
Memory[_ROMpaged][addr % 0x4000] = value;
/*
switch (_ROMpaged)
{
// cannot write to ROMs
case 0:
ROM0[addr % 0x4000] = value;
break;
case 1:
ROM1[addr % 0x4000] = value;
break;
case 2:
ROM2[addr % 0x4000] = value;
break;
case 3:
ROM3[addr % 0x4000] = value;
break;
}
*/
break;
// RAM 0x4000 (RAM5 - Bank5 only)
case 1:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
// RAM 0x8000 (RAM2 - Bank2)
case 2:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
// RAM 0xc000 (any ram bank 0 - 7 may be paged in - default bank0)
@ -279,28 +310,28 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
switch (RAMPaged)
{
case 0:
Memory[4][addr % 0x4000] = value;
RAM0[addr % 0x4000] = value;
break;
case 1:
Memory[5][addr % 0x4000] = value;
RAM1[addr % 0x4000] = value;
break;
case 2:
Memory[6][addr % 0x4000] = value;
RAM2[addr % 0x4000] = value;
break;
case 3:
Memory[7][addr % 0x4000] = value;
RAM3[addr % 0x4000] = value;
break;
case 4:
Memory[8][addr % 0x4000] = value;
RAM4[addr % 0x4000] = value;
break;
case 5:
Memory[9][addr % 0x4000] = value;
RAM5[addr % 0x4000] = value;
break;
case 6:
Memory[10][addr % 0x4000] = value;
RAM6[addr % 0x4000] = value;
break;
case 7:
Memory[11][addr % 0x4000] = value;
RAM7[addr % 0x4000] = value;
break;
}
break;
@ -343,7 +374,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
WriteBus(addr, value);
}
/*
public override void ReInitMemory()
{
if (Memory.ContainsKey(0))
@ -406,6 +437,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
else
Memory.Add(11, RAM7);
}
*/
/// <summary>
/// ULA reads the memory at the specified address

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.ULA.cs
View File

@ -57,7 +57,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
contentionStartPeriod = 14361; // + LateTiming;
contentionEndPeriod = contentionStartPeriod + (ScreenHeight * TstatesPerScanline);
screen = _machine.Memory[9];
screen = _machine.RAM5;
screenByteCtr = DisplayStart;
ULAByteCtr = 0;
actualULAStart = 14365 - 24 - (TstatesPerScanline * BorderTopHeight);// + LateTiming;

3
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.cs
View File

@ -26,9 +26,6 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
RAMPaged = 0;
PagingDisabled = false;
// init addressable memory from ROM and RAM banks
ReInitMemory();
ULADevice = new ULAPlus3(this);
BuzzerDevice = new Buzzer(this);

3
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum16K/ZX16.cs
View File

@ -119,7 +119,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
WriteBus(addr, value);
}
/*
public override void ReInitMemory()
{
if (Memory.ContainsKey(0))
@ -132,6 +132,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
else
Memory.Add(1, RAM1);
}
*/
/// <summary>
/// Sets up the ROM

35
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.Memory.cs
View File

@ -42,11 +42,18 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
public override byte ReadBus(ushort addr)
{
int divisor = addr / 0x4000;
var index = addr % 0x4000;
// paging logic goes here
var bank = Memory[divisor];
var index = addr % 0x4000;
return bank[index];
switch (divisor)
{
case 0: return ROM0[index];
case 1: return RAM0[index];
case 2: return RAM1[index];
case 3: return RAM2[index];
default: return 0;
}
}
/// <summary>
@ -58,11 +65,25 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
public override void WriteBus(ushort addr, byte value)
{
int divisor = addr / 0x4000;
var index = addr % 0x4000;
// paging logic goes here
var bank = Memory[divisor];
var index = addr % 0x4000;
bank[index] = value;
switch (divisor)
{
case 0:
// cannot write to ROM
break;
case 1:
RAM0[index] = value;
break;
case 2:
RAM1[index] = value;
break;
case 3:
RAM2[index] = value;
break;
}
// update ULA screen buffer if necessary
if ((addr & 49152) == 16384 && _render)
@ -100,6 +121,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
WriteBus(addr, value);
}
/*
public override void ReInitMemory()
{
if (Memory.ContainsKey(0))
@ -127,6 +149,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
else
Memory.Add(4, RAM3);
}
*/
/// <summary>
/// Sets up the ROM

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.ULA.cs
View File

@ -57,7 +57,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{
contentionStartPeriod = 14335; // + LateTiming;
contentionEndPeriod = contentionStartPeriod + (ScreenHeight * TstatesPerScanline);
screen = _machine.Memory[1];
screen = _machine.RAM0;
screenByteCtr = DisplayStart;
ULAByteCtr = 0;
actualULAStart = 14340 - 24 - (TstatesPerScanline * BorderTopHeight);// + LateTiming;

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.cs
View File

@ -21,8 +21,6 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
Spectrum = spectrum;
CPU = cpu;
ReInitMemory();
ULADevice = new ULA48(this);
BuzzerDevice = new Buzzer(this);

6
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/ZXSpectrum.IMemoryDomains.cs
View File

@ -45,8 +45,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
}
private void SyncAllByteArrayDomains()
{
{
SyncByteArrayDomain("ROM0", _machine.ROM0);
SyncByteArrayDomain("ROM1", _machine.ROM1);
SyncByteArrayDomain("ROM2", _machine.ROM2);
@ -58,8 +57,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
SyncByteArrayDomain("RAM4", _machine.RAM4);
SyncByteArrayDomain("RAM5", _machine.RAM5);
SyncByteArrayDomain("RAM6", _machine.RAM6);
SyncByteArrayDomain("RAM7", _machine.RAM7);
SyncByteArrayDomain("RAM7", _machine.RAM7);
}
private void SyncByteArrayDomain(string name, byte[] data)

2
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/ZXSpectrum.IStatable.cs
View File

@ -53,12 +53,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
_cpu.SyncState(ser);
ser.BeginSection("ZXSpectrum");
//_cpu.SyncState(ser);
_machine.SyncState(ser);
ser.Sync("Frame", ref _machine.FrameCount);
ser.Sync("LagCount", ref _lagCount);
ser.Sync("IsLag", ref _isLag);
//ser.Sync("_memoryDomainsInit", ref _memoryDomainsInit);
ser.EndSection();