Some progress on mapper 83
loads the 128 k PRG games, with some CHR bugs
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alyosha-tas
GitHub
parent
7d644b4a10
commit
1f484854a9
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@ -8,12 +8,15 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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// http://problemkaputt.de/everynes.htm#mapper83cony
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public class ConyA : NES.NESBoardBase
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{
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private ByteBuffer chr_regs = new ByteBuffer(8);
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private ByteBuffer prg_regs = new ByteBuffer(4);
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private ByteBuffer low = new ByteBuffer(4); // some kind of security feature?
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private ByteBuffer chr_regs = new ByteBuffer(8);
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private int prg_mask_8k;
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private int prg_bank_mask_16k, prg_bank_mask_8k, chr_bank_mask_2k;
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private int IRQCount;
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private bool IRQa, IRQ_enable;
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private bool IRQa;
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private byte bank, mode;
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private bool is_2k_bank, is_not_2k_bank;
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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@ -22,12 +25,13 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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case "MAPPER083":
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if (Cart.prg_size == 128)
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{
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prg_mask_8k = Cart.prg_size / 8 - 1;
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prg_regs[0] = 0xC;
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prg_regs[1] = 0xB;
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prg_regs[2] = 0xE;
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prg_regs[3] = 0xF;
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prg_bank_mask_8k = Cart.prg_size / 8 - 1;
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prg_bank_mask_16k = Cart.prg_size / 16 - 1;
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chr_bank_mask_2k = 127;
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//prg_regs[0] = 0xC;
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//prg_regs[1] = 0xB;
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//prg_regs[2] = 0xE;
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//prg_regs[3] = 0xF;
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return true;
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}
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return false;
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@ -39,71 +43,125 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("chr_regs", ref chr_regs);
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ser.Sync("prg_regs", ref prg_regs);
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ser.Sync("chr_regs", ref chr_regs);
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ser.Sync("IRQCount", ref IRQCount);
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ser.Sync("IRQa", ref IRQa);
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ser.Sync("bank", ref bank);
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ser.Sync("mode", ref mode);
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ser.Sync("is_2k_bank", ref is_2k_bank);
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ser.Sync("is_not_2k_bank", ref is_not_2k_bank);
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}
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public void Mirroring()
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{
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switch (mode & 3)
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{
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case 0: SetMirrorType(EMirrorType.Vertical); break;
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case 1: SetMirrorType(EMirrorType.Horizontal); break;
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case 2: SetMirrorType(EMirrorType.OneScreenA); break;
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case 3: SetMirrorType(EMirrorType.OneScreenB); break;
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}
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}
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public override void WritePRG(int addr, byte value)
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{
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if (addr == 0x100)
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switch (addr)
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{
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IRQ_enable = value.Bit(7);
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}
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case 0x0000: is_2k_bank = true; bank = value; mode |= 0x40; break;
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case 0x3000:
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case 0x30FF:
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case 0x31FF:
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bank = value;
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mode |= 0x40;
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break;
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if (addr == 0x200)
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{
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IRQCount &= 0xFF00; IRQCount |= value; ;
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case 0x0100: mode = (byte)(value | (mode & 0x40)); break;
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case 0x0300: prg_regs[0] = value; mode &= 0xBF; break;
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case 0x0301: prg_regs[1] = value; mode &= 0xBF; break;
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case 0x0302: prg_regs[2] = value; mode &= 0xBF; break;
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// used in 1k CHR bank switching
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case 0x0312: chr_regs[2] = value; is_not_2k_bank = true; break;
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case 0x0313: chr_regs[3] = value; is_not_2k_bank = true; break;
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case 0x0314: chr_regs[4] = value; is_not_2k_bank = true; break;
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case 0x0315: chr_regs[5] = value; is_not_2k_bank = true; break;
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// used in 1k and 2k CHR bank switching
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case 0x0310: chr_regs[0] = value; break;
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case 0x0311: chr_regs[1] = value; break;
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case 0x0316: chr_regs[6] = value; break;
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case 0x0317: chr_regs[7] = value; break;
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case 0x0200:
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IRQCount &= 0xFF00; IRQCount |= value;
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IRQSignal = false;
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}
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if (addr == 0x201)
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{
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break;
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case 0x0201:
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IRQCount &= 0xFF;
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IRQCount |= value << 8;
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IRQa = true;
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IRQa = mode.Bit(7);
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break;
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}
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if (addr >= 0x300 && addr <= 0x302)
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{
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prg_regs[addr & 0x3] = value;
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}
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if (addr >= 0x310 && addr < 0x318)
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{
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chr_regs[addr & 0x7] = value;
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}
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/* TODO
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B000h Select 256K ROM/ VROM Windows(upper two address bits)
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Bit0 - 3 Unknown
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Bit4,6 Bit0 of 256K Block Number
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Bit5,7 Bit1 of 256K Block Number
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Used values are 00h,50h,A0h,F0h.Other values could probably select
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separate 256K banks for ROM / VROM.The ROM selection also affects
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the "fixed" 16K at C000h - FFFFh(last bank in current 256K block).
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B0FFh Probably same as B000h
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B1FFh Probably same as B000h
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*/
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Mirroring();
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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if (is_2k_bank && !is_not_2k_bank)
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{
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int index = (addr >> 11) & 0x3;
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int bank = chr_regs[index];
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// indexes are numbered oddly for different bank switching schemes
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if (index == 2)
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bank = chr_regs[6];
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if (index == 3)
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bank = chr_regs[7];
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bank &= chr_bank_mask_2k;
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return VROM[(bank << 11) + (addr & 0x7FF)];
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}
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else
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{
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int index = (addr >> 10) & 0x7;
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int bank = chr_regs[index];
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bank |= ((bank & 0x30) << 4);
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bank &= 0xFF;
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return VROM[(bank << 10) + (addr & 0x3FF)];
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}
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}
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return base.ReadPPU(addr);
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}
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public override byte ReadPRG(int addr)
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{
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if ((mode & 0x40) > 0)
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{
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if (addr < 0x4000)
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{
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return ROM[(((bank & 0x7) & 0x3F) << 14) + (addr & 0x3FFF)];
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}
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return ROM[((((bank & 0x7) & 0x30) | 0x7) << 14) + (addr & 0x3FFF)];
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}
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else
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{
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int index = (addr >> 13) & 0x3;
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int bank = prg_regs[index] & prg_mask_8k;
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int bank = prg_regs[index];
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// last bank is fixed
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if (index == 3)
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bank = prg_bank_mask_8k;
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return ROM[(bank << 13) + (addr & 0x1FFF)];
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}
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}
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public override void ClockCPU()
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@ -114,10 +172,30 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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if (IRQCount == 0)
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{
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IRQCount = 0xFFFF;
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IRQSignal = IRQ_enable;
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IRQSignal = true;
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IRQa = false;
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}
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}
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}
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public override void WriteEXP(int addr, byte value)
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{
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if (addr >= 0x1100 && addr <= 0x1103)
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low[addr & 0x3] = value;
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else
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base.WriteEXP(addr, value);
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}
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public override byte ReadEXP(int addr)
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{
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if (addr == 0x1000)
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return (byte)((NES.DB & 0xFC) | 0);
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else if (addr >= 0x1100 && addr <= 0x1103)
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return low[addr & 0x3];
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else
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return base.ReadEXP(addr);
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}
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}
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public class ConyB : NES.NESBoardBase
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@ -158,6 +236,12 @@ namespace BizHawk.Emulation.Cores.Nintendo.NES
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base.SyncState(ser);
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ser.Sync("prg_regs", ref prg_regs);
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ser.Sync("chr_regs", ref chr_regs);
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ser.Sync("IRQCount", ref IRQCount);
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ser.Sync("IRQa", ref IRQa);
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ser.Sync("bank", ref bank);
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ser.Sync("mode", ref mode);
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ser.Sync("is_2k_bank", ref is_2k_bank);
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ser.Sync("is_not_2k_bank", ref is_not_2k_bank);
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}
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public void Mirroring()
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