diff --git a/BizHawk.Emulation.Cores/CPUs/LR35902/LR35902.cs b/BizHawk.Emulation.Cores/CPUs/LR35902/LR35902.cs index c49ae6b72c..8decc26e76 100644 --- a/BizHawk.Emulation.Cores/CPUs/LR35902/LR35902.cs +++ b/BizHawk.Emulation.Cores/CPUs/LR35902/LR35902.cs @@ -310,6 +310,7 @@ namespace BizHawk.Emulation.Common.Components.LR35902 { // call interrupt processor INTERRUPT_(); + Halt_bug_3 = false; } } else if (temp) @@ -324,15 +325,15 @@ namespace BizHawk.Emulation.Common.Components.LR35902 }); } halted = false; - if (OnExecFetch != null) OnExecFetch(RegPC); - if (TraceCallback != null && !CB_prefix) TraceCallback(State()); - - + if (is_GBC) { // extra 4 cycles for GBC if (Halt_bug_3) { + if (OnExecFetch != null) OnExecFetch(RegPC); + if (TraceCallback != null && !CB_prefix) TraceCallback(State()); + RegPC++; FetchInstruction(ReadMemory(RegPC)); Halt_bug_3 = false; @@ -348,7 +349,10 @@ namespace BizHawk.Emulation.Common.Components.LR35902 } } else - { + { + if (OnExecFetch != null) OnExecFetch(RegPC); + if (TraceCallback != null && !CB_prefix) TraceCallback(State()); + if (Halt_bug_3) { //special variant of halt bug where RegPC also isn't incremented post fetch diff --git a/BizHawk.Emulation.Cores/CPUs/LR35902/Tables_Direct.cs b/BizHawk.Emulation.Cores/CPUs/LR35902/Tables_Direct.cs index b7dd1ccb0e..b5e005948f 100644 --- a/BizHawk.Emulation.Cores/CPUs/LR35902/Tables_Direct.cs +++ b/BizHawk.Emulation.Cores/CPUs/LR35902/Tables_Direct.cs @@ -114,7 +114,7 @@ namespace BizHawk.Emulation.Common.Components.LR35902 // then a bug is triggered // With interrupts enabled, this runs the halt command twice // when they are disabled, it reads the next byte twice - if (!FlagI) { Halt_bug_2 = true; } + if (!FlagI ||(FlagI && !interrupts_enabled)) { Halt_bug_2 = true; } } }