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z80: IORQ signal interrupt acknowledge

This commit is contained in:
alyosha-tas 2018-09-30 12:21:47 -05:00 committed by GitHub
parent 7ba4e8a437
commit 19a25e55fb
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2 changed files with 11 additions and 12 deletions
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18
BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs
View File

@ -64,8 +64,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
cur_instr = new ushort[] cur_instr = new ushort[]
{IDLE, {IDLE,
IDLE, IDLE,
IDLE, IORQ,
IDLE, WAIT,
IDLE, IDLE,
WAIT, WAIT,
RD_INC, ALU, PCl, PCh }; RD_INC, ALU, PCl, PCh };
@ -73,8 +73,6 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0 }; BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0 };
MEMRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0 }; MEMRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0 };
IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 1 }; IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 1 };
IRQACKCallback();
} }
// Just jump to $0038 // Just jump to $0038
@ -83,8 +81,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
cur_instr = new ushort[] cur_instr = new ushort[]
{IDLE, {IDLE,
IDLE, IDLE,
IDLE, IORQ,
IDLE, WAIT,
IDLE, IDLE,
TR, ALU, PCl, TR, ALU, PCl,
DEC16, SPl, SPh, DEC16, SPl, SPh,
@ -98,8 +96,6 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
BUSRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 }; BUSRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 };
MEMRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 }; MEMRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0 };
IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }; IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
IRQACKCallback();
} }
// Interrupt mode 2 uses the I vector combined with a byte on the data bus // Interrupt mode 2 uses the I vector combined with a byte on the data bus
@ -108,8 +104,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
cur_instr = new ushort[] cur_instr = new ushort[]
{IDLE, {IDLE,
IDLE, IDLE,
IDLE, IORQ,
IDLE, WAIT,
FTCH_DB, FTCH_DB,
IDLE, IDLE,
DEC16, SPl, SPh, DEC16, SPl, SPh,
@ -129,8 +125,6 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
BUSRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0 ,0 }; BUSRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0 ,0 };
MEMRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0 }; MEMRQ = new ushort[] { 0, 0, 0, 0, I, 0, 0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, W, 0, 0 };
IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }; IRQS = new ushort[] { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 };
IRQACKCallback();
} }
private void ResetInterrupts() private void ResetInterrupts()

5
BizHawk.Emulation.Cores/CPUs/Z80A/Z80A.cs
View File

@ -87,6 +87,7 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
public const ushort IN_INC = 72; public const ushort IN_INC = 72;
public const ushort WR_INC_WA = 73; // A -> W after WR_INC public const ushort WR_INC_WA = 73; // A -> W after WR_INC
public const ushort RD_OP = 74; public const ushort RD_OP = 74;
public const ushort IORQ = 75;
// non-state variables // non-state variables
public ushort Ztemp1, Ztemp2, Ztemp3, Ztemp4; public ushort Ztemp1, Ztemp2, Ztemp3, Ztemp4;
@ -627,6 +628,10 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
I_skip = true; I_skip = true;
} }
break; break;
case IORQ:
IRQACKCallback();
break;
} }
if (I_skip) if (I_skip)