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68000: implement AND, OR, EOR. Fix interrupt bug. Fix bug with SR register

This commit is contained in:
beirich 2011-10-08 19:57:22 +00:00
parent ccea71e74d
commit 18de3c9efc
11 changed files with 424 additions and 147 deletions
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7
BizHawk.Emulation/CPUs/68000/Diassembler.cs
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@ -1,6 +1,6 @@
using System.Text; using System.Text;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
public class DisassemblyInfo public class DisassemblyInfo
{ {
@ -42,6 +42,11 @@ namespace BizHawk.Emulation.CPUs.M68K
else if (Opcodes[op] == ROLd) ROLd_Disasm(info); else if (Opcodes[op] == ROLd) ROLd_Disasm(info);
else if (Opcodes[op] == RORd) RORd_Disasm(info); else if (Opcodes[op] == RORd) RORd_Disasm(info);
else if (Opcodes[op] == SWAP) SWAP_Disasm(info); else if (Opcodes[op] == SWAP) SWAP_Disasm(info);
else if (Opcodes[op] == AND0) AND0_Disasm(info);
else if (Opcodes[op] == AND1) AND1_Disasm(info);
else if (Opcodes[op] == EOR) EOR_Disasm(info);
else if (Opcodes[op] == OR0) OR0_Disasm(info);
else if (Opcodes[op] == OR1) OR1_Disasm(info);
else if (Opcodes[op] == JMP) JMP_Disasm(info); else if (Opcodes[op] == JMP) JMP_Disasm(info);
else if (Opcodes[op] == JSR) JSR_Disasm(info); else if (Opcodes[op] == JSR) JSR_Disasm(info);

536
BizHawk.Emulation/CPUs/68000/Instructions/BitArithemetic.cs
View File

@ -1,14 +1,150 @@
using System; using System;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {
void ANDI() // AND immediate void AND0() // AND <ea>, Dn
{ {
int size = ((op >> 6) & 0x03); int dstReg = (op >> 9) & 0x07;
int dstMode = ((op >> 3) & 0x07); int size = (op >> 6) & 0x03;
int dstReg = (op & 0x07); int srcMode = (op >> 3) & 0x07;
int srcReg = op & 0x07;
V = false;
C = false;
switch (size)
{
case 0: // Byte
D[dstReg].s8 &= ReadValueB(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 4 : 8 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s8 & 0x80) != 0;
Z = (D[dstReg].s8 == 0);
return;
case 1: // Word
D[dstReg].s16 &= ReadValueW(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 4 : 8 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s16 & 0x8000) != 0;
Z = (D[dstReg].s16 == 0);
return;
case 2: // Long
D[dstReg].s32 &= ReadValueL(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 8 : 12 + EACyclesL[srcMode, srcReg];
N = (D[dstReg].s32 & 0x80000000) != 0;
Z = (D[dstReg].s32 == 0);
return;
}
}
void AND0_Disasm(DisassemblyInfo info)
{
int dstReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int srcMode = (op >> 3) & 0x07;
int srcReg = op & 0x07;
int pc = info.PC + 2;
switch (size)
{
case 0: // Byte
info.Mnemonic = "and.b";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 1, ref pc), dstReg);
break;
case 1: // Word
info.Mnemonic = "and.w";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 2, ref pc), dstReg);
break;
case 2: // Long
info.Mnemonic = "and.l";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 4, ref pc), dstReg);
break;
}
info.Length = pc - info.PC;
}
void AND1() // AND Dn, <ea>
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
V = false;
C = false;
throw new NotTestedException();
switch (size)
{
case 0: // Byte
{
sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest & D[srcReg].s8);
WriteValueB(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0;
Z = (value == 0);
return;
}
case 1: // Word
{
short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest & D[srcReg].s16);
WriteValueW(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0;
Z = (value == 0);
return;
}
case 2: // Long
{
int dest = PeekValueL(dstMode, dstReg);
int value = dest & D[srcReg].s32;
WriteValueL(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0;
Z = (value == 0);
return;
}
}
}
void AND1_Disasm(DisassemblyInfo info)
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
int pc = info.PC + 2;
switch (size)
{
case 0: // Byte
info.Mnemonic = "and.b";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
break;
case 1: // Word
info.Mnemonic = "and.w";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
break;
case 2: // Long
info.Mnemonic = "and.l";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
break;
}
info.Length = pc - info.PC;
}
void ANDI() // ANDI #<data>, <ea>
{
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
V = false; V = false;
C = false; C = false;
@ -17,9 +153,9 @@ namespace BizHawk.Emulation.CPUs.M68K
{ {
case 0: // Byte case 0: // Byte
{ {
sbyte imm = (sbyte) ReadWord(PC); PC += 2; sbyte imm = (sbyte)ReadWord(PC); PC += 2;
sbyte arg = PeekValueB(dstMode, dstReg); sbyte arg = PeekValueB(dstMode, dstReg);
sbyte result = (sbyte) (imm & arg); sbyte result = (sbyte)(imm & arg);
WriteValueB(dstMode, dstReg, result); WriteValueB(dstMode, dstReg, result);
PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesBW[dstMode, dstReg]; PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesBW[dstMode, dstReg];
N = (result & 0x80) != 0; N = (result & 0x80) != 0;
@ -30,7 +166,7 @@ namespace BizHawk.Emulation.CPUs.M68K
{ {
short imm = ReadWord(PC); PC += 2; short imm = ReadWord(PC); PC += 2;
short arg = PeekValueW(dstMode, dstReg); short arg = PeekValueW(dstMode, dstReg);
short result = (short) (imm & arg); short result = (short)(imm & arg);
WriteValueW(dstMode, dstReg, result); WriteValueW(dstMode, dstReg, result);
PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesBW[dstMode, dstReg]; PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesBW[dstMode, dstReg];
N = (result & 0x8000) != 0; N = (result & 0x8000) != 0;
@ -53,9 +189,9 @@ namespace BizHawk.Emulation.CPUs.M68K
void ANDI_Disasm(DisassemblyInfo info) void ANDI_Disasm(DisassemblyInfo info)
{ {
int size = ((op >> 6) & 0x03); int size = ((op >> 6) & 0x03);
int dstMode = ((op >> 3) & 0x07); int dstMode = ((op >> 3) & 0x07);
int dstReg = (op & 0x07); int dstReg = (op & 0x07);
int pc = info.PC + 2; int pc = info.PC + 2;
@ -90,13 +226,221 @@ namespace BizHawk.Emulation.CPUs.M68K
info.Length = pc - info.PC; info.Length = pc - info.PC;
} }
void EOR() // EOR Dn, <ea>
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
V = false;
C = false;
switch (size)
{
case 0: // Byte
{
sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest ^ D[srcReg].s8);
WriteValueB(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0;
Z = (value == 0);
return;
}
case 1: // Word
{
short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest ^ D[srcReg].s16);
WriteValueW(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0;
Z = (value == 0);
return;
}
case 2: // Long
{
int dest = PeekValueL(dstMode, dstReg);
int value = dest ^ D[srcReg].s32;
WriteValueL(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0;
Z = (value == 0);
return;
}
}
}
void EOR_Disasm(DisassemblyInfo info)
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
int pc = info.PC + 2;
switch (size)
{
case 0: // Byte
info.Mnemonic = "eor.b";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
break;
case 1: // Word
info.Mnemonic = "eor.w";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
break;
case 2: // Long
info.Mnemonic = "eor.l";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
break;
}
info.Length = pc - info.PC;
}
void OR0() // OR <ea>, Dn
{
int dstReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int srcMode = (op >> 3) & 0x07;
int srcReg = op & 0x07;
V = false;
C = false;
switch (size)
{
case 0: // Byte
D[dstReg].s8 |= ReadValueB(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 4 : 8 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s8 & 0x80) != 0;
Z = (D[dstReg].s8 == 0);
return;
case 1: // Word
D[dstReg].s16 |= ReadValueW(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 4 : 8 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s16 & 0x8000) != 0;
Z = (D[dstReg].s16 == 0);
return;
case 2: // Long
D[dstReg].s32 |= ReadValueL(srcMode, srcReg);
PendingCycles -= (srcMode == 0) ? 8 : 12 + EACyclesL[srcMode, srcReg];
N = (D[dstReg].s32 & 0x80000000) != 0;
Z = (D[dstReg].s32 == 0);
return;
}
}
void OR0_Disasm(DisassemblyInfo info)
{
int dstReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int srcMode = (op >> 3) & 0x07;
int srcReg = op & 0x07;
int pc = info.PC + 2;
switch (size)
{
case 0: // Byte
info.Mnemonic = "or.b";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 1, ref pc), dstReg);
break;
case 1: // Word
info.Mnemonic = "or.w";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 2, ref pc), dstReg);
break;
case 2: // Long
info.Mnemonic = "or.l";
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 4, ref pc), dstReg);
break;
}
info.Length = pc - info.PC;
}
void OR1() // OR Dn, <ea>
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
V = false;
C = false;
switch (size)
{
case 0: // Byte
{
sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest | D[srcReg].s8);
WriteValueB(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0;
Z = (value == 0);
return;
}
case 1: // Word
{
short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest | D[srcReg].s16);
WriteValueW(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0;
Z = (value == 0);
return;
}
case 2: // Long
{
int dest = PeekValueL(dstMode, dstReg);
int value = dest | D[srcReg].s32;
WriteValueL(dstMode, dstReg, value);
PendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0;
Z = (value == 0);
return;
}
}
}
void OR1_Disasm(DisassemblyInfo info)
{
int srcReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03;
int dstMode = (op >> 3) & 0x07;
int dstReg = op & 0x07;
int pc = info.PC + 2;
switch (size)
{
case 0: // Byte
info.Mnemonic = "or.b";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
break;
case 1: // Word
info.Mnemonic = "or.w";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
break;
case 2: // Long
info.Mnemonic = "or.l";
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
break;
}
info.Length = pc - info.PC;
}
void ORI() void ORI()
{ {
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
V = C = false; V = false;
C = false;
switch (size) switch (size)
{ {
@ -135,7 +479,7 @@ namespace BizHawk.Emulation.CPUs.M68K
void ORI_Disasm(DisassemblyInfo info) void ORI_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
@ -168,94 +512,12 @@ namespace BizHawk.Emulation.CPUs.M68K
info.Length = pc - info.PC; info.Length = pc - info.PC;
} }
void OR()
{
throw new Exception();
/*int size = (op >> 6) & 3;
int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7;
V = C = false;
switch (size)
{
case 0: // byte
{
sbyte immed = (sbyte)ReadWord(PC); PC += 2;
sbyte value = (sbyte)(PeekValueB(mode, reg) | immed);
WriteValueB(mode, reg, value);
N = (value & 0x80) != 0;
Z = value == 0;
PendingCycles -= mode == 0 ? 8 : 12 + EACyclesBW[mode, reg];
return;
}
case 1: // word
{
short immed = ReadWord(PC); PC += 2;
short value = (short)(PeekValueW(mode, reg) | immed);
WriteValueW(mode, reg, value);
N = (value & 0x8000) != 0;
Z = value == 0;
PendingCycles -= mode == 0 ? 8 : 12 + EACyclesBW[mode, reg];
return;
}
case 2: // long
{
int immed = ReadLong(PC); PC += 4;
int value = PeekValueL(mode, reg) | immed;
WriteValueL(mode, reg, value);
N = (value & 0x80000000) != 0;
Z = value == 0;
PendingCycles -= mode == 0 ? 17 : 20 + EACyclesL[mode, reg];
return;
}
}*/
}
void OR_Disasm(DisassemblyInfo info)
{
int pc = info.PC + 2;
int dReg = (op >> 9) & 3;
int d = (op >> 8) & 1;
int size = (op >> 6) & 3;
int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7;
switch (size)
{
case 0: // byte
{
info.Mnemonic = "ori.b";
sbyte immed = (sbyte)ReadWord(pc); pc += 2;
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 1, ref pc));
break;
}
case 1: // word
{
info.Mnemonic = "ori.w";
short immed = ReadWord(pc); pc += 2;
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 2, ref pc));
break;
}
case 2: // long
{
info.Mnemonic = "ori.l";
int immed = ReadLong(pc); pc += 4;
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 4, ref pc));
break;
}
}
info.Length = pc - info.PC;
}
void LSLd() void LSLd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -300,11 +562,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void LSLd_Disasm(DisassemblyInfo info) void LSLd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
@ -322,10 +584,10 @@ namespace BizHawk.Emulation.CPUs.M68K
void LSRd() void LSRd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -370,11 +632,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void LSRd_Disasm(DisassemblyInfo info) void LSRd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
@ -392,10 +654,10 @@ namespace BizHawk.Emulation.CPUs.M68K
void ASLd() void ASLd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -440,11 +702,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void ASLd_Disasm(DisassemblyInfo info) void ASLd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
@ -462,10 +724,10 @@ namespace BizHawk.Emulation.CPUs.M68K
void ASRd() void ASRd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -510,11 +772,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void ASRd_Disasm(DisassemblyInfo info) void ASRd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
@ -532,10 +794,10 @@ namespace BizHawk.Emulation.CPUs.M68K
void ROLd() void ROLd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -580,11 +842,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void ROLd_Disasm(DisassemblyInfo info) void ROLd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
@ -602,10 +864,10 @@ namespace BizHawk.Emulation.CPUs.M68K
void RORd() void RORd()
{ {
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D[rot].s32 & 63;
@ -650,11 +912,11 @@ namespace BizHawk.Emulation.CPUs.M68K
void RORd_Disasm(DisassemblyInfo info) void RORd_Disasm(DisassemblyInfo info)
{ {
int pc = info.PC + 2; int pc = info.PC + 2;
int rot = (op >> 9) & 7; int rot = (op >> 9) & 7;
int size = (op >> 6) & 3; int size = (op >> 6) & 3;
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;

2
BizHawk.Emulation/CPUs/68000/Instructions/DataMovement.cs
View File

@ -1,7 +1,7 @@
using System; using System;
using System.Text; using System.Text;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

2
BizHawk.Emulation/CPUs/68000/Instructions/IntegerMath.cs
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@ -1,6 +1,6 @@
using System; using System;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

2
BizHawk.Emulation/CPUs/68000/Instructions/ProgramFlow.cs
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@ -1,7 +1,7 @@
 
using System; using System;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

2
BizHawk.Emulation/CPUs/68000/Instructions/Supervisor.cs
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@ -1,6 +1,6 @@
using System; using System;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

4
BizHawk.Emulation/CPUs/68000/M68000.cs
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@ -1,7 +1,7 @@
using System; using System;
using System.Runtime.InteropServices; using System.Runtime.InteropServices;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
public sealed partial class MC68000 public sealed partial class MC68000
{ {
@ -38,6 +38,7 @@ namespace BizHawk.Emulation.CPUs.M68K
Console.WriteLine("&^&^&^&^& LEAVE SUPERVISOR MODE"); Console.WriteLine("&^&^&^&^& LEAVE SUPERVISOR MODE");
ssp = A[7].s32; ssp = A[7].s32;
A[7].s32 = usp; A[7].s32 = usp;
s = false;
} }
} }
} }
@ -135,6 +136,7 @@ namespace BizHawk.Emulation.CPUs.M68K
A[7].s32 -= 2; // Push SR on stack A[7].s32 -= 2; // Push SR on stack
WriteLong(A[7].s32, sr); WriteLong(A[7].s32, sr);
PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector
InterruptMaskLevel = Interrupt; // Set interrupt mask to level currently being entered
Interrupt = 0; // "ack" interrupt. Note: this is wrong. Interrupt = 0; // "ack" interrupt. Note: this is wrong.
} }

2
BizHawk.Emulation/CPUs/68000/Memory.cs
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@ -1,6 +1,6 @@
using System; using System;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

8
BizHawk.Emulation/CPUs/68000/OpcodeTable.cs
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@ -1,7 +1,7 @@
using System; using System;
using System.Collections.Generic; using System.Collections.Generic;
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {
@ -33,7 +33,11 @@ namespace BizHawk.Emulation.CPUs.M68K
Assign("rol", ROLd, "1110", "Data3", "1", "Size2_1", "Data1", "11", "Xn"); Assign("rol", ROLd, "1110", "Data3", "1", "Size2_1", "Data1", "11", "Xn");
Assign("ror", RORd, "1110", "Data3", "0", "Size2_1", "Data1", "11", "Xn"); Assign("ror", RORd, "1110", "Data3", "0", "Size2_1", "Data1", "11", "Xn");
Assign("swap", SWAP, "0100100001000","Xn"); Assign("swap", SWAP, "0100100001000","Xn");
//Assign("or", OR, "1000", "Xn", "Data1","Size2_1", "AmXn"); Assign("and", AND0, "1100", "Xn", "0", "Size2_1", "AmXn");
Assign("and", AND1, "1100", "Xn", "1", "Size2_1", "AmXn");
Assign("eor", EOR, "1011", "Xn", "1", "Size2_1", "AmXn");
Assign("or", OR0, "1000", "Xn", "0", "Size2_1", "AmXn");
Assign("or", OR1, "1000", "Xn", "1", "Size2_1", "AmXn");
Assign("jmp", JMP, "0100111011", "AmXn"); Assign("jmp", JMP, "0100111011", "AmXn");
Assign("jsr", JSR, "0100111010", "AmXn"); Assign("jsr", JSR, "0100111010", "AmXn");

2
BizHawk.Emulation/CPUs/68000/Tables.cs
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@ -1,4 +1,4 @@
namespace BizHawk.Emulation.CPUs.M68K namespace BizHawk.Emulation.CPUs.M68000
{ {
partial class MC68000 partial class MC68000
{ {

4
BizHawk.Emulation/Util.cs
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@ -1094,4 +1094,8 @@ namespace BizHawk
} }
} }
} }
public class NotTestedException : Exception
{
}
} }