From 138a2bcef5eab03978f5bde0a065c591e5da222e Mon Sep 17 00:00:00 2001 From: alyosha-tas Date: Mon, 11 Nov 2019 22:19:41 -0500 Subject: [PATCH] O2Hawk: Finish disasm, start execution --- .../CPUs/Intel8048/Disassembler.cs | 420 +++++++++--------- .../CPUs/Intel8048/Execute.cs | 20 +- .../CPUs/Intel8048/I8048.cs | 84 ++-- .../CPUs/Intel8048/OP_Tables.cs | 4 +- .../CPUs/Intel8048/Operations.cs | 40 -- .../CPUs/Intel8048/Registers.cs | 58 +-- 6 files changed, 305 insertions(+), 321 deletions(-) diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/Disassembler.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/Disassembler.cs index dc21ab5a2f..4ab7b0d953 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/Disassembler.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/Disassembler.cs @@ -56,214 +56,214 @@ namespace BizHawk.Emulation.Common.Components.I8048 "XCH A,R5", // 2d "XCH A,R6", // 2e "XCH A,R7", // 2f - "LEAX ix16", // 30 - "LEAY ix16", // 31 - "LEAS ix16", // 32 - "LEAU ix16", // 33 - "PSHS i8", // 34 - "PULS i8", // 35 - "PSHU i8", // 36 - "PULU i8", // 37 + "XCHD A,@R0", // 30 + "XCHD A,@R1", // 31 + "JPB 1", // 32 + "???", // 33 + "CALL 1", // 34 + "DN", // 35 + "JP T0", // 36 + "COM A", // 37 "???", // 38 - "RTS", // 39 - "ABX", // 3a - "RTI", // 3b - "CWAI i8", // 3c - "MUL", // 3d - "???", // 3e - "SWI1", // 3f - "NEG A", // 40 - "???", // 41 - "???", // 42 - "COM A", // 43 - "LSR A", // 44 - "???", // 45 - "ROR A", // 46 - "ASR A", // 47 - "ASL A", // 48 - "ROL A", // 49 - "DEC A", // 4a - "???", // 4b - "INC A", // 4c - "TST A", // 4d - "???", // 4e - "CLR A", // 4f - "NEG B", // 50 - "???", // 51 - "???", // 52 - "COM B", // 53 - "LSR B", // 54 - "???", // 55 - "ROR B", // 56 - "ASR B", // 57 - "ASL B", // 58 - "ROL B", // 59 - "DEC B", // 5a - "???", // 5b - "INC B", // 5c - "TST B", // 5d - "???", // 5e - "CLR B", // 5f - "NEG ix16", // 60 - "???", // 61 - "???", // 62 - "COM ix16", // 63 - "LSR ix16", // 64 - "???", // 65 - "ROR ix16", // 66 - "ASR ix16", // 67 - "ASL ix16", // 68 - "ROL ix16", // 69 - "DEC ix16", // 6a - "???", // 6b - "INC ix16", // 6c - "TST ix16", // 6d - "JMP ix16", // 6e - "CLR ix16", // 6f - "NEG ex16", // 70 - "???", // 71 - "???", // 72 - "COM ex16", // 73 - "LSR ex16", // 74 - "???", // 75 - "ROR ex16", // 76 - "ASR ex16", // 77 - "ASL ex16", // 78 - "ROL ex16", // 79 - "DEC ex16", // 7a - "???", // 7b - "INC ex16", // 7c - "TST ex16", // 7d - "JMP ex16", // 7e - "CLR ex16", // 7f - "SUB A,i8", // 80 - "CMP A,i8", // 81 - "SBC A,i8", // 82 - "SUB D,i16", // 83 - "AND A,i8", // 84 - "BIT A,i8", // 85 - "LD A,i8", // 86 + "OUT P1", // 39 + "OUT P2", // 3a + "???", // 3b + "MOV P4,A", // 3c + "MOV P5,A", // 3d + "MOV P6,A", // 3e + "MOV P7,A", // 3f + "OR A,@R0", // 40 + "OR A,@R1", // 41 + "MOV A,TIM", // 42 + "OR A,i8", // 43 + "JP 2K 2", // 44 + "START CNT", // 45 + "JP NT1", // 46 + "SWP", // 47 + "OR A,R0", // 48 + "OR A,R1", // 49 + "OR A,R2", // 4a + "OR A,R3", // 4b + "OR A,R4", // 4c + "OR A,R5", // 4d + "OR A,R6", // 4e + "OR A,R7", // 4f + "AND A,@R0", // 50 + "AND A,@R1", // 51 + "JPB 2", // 52 + "AND A,i8", // 53 + "CALL 2", // 54 + "START TIM", // 55 + "JP T1", // 56 + "DAA", // 57 + "AND A,R0", // 58 + "AND A,R1", // 59 + "AND A,R2", // 5a + "AND A,R3", // 5b + "AND A,R4", // 5c + "AND A,R5", // 5d + "AND A,R6", // 5e + "AND A,R7", // 5f + "ADD A,@R0", // 60 + "ADD A,@R1", // 61 + "MOV TIM,A", // 62 + "???", // 63 + "JP 2K 3", // 64 + "STOP CNT", // 65 + "???", // 66 + "RRC", // 67 + "ADD A,R0", // 68 + "ADD A,R1", // 69 + "ADD A,R2", // 6a + "ADD A,R3", // 6b + "ADD A,R4", // 6c + "ADD A,R5", // 6d + "ADD A,R6", // 6e + "ADD A,R7", // 6f + "ADC A,@R0", // 70 + "ADC A,@R1", // 71 + "JPB 3", // 72 + "???", // 73 + "CALL 3", // 74 + "ENT0 CLK", // 75 + "JP F1", // 76 + "ROR", // 77 + "ADC A,R0", // 78 + "ADC A,R1", // 79 + "ADC A,R2", // 7a + "ADC A,R3", // 7b + "ADC A,R4", // 7c + "ADC A,R5", // 7d + "ADC A,R6", // 7e + "ADC A,R7", // 7f + "MOVX A,@R0", // 80 + "MOVX A,@R1", // 81 + "???", // 82 + "RET", // 83 + "JP 2K 4", // 84 + "CLR F0", // 85 + "JP !IRQ", // 86 "???", // 87 - "EOR A,i8", // 88 - "ADC A,i8", // 89 - "OR A,i8", // 8a - "ADD A,i8", // 8b - "CMP X,i16", // 8c - "BSR i8", // 8d - "LD X,i16", // 8e - "???", // 8f - "SUB A,DP+i8", // 90 - "CMP A,DP+i8", // 91 - "SBC A,DP+i8", // 92 - "SUB D,DP+i8", // 93 - "AND A,DP+i8", // 94 - "BIT A,DP+i8", // 95 - "LD A,DP+i8", // 96 - "ST A,DP+i8", // 97 - "EOR A,DP+i8", // 98 - "ADC A,DP+i8", // 99 - "OR A,DP+i8", // 9a - "ADD A,DP+i8", // 9b - "CMP X,DP+i8", // 9c - "JSR DP+i8", // 9d - "LD X,DP+i8", // 9e - "ST X,DP+i8", // 9f - "SUB A,ix16", // a0 - "CMP A,ix16", // a1 - "SBC A,ix16", // a2 - "SUB D,ix16", // a3 - "AND A,ix16", // a4 - "BIT A,ix16", // a5 - "LD A,ix16", // a6 - "ST A,ix16", // a7 - "EOR A,ix16", // a8 - "ADC A,ix16", // a9 - "OR A,ix16", // aa - "ADD A,ix16", // ab - "CMP X,ix16", // ac - "JSR ix16", // ad - "LD X,ix16", // ae - "ST X,ix16", // af - "SUB A,ex16", // b0 - "CMP A,ex16", // b1 - "SBC A,ex16", // b2 - "SUB D,ex16", // b3 - "AND A,ex16", // b4 - "BIT A,ex16", // b5 - "LD A,ex16", // b6 - "ST A,ex16", // b7 - "EOR A,ex16", // b8 - "ADC A,ex16", // b9 - "OR A,ex16", // ba - "ADD A,ex16", // bb - "CMP X,ex16", // bc - "JSR ex16", // bd - "LD X,ex16", // be - "ST X,ex16", // bf - "SUB B,i8", // c0 - "CMP B,i8", // c1 - "SBC B,i8", // c2 - "ADD D,i16", // c3 - "AND B,i8", // c4 - "BIT B,i8", // c5 - "LD B,i8", // c6 - "???", // c7 - "EOR B,i8", // c8 - "ADC B,i8", // c9 - "OR B,i8", // ca - "ADD B,i8", // cb - "LD D,i16", // cc - "???", // cd - "LD U,i16", // ce - "???", // cf - "SUB B,DP+i8", // d0 - "CMP B,DP+i8", // d1 - "SBC B,DP+i8", // d2 - "ADD D,DP+i8", // d3 - "AND B,DP+i8", // d4 - "BIT B,DP+i8", // d5 - "LD B,DP+i8", // d6 - "ST B,DP+i8", // d7 - "EOR B,DP+i8", // d8 - "ADC B,DP+i8", // d9 - "OR B,DP+i8", // da - "ADD B,DP+i8", // db - "LD D,DP+i8", // dc - "ST D,DP+i8", // dd - "LD U,DP+i8", // de - "ST U,DP+i8", // df - "SUB B,ix16", // e0 - "CMP B,ix16", // e1 - "SBC B,ix16", // e2 - "ADD D,ix16", // e3 - "AND B,ix16", // e4 - "BIT B,ix16", // e5 - "LD B,ix16", // e6 - "ST B,ix16", // e7 - "EOR B,ix16", // e8 - "ADC B,ix16", // e9 - "OR B,ix16", // ea - "ADD B,ix16", // eb - "LD D,ix16", // ec - "ST D,ix16", // ed - "LD U,ix16", // ee - "ST U,ix16", // ef - "SUB B,ex16", // f0 - "CMP B,ex16", // f1 - "SBC B,ex16", // f2 - "ADD D,ex16", // f3 - "AND B,ex16", // f4 - "BIT B,ex16", // f5 - "LD B,ex16", // f6 - "ST B,ex16", // f7 - "EOR B,ex16", // f8 - "ADC B,ex16", // f9 - "OR B,ex16", // fa - "ADD B,ex16", // fb - "LD D,ex16", // fc - "ST D,ex16", // fd - "LD U,ex16", // fe - "ST U,ex16", // ff + "OR BUS,i8", // 88 + "OR P1,i8", // 89 + "OR P2,i8", // 8a + "???", // 8b + "OR P4,A", // 8c + "OR P5,A", // 8d + "OR P6,A", // 8e + "OR P7,A", // 8f + "MOVX @R0,A", // 90 + "MOVX @R1,A", // 91 + "JPB 4", // 92 + "RETR", // 93 + "CALL 4", // 94 + "COM F0", // 95 + "JP A!=0", // 96 + "CLR C", // 97 + "AND BUS,i8", // 98 + "AND P1,i8", // 99 + "AND P2,i8", // 9a + "???", // 9b + "AND P4,A", // 9c + "AND P5,A", // 9d + "AND P6,A", // 9e + "AND P7,A", // 9f + "MOV @R0,A", // a0 + "MOV @R1,A", // a1 + "???", // a2 + "MOV A,@A", // a3 + "JP 2K 5", // a4 + "CLR F1", // a5 + "???", // a6 + "COM C", // a7 + "MOV R0,A", // a8 + "MOV R1,A", // a9 + "MOV R2,A", // aa + "MOV R3,A", // ab + "MOV R4,A", // ac + "MOV R5,A", // ad + "MOV R6,A", // ae + "MOV R7,A", // af + "???", // b0 + "???", // b1 + "JPB 5", // b2 + "JPP A", // b3 + "CALL 5", // b4 + "COM F1", // b5 + "JP F0", // b6 + "???", // b7 + "MOV R0,i8", // b8 + "MOV R1,i8", // b9 + "MOV R2,i8", // ba + "MOV R3,i8", // bb + "MOV R4,i8", // bc + "MOV R5,i8", // bd + "MOV R6,i8", // be + "MOV R7,i8", // bf + "???", // c0 + "???", // c1 + "???", // c2 + "???", // c3 + "JP 2K 6", // c4 + "SEL RB 0", // c5 + "JP A==0", // c6 + "MOV A,PSW", // c7 + "DEC R0", // c8 + "DEC R1", // c9 + "DEC R2", // ca + "DEC R3", // cb + "DEC R4", // cc + "DEC R5", // cd + "DEC R6", // ce + "DEC R7", // cf + "XOR A,@R0", // d0 + "XOR A,@R1", // d1 + "JPB 6", // d2 + "XOR A,i8", // d3 + "CALL 6", // d4 + "SEL RB 1", // d5 + "???", // d6 + "MOV PSW,A", // d7 + "XOR A,R0", // d8 + "XOR A,R1", // d9 + "XOR A,R2", // da + "XOR A,R3", // db + "XOR A,R4", // dc + "XOR A,R5", // dd + "XOR A,R6", // de + "XOR A,R7", // df + "???", // e0 + "???", // e1 + "???", // e2 + "MOV3 A,@A", // e3 + "JP 2K 7", // e4 + "SEL MB 0", // e5 + "JP NC", // e6 + "ROL", // e7 + "DJNZ R0", // e8 + "DJNZ R1", // e9 + "DJNZ R2", // ea + "DJNZ R3", // eb + "DJNZ R4", // ec + "DJNZ R5", // ed + "DJNZ R6", // ee + "DJNZ R7", // ef + "MOV A,@R0", // f0 + "MOV A,@R1", // f1 + "JPB 7", // f2 + "???", // f3 + "CALL 7", // f4 + "SEL MB 1", // f5 + "JP C", // f6 + "RLC", // f7 + "MOV A,R0", // f8 + "MOV A,R1", // f9 + "MOV A,R2", // fa + "MOV A,R3", // fb + "MOV A,R4", // fc + "MOV A,R5", // fd + "MOV A,R6", // fe + "MOV A,R7" // ff }; public static string Disassemble(ushort addr, Func reader, out ushort size) @@ -280,14 +280,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 bytes.Add(d); result = result.Replace("i8", string.Format("#{0:X2}h", d)); } - else if (result.Contains("i16")) - { - byte dhi = reader(addr++); - byte dlo = reader(addr++); - bytes.Add(dhi); - bytes.Add(dlo); - result = result.Replace("i16", string.Format("#{0:X2}{1:X2}h", dhi, dlo)); - } StringBuilder ret = new StringBuilder(); ret.Append(string.Format("{0:X4}: ", origaddr)); diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/Execute.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/Execute.cs index bb3b9c7189..5b8c2c56a3 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/Execute.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/Execute.cs @@ -39,8 +39,8 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0x0D: MOV_A_P4(5); break; // MOV A,P5 case 0x0E: MOV_A_P4(6); break; // MOV A,P6 case 0x0F: MOV_A_P4(7); break; // MOV A,P7 - case 0x10: OP_A_R(INC_RAM, R0); break; // INC #,R0 - case 0x11: OP_A_R(INC_RAM, R1); break; // INC #,R1 + case 0x10: OP_A_R(INC_RAM, R0); break; // INC #,@R0 + case 0x11: OP_A_R(INC_RAM, R1); break; // INC #,@R1 case 0x12: JPB(0); break; // JPB 0 case 0x13: OP_A_DIR(ADC8); break; // ADC A,# case 0x14: CALL(0); break; // CALL @@ -62,7 +62,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0x24: JP_2k(1); break; // JP 2K 1 case 0x25: OP_IMP(EN); break; // EN case 0x26: JP_COND(!T0, IDLE); break; // JP NT0 - case 0x27: OP_IMP(CLR); break; // CLR A + case 0x27: OP_IMP(CLRA); break; // CLR A case 0x28: OP_A_R(XCH, R0); break; // XCH A,R0 case 0x29: OP_A_R(XCH, R1); break; // XCH A,R1 case 0x2A: OP_A_R(XCH, R2); break; // XCH A,R2 @@ -72,13 +72,13 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0x2E: OP_A_R(XCH, R6); break; // XCH A,R6 case 0x2F: OP_A_R(XCH, R7); break; // XCH A,R7 case 0x30: OP_A_R(XCHD_RAM, R0); break; // XCHD A,@R0 - case 0x31: OP_A_R(XCHD_RAM, R1); break; // XCHD A,@R0 + case 0x31: OP_A_R(XCHD_RAM, R1); break; // XCHD A,@R1 case 0x32: JPB(1); break; // JPB 1 case 0x33: ILLEGAL(); break; // ILLEGAL case 0x34: CALL(1); break; // CALL case 0x35: OP_IMP(DN); break; // DN case 0x36: JP_COND(T0, IDLE); break; // JP T0 - case 0x37: OP_IMP(COM); break; // COM A + case 0x37: OP_IMP(COMA); break; // COM A case 0x38: ILLEGAL(); break; // ILLEGAL case 0x39: OUT_P(1); break; // OUT P1,A case 0x3A: OUT_P(2); break; // OUT P2,A @@ -151,8 +151,8 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0x7D: OP_A_R(ADC8, R5); break; // ADC A,R5 case 0x7E: OP_A_R(ADC8, R6); break; // ADC A,R6 case 0x7F: OP_A_R(ADC8, R7); break; // ADC A,R7 - case 0x80: MOVX_A_R(0); break; // MOVX A,R0 - case 0x81: MOVX_A_R(1); break; // MOVX A,R1 + case 0x80: MOVX_A_R(0); break; // MOVX A,@R0 + case 0x81: MOVX_A_R(1); break; // MOVX A,@R1 case 0x82: ILLEGAL(); break; // ILLEGAL case 0x83: RET(); break; // RET case 0x84: JP_2k(4); break; // JP 2K 4 @@ -167,8 +167,8 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0x8D: OP_EXP_A(OR8, P5); break; // OR P5,A case 0x8E: OP_EXP_A(OR8, P6); break; // OR P6,A case 0x8F: OP_EXP_A(OR8, P7); break; // OR P7,A - case 0x90: MOVX_R_A(0); break; // MOVX R0,A - case 0x91: MOVX_R_A(1); break; // MOVX R1,A + case 0x90: MOVX_R_A(0); break; // MOVX @R0,A + case 0x91: MOVX_R_A(1); break; // MOVX @R1,A case 0x92: JPB(4); break; // JPB 4 case 0x93: RETR(); break; //RETR case 0x94: CALL(4); break; // CALL @@ -222,7 +222,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 case 0xC4: JP_2k(6); break; // JP 2K 6 case 0xC5: OP_IMP(SEL_RB0); break; // SEL RB 0 case 0xC6: JP_COND(Regs[A] == 0, IDLE); break; // JP (A == 0) - case 0xC7: MOV_R(A, PSW); break; // MOV A, PSW + case 0xC7: MOV_R(A, PSW); break; // MOV A,PSW case 0xC8: OP_R_IMP(DEC8, R0); break; // DEC R0 case 0xC9: OP_R_IMP(DEC8, R1); break; // DEC R1 case 0xCA: OP_R_IMP(DEC8, R2); break; // DEC R2 diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/I8048.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/I8048.cs index 463745bd8e..5c2be40a23 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/I8048.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/I8048.cs @@ -29,7 +29,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 public const ushort RLC = 18; public const ushort RRC = 19; public const ushort SWP = 20; - public const ushort COM = 21; + public const ushort COMA = 21; public const ushort CMC = 22; public const ushort CM0 = 23; public const ushort CM1 = 24; @@ -48,7 +48,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 public const ushort SET_ADDR = 37; public const ushort NEG = 38; public const ushort TST = 39; - public const ushort CLR = 40; + public const ushort CLRA = 40; public const ushort CLC = 41; public const ushort CL0 = 42; public const ushort CL1 = 43; @@ -56,7 +56,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 public const ushort EN = 45; public const ushort DI = 46; public const ushort DN = 47; - public const ushort TFR = 48; public const ushort ADD8BR = 49; public const ushort ABX = 50; public const ushort JPE = 51; @@ -66,7 +65,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 public const ushort ADD16 = 55; public const ushort CMP16 = 56; public const ushort CMP16D = 57; - public const ushort CLR_E = 63; public const ushort CLK_OUT = 64; public const ushort IN = 65; public const ushort OUT = 66; @@ -188,9 +186,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 case TR: TR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]); break; - case TFR: - TFR_Func(cur_instr[instr_pntr++]); - break; case SET_ADDR: reg_d_ad = cur_instr[instr_pntr++]; reg_h_ad = cur_instr[instr_pntr++]; @@ -204,11 +199,17 @@ namespace BizHawk.Emulation.Common.Components.I8048 case TST: TST_Func(cur_instr[instr_pntr++]); break; - case CLR: - CLR_Func(cur_instr[instr_pntr++]); + case CLRA: + Regs[A] = 0; break; - case CLR_E: - + case CLC: + FlagC = false; + break; + case CL0: + FlagF0 = false; + break; + case CL1: + F1 = false; break; case ADD16BR: ADD16BR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]); @@ -246,8 +247,17 @@ namespace BizHawk.Emulation.Common.Components.I8048 case ROR: ROR_Func(cur_instr[instr_pntr++]); break; - case COM: - COM_Func(cur_instr[instr_pntr++]); + case COMA: + Regs[A] = (ushort)((~Regs[A]) & 0xFF); + break; + case CMC: + FlagC = !FlagC; + break; + case CM0: + FlagF0 = !FlagF0; + break; + case CM1: + F1 = !F1; break; case DA: DA_Func(cur_instr[instr_pntr++]); @@ -283,7 +293,9 @@ namespace BizHawk.Emulation.Common.Components.I8048 break; case XCH: - + Regs[ALU] = Regs[cur_instr[instr_pntr]]; + Regs[cur_instr[instr_pntr++]] = Regs[cur_instr[instr_pntr]]; + Regs[cur_instr[instr_pntr++]] = Regs[ALU]; break; case XCH_RAM: @@ -298,10 +310,10 @@ namespace BizHawk.Emulation.Common.Components.I8048 break; case SEL_RB0: - + RB = 0; break; case SEL_RB1: - + RB = 24; break; case INC_RAM: @@ -310,7 +322,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 break; case MOV: - + Regs[cur_instr[instr_pntr++]] = Regs[cur_instr[instr_pntr++]]; break; case MOV_RAM: @@ -330,6 +342,19 @@ namespace BizHawk.Emulation.Common.Components.I8048 case ST_T: break; + case EI: + IntEn = true; + break; + case DI: + IntEn = false; + break; + case INCA: + INC8_Func(A); + break; + case DECA: + DEC8_Func(A); + break; + } if (++irq_pntr == IRQS) @@ -374,16 +399,16 @@ namespace BizHawk.Emulation.Common.Components.I8048 { Disassembly = $"{(disassemble ? Disassemble(Regs[PC], ReadMemory, out notused) : "---")} ".PadRight(50), RegisterInfo = string.Format( - "A:{0:X2} R0:{1:X2} R1:{2:X2} R2:{3:X2} R3:{4:X2} R4:{5:X2} R5:{6:X2} R6:{7:X2} R7:{8:X2} PSW:{9:X4} Cy:{10} {11}{12}{13}{14} {15}{16}{17}{18}", + "A:{0:X2} R0:{1:X2} R1:{2:X2} R2:{3:X2} R3:{4:X2} R4:{5:X2} R5:{6:X2} R6:{7:X2} R7:{8:X2} PSW:{9:X4} Cy:{10} {11}{12}{13}{14} {15}{16}{17}{18}{19}", Regs[A], - Regs[R0], - Regs[R1], - Regs[R2], - Regs[R3], - Regs[R4], - Regs[R5], - Regs[R6], - Regs[R7], + Regs[(ushort)(R0 + RB)], + Regs[(ushort)(R1 + RB)], + Regs[(ushort)(R2 + RB)], + Regs[(ushort)(R3 + RB)], + Regs[(ushort)(R4 + RB)], + Regs[(ushort)(R5 + RB)], + Regs[(ushort)(R6 + RB)], + Regs[(ushort)(R7 + RB)], Regs[PSW], TotalExecutedCycles, FlagC ? "C" : "c", @@ -393,7 +418,8 @@ namespace BizHawk.Emulation.Common.Components.I8048 IntEn ? "I" : "i", F1 ? "F" : "f", T0 ? "T" : "t", - T1 ? "T" : "t" + T1 ? "T" : "t", + RB > 0 ? "R" : "r" ) }; } @@ -438,8 +464,10 @@ namespace BizHawk.Emulation.Common.Components.I8048 ser.Sync(nameof(TF), ref TF); ser.Sync(nameof(timer_en), ref timer_en); + ser.Sync(nameof(RB), ref RB); + ser.Sync(nameof(RAM_ptr), ref RAM_ptr); + ser.Sync(nameof(Regs), ref Regs, false); - ser.Sync(nameof(RAM), ref RAM, false); ser.Sync(nameof(F1), ref F1); ser.Sync(nameof(T0), ref T0); diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/OP_Tables.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/OP_Tables.cs index 364663d2ec..84f2469304 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/OP_Tables.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/OP_Tables.cs @@ -32,7 +32,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 PopulateCURINSTR(IDLE, IDLE, IDLE, - oper, reg); + oper, (ushort)(reg + RB)); IRQS = 4; } @@ -43,7 +43,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 PopulateCURINSTR(IDLE, IDLE, IDLE, - oper, A, reg); + oper, A, (ushort)(reg + RB)); IRQS = 4; } diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/Operations.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/Operations.cs index 24f54091c9..2cedefe386 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/Operations.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/Operations.cs @@ -50,13 +50,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 } - public void CLR_Func(ushort src) - { - Regs[src] = 0; - - FlagC = false; - } - // source is considered a 16 bit signed value, used for long relative branch // no flags used public void ADD16BR_Func(ushort dest, ushort src) @@ -79,10 +72,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 ushort ans = (ushort)(Reg16_d & 0xFF); - // redo for half carry flag - Reg16_d = Regs[dest] & 0xF; - Reg16_d += (Regs[src] & 0xF); - Regs[dest] = ans; } @@ -95,10 +84,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 ushort ans = (ushort)(Reg16_d & 0xFF); - // redo for half carry flag - Reg16_d = Regs[dest] & 0xF; - Reg16_d -= (Regs[src] & 0xF); - Regs[dest] = ans; } @@ -111,10 +96,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 FlagC = Reg16_d.Bit(8); ushort ans = (ushort)(Reg16_d & 0xFF); - - // redo for half carry flag - Reg16_d = Regs[dest] & 0xF; - Reg16_d -= (Regs[src] & 0xF); } public void BIT_Func(ushort dest, ushort src) @@ -145,13 +126,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 Regs[src] = (ushort)(Regs[src] >> 1); } - public void COM_Func(ushort src) - { - Regs[src] = (ushort)((~Regs[src]) & 0xFF); - - FlagC = true; - } - public void AND8_Func(ushort dest, ushort src) { Regs[dest] = (ushort)(Regs[dest] & Regs[src]); @@ -232,10 +206,6 @@ namespace BizHawk.Emulation.Common.Components.I8048 ushort ans = (ushort)(Reg16_d & 0xFF); - // redo for half carry flag - Reg16_d = Regs[dest] & 0xF; - Reg16_d += ((Regs[src] & 0xF) + c); - Regs[dest] = ans; } @@ -277,15 +247,5 @@ namespace BizHawk.Emulation.Common.Components.I8048 ushort ans = (ushort)(Reg16_d & 0xFFFF); } - - public void EXG_Func(ushort sel) - { - - } - - public void TFR_Func(ushort sel) - { - - } } } diff --git a/BizHawk.Emulation.Cores/CPUs/Intel8048/Registers.cs b/BizHawk.Emulation.Cores/CPUs/Intel8048/Registers.cs index d0008fbee0..abd4a81dc8 100644 --- a/BizHawk.Emulation.Cores/CPUs/Intel8048/Registers.cs +++ b/BizHawk.Emulation.Cores/CPUs/Intel8048/Registers.cs @@ -5,10 +5,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 public partial class I8048 { // registers - public ushort[] Regs = new ushort[22]; - - // 64 bytes of onboard ram - public ushort[] RAM = new ushort[64]; + public ushort[] Regs = new ushort[78]; // The 8048 has 2 flags that can be used for conditionals // F0 is on the PSW, F1 is seperate @@ -21,28 +18,35 @@ namespace BizHawk.Emulation.Common.Components.I8048 // The 8048 has 2 test lines which can be used for conditionals, T0 can be used as an output public bool T0, T1; - public const ushort PC = 0; - public const ushort PSW = 1; - public const ushort BUS = 2; - public const ushort A = 3; - public const ushort R0 = 4; - public const ushort R1 = 5; - public const ushort R2 = 6; - public const ushort R3 = 7; - public const ushort R4 = 8; - public const ushort R5 = 9; - public const ushort R6 = 10; - public const ushort R7 = 11; - public const ushort ADDR = 12; // internal - public const ushort ALU = 13; // internal - public const ushort ALU2 = 14; // internal - public const ushort P1 = 15; - public const ushort P2 = 16; - public const ushort P4 = 17; - public const ushort P5 = 18; - public const ushort P6 = 19; - public const ushort P7 = 20; - public const ushort TIM = 21; + // 8 'registers' but really they point to locations in RAM + public const ushort R0 = 0; + public const ushort R1 = 1; + public const ushort R2 = 2; + public const ushort R3 = 3; + public const ushort R4 = 4; + public const ushort R5 = 5; + public const ushort R6 = 6; + public const ushort R7 = 7; + + // the location pointed to by the registers is controlled by the RAM bank + public ushort RB = 0; + public ushort RAM_ptr = 0; + + //RAM occupies registers 0-63 + public const ushort PC = 64; + public const ushort PSW = 65; + public const ushort BUS = 66; + public const ushort A = 67; + public const ushort ADDR = 68; // internal + public const ushort ALU = 69; // internal + public const ushort ALU2 = 70; // internal + public const ushort P1 = 71; + public const ushort P2 = 72; + public const ushort P4 = 73; + public const ushort P5 = 74; + public const ushort P6 = 75; + public const ushort P7 = 76; + public const ushort TIM = 77; public bool Flag3 { @@ -76,7 +80,7 @@ namespace BizHawk.Emulation.Common.Components.I8048 private void ResetRegisters() { - for (int i = 0; i < 22; i++) + for (int i = 0; i < 78; i++) { Regs[i] = 0; }