ShuriZma
/
BizHawk
mirror of https://github.com/TASEmulators/BizHawk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ZX Spectrum draft DB access

This commit is contained in:
alyosha-tas 2017-11-29 16:31:53 -05:00 committed by GitHub
parent 7428e8e673
commit 07b9e1243c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 196 additions and 186 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

382
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.cs
View File

@ -1,186 +1,196 @@
using BizHawk.Emulation.Cores.Components.Z80A; using BizHawk.Emulation.Cores.Components.Z80A;
using System; using System;
using System.Collections.Generic; using System.Collections.Generic;
using System.Linq; using System.Linq;
using System.Text; using System.Text;
using System.Threading.Tasks; using System.Threading.Tasks;
namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
{ {
public class ZX48 : SpectrumBase public class ZX48 : SpectrumBase
{ {
#region Construction #region Construction
/// <summary> /// <summary>
/// Main constructor /// Main constructor
/// </summary> /// </summary>
/// <param name="spectrum"></param> /// <param name="spectrum"></param>
/// <param name="cpu"></param> /// <param name="cpu"></param>
public ZX48(ZXSpectrum spectrum, Z80A cpu, byte[] file) public ZX48(ZXSpectrum spectrum, Z80A cpu, byte[] file)
{ {
Spectrum = spectrum; Spectrum = spectrum;
CPU = cpu; CPU = cpu;
// init addressable memory from ROM and RAM banks // init addressable memory from ROM and RAM banks
/* /*
Memory.Add(0, ROM0); Memory.Add(0, ROM0);
Memory.Add(1, RAM0); Memory.Add(1, RAM0);
Memory.Add(2, RAM1); Memory.Add(2, RAM1);
Memory.Add(3, RAM2); Memory.Add(3, RAM2);
*/ */
ReInitMemory(); ReInitMemory();
//RAM = new byte[0x4000 + 0xC000]; //RAM = new byte[0x4000 + 0xC000];
InitScreenConfig(); InitScreenConfig();
InitScreen(); InitScreen();
ResetULACycle(); ResetULACycle();
BuzzerDevice = new Buzzer(this); BuzzerDevice = new Buzzer(this);
BuzzerDevice.Init(44100, UlaFrameCycleCount); BuzzerDevice.Init(44100, UlaFrameCycleCount);
KeyboardDevice = new Keyboard48(this); KeyboardDevice = new Keyboard48(this);
TapeProvider = new DefaultTapeProvider(file); TapeProvider = new DefaultTapeProvider(file);
TapeDevice = new Tape(TapeProvider); TapeDevice = new Tape(TapeProvider);
TapeDevice.Init(this); TapeDevice.Init(this);
} }
#endregion #endregion
#region MemoryMapping #region MemoryMapping
/* 48K Spectrum has NO memory paging /* 48K Spectrum has NO memory paging
* *
* 0xffff +--------+ * 0xffff +--------+
| Bank 2 | | Bank 2 |
| | | |
| | | |
| | | |
0xc000 +--------+ 0xc000 +--------+
| Bank 1 | | Bank 1 |
| | | |
| | | |
| | | |
0x8000 +--------+ 0x8000 +--------+
| Bank 0 | | Bank 0 |
| | | |
| | | |
| screen | | screen |
0x4000 +--------+ 0x4000 +--------+
| ROM 0 | | ROM 0 |
| | | |
| | | |
| | | |
0x0000 +--------+ 0x0000 +--------+
*/ */
/// <summary> /// <summary>
/// Simulates reading from the bus (no contention) /// Simulates reading from the bus (no contention)
/// Paging should be handled here /// Paging should be handled here
/// </summary> /// </summary>
/// <param name="addr"></param> /// <param name="addr"></param>
/// <returns></returns> /// <returns></returns>
public override byte ReadBus(ushort addr) public override byte ReadBus(ushort addr)
{ {
int divisor = addr / 0x4000; int divisor = addr / 0x4000;
// paging logic goes here // paging logic goes here
var bank = Memory[divisor]; var bank = Memory[divisor];
var index = addr % 0x4000; var index = addr % 0x4000;
return bank[index]; return bank[index];
} }
/// <summary> /// <summary>
/// Simulates writing to the bus (no contention) /// Pushes a value onto the data bus that should be valid as long as the interrupt is true
/// Paging should be handled here /// </summary>
/// </summary> /// <param name="addr"></param>
/// <param name="addr"></param> /// <returns></returns>
/// <param name="value"></param> public override byte PushBus()
public override void WriteBus(ushort addr, byte value) {
{ return 0xFF;
int divisor = addr / 0x4000; }
// paging logic goes here
/// <summary>
var bank = Memory[divisor]; /// Simulates writing to the bus (no contention)
var index = addr % 0x4000; /// Paging should be handled here
bank[index] = value; /// </summary>
} /// <param name="addr"></param>
/// <param name="value"></param>
/// <summary> public override void WriteBus(ushort addr, byte value)
/// Reads a byte of data from a specified memory address {
/// (with memory contention if appropriate) int divisor = addr / 0x4000;
/// </summary> // paging logic goes here
/// <param name="addr"></param>
/// <returns></returns> var bank = Memory[divisor];
public override byte ReadMemory(ushort addr) var index = addr % 0x4000;
{ bank[index] = value;
var data = ReadBus(addr); }
if ((addr & 0xC000) == 0x4000)
{ /// <summary>
// addr is in RAM not ROM - apply memory contention if neccessary /// Reads a byte of data from a specified memory address
var delay = GetContentionValue(CurrentFrameCycle); /// (with memory contention if appropriate)
CPU.TotalExecutedCycles += delay; /// </summary>
} /// <param name="addr"></param>
return data; /// <returns></returns>
} public override byte ReadMemory(ushort addr)
{
/// <summary> var data = ReadBus(addr);
/// Writes a byte of data to a specified memory address if ((addr & 0xC000) == 0x4000)
/// (with memory contention if appropriate) {
/// </summary> // addr is in RAM not ROM - apply memory contention if neccessary
/// <param name="addr"></param> var delay = GetContentionValue(CurrentFrameCycle);
/// <param name="value"></param> CPU.TotalExecutedCycles += delay;
public override void WriteMemory(ushort addr, byte value) }
{ return data;
if (addr < 0x4000) }
{
// Do nothing - we cannot write to ROM /// <summary>
return; /// Writes a byte of data to a specified memory address
} /// (with memory contention if appropriate)
else if (addr < 0xC000) /// </summary>
{ /// <param name="addr"></param>
// possible contended RAM /// <param name="value"></param>
var delay = GetContentionValue(CurrentFrameCycle); public override void WriteMemory(ushort addr, byte value)
CPU.TotalExecutedCycles += delay; {
} if (addr < 0x4000)
{
WriteBus(addr, value); // Do nothing - we cannot write to ROM
} return;
}
public override void ReInitMemory() else if (addr < 0xC000)
{ {
if (Memory.ContainsKey(0)) // possible contended RAM
Memory[0] = ROM0; var delay = GetContentionValue(CurrentFrameCycle);
else CPU.TotalExecutedCycles += delay;
Memory.Add(0, ROM0); }
if (Memory.ContainsKey(1)) WriteBus(addr, value);
Memory[1] = RAM0; }
else
Memory.Add(1, RAM0); public override void ReInitMemory()
{
if (Memory.ContainsKey(2)) if (Memory.ContainsKey(0))
Memory[2] = RAM1; Memory[0] = ROM0;
else else
Memory.Add(2, RAM1); Memory.Add(0, ROM0);
if (Memory.ContainsKey(3)) if (Memory.ContainsKey(1))
Memory[3] = RAM2; Memory[1] = RAM0;
else else
Memory.Add(3, RAM2); Memory.Add(1, RAM0);
if (Memory.ContainsKey(4)) if (Memory.ContainsKey(2))
Memory[4] = RAM3; Memory[2] = RAM1;
else else
Memory.Add(4, RAM3); Memory.Add(2, RAM1);
}
if (Memory.ContainsKey(3))
Memory[3] = RAM2;
#endregion else
Memory.Add(3, RAM2);
} if (Memory.ContainsKey(4))
} Memory[4] = RAM3;
else
Memory.Add(4, RAM3);
}
#endregion
}
}