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Pull in some GPGX fixes from upstream (#1971) 

Fixes #1916
Fixes #1968

Pulls in 4017d379e6
Pulls in 147ad71a3c
Pulls in (more or less) a modified form of 200f9a7349
This commit is contained in:
nattthebear 2020-05-02 10:57:42 -04:00 committed by GitHub
parent ac2d5d7aac
commit 061410a097
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 60 additions and 43 deletions
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BIN
output/dll/gpgx.wbx.gz
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8
waterbox/gpgx/core/cart_hw/md_cart.c
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@ -566,6 +566,14 @@ void md_cart_init(void)
}
/* detect specific mappers */
if (strstr(rominfo.consoletype,"SEGA SSF"))
{
/* Everdrive extended SSF mapper */
cart.hw.bankshift = 1;
/* specific !TIME handler */
cart.hw.time_w = mapper_ssf2_w;
}
if (strstr(rominfo.domestic,"SUPER STREET FIGHTER2"))
{
/* SSF2 mapper */

95
waterbox/gpgx/core/vdp_ctrl.c
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@ -141,8 +141,9 @@ static uint16 fifo[4]; /* FIFO ring-buffer */
static int fifo_idx; /* FIFO write index */
static int fifo_byte_access; /* FIFO byte access flag */
static uint32 fifo_cycles; /* FIFO next access cycle */
static int *fifo_timing; /* FIFO slots timing table */
/* set Z80 or 68k interrupt lines */
/* set Z80 or 68k interrupt lines */
static void (*set_irq_line)(unsigned int level);
static void (*set_irq_line_delay)(unsigned int level);
@ -156,12 +157,25 @@ static const uint16 vc_table[4][2] =
{0x106, 0x10A} /* Mode 5 (240 lines) */
};
/* FIFO access slots timings */
static const int fifo_timing_h32[16+4] =
{
230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370,
MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510, MCYCLES_PER_LINE + 810, MCYCLES_PER_LINE + 970,
};
static const int fifo_timing_h40[18+4] =
{
352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380,
MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820, MCYCLES_PER_LINE + 948, MCYCLES_PER_LINE + 1076,
};
/* DMA Timings (number of access slots per line) */
static const uint8 dma_timing[2][2] =
{
/* H32, H40 */
{16 , 18}, /* active display */
{167, 205} /* blank display */
{166, 204} /* blank display */
};
/* DMA processing functions (set by VDP register 23 high nibble) */
@ -317,6 +331,9 @@ void vdp_reset(void)
/* default sprite pixel width */
max_sprite_pixels = 256;
/* default FIFO access slots timings */
fifo_timing = (int *)fifo_timing_h32;
/* default overscan area */
if ((system_hw == SYSTEM_GG) && !config.gg_extra)
{
@ -454,13 +471,13 @@ void vdp_dma_update(unsigned int cycles)
DMA Mode Width Display Transfer Count
-----------------------------------------------------
68K > VDP 32-cell Active 16
Blanking 167
40-cell Active 18
Blanking 205
VRAM Fill 32-cell Active 15
Blanking 166
40-cell Active 17
40-cell Active 18
Blanking 204
VRAM Fill 32-cell Active 15
Blanking 165
40-cell Active 17
Blanking 203
VRAM Copy 32-cell Active 8
Blanking 83
40-cell Active 9
@ -785,8 +802,11 @@ void vdp_z80_ctrl_w(unsigned int data)
{
case 2:
{
/* DMA Fill will be triggered by next write to DATA port */
dmafill = 1;
/* DMA Fill */
dma_type = 2;
/* DMA is pending until next DATA port write */
dmafill = 1;
/* Set DMA Busy flag */
status |= 0x02;
@ -1908,6 +1928,13 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
/* Active display width */
if (r & 0x01)
{
/* FIFO access slots timings depend on active width */
if (fifo_slots)
{
/* Synchronize VDP FIFO */
vdp_fifo_update(cycles);
}
if (d & 0x01)
{
/* Update display-dependant registers */
@ -1924,6 +1951,9 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
/* Max. sprite pixels per line */
max_sprite_pixels = 320;
/* FIFO access slots timings */
fifo_timing = (int *)fifo_timing_h40;
}
else
{
@ -1941,6 +1971,9 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
/* Max. sprite pixels per line */
max_sprite_pixels = 256;
/* FIFO access slots timings */
fifo_timing = (int *)fifo_timing_h32;
}
/* Active display width modified during HBLANK (Bugs Bunny Double Trouble) */
@ -2017,49 +2050,25 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
static void vdp_fifo_update(unsigned int cycles)
{
int num, slots, count = 0;
const int *fifo_timing;
const int fifo_cycles_h32[16+4] =
{
230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370,
MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510, MCYCLES_PER_LINE + 810, MCYCLES_PER_LINE + 970,
};
const int fifo_cycles_h40[18+4] =
{
352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380,
MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820, MCYCLES_PER_LINE + 948, MCYCLES_PER_LINE + 1076,
};
int fifo_read_cnt, line_slots = 0;
/* number of access slots up to current line */
if (reg[12] & 0x01)
{
fifo_timing = fifo_cycles_h40;
slots = 18 * ((v_counter + 1) % lines_per_frame);
}
else
{
fifo_timing = fifo_cycles_h32;
slots = 16 * ((v_counter + 1) % lines_per_frame);
}
int total_slots = dma_timing[0][reg[12] & 1] * ((v_counter + 1) % lines_per_frame);
/* number of access slots within current line */
cycles -= mcycles_vdp;
while (fifo_timing[count] <= cycles)
while (fifo_timing[line_slots] <= cycles)
{
count++;
line_slots++;
}
/* number of processed FIFO entries since last access (byte access needs two slots to process one FIFO word) */
num = (slots + count - fifo_slots) >> fifo_byte_access;
fifo_read_cnt = (total_slots + line_slots - fifo_slots) >> fifo_byte_access;
if (num > 0)
if (fifo_read_cnt > 0)
{
/* process FIFO entries */
fifo_write_cnt -= num;
fifo_write_cnt -= fifo_read_cnt;
/* Clear FIFO full flag */
status &= 0xFEFF;
@ -2073,17 +2082,17 @@ static void vdp_fifo_update(unsigned int cycles)
status |= 0x200;
/* Reinitialize FIFO access slot counter */
fifo_slots = slots + count;
fifo_slots = total_slots + line_slots;
}
else
{
/* Update FIFO access slot counter */
fifo_slots += (num << fifo_byte_access);
fifo_slots += (fifo_read_cnt << fifo_byte_access);
}
}
/* next FIFO update cycle */
fifo_cycles = mcycles_vdp + fifo_timing[fifo_slots - slots + fifo_byte_access];
fifo_cycles = mcycles_vdp + fifo_timing[fifo_slots - total_slots + fifo_byte_access];
}