388 lines
12 KiB
C#
388 lines
12 KiB
C#
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using System;
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namespace BizHawk.Emulation.CPUs.M68K
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{
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public partial class M68000
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{
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private bool TestCondition(int condition)
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{
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switch (condition)
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{
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case 0x00: return true; // True
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case 0x01: return false; // False
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case 0x02: return !C && !Z; // High (Unsigned)
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case 0x03: return C || Z; // Less or Same (Unsigned)
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case 0x04: return !C; // Carry Clear (High or Same)
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case 0x05: return C; // Carry Set (Lower)
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case 0x06: return !Z; // Not Equal
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case 0x07: return Z; // Equal
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case 0x08: return !V; // Overflow Clear
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case 0x09: return V; // Overflow Set
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case 0x0A: return !N; // Plus (Positive)
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case 0x0B: return N; // Minus (Negative)
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case 0x0C: return N && V || !N && !V; // Greater or Equal
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case 0x0D: return N && !V || !N && V; // Less Than
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case 0x0E: return N && V && !Z || !N && !V && !Z; // Greater Than
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case 0x0F: return Z || N && !V || !N && V; // Less or Equal
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default:
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throw new Exception("Invalid condition "+condition);
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}
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}
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private string DisassembleCondition(int condition)
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{
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switch (condition)
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{
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case 0x00: return "t"; // True
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case 0x01: return "f"; // False
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case 0x02: return "hi"; // High (Unsigned)
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case 0x03: return "ls"; // Less or Same (Unsigned)
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case 0x04: return "cc"; // Carry Clear (High or Same)
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case 0x05: return "cs"; // Carry Set (Lower)
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case 0x06: return "ne"; // Not Equal
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case 0x07: return "eq"; // Equal
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case 0x08: return "vc"; // Overflow Clear
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case 0x09: return "vs"; // Overflow Set
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case 0x0A: return "pl"; // Plus (Positive)
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case 0x0B: return "mi"; // Minus (Negative)
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case 0x0C: return "ge"; // Greater or Equal
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case 0x0D: return "lt"; // Less Than
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case 0x0E: return "gt"; // Greater Than
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case 0x0F: return "le"; // Less or Equal
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default: return "??"; // Invalid condition
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}
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}
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private void Bcc() // Branch on condition
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{
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sbyte displacement8 = (sbyte) op;
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int cond = (op >> 8) & 0x0F;
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if (TestCondition(cond) == true)
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{
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if (displacement8 != 0)
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{
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// use opcode-embedded displacement
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PC += displacement8;
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PendingCycles -= 10;
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} else {
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// use extension word displacement
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PC += ReadWord(PC);
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PendingCycles -= 10;
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}
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} else { // false
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if (displacement8 != 0)
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PendingCycles -= 8;
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else {
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PC += 2;
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PendingCycles -= 12;
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}
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}
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}
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private void Bcc_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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sbyte displacement8 = (sbyte)op;
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int cond = (op >> 8) & 0x0F;
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info.Mnemonic = "b" + DisassembleCondition(cond);
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if (displacement8 != 0)
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{
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info.Args = string.Format("${0:X}", pc + displacement8);
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} else {
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info.Args = string.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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private void BRA()
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{
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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PC += displacement8;
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else
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PC += ReadWord(PC);
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PendingCycles -= 10;
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}
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private void BRA_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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info.Mnemonic = "bra";
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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info.Args = String.Format("${0:X}", pc + displacement8);
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else
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{
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info.Args = String.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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private void BSR()
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{
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sbyte displacement8 = (sbyte)op;
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A[7].s32 -= 4;
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if (displacement8 != 0)
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{
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// use embedded displacement
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WriteLong(A[7].s32, PC);
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PC += displacement8;
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} else {
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// use extension word displacement
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WriteLong(A[7].s32, PC + 2);
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PC += ReadWord(PC);
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}
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PendingCycles -= 18;
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}
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private void BSR_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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info.Mnemonic = "bsr";
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sbyte displacement8 = (sbyte)op;
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if (displacement8 != 0)
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info.Args = String.Format("${0:X}", pc + displacement8);
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else {
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info.Args = String.Format("${0:X}", pc + ReadWord(pc));
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pc += 2;
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}
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info.Length = pc - info.PC;
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}
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private void DBcc()
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{
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if (TestCondition((op >> 8) & 0x0F) == true)
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{
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// break out of loop
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PC += 2;
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PendingCycles -= 12;
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} else {
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int reg = op & 7;
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D[reg].u16--;
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if (D[reg].u16 == 0xFFFF)
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{
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PC += 2;
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PendingCycles -= 14;
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} else {
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PC += ReadWord(PC);
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TotalExecutedCycles -= 10;
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}
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}
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}
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private void DBcc_Disasm(DisassemblyInfo info)
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{
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int cond = (op >> 8) & 0x0F;
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if (cond == 1)
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info.Mnemonic = "dbra";
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else
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info.Mnemonic = "db" + DisassembleCondition(cond);
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int pc = info.PC + 2;
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info.Args = String.Format("D{0}, ${1:X}", op & 7, pc + ReadWord(pc));
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info.Length = 4;
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}
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private void RTS()
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{
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PC = ReadLong(A[7].s32);
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A[7].s32 += 4;
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PendingCycles -= 16;
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}
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private void RTS_Disasm(DisassemblyInfo info)
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{
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info.Mnemonic = "rts";
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info.Args = "";
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}
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private void TST()
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{
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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int value;
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switch (size)
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{
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case 0: value = ReadValueB(mode, reg); PendingCycles -= 4 + EACyclesBW[mode, reg]; break;
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case 1: value = ReadValueW(mode, reg); PendingCycles -= 4 + EACyclesBW[mode, reg]; break;
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default: value = ReadValueL(mode, reg); PendingCycles -= 4 + EACyclesL[mode, reg]; break;
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}
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V = false;
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C = false;
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N = (value < 0);
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Z = (value == 0);
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}
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private void TST_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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switch (size)
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{
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case 0: info.Mnemonic = "tst.b"; info.Args = DisassembleValue(mode, reg, 1, ref pc); break;
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case 1: info.Mnemonic = "tst.w"; info.Args = DisassembleValue(mode, reg, 2, ref pc); break;
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case 2: info.Mnemonic = "tst.l"; info.Args = DisassembleValue(mode, reg, 4, ref pc); break;
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}
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info.Length = pc - info.PC;
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}
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private void BTSTi()
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{
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int bit = ReadWord(PC);
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PC += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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if (mode == 0)
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{
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bit &= 31;
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int mask = 1 << bit;
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Z = (D[reg].s32 & mask) == 0;
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PendingCycles -= 10;
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} else {
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bit &= 7;
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int mask = 1 << bit;
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Z = (ReadValueB(mode, reg) & mask) == 0;
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PendingCycles -= 8 + EACyclesBW[mode, reg];
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}
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}
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private void BTSTi_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int bit = ReadWord(pc); pc += 2;
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int mode = (op >> 3) & 7;
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int reg = op & 7;
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info.Mnemonic = "btst";
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info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
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info.Length = pc - info.PC;
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}
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private void BTSTr()
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{
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throw new NotImplementedException();
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}
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private void BTSTr_Disasm(DisassemblyInfo info)
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{
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throw new NotImplementedException();
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}
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private void JMP()
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{
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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PC = ReadAddress(mode, reg);
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switch (mode)
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{
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case 2: PendingCycles -= 8; break;
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case 5: PendingCycles -= 10; break;
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case 6: PendingCycles -= 14; break;
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case 7:
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switch (reg)
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{
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case 0: PendingCycles -= 10; break;
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case 1: PendingCycles -= 12; break;
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case 2: PendingCycles -= 10; break;
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case 3: PendingCycles -= 14; break;
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}
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break;
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}
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}
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private void JMP_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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info.Mnemonic = "jmp";
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info.Args = DisassembleValue(mode, reg, 1, ref pc);
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info.Length = pc - info.PC;
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}
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private void JSR()
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{
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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int addr = ReadAddress(mode, reg);
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A[7].s32 -= 4;
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WriteLong(A[7].s32, PC);
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PC = addr;
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switch (mode)
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{
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case 2: PendingCycles -= 16; break;
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case 5: PendingCycles -= 18; break;
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case 6: PendingCycles -= 22; break;
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case 7:
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switch (reg)
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{
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case 0: PendingCycles -= 18; break;
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case 1: PendingCycles -= 20; break;
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case 2: PendingCycles -= 18; break;
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case 3: PendingCycles -= 22; break;
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}
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break;
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}
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}
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private void JSR_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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info.Mnemonic = "jsr";
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info.Args = DisassembleAddress(mode, reg, ref pc);
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info.Length = pc - info.PC;
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}
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private void LINK()
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{
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int reg = op & 7;
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A[7].s32 -= 4;
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short offset = ReadWord(PC); PC += 2;
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WriteLong(A[7].s32, A[reg].s32);
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A[reg].s32 = A[7].s32 + offset;
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PendingCycles -= 16;
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}
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private void LINK_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int reg = op & 7;
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info.Mnemonic = "link";
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info.Args = "A"+reg+", "+DisassembleImmediate(2, ref pc); // TODO need a DisassembleSigned or something
|
|||
|
|
info.Length = pc - info.PC;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
private void NOP()
|
|||
|
|
{
|
|||
|
|
PendingCycles -= 4;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
private void NOP_Disasm(DisassemblyInfo info)
|
|||
|
|
{
|
|||
|
|
info.Mnemonic = "nop";
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|