397 lines
9.5 KiB
C#
397 lines
9.5 KiB
C#
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using System;
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using System.Collections.Generic;
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using System.Text;
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namespace MC68000
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{
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public partial class MC68K
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{
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private void EXG() // Exchange registers
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{
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this.m_Cycles += 6;
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switch ((this.m_IR >> 3) & 0x31)
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{
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case 8:
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Helpers.Swap(ref this.m_D[(this.m_IR >> 9) & 0x7], ref this.m_D[this.m_IR & 0x7]);
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return;
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case 9:
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Helpers.Swap(ref this.m_A[(this.m_IR >> 9) & 0x7], ref this.m_A[this.m_IR & 0x7]);
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return;
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case 17:
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Helpers.Swap(ref this.m_D[(this.m_IR >> 9) & 0x7], ref this.m_A[this.m_IR & 0x7]);
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return;
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}
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}
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private void LEA() // Load effective address
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{
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this.m_A[(this.m_IR >> 9) & 0x7] =
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FetchAddress((this.m_IR >> 3) & 0x7, this.m_IR & 0x7);
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switch ((this.m_IR >> 3) & 0x7)
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{
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case 0x2: this.m_Cycles += 4; break;
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case 0x5: this.m_Cycles += 8; break;
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case 0x6: this.m_Cycles += 12; break;
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case 0x7:
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switch (this.m_IR & 0x7)
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{
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case 0x0: this.m_Cycles += 8; break;
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case 0x1: this.m_Cycles += 12; break;
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case 0x2: this.m_Cycles += 8; break;
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case 0x3: this.m_Cycles += 12; break;
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}
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break;
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}
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}
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private void LINK()
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{
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this.SP -= 4;
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WriteL(this.SP, this.m_A[this.m_IR & 0x7]);
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this.m_A[this.m_IR & 0x7] = this.SP;
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this.SP += FetchW();
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this.m_Cycles += 16;
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}
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private void MOVE() // Move data from source to destination
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{
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int src_mode = (this.m_IR >> 3) & 0x7;
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int src_reg = this.m_IR & 0x7;
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int dest_mode = (this.m_IR >> 6) & 0x7;
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int dest_reg = (this.m_IR >> 9) & 0x7;
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int operand = 0;
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switch ((this.m_IR >> 12) & 0x3)
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{
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case 1: // B
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operand = FetchOperandB(src_mode, src_reg);
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SetOperandB(dest_mode, dest_reg, (sbyte)operand);
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this.m_Cycles += Helpers.MOVECyclesBW[src_mode + ((src_mode == 7) ? src_reg : 0),
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dest_mode + ((dest_mode == 7) ? dest_reg : 0)];
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break;
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case 3: // W
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operand = FetchOperandW(src_mode, src_reg);
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SetOperandW(dest_mode, dest_reg, (short)operand);
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this.m_Cycles += Helpers.MOVECyclesBW[src_mode + ((src_mode == 7) ? src_reg : 0),
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dest_mode + ((dest_mode == 7) ? dest_reg : 0)];
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break;
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case 2: // L
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operand = FetchOperandL(src_mode, src_reg);
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SetOperandL(dest_mode, dest_reg, operand);
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this.m_Cycles += Helpers.MOVECyclesL[src_mode + ((src_mode == 7) ? src_reg : 0),
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dest_mode + ((dest_mode == 7) ? dest_reg : 0)];
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break;
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}
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this.V = this.C = false;
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this.N = (operand < 0);
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this.Z = (operand == 0);
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}
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private void MOVEA() // Move Address
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{
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// W
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if ((this.m_IR >> 12 & 0x3) == 3)
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{
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this.m_A[this.m_IR >> 9 & 0x7] =
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FetchOperandW(this.m_IR >> 3 & 0x7, this.m_IR & 0x7);
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// TODO Need to check these clock cycles
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this.m_Cycles += Helpers.MOVECyclesBW[(this.m_IR >> 3 & 0x7) + (((this.m_IR >> 3 & 0x7) == 7) ? (this.m_IR & 0x7) : 0), 1];
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}
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// L
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else
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{
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this.m_A[this.m_IR >> 9 & 0x7] =
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FetchOperandL(this.m_IR >> 3 & 0x7, this.m_IR & 0x7);
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// TODO Need to check these clock cycles
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this.m_Cycles += Helpers.MOVECyclesL[(this.m_IR >> 3 & 0x7) + (((this.m_IR >> 3 & 0x7) == 7) ? (this.m_IR & 0x7) : 0), 1];
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}
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}
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private void MOVEM_Mem2Reg()
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{
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int size = (this.m_IR >> 6) & 0x1;
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int src_mode = (this.m_IR >> 3) & 0x7;
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int src_register = this.m_IR & 0x7;
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ushort regMap = (ushort)FetchW();
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int count = 0;
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int address = FetchAddress(src_mode, src_register);
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switch (size)
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{
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case 0: // W
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{
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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this.m_D[i] = ReadW(address);
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address += 2;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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this.m_A[i] = ReadW(address);
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address += 2;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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if (src_mode == 3) // Postincrement mode
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{
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this.m_A[src_register] = address;
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}
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this.m_Cycles += count * 4;
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break;
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}
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case 1: // L
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{
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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this.m_D[i] = (int)ReadL(address);
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address += 4;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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this.m_A[i] = (int)ReadL(address);
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address += 4;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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if (src_mode == 3) // Postincrement mode
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{
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this.m_A[src_register] = address;
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}
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this.m_Cycles += count * 8;
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break;
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}
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}
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switch (src_mode)
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{
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case 0x2: this.m_Cycles += 12; break;
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case 0x3: this.m_Cycles += 12; break;
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case 0x5: this.m_Cycles += 16; break;
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case 0x6: this.m_Cycles += 18; break;
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case 0x7:
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switch (src_register)
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{
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case 0x0: this.m_Cycles += 16; break;
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case 0x1: this.m_Cycles += 20; break;
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case 0x2: this.m_Cycles += 16; break;
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case 0x3: this.m_Cycles += 18; break;
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}
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break;
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}
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}
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private void MOVEM_Reg2Mem()
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{
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int size = (this.m_IR >> 6) & 0x1;
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int src_mode = (this.m_IR >> 3) & 0x7;
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int src_register = this.m_IR & 0x7;
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ushort regMap = (ushort)FetchW();
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int count = 0;
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int address = FetchAddress(src_mode, src_register);
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switch (size)
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{
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case 0: // W
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{
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if (src_mode == 4) // Pre-decrement mode
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{
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for (int i = 7; i >= 0; i--)
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{
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if ((regMap & 0x1) > 0)
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{
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address -= 2;
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WriteW(address, (sbyte)this.m_A[i]);
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 7; i >= 0; i--)
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{
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if ((regMap & 0x1) > 0)
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{
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address -= 2;
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WriteW(address, (sbyte)this.m_D[i]);
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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this.m_A[src_register] = address;
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}
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else
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{
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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WriteW(address, (sbyte)this.m_D[i]);
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address += 2;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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WriteW(address, (sbyte)this.m_A[i]);
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address += 2;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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}
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this.m_Cycles += 4 * count;
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break;
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}
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case 1: // L
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{
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if (src_mode == 4) // Pre-decrement mode
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{
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for (int i = 7; i >= 0; i--)
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{
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if ((regMap & 0x1) > 0)
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{
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address -= 4;
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WriteL(address, this.m_A[i]);
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 7; i >= 0; i--)
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{
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if ((regMap & 0x1) > 0)
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{
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address -= 4;
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WriteL(address, this.m_D[i]);
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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this.m_A[src_register] = address;
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}
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else
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{
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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WriteL(address, this.m_D[i]);
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address += 4;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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for (int i = 0; i < 8; i++)
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{
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if ((regMap & 0x1) > 0)
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{
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WriteL(address, this.m_A[i]);
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address += 4;
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count++;
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}
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regMap = (ushort)(regMap >> 1);
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}
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}
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this.m_Cycles += 8 * count;
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break;
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}
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}
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switch (src_mode)
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{
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case 0x2: this.m_Cycles += 8; break;
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case 0x4: this.m_Cycles += 8; break;
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case 0x5: this.m_Cycles += 12; break;
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case 0x6: this.m_Cycles += 14; break;
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case 0x7:
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switch (src_register)
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{
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case 0x0: this.m_Cycles += 12; break;
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case 0x1: this.m_Cycles += 16; break;
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}
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break;
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}
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}
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private void MOVEP()
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{
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int dataregister = (this.m_IR >> 9) & 0x7;
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int opmode = (this.m_IR >> 6) & 0x7;
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int addressregister = this.m_IR & 0x7;
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short displacement = FetchW();
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throw new NotImplementedException();
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}
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private void MOVEQ() // Move quick
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{
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// Data byte is sign-extended to 32 bits
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int data = (sbyte)this.m_IR;
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this.N = (data < 0);
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this.Z = (data == 0);
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this.V = this.C = false;
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this.m_D[(this.m_IR >> 9) & 0x7] = data;
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this.m_Cycles += 4;
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}
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private void PEA() // Push effective address
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{
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this.SP -= 4;
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WriteL(this.SP, FetchAddress((this.m_IR >> 3) & 0x7, this.m_IR & 0x7));
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switch ((this.m_IR >> 3) & 0x7)
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{
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case 0x2: this.m_Cycles += 12; break;
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case 0x5: this.m_Cycles += 16; break;
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case 0x6: this.m_Cycles += 20; break;
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case 0x7:
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switch (this.m_IR & 0x7)
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{
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case 0x0: this.m_Cycles += 16; break;
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case 0x1: this.m_Cycles += 20; break;
|
||
|
|
case 0x2: this.m_Cycles += 16; break;
|
||
|
|
case 0x3: this.m_Cycles += 20; break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
private void UNLK()
|
||
|
|
{
|
||
|
|
this.SP = this.m_A[this.m_IR & 0x7];
|
||
|
|
this.m_A[this.m_IR & 0x7] = ReadL(this.SP);
|
||
|
|
this.SP += 4;
|
||
|
|
|
||
|
|
this.m_Cycles += 12;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|