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BizHawk/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs

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namespace BizHawk.Emulation.Cores.Components.Z80A
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{
public partial class Z80A
{
private void INT_OP_IND(ushort operation, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
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RD, ALU, src_l, src_h,
IDLE,
operation, ALU,
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WAIT,
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WR, src_l, src_h, ALU,
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IDLE,
WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, src_l, 0, 0, 0, PCl, 0, 0, 0 };
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}
private void BIT_OP_IND(ushort operation, ushort bit, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, src_l, src_h,
operation, bit, ALU,
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WAIT,
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WR, src_l, src_h, ALU,
IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, src_l, 0, 0, src_l, 0, 0, PCl, 0, 0, 0 };
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}
// Note that this operation uses I_BIT, same as indexed BIT.
// This is where the strange behaviour in Flag bits 3 and 5 come from.
// normally WZ contain I* + n when doing I_BIT ops, but here we use that code path
// even though WZ is not assigned to, letting it's value from other operations show through
private void BIT_TE_IND(ushort operation, ushort bit, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, src_l, src_h,
I_BIT, bit, ALU,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void REG_OP_IND_INC(ushort operation, ushort dest, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, ALU, src_l, src_h,
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operation, dest, ALU,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void REG_OP_IND(ushort operation, ushort dest, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
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{TR16, Z, W, src_l, src_h,
WAIT,
RD_INC, ALU, Z, W,
operation, dest, ALU,
WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_16_IND_nn(ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, Z, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, W, PCl, PCh,
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IDLE,
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WAIT,
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WR_INC, Z, W, src_l,
IDLE,
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WAIT,
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WR, Z, W, src_h,
IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { PCl, 0, 0, PCl, 0, 0, Z, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_IND_16_nn(ushort dest_l, ushort dest_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, Z, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, W, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, dest_l, Z, W,
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IDLE,
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WAIT,
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RD, dest_h, Z, W,
IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { PCl, 0, 0, PCl, 0, 0, Z, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_8_IND_nn(ushort src)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, Z, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, W, PCl, PCh,
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IDLE,
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WAIT,
WR_INC, Z, W, src,
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TR, W, A,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { PCl, 0, 0, PCl, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_IND_8_nn(ushort dest)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, Z, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, W, PCl, PCh,
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IDLE,
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WAIT,
RD_INC, dest, Z, W,
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IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { PCl, 0, 0, PCl, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_8_IND(ushort dest_l, ushort dest_h, ushort src)
{
cur_instr = new ushort[]
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{TR16, Z, W, dest_l, dest_h,
WAIT,
WR_INC, Z, W, src,
TR, W, A,
WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { dest_l, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_8_IND_IND(ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, ALU, src_l, src_h,
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IDLE,
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WAIT,
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WR, dest_l, dest_h, ALU,
IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, dest_l, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_IND_8_INC(ushort dest, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, dest, src_l, src_h,
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IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void LD_IND_16(ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, dest_l, src_l, src_h,
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IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
RD_INC, dest_h, src_l, src_h,
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IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { src_l, 0, 0, src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void INC_8_IND(ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, src_l, src_h,
INC8, ALU,
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WAIT,
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WR, src_l, src_h, ALU,
IDLE,
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WAIT,
OP_F,
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OP };
z80: Add bus request timing array to work with zx spectrum Also some clean up
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BUSRQ = new ushort[] { 0, src_l, 0, 0, src_l, 0, 0, PCl, 0, 0, 0 };
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}
private void DEC_8_IND(ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, src_l, src_h,
DEC8, ALU,
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WAIT,
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WR, src_l, src_h, ALU,
IDLE,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, src_l, 0, 0, src_l, 0, 0, PCl, 0, 0, 0 };
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}
// NOTE: WZ implied for the wollowing 3 functions
private void I_INT_OP(ushort operation, ushort dest)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, Z, W,
operation, ALU,
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WAIT,
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WR, Z, W, ALU,
TR, dest, ALU,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, Z, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_BIT_OP(ushort operation, ushort bit, ushort dest)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, Z, W,
operation, bit, ALU,
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WAIT,
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WR, Z, W, ALU,
TR, dest, ALU,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, Z, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_BIT_TE(ushort bit)
{
cur_instr = new ushort[]
{IDLE,
IDLE,
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WAIT,
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RD, ALU, Z, W,
I_BIT, bit, ALU,
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_OP_n(ushort operation, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, ALU, PCl, PCh,
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IDLE,
IDLE,
TR16, Z, W, src_l, src_h,
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ADDS, Z, W, ALU, ZERO,
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IDLE,
IDLE,
IDLE,
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WAIT,
RD, ALU, Z, W,
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operation, ALU,
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WAIT,
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WR, Z, W, ALU,
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
OP_F,
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OP };
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BUSRQ = new ushort[] { PCl, 0, 0, 0, 0, 0, 0, 0, 0, Z, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_OP_n_n(ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
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WAIT,
RD_INC, ALU, PCl, PCh,
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IDLE,
TR16, Z, W, src_l, src_h,
ADDS, Z, W, ALU, ZERO,
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WAIT,
RD_INC, ALU, PCl, PCh,
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IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
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WR, Z, W, ALU,
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
OP_F,
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OP };
z80: Add bus request timing array to work with zx spectrum Also some clean up
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BUSRQ = new ushort[] { PCl, 0, 0, 0, 0, PCl, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_REG_OP_IND_n(ushort operation, ushort dest, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
RD_INC, ALU, PCl, PCh,
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IDLE,
TR16, Z, W, src_l, src_h,
IDLE,
ADDS, Z, W, ALU, ZERO,
IDLE,
z80: IN/OUT access fixes
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IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
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2017-10-13 00:20:13 +00:00
RD, ALU, Z, W,
z80: IN/OUT access fixes
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operation, dest, ALU,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
OP_F,
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OP };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
z80: IN/OUT access fixes
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BUSRQ = new ushort[] { PCl, 0, 0, 0, 0, 0, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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}
private void I_LD_8_IND_n(ushort dest_l, ushort dest_h, ushort src)
{
cur_instr = new ushort[]
{IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
RD_INC, ALU, PCl, PCh,
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2017-10-13 00:20:13 +00:00
IDLE,
IDLE,
TR16, Z, W, dest_l, dest_h,
ADDS, Z, W, ALU, ZERO,
IDLE,
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
WR, Z, W, src,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
z80: IN/OUT access fixes
2018-06-04 15:42:59 +00:00
BUSRQ = new ushort[] { PCl, 0, 0, 0, 0, 0, 0, 0, Z, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
private void LD_OP_R(ushort operation, ushort repeat_instr)
{
cur_instr = new ushort[]
Z80: Recast core to cycle accurate memory accesses and wait state timing
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{IDLE,
WAIT,
RD, ALU, L, H,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
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2017-10-13 00:20:13 +00:00
WR, E, D, ALU,
operation, L, H,
operation, E, D,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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SET_FL_LD, // BC gets decremented in here
WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP_R, 0, operation, repeat_instr };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
BUSRQ = new ushort[] { L, 0, 0, E, 0, 0, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
private void CP_OP_R(ushort operation, ushort repeat_instr)
{
cur_instr = new ushort[]
{IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
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2017-10-13 00:20:13 +00:00
RD, ALU, L, H,
operation, L, H,
DEC16, C, B,
SET_FL_CP,
operation, Z, W,
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
IDLE,
WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP_R, 1, operation, repeat_instr };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
BUSRQ = new ushort[] { L, 0, 0, 0, 0, 0, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
private void IN_OP_R(ushort operation, ushort repeat_instr)
{
cur_instr = new ushort[]
z80: fix some instruction timings for IN/OUT
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{IDLE,
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2017-10-13 00:20:13 +00:00
IDLE,
z80: fix some instruction timings for IN/OUT
2018-06-01 19:21:05 +00:00
WAIT,
IN, ALU, C, B,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
WR, L, H, ALU,
REP_OP_I, operation,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP_R, 2, operation, repeat_instr };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
BUSRQ = new ushort[] { 0, 0, 0, 0, L, 0, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
private void OUT_OP_R(ushort operation, ushort repeat_instr)
{
cur_instr = new ushort[]
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
{IDLE,
WAIT,
RD, ALU, L, H,
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2017-10-13 00:20:13 +00:00
IDLE,
IDLE,
z80: fix some instruction timings for IN/OUT
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WAIT,
OUT, C, B, ALU,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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REP_OP_O, operation,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP_R, 3, operation, repeat_instr };
z80: Add bus request timing array to work with zx spectrum Also some clean up
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BUSRQ = new ushort[] { L, 0, 0, 0, 0, 0, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
// this is an indirect change of a a 16 bit register with memory
private void EXCH_16_IND_(ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
{
cur_instr = new ushort[]
{IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
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WAIT,
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2017-10-13 00:20:13 +00:00
RD, Z, dest_l, dest_h,
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
INC16, dest_l, dest_h,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
z80: Add bus request timing array to work with zx spectrum Also some clean up
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RD, W, dest_l, dest_h,
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2017-10-13 00:20:13 +00:00
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
WR_DEC, dest_l, dest_h, src_h,
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2017-10-13 00:20:13 +00:00
IDLE,
IDLE,
IDLE,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
z80: fix a bug
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WR, dest_l, dest_h, src_l,
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2017-10-13 00:20:13 +00:00
TR16, src_l, src_h, Z, W,
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-06-01 01:05:41 +00:00
WAIT,
OP_F,
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2017-10-13 00:20:13 +00:00
OP };
z80: Add bus request timing array to work with zx spectrum Also some clean up
2018-06-03 23:14:30 +00:00
BUSRQ = new ushort[] { dest_l, 0, 0, 0, dest_l, 0, 0, dest_l, 0, 0, 0, 0, dest_l, 0, 0, PCl, 0, 0, 0 };
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2017-10-13 00:20:13 +00:00
}
}
}