2017-10-13 00:20:13 +00:00
|
|
|
using System;
|
|
|
|
|
2017-10-13 21:58:36 +00:00
|
|
|
namespace BizHawk.Emulation.Cores.Components.Z80A
|
2017-10-13 00:20:13 +00:00
|
|
|
{
|
|
|
|
public partial class Z80A
|
|
|
|
{
|
|
|
|
// this contains the vectors of instrcution operations
|
|
|
|
// NOTE: This list is NOT confirmed accurate for each individual cycle
|
|
|
|
|
|
|
|
private void NOP_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{ IDLE,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// NOTE: In a real Z80, this operation just flips a switch to choose between 2 registers
|
|
|
|
// but it's simpler to emulate just by exchanging the register with it's shadow
|
|
|
|
private void EXCH_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{EXCH,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void EXX_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{EXX,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// this exchanges 2 16 bit registers
|
|
|
|
private void EXCH_16_(ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{EXCH_16, dest_l, dest_h, src_l, src_h,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void INC_16(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-03 23:14:30 +00:00
|
|
|
{INC16, src_l, src_h,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, 0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
private void DEC_16(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{DEC16, src_l, src_h,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, 0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// this is done in two steps technically, but the flags don't work out using existing funcitons
|
|
|
|
// so let's use a different function since it's an internal operation anyway
|
|
|
|
private void ADD_16(ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{TR16, Z, W, dest_l, dest_h,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
|
|
|
INC16, Z, W,
|
|
|
|
IDLE,
|
|
|
|
ADD16, dest_l, dest_h, src_l, src_h,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
IDLE,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, 0, 0, 0, 0, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void REG_OP(ushort operation, ushort dest, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{operation, dest, src,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Operations using the I and R registers take one T-cycle longer
|
|
|
|
private void REG_OP_IR(ushort operation, ushort dest, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{operation, dest, src,
|
2017-10-14 18:07:17 +00:00
|
|
|
SET_FL_IR, dest,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// note: do not use DEC here since no flags are affected by this operation
|
|
|
|
private void DJNZ_()
|
|
|
|
{
|
|
|
|
if ((Regs[B] - 1) != 0)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
ASGN, B, (ushort)((Regs[B] - 1) & 0xFF),
|
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
|
|
|
IDLE,
|
|
|
|
ASGN, W, 0,
|
|
|
|
ADDS, PCl, PCh, Z, W,
|
|
|
|
TR16, Z, W, PCl, PCh,
|
2018-06-01 01:05:41 +00:00
|
|
|
IDLE,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 22:04:19 +00:00
|
|
|
BUSRQ = new ushort[] {I, PCh, 0, 0, PCh, PCh, PCh, PCh, PCh, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
ASGN, B, (ushort)((Regs[B] - 1) & 0xFF),
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, ALU, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 22:04:19 +00:00
|
|
|
BUSRQ = new ushort[] {I, PCh, 0, 0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void HALT_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
|
|
|
HALT };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void JR_COND(bool cond)
|
|
|
|
{
|
|
|
|
if (cond)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
|
|
|
ASGN, W, 0,
|
2018-06-01 01:05:41 +00:00
|
|
|
IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-05 16:52:10 +00:00
|
|
|
ADDS, PCl, PCh, Z, W,
|
|
|
|
TR16, Z, W, PCl, PCh,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 16:52:10 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, PCh, PCh, PCh, PCh, PCh, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, ALU, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void JP_COND(bool cond)
|
|
|
|
{
|
|
|
|
if (cond)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, PCh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, PCh, 0, 0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void RET_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, SPl, SPh,
|
|
|
|
TR16, PCl, PCh, Z, W,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void RETI_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void RETN_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
EI_RETN,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
private void RET_COND(bool cond)
|
|
|
|
{
|
|
|
|
if (cond)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] {0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void CALL_COND(bool cond)
|
|
|
|
{
|
|
|
|
if (cond)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-03 23:14:30 +00:00
|
|
|
DEC16, SPl, SPh,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, PCl, PCh,
|
2018-06-03 23:14:30 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-03 23:14:30 +00:00
|
|
|
WR_DEC, SPl, SPh, PCh,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2017-10-13 00:20:13 +00:00
|
|
|
WR, SPl, SPh, PCl,
|
2018-06-01 01:05:41 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] {PCh, 0, 0, PCh, 0, 0, PCh, SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, W, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, PCh, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void INT_OP(ushort operation, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{operation, src,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void BIT_OP(ushort operation, ushort bit, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{operation, bit, src,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void PUSH_(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-03 23:14:30 +00:00
|
|
|
{DEC16, SPl, SPh,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-03 23:14:30 +00:00
|
|
|
WR_DEC, SPl, SPh, src_h,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2017-10-13 00:20:13 +00:00
|
|
|
WR, SPl, SPh, src_l,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { I, SPh, 0, 0, SPh, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
private void POP_(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, src_l, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, src_h, SPl, SPh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { SPh, 0, 0, SPh, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void RST_(ushort n)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-03 23:14:30 +00:00
|
|
|
{DEC16, SPl, SPh,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-03 23:14:30 +00:00
|
|
|
WR_DEC, SPl, SPh, PCh,
|
|
|
|
RST, n,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-01 19:21:05 +00:00
|
|
|
WR, SPl, SPh, PCl,
|
2018-06-03 23:14:30 +00:00
|
|
|
TR16, PCl, PCh, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { I, SPh, 0, 0, SPh, 0, 0, W, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void PREFIX_(ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2017-10-19 16:08:34 +00:00
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-19 16:08:34 +00:00
|
|
|
PREFIX, src};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
2018-06-05 16:52:10 +00:00
|
|
|
private void PREFETCH_(ushort src)
|
2017-10-13 00:20:13 +00:00
|
|
|
{
|
2018-06-05 16:52:10 +00:00
|
|
|
if (src == IXCBpre)
|
|
|
|
{
|
|
|
|
Regs[W] = Regs[Ixh];
|
|
|
|
Regs[Z] = Regs[Ixl];
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Regs[W] = Regs[Iyh];
|
|
|
|
Regs[Z] = Regs[Iyl];
|
|
|
|
}
|
|
|
|
|
2017-10-13 00:20:13 +00:00
|
|
|
cur_instr = new ushort[]
|
2018-06-05 16:52:10 +00:00
|
|
|
{IDLE,
|
|
|
|
WAIT,
|
|
|
|
RD_INC, ALU, PCl, PCh,
|
|
|
|
ADDS, Z, W, ALU, ZERO,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2018-06-05 16:52:10 +00:00
|
|
|
IDLE,
|
|
|
|
PREFIX, src,};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 22:04:19 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, PCh, 0, 0, PCh, PCh };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void DI_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{DI,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void EI_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{EI,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void JP_16(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{TR16, PCl, PCh, src_l, src_h,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { src_h, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void LD_SP_16(ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2017-10-13 20:27:41 +00:00
|
|
|
{IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
TR16, SPl, SPh, src_l, src_h,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { I, I, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void OUT_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-04 15:42:59 +00:00
|
|
|
IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR, W, A,
|
2017-12-01 13:20:18 +00:00
|
|
|
OUT, Z, W, A,
|
2018-06-04 15:42:59 +00:00
|
|
|
INC16, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0, 0, 0 ,0, PCh, 0, 0, 0};
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void OUT_REG_(ushort dest, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-04 15:42:59 +00:00
|
|
|
IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR16, Z, W, C, B,
|
2017-12-01 13:20:18 +00:00
|
|
|
OUT, Z, W, src,
|
2018-06-04 15:42:59 +00:00
|
|
|
INC16, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void IN_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
RD_INC, Z, PCl, PCh,
|
2017-10-13 00:20:13 +00:00
|
|
|
IDLE,
|
2018-06-04 15:42:59 +00:00
|
|
|
IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
TR, W, A,
|
2017-12-01 13:20:18 +00:00
|
|
|
IN, A, Z, W,
|
2017-10-13 00:20:13 +00:00
|
|
|
INC16, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0, 0, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void IN_REG_(ushort dest, ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
TR16, Z, W, C, B,
|
2018-06-01 19:21:05 +00:00
|
|
|
WAIT,
|
|
|
|
IN, dest, src, B,
|
2017-10-13 00:20:13 +00:00
|
|
|
INC16, Z, W,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { 0, 0, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void REG_OP_16_(ushort op, ushort dest_l, ushort dest_h, ushort src_l, ushort src_h)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
|
|
|
{IDLE,
|
|
|
|
IDLE,
|
|
|
|
TR16, Z, W, dest_l, dest_h,
|
|
|
|
INC16, Z, W,
|
|
|
|
IDLE,
|
2017-10-13 20:27:41 +00:00
|
|
|
IDLE,
|
2017-10-13 00:20:13 +00:00
|
|
|
op, dest_l, dest_h, src_l, src_h,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP};
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { I, I, I, I, I, I, I, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void INT_MODE_(ushort src)
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{INT_MODE, src,
|
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-04 18:27:57 +00:00
|
|
|
BUSRQ = new ushort[] { PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void RRD_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{TR16, Z, W, L, H,
|
|
|
|
WAIT,
|
2017-10-13 00:20:13 +00:00
|
|
|
RD, ALU, Z, W,
|
|
|
|
IDLE,
|
|
|
|
RRD, ALU, A,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-03 23:14:30 +00:00
|
|
|
WR_INC, Z, W, ALU,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { H, 0, 0, H, H, H, H, W, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
private void RLD_()
|
|
|
|
{
|
|
|
|
cur_instr = new ushort[]
|
2018-06-01 01:05:41 +00:00
|
|
|
{TR16, Z, W, L, H,
|
|
|
|
WAIT,
|
2017-10-13 00:20:13 +00:00
|
|
|
RD, ALU, Z, W,
|
|
|
|
IDLE,
|
|
|
|
RLD, ALU, A,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
2018-06-03 23:14:30 +00:00
|
|
|
WR_INC, Z, W, ALU,
|
|
|
|
IDLE,
|
2018-06-01 01:05:41 +00:00
|
|
|
WAIT,
|
|
|
|
OP_F,
|
2017-10-13 00:20:13 +00:00
|
|
|
OP };
|
2018-06-03 23:14:30 +00:00
|
|
|
|
2018-06-05 19:05:48 +00:00
|
|
|
BUSRQ = new ushort[] { H, 0, 0, H, H, H, H, W, 0, 0, PCh, 0, 0, 0 };
|
2017-10-13 00:20:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|