501 lines
15 KiB
C#
501 lines
15 KiB
C#
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namespace GarboDev
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{
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using System;
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using System.Collections.Generic;
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using System.Text;
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public class Arm7Processor
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{
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private Memory memory = null;
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private FastArmCore armCore = null;
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private ThumbCore thumbCore = null;
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private Dictionary<uint, bool> breakpoints = null;
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private int cycles = 0;
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private int timerCycles = 0;
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private int soundCycles = 0;
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// CPU mode definitions
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public const uint USR = 0x10;
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public const uint FIQ = 0x11;
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public const uint IRQ = 0x12;
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public const uint SVC = 0x13;
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public const uint ABT = 0x17;
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public const uint UND = 0x1B;
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public const uint SYS = 0x1F;
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// CPSR bit definitions
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public const int N_BIT = 31;
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public const int Z_BIT = 30;
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public const int C_BIT = 29;
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public const int V_BIT = 28;
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public const int I_BIT = 7;
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public const int F_BIT = 6;
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public const int T_BIT = 5;
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public const uint N_MASK = (uint)(1U << N_BIT);
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public const uint Z_MASK = (uint)(1U << Z_BIT);
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public const uint C_MASK = (uint)(1U << C_BIT);
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public const uint V_MASK = (uint)(1U << V_BIT);
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public const uint I_MASK = (uint)(1U << I_BIT);
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public const uint F_MASK = (uint)(1U << F_BIT);
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public const uint T_MASK = (uint)(1U << T_BIT);
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// Standard registers
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private uint[] registers = new uint[16];
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private uint cpsr = 0;
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// Banked registers
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private uint[] bankedFIQ = new uint[7];
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private uint[] bankedIRQ = new uint[2];
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private uint[] bankedSVC = new uint[2];
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private uint[] bankedABT = new uint[2];
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private uint[] bankedUND = new uint[2];
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// Saved CPSR's
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private uint spsrFIQ = 0;
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private uint spsrIRQ = 0;
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private uint spsrSVC = 0;
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private uint spsrABT = 0;
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private uint spsrUND = 0;
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private ushort keyState;
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private bool breakpointHit = false;
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private bool cpuHalted = false;
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public ushort KeyState
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{
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set { this.keyState = value; }
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}
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public int Cycles
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{
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get { return this.cycles; }
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set { this.cycles = value; }
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}
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public bool ArmState
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{
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get { return (this.cpsr & Arm7Processor.T_MASK) != Arm7Processor.T_MASK; }
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}
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public uint[] Registers
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{
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get { return this.registers; }
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}
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public uint CPSR
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{
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get { return this.cpsr; }
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set { this.cpsr = value; }
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}
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public bool SPSRExists
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{
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get
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{
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switch (this.cpsr & 0x1F)
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{
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case USR:
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case SYS:
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return false;
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case FIQ:
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case SVC:
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case ABT:
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case IRQ:
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case UND:
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return true;
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default:
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return false;
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}
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}
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}
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public uint SPSR
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{
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get
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{
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switch (this.cpsr & 0x1F)
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{
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case USR:
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case SYS:
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return 0xFFFFFFFF;
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case FIQ:
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return this.spsrFIQ;
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case SVC:
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return this.spsrSVC;
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case ABT:
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return this.spsrABT;
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case IRQ:
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return this.spsrIRQ;
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case UND:
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return this.spsrUND;
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default:
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throw new Exception("Unhandled CPSR state...");
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}
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}
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set
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{
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switch (this.cpsr & 0x1F)
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{
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case USR:
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case SYS:
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break;
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case FIQ:
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this.spsrFIQ = value;
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break;
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case SVC:
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this.spsrSVC = value;
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break;
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case ABT:
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this.spsrABT = value;
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break;
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case IRQ:
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this.spsrIRQ = value;
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break;
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case UND:
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this.spsrUND = value;
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break;
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default:
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throw new Exception("Unhandled CPSR state...");
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}
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}
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}
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public Dictionary<uint, bool> Breakpoints
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{
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get
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{
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return this.breakpoints;
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}
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}
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public bool BreakpointHit
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{
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get { return this.breakpointHit; }
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set { this.breakpointHit = value; }
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}
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public Arm7Processor(Memory memory)
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{
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this.memory = memory;
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this.memory.Processor = this;
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this.armCore = new FastArmCore(this, this.memory);
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this.thumbCore = new ThumbCore(this, this.memory);
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this.breakpoints = new Dictionary<uint, bool>();
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this.breakpointHit = false;
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}
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private void SwapRegsHelper(uint[] swapRegs)
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{
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for (int i = 14; i > 14 - swapRegs.Length; i--)
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{
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uint tmp = this.registers[i];
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this.registers[i] = swapRegs[swapRegs.Length - (14 - i) - 1];
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swapRegs[swapRegs.Length - (14 - i) - 1] = tmp;
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}
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}
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private void SwapRegisters(uint bank)
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{
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switch (bank & 0x1F)
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{
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case FIQ:
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this.SwapRegsHelper(this.bankedFIQ);
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break;
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case SVC:
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this.SwapRegsHelper(this.bankedSVC);
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break;
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case ABT:
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this.SwapRegsHelper(this.bankedABT);
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break;
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case IRQ:
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this.SwapRegsHelper(this.bankedIRQ);
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break;
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case UND:
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this.SwapRegsHelper(this.bankedUND);
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break;
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}
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}
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public void WriteCpsr(uint newCpsr)
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{
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if ((newCpsr & 0x1F) != (this.cpsr & 0x1F))
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{
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// Swap out the old registers
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this.SwapRegisters(this.cpsr);
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// Swap in the new registers
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this.SwapRegisters(newCpsr);
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}
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this.cpsr = newCpsr;
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}
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public void EnterException(uint mode, uint vector, bool interruptsDisabled, bool fiqDisabled)
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{
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uint oldCpsr = this.cpsr;
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if ((oldCpsr & Arm7Processor.T_MASK) != 0)
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{
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registers[15] += 2U;
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}
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// Clear T bit, and set mode
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uint newCpsr = (oldCpsr & ~0x3FU) | mode;
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if (interruptsDisabled) newCpsr |= 1 << 7;
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if (fiqDisabled) newCpsr |= 1 << 6;
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this.WriteCpsr(newCpsr);
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this.SPSR = oldCpsr;
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registers[14] = registers[15];
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registers[15] = vector;
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this.ReloadQueue();
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}
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public void RequestIrq(int irq)
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{
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ushort iflag = Memory.ReadU16(this.memory.IORam, Memory.IF);
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iflag |= (ushort)(1 << irq);
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Memory.WriteU16(this.memory.IORam, Memory.IF, iflag);
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}
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public void FireIrq()
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{
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ushort ime = Memory.ReadU16(this.memory.IORam, Memory.IME);
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ushort ie = Memory.ReadU16(this.memory.IORam, Memory.IE);
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ushort iflag = Memory.ReadU16(this.memory.IORam, Memory.IF);
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if ((ie & (iflag)) != 0 && (ime & 1) != 0 && (this.cpsr & (1 << 7)) == 0)
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{
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// Off to the irq exception vector
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this.EnterException(Arm7Processor.IRQ, 0x18, true, false);
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}
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}
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public void Reset(bool skipBios)
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{
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this.breakpointHit = false;
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this.cpuHalted = false;
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// Default to ARM state
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this.cycles = 0;
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this.timerCycles = 0;
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this.soundCycles = 0;
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this.bankedSVC[0] = 0x03007FE0;
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this.bankedIRQ[0] = 0x03007FA0;
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this.cpsr = SYS;
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this.spsrSVC = this.cpsr;
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for (int i = 0; i < 15; i++) this.registers[i] = 0;
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if (skipBios)
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{
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this.registers[15] = 0x8000000;
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}
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else
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{
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this.registers[15] = 0;
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}
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this.armCore.BeginExecution();
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}
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public void Halt()
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{
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this.cpuHalted = true;
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this.cycles = 0;
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}
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public void Step()
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{
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this.breakpointHit = false;
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if ((this.cpsr & Arm7Processor.T_MASK) == Arm7Processor.T_MASK)
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{
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this.thumbCore.Step();
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}
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else
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{
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this.armCore.Step();
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}
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this.UpdateTimers();
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}
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public void ReloadQueue()
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{
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if ((this.cpsr & Arm7Processor.T_MASK) == Arm7Processor.T_MASK)
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{
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this.thumbCore.BeginExecution();
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}
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else
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{
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this.armCore.BeginExecution();
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}
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}
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private void UpdateTimer(int timer, int cycles, bool countUp)
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{
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ushort control = Memory.ReadU16(this.memory.IORam, Memory.TM0CNT + (uint)(timer * 4));
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// Make sure timer is enabled, or count up is disabled
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if ((control & (1 << 7)) == 0) return;
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if (!countUp && (control & (1 << 2)) != 0) return;
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if (!countUp)
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{
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switch (control & 3)
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{
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case 0: cycles *= 1 << 10; break;
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case 1: cycles *= 1 << 4; break;
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case 2: cycles *= 1 << 2; break;
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// Don't need to do anything for case 3
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}
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}
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this.memory.TimerCnt[timer] += (uint)cycles;
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uint timerCnt = this.memory.TimerCnt[timer] >> 10;
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if (timerCnt > 0xffff)
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{
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ushort soundCntX = Memory.ReadU16(this.memory.IORam, Memory.SOUNDCNT_X);
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if ((soundCntX & (1 << 7)) != 0)
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{
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ushort soundCntH = Memory.ReadU16(this.memory.IORam, Memory.SOUNDCNT_H);
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if (timer == ((soundCntH >> 10) & 1))
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{
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// FIFO A overflow
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this.memory.SoundManager.DequeueA();
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if (this.memory.SoundManager.QueueSizeA < 16)
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{
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this.memory.FifoDma(1);
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// TODO
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if (this.memory.SoundManager.QueueSizeA < 16)
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{
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}
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}
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}
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if (timer == ((soundCntH >> 14) & 1))
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{
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// FIFO B overflow
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this.memory.SoundManager.DequeueB();
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if (this.memory.SoundManager.QueueSizeB < 16)
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{
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this.memory.FifoDma(2);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Overflow, attempt to fire IRQ
|
|||
|
|
if ((control & (1 << 6)) != 0)
|
|||
|
|
{
|
|||
|
|
this.RequestIrq(3 + timer);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (timer < 3)
|
|||
|
|
{
|
|||
|
|
ushort control2 = Memory.ReadU16(this.memory.IORam, Memory.TM0CNT + (uint)((timer + 1) * 4));
|
|||
|
|
if ((control2 & (1 << 2)) != 0)
|
|||
|
|
{
|
|||
|
|
// Count-up
|
|||
|
|
this.UpdateTimer(timer + 1, (int)((timerCnt >> 16) << 10), true);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Reset the original value
|
|||
|
|
uint count = Memory.ReadU16(this.memory.IORam, Memory.TM0D + (uint)(timer * 4));
|
|||
|
|
this.memory.TimerCnt[timer] = count << 10;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public void UpdateTimers()
|
|||
|
|
{
|
|||
|
|
int cycles = this.timerCycles - this.cycles;
|
|||
|
|
|
|||
|
|
for (int i = 0; i < 4; i++)
|
|||
|
|
{
|
|||
|
|
this.UpdateTimer(i, cycles, false);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
this.timerCycles = this.cycles;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public void UpdateKeyState()
|
|||
|
|
{
|
|||
|
|
ushort KEYCNT = this.memory.ReadU16Debug(Memory.REG_BASE + Memory.KEYCNT);
|
|||
|
|
|
|||
|
|
if ((KEYCNT & (1 << 14)) != 0)
|
|||
|
|
{
|
|||
|
|
if ((KEYCNT & (1 << 15)) != 0)
|
|||
|
|
{
|
|||
|
|
KEYCNT &= 0x3FF;
|
|||
|
|
if (((~this.keyState) & KEYCNT) == KEYCNT)
|
|||
|
|
this.RequestIrq(12);
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
KEYCNT &= 0x3FF;
|
|||
|
|
if (((~this.keyState) & KEYCNT) != 0)
|
|||
|
|
this.RequestIrq(12);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
this.memory.KeyState = this.keyState;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public void UpdateSound()
|
|||
|
|
{
|
|||
|
|
this.memory.SoundManager.Mix(this.soundCycles);
|
|||
|
|
this.soundCycles = 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public void Execute(int cycles)
|
|||
|
|
{
|
|||
|
|
this.cycles += cycles;
|
|||
|
|
this.timerCycles += cycles;
|
|||
|
|
this.soundCycles += cycles;
|
|||
|
|
this.breakpointHit = false;
|
|||
|
|
|
|||
|
|
if (this.cpuHalted)
|
|||
|
|
{
|
|||
|
|
ushort ie = Memory.ReadU16(this.memory.IORam, Memory.IE);
|
|||
|
|
ushort iflag = Memory.ReadU16(this.memory.IORam, Memory.IF);
|
|||
|
|
|
|||
|
|
if ((ie & iflag) != 0)
|
|||
|
|
{
|
|||
|
|
this.cpuHalted = false;
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
this.cycles = 0;
|
|||
|
|
this.UpdateTimers();
|
|||
|
|
this.UpdateSound();
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
while (this.cycles > 0)
|
|||
|
|
{
|
|||
|
|
if ((this.cpsr & Arm7Processor.T_MASK) == Arm7Processor.T_MASK)
|
|||
|
|
{
|
|||
|
|
this.thumbCore.Execute();
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
this.armCore.Execute();
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
this.UpdateTimers();
|
|||
|
|
this.UpdateSound();
|
|||
|
|
|
|||
|
|
if (this.breakpointHit)
|
|||
|
|
{
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|